Semiconductor substrates and semiconductor devices

Abstract

To provide low-cost, high-quality semiconductor substrates and semiconductor devices. [Solution] The semiconductor substrate (1) comprises a hexagonal SiC single crystal layer (13I), a SiC epitaxial growth layer (12E) disposed on the Si plane of the SiC single crystal layer (13I), and a SiC polycrystalline growth layer (18PC) disposed on the C plane facing the Si plane of the SiC single crystal layer (13I). The SiC single crystal layer comprises a single crystal SiC thinning layer (10HE). The single crystal SiC thinning layer comprises a first ion implantation layer. The SiC single crystal layer comprises a second ion implantation layer. The SiC polycrystalline growth layer has an impurity density of 1 × 10⁻¹⁶ 18 cm -3 ~1 × 10 21 cm -3 He is doped.

Description

Technical Field

[0001] This embodiment relates to a semiconductor substrate and a semiconductor device.

Background Art

[0002] In recent years, silicon carbide (SiC) semiconductors have attracted attention because they have a wider bandgap energy and higher breakdown voltage performance than Si semiconductors and GaAs semiconductors, enabling high breakdown voltage, large current, low on-resistance, high efficiency, low power consumption, high-speed switching, etc.

[0003] As a method for forming a SiC wafer, for example, a method of forming a SiC epitaxial growth layer by chemical vapor deposition (CVD) on a SiC single crystal substrate by sublimation method, or a method of attaching a SiC single crystal substrate by sublimation method to a CVD polycrystalline substrate of SiC, and further forming a SiC epitaxial growth layer on the SiC single crystal substrate by CVD method, etc. are available.

[0004] Conventionally, SiC devices such as Schottky Barrier Diode (SBD), MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and IGBT (Insulated Gate Bipolar Transistor) have been provided for power control applications.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

[0006] SiC semiconductor substrates on which such SiC-based devices are formed were sometimes fabricated by bonding a single-crystal SiC semiconductor substrate to a polycrystalline SiC semiconductor substrate in order to reduce manufacturing costs or provide desired physical properties.

[0007] Furthermore, in order to grow an epitaxial layer on a single-crystal SiC semiconductor substrate attached to a polycrystalline SiC semiconductor substrate, it was necessary to attach a high-quality single-crystal SiC semiconductor substrate to the polycrystalline SiC semiconductor substrate without defects. However, the polishing process required to ensure the surface roughness necessary for attaching the single-crystal SiC semiconductor substrate to the polycrystalline SiC semiconductor substrate by room-temperature bonding or diffusion bonding was costly, and defects occurring at the bonding interface sometimes reduced the yield.

[0008] This embodiment provides low-cost, high-quality semiconductor substrates and semiconductor devices. [Means for solving the problem]

[0009] According to one aspect of the present disclosure, the SiC single crystal layer comprises a SiC single crystal layer, a SiC epitaxial growth layer disposed on the Si plane of the SiC single crystal layer, and a SiC polycrystalline growth layer disposed on the C plane facing the Si plane of the SiC single crystal layer, wherein the SiC single crystal layer comprises a single crystal SiC thinning layer, the single crystal SiC thinning layer comprises a first ion implantation layer, the SiC single crystal layer comprises a second ion implantation layer, and the SiC polycrystalline growth layer has an impurity density of 1 × 10⁻¹⁶ 18 cm -3 ~1 × 10 21 cm -3 A semiconductor substrate that has been doped is provided.

[0010] According to other aspects of this disclosure, a semiconductor device comprising the above-mentioned semiconductor substrate is provided. [Effects of the Invention]

[0011] According to this embodiment, it is possible to provide low-cost and high-quality semiconductor substrates and semiconductor devices. [Brief explanation of the drawing]

[0012] [Figure 1] Figure 1 shows a cross-sectional view of a structure in which a hydrogen ion implantation layer and a phosphate ion implantation layer are formed on the C-plane of a SiC single crystal substrate, according to a first embodiment of a semiconductor substrate manufacturing method. [Figure 2] Figure 2 shows a cross-sectional view of a structure in which a SiC polycrystalline growth layer is formed on the C-plane of a phosphate ion implantation layer by CVD, according to a method for manufacturing a semiconductor substrate according to the first embodiment. [Figure 3A] Figure 3A shows a cross-sectional view of a semiconductor substrate manufacturing method according to the first embodiment, in which a SiC single crystal substrate is separated from a SiC polycrystalline growth layer and a SiC single crystal layer is formed on the SiC polycrystalline growth layer, separated from the SiC single crystal substrate via a delamination surface within the single crystal SiC thinning layer. [Figure 3B] Figure 3B shows a cross-sectional view of the structure of the exfoliated and separated SiC single crystal substrate. [Figure 4] Figure 4 shows a cross-sectional view of a structure in which the Si surface of a SiC single crystal layer has been polished, representing a method for manufacturing a semiconductor substrate according to the first embodiment. [Figure 5] Figure 5 shows a cross-sectional view of a structure in which a SiC epitaxial growth layer is formed on a SiC thinning layer, which is a method for manufacturing a semiconductor substrate according to the first embodiment. [Figure 6] Figure 6 shows a cross-sectional view of a structure in which a hydrogen ion implantation layer is formed on the Si surface of a SiC single crystal substrate, which is a method for manufacturing a semiconductor substrate according to the second embodiment. [Figure 7] Figure 7 shows a cross-sectional view of a semiconductor substrate manufacturing method according to the second embodiment, in which a hydrogen ion implanted layer is weakened by annealing to form a thinned single-crystal SiC layer, and then a SiC epitaxial growth layer is formed on the Si surface of the thinned single-crystal SiC layer. [Figure 8]Figure 8 shows a cross-sectional view of a structure obtained by a second embodiment of a semiconductor substrate manufacturing method, in which an adhesive layer is applied to the Si surface of a SiC epitaxial growth layer, a graphite substrate is attached, and then the SiC single crystal substrate is peeled and separated via a thinned single crystal SiC layer formed by weakening annealing. [Figure 9] Figure 9 shows a cross-sectional view of a semiconductor substrate manufacturing method according to a second embodiment, in which a phosphate ion implanted layer is formed by smoothing the peeled surface of a thinned single-crystal SiC layer and then performing P ion implantation on the C-plane of the thinned single-crystal SiC layer. [Figure 10] Figure 10 shows a cross-sectional view of a structure in which the adhesive has been removed, the laminate of the thinned single-crystal SiC layer and the epitaxially grown SiC layer is separated from the graphite substrate, the separated laminate of the thinned single-crystal SiC layer and the epitaxially grown SiC layer is mounted so that the Si surface is in contact with the carbon tray, the C surface is exposed with the C surface facing upward, and a polycrystalline SiC grown layer is formed on the same surface by the CVD method. [Figure 11] Figure 11 shows a cross-sectional view of a structure in which the carbon tray has been removed, which is a method for manufacturing a semiconductor substrate according to the second embodiment. [Figure 12] Figure 12 shows a cross-sectional view of a Schottky barrier diode fabricated using a semiconductor substrate according to the embodiment. [Figure 13] Figure 13 shows a cross-sectional view of a trench gate type MOSFET fabricated using a semiconductor substrate according to the embodiment. [Figure 14] Figure 14 shows a cross-sectional view of a planar gate type MOSFET fabricated using a semiconductor substrate according to the embodiment. [Figure 15A] Figure 15A shows a plan view illustrating the crystal planes of SiC. [Figure 15B] Figure 15B shows a side view illustrating the crystal plane of SiC. [Figure 16] Figure 16 shows a bird's-eye view of a semiconductor substrate (wafer) according to an embodiment. [Figure 17A] Figure 17A shows a bird's-eye view of a 4H-SiC crystal unit cell applicable to a SiC epitaxial substrate semiconductor substrate according to the embodiment. [Figure 17B]Figure 17B shows the structure of the two layers of a 4H-SiC crystal. [Figure 17C] Figure 17C shows the structure of the four layers of a 4H-SiC crystal. [Figure 18] Figure 18 shows a configuration diagram of the 4H-SiC crystal unit cell shown in Figure 17A, viewed from directly above the (0001) plane. [Modes for carrying out the invention]

[0013] Next, embodiments will be described with reference to the drawings. In the drawings described below, identical or similar parts are denoted by the same or similar reference numerals. The drawings are schematic. Furthermore, the embodiments shown below are illustrative examples of devices and methods for realizing the technical idea and do not specify the material, shape, structure, arrangement, etc. of the parts. Various modifications can be made to the embodiments.

[0014] In the following description of the embodiments, [C] indicates the C-plane of SiC, and [S] indicates the Si-plane of SiC. (First Embodiment) (Semiconductor substrate)

[0015] As shown in Figure 5, the semiconductor substrate 1 according to the first embodiment comprises a hexagonal SiC single crystal layer 13I, a SiC epitaxial growth layer (SiC-epi) 12E disposed on the Si plane of the SiC single crystal layer 13I, and a SiC polycrystalline growth layer (SiC-polyCVD) 18PC disposed on the C plane facing the Si plane of the SiC single crystal layer 13I.

[0016] As shown in Figure 5, the SiC single crystal layer 13I comprises a thinned single crystal SiC layer 10HE. The thinned single crystal SiC layer 10HE comprises a first ion implantation layer. As shown in Figure 5, the first ion implantation layer comprises a hydrogen ion implantation layer 10HI. The thinned single crystal SiC layer 10HE comprises an embrittlement layer of the hydrogen ion implantation layer 10HI. The SiC single crystal layer 13I may also comprise a second ion implantation layer. Here, as shown in Figure 5, the second ion implantation layer is positioned between the thinned single crystal SiC layer 10HE and the SiC polycrystalline growth layer 18PC. As shown in Figure 5, the second ion implantation layer may also comprise a phosphorus ion implantation layer 10PI.

[0017] Here, the Si plane of the SiC single crystal layer 13I is, for example, the

[0001] orientation plane of 4H-SiC, and the C plane of the SiC single crystal layer 13I is the [000-1] orientation plane of 4H-SiC.

[0018] Furthermore, the SiC single crystal substrate 10SB can be reused by peeling it off from the SiC epitaxial growth layer 12E.

[0019] (Manufacturing method) A cross-sectional view of a semiconductor substrate manufacturing method according to the first embodiment, in which a hydrogen ion implantation layer 10HI and a phosphorus ion implantation layer 10PI are sequentially formed on the C-plane of a SiC single crystal substrate (SiCSB) 10SB, is shown in Figure 1.

[0020] A cross-sectional view of a structure in which a SiC polycrystalline growth layer (SiC-poly CVD) 18PC is formed on the C-plane of a phosphate ion implantation layer 10PI by a CVD method, according to the first embodiment of the semiconductor substrate manufacturing method, is shown in Figure 2.

[0021] A cross-sectional view of a semiconductor substrate manufacturing method according to the first embodiment, in which a SiC single crystal substrate 10SB is separated from a SiC polycrystalline growth layer 18PC and a SiC single crystal layer 13I is formed on the SiC polycrystalline growth layer 18PC via a delamination surface BP in the single crystal SiC thinning layer 10HE, is shown in Figure 3A.

[0022] On the other hand, a cross-sectional view of the structure of the exfoliated and separated SiC single crystal substrate 10SB is shown in Figure 3B.

[0023] A method for manufacturing a semiconductor substrate according to the first embodiment, in which the Si surface of the SiC single crystal layer 13I is polished, is shown in Figure 4 as a cross-sectional view of the structure.

[0024] A cross-sectional view of a structure in which a SiC epitaxial growth layer 12E is formed on the Si surface of a SiC single crystal layer 13I, according to the first embodiment of the semiconductor substrate manufacturing method, is shown in Figure 5.

[0025] (Ion implantation exfoliation method) In the semiconductor substrate manufacturing method according to the first embodiment, an ion implantation exfoliation method is applied. By the ion implantation exfoliation method, a thinned single-crystal SiC layer 10HE can be formed on the surface of the SiC single-crystal substrate 10SB. The ion implantation exfoliation method has the following steps.

[0026] (a) First, hydrogen ion implantation is performed on the Si surface of the hexagonal SiC single crystal substrate 10SB to form a hydrogen ion implanted layer 10HI to a predetermined depth.

[0027] (b) Next, an annealing treatment is performed to weaken the hydrogen ion implanted layer 10HI, and a thinned single-crystal SiC layer 10HE is formed. The embrittlemented hydrogen ion implanted layer 10HI becomes the thinned single-crystal SiC layer 10HE. Here, the annealing treatment is a brittle thermal annealing treatment. This treatment generates hydrogen microbubbles after hydrogen ion implantation to make the thinned single-crystal SiC layer 10HE easier to fracture. When stress such as shear stress is applied, a delamination surface BP is formed within the thinned single-crystal SiC layer 10HE.

[0028] The first embodiment of the method for manufacturing a semiconductor substrate is a method for manufacturing a semiconductor substrate 1 having a single-crystal SiC thinned layer 10HE and a SiC epitaxial growth layer 12E on a SiC polycrystalline growth layer 18PC. The method comprises the steps of thinning the surface of a hexagonal SiC single-crystal substrate 10SB by ion implantation exfoliation, epitaxially growing single-crystal SiC on the first surface of the thinned SiC single-crystal layer 13I, and directly growing a SiC polycrystalline growth layer 18PC on the second surface of the thinned SiC single-crystal layer 13I by CVD. Here, no substrate bonding method is used for bonding the interfaces of the first and second surfaces.

[0029] Furthermore, the method for manufacturing a semiconductor substrate according to the first embodiment includes a step of thinning the (000-1)C plane of a hexagonal SiC single crystal substrate 10SB by an ion implantation exfoliation method.

[0030] The method for manufacturing a semiconductor substrate according to the first embodiment includes the following steps: forming a hydrogen ion implantation layer 10HI on the C-plane of a SiC single crystal substrate 10SB; forming a SiC polycrystalline growth layer 18PC on the C-plane of a SiC single crystal substrate 10SB; forming a SiC polycrystalline growth layer 18PC along with the hydrogen ion implantation layer 10HI to form a single crystal SiC thinning layer 10HE; peeling off a first laminate of the single crystal SiC thinning layer 10HE and the SiC polycrystalline growth layer 18PC from the SiC single crystal substrate 10SB; smoothing the surface of the peeled single crystal SiC thinning layer 10HE; and forming a SiC epitaxial growth layer 12E on the smoothed surface of the single crystal SiC thinning layer 10HE.

[0031] Referring to the drawings, the method for manufacturing a semiconductor substrate according to the first embodiment will be described in detail below.

[0032] (A) First, as shown in FIG. 1, hydrogen ions are implanted into the C-plane of a hexagonal SiC single crystal substrate (SiCSB) 10SB. When hydrogen ions are implanted into the C-plane of the SiC single crystal substrate 10SB, the hydrogen ions reach a depth corresponding to the incident energy and are distributed at a high concentration. As a result, as shown in FIG. 1, a hydrogen ion implantation layer 10HI is formed from the surface to a predetermined depth.

[0033] A hydrogen ion implantation layer 10HI having a specified depth (about 0.5 μm to 1 μm) is formed by hydrogen ion implantation using an ion implantation and exfoliation method. Here, as the ion implantation conditions, the acceleration energy is, for example, about 100 keV, and the dose amount is, for example, about 2.0×10 17 / cm 2 or so.

[0034] (B) Next, as shown in FIG. 1, other ions (such as P) may be implanted into the C-plane of the SiC single crystal substrate 10SB to reduce the electrical resistance value of the laminated contact interface. Here, the depth of the phosphorus ion implantation layer 10PI is, for example, about 0.01 μm to 0.5 μm. As the ion implantation conditions, the acceleration energy is, for example, about 10 keV to 180 keV, and the dose amount is, for example, about 4×10 15 / cm 2 ~6×10 16 / cm 2 or so.

[0035] (C) Next, as shown in FIG. 2, a SiC polycrystalline growth layer 18PC is formed on the C-plane of the SiC single crystal substrate 10SB. Here, the SiC polycrystalline growth layer 18PC can be deposited on the C-plane of the SiC single crystal substrate 10SB by, for example, the CVD method. The thickness of the SiC polycrystalline growth layer 18PC is preferably about 150 μm to 500 μm, for example. The thickness of the semiconductor substrate 1 (see FIG. 5) is adjusted to be about 150 μm to 500 μm as required. Here, as shown in FIG. 5, the thickness of the semiconductor substrate 1 is the sum of each layer of the SiC polycrystalline growth layer 18PC, the SiC single crystal layer 13I, and the SiC epitaxial growth layer 12E.

[0036] Furthermore, the hydrogen ion implanted layer 10HI can be embrittlement simultaneously with the high-temperature treatment during the deposition of the SiC polycrystalline growth layer 18PC. Simultaneously, activation annealing with hydrogen ions and P ions is performed. The hydrogen ion implanted layer 10HI is weakened simultaneously with the heat treatment during the formation of the SiC polycrystalline growth layer 18PC, and a thinned single-crystal SiC layer 10HE is formed.

[0037] Of the two ion implantations performed on the C-plane of the SiC single-crystal substrate 10SB, the first is hydrogen ion implantation for ion implantation exfoliation. After implanting hydrogen ions (protons), hydrogen microbubbles are generated to embrittle the hydrogen ion implanted layer 10HI. When hydrogen ions are implanted, they accumulate to a depth of approximately 1 μm. When thermal annealing is performed, the hydrogen ions gasify, forming a porous layer within the SiC single-crystal substrate 10SB. This porous layer embrittles the SiC single-crystal substrate 10SB, forming a fragile layer of the hydrogen ion implanted layer 10HI, i.e., a thinned single-crystal SiC layer 10HE. As shown in Figure 2, the fracture surface BP of the thinned single-crystal SiC layer 10HE is made more prone to fracture. By weakening the hydrogen ion implanted layer 10HI, it is possible to avoid the occurrence of crystal defects and warping due to the difference in the coefficient of thermal expansion (CTE) between the SiC single-crystal substrate 10SB and the SiC polycrystalline growth layer 18PC.

[0038] The second ion implantation was P-ion implantation to reduce the ohmic contact resistance at the contact interface between the SiC single-crystal substrate 10SB and the SiC polycrystalline growth layer 18PC, resulting in a donor density of approximately 1 × 10⁻⁶ near the implanted surface. 18 / cm 3 ~1 × 10 20 / cm 3 Multistage P-ion implantation is performed to achieve this. After implantation, activation thermal annealing is necessary to activate the P-ions and improve donor density.

[0039] Both of these annealing processes are achieved simultaneously by heating the substrate during the deposition of the SiC polycrystalline growth layer 18PC using the CVD method.

[0040] (D1) Next, as shown in Figure 3A, the laminate (18PC, 10PI, 10HE) consisting of a single-crystal SiC thinning layer 10HE, a phosphate ion implantation layer 10HP, and a SiC polycrystalline growth layer 18PC is peeled off from the SiC single-crystal substrate 10SB. Here, the peeling process is carried out at the peeling surface BP of the embrittlement-treated single-crystal SiC thinning layer 10HE.

[0041] (D2) On the other hand, as shown in Figure 3B, the uneven structure of the thinned single-crystal SiC layer 10HE is exposed on the C-plane of the peeled SiC single-crystal substrate 10SB. The Si-plane of the SiC single-crystal substrate 10SB is smoothed by sequentially using mechanical polishing and mechanochemical polishing to remove the uneven structure of the thinned single-crystal SiC layer 10HE. As a result of the above process, the average surface roughness Ra of the C-plane of the SiC single-crystal substrate 10SB is, for example, about 1 nm or less. As a result, the SiC single-crystal substrate 10SB can be reused. The SiC single-crystal substrate 10SB becomes reusable.

[0042] (E) Next, as shown in Figure 4, the surface of the peeled single-crystal SiC thinning layer 10HE is smoothed by mechanical polishing and then by mechanical-chemical polishing in sequence. As a result of the above process, the average surface roughness Ra of the Si surface of the single-crystal SiC thinning layer 10HE is, for example, about 1 nm or less.

[0043] (F) Next, as shown in Figure 5, a SiC epitaxial growth layer 12E with good crystallinity is formed on the smoothed surface by homoepitaxial growth using the CVD method. The CVD apparatus for forming the SiC epitaxial growth layer 12E by homoepitaxial growth may be the same as the CVD apparatus for forming the SiC polycrystalline growth layer 18PC on the C-plane of the SiC single crystal substrate 10SB, or it may be configured as a separate, dedicated apparatus.

[0044] By following the above steps, a semiconductor substrate according to the first embodiment can be formed.

[0045] According to the first embodiment, a semiconductor substrate and a method for manufacturing the same can be provided that does not use a substrate bonding method between a SiC epitaxial growth layer and a SiC polycrystalline layer, by forming a thinned single-crystal SiC layer on the C-plane of a hexagonal SiC single-crystal substrate by an ion implantation exfoliation method, and further combining this with the direct growth of a SiC polycrystalline layer on the C-plane of the thinned single-crystal SiC layer.

[0046] According to the first embodiment, a thinned single-crystal SiC layer is formed on the C-plane of a SiC single-crystal substrate by ion implantation exfoliation, and a polycrystalline SiC layer is directly deposited onto the thinned single-crystal SiC layer by CVD. This eliminates the bonding process between the SiC epitaxial growth layer and the SiC polycrystalline growth layer, thereby simplifying the manufacturing process and reducing manufacturing costs. This provides a semiconductor substrate and a method for manufacturing the same.

[0047] According to the semiconductor substrate manufacturing method of the first embodiment, a semiconductor substrate consisting of a SiC epitaxial growth layer and a SiC polycrystalline growth layer can be fabricated without joining substrates by combining ion implantation exfoliation and CVD direct deposition technology.

[0048] According to the first embodiment, a hexagonal SiC single crystal substrate is thinned, and an epitaxial growth layer is formed on the thinned single-crystal SiC layer by homoepitaxial growth. As a result, the Si surface of the hexagonal SiC epitaxial growth layer is obtained on the fabrication surface of the device. Furthermore, although a SiC single crystal substrate, which is more expensive than a Si substrate, is used as the seed substrate, the seed substrate can be reused dozens of times or more, so the cost is not significantly different compared to using a Si substrate.

[0049] According to the first embodiment, since a SiC single crystal substrate is used as the base, the formation of a thinned single crystal SiC layer by ion implantation exfoliation is fundamental. However, there is no need to remove the holding substrate by polishing or etching, and a hexagonal SiC epitaxial growth layer can be obtained, making it suitable as a semiconductor substrate for SiC-based power devices.

[0050] The first embodiment is a method for manufacturing a semiconductor substrate having a SiC epitaxial growth layer on a SiC polycrystalline substrate. In this method, the SiC polycrystalline growth layer is directly deposited by thermal CVD onto a thinned single-crystal SiC layer obtained by thinning the surface of a SiC single-crystal substrate using an ion implantation exfoliation method on the (000-1)C plane of a hexagonal single-crystal SiC substrate. This eliminates the substrate bonding between the SiC epitaxial growth layer and the SiC polycrystalline growth layer, simplifying the manufacturing process and reducing manufacturing costs.

[0051] In the first embodiment, the following effects (1) to (6) can be obtained. (1) Because this method does not require substrate bonding, which is necessary for manufacturing composite substrates using conventional ion implantation delamination methods, it eliminates bonding defects and yield reductions due to voids caused by bonding. In addition, it reduces man-hours, fixed and variable cost losses due to defects, and improves productivity and quality. (2) Precise polishing to ensure bonding is no longer required, eliminating the high costs associated with defective products and increased processing costs, and enabling the provision of inexpensive SiC composite substrates. (3) By pre-implanting ions on one side of the contact surface between the SiC polycrystalline growth layer and the single-crystal SiC epitaxial growth layer, and controlling high-concentration doping on the other side during film deposition, the interfacial contact resistance can be reduced, thereby reducing ohmic contact resistance and lowering the driving voltage specific to composite substrates. (4) The thermal CVD method allows for high-concentration autodoping during the deposition of the SiC polycrystalline growth layer, enabling the bulk electrical resistance to be reduced to a level comparable to that of SiC single-crystal substrates fabricated by the sublimation method. (5) Of the two ion implantations performed on the C-plane of the SiC single crystal substrate, the first is hydrogen ion implantation for ion implantation exfoliation, and after ion implantation, brittle thermal annealing is required to generate hydrogen microbubbles and facilitate the rupture of the thinned layer. The second ion implantation is P ion implantation to reduce the contact interface resistance (ohmic contact) between the single crystal SiC and polycrystalline SiC, and after implantation, activation thermal annealing is required to activate the P ions and improve the donor density. Since both of these annealing processes are achieved simultaneously by heating the substrate during the deposition of the SiC polycrystalline growth layer by CVD, there is no need to perform these annealing processes separately, which reduces manufacturing costs. (6) Before the deposition of a thick film of the SiC polycrystalline growth layer by CVD, a delamination phenomenon occurs due to the embrittlement annealing effect, which mitigates the mismatch in thermal expansion coefficients between the SiC single crystal substrate and the SiC polycrystalline growth layer, thereby suppressing warping.

[0052] (Second Embodiment) (Semiconductor substrate) As shown in Figure 11, the semiconductor substrate 1 according to the second embodiment comprises a hexagonal SiC single crystal layer 13I, a SiC epitaxial growth layer 12E disposed on the Si plane of the SiC single crystal layer 13I, and a SiC polycrystalline growth layer 18PC disposed on the C plane facing the Si plane of the SiC single crystal layer 13I.

[0053] The SiC single crystal layer 13I comprises a thinned single crystal SiC layer 10HE. The thinned single crystal SiC layer 10HE comprises a first ion implantation layer. The first ion implantation layer comprises a hydrogen ion implantation layer 10HI. The thinned single crystal SiC layer 10HE comprises an embrittlement layer of the hydrogen ion implantation layer 10HI. The SiC single crystal layer 13I may also comprise a second ion implantation layer. Here, the second ion implantation layer is positioned between the first ion implantation layer and the SiC polycrystalline growth layer. The second ion implantation layer may also comprise a phosphorus ion implantation layer 10PI.

[0054] Here, the Si plane of the SiC single crystal layer 13I is, for example, a plane with the

[0001] orientation of 4H-SiC, and the C plane of the SiC single crystal layer 13I is, for example, a plane with the [000-1] orientation of 4H-SiC.

[0055] Furthermore, the SiC single crystal substrate 10SB can be reused by peeling it off from the SiC epitaxial growth layer 12E.

[0056] (Manufacturing method) A cross-sectional view of a semiconductor substrate manufacturing method according to a second embodiment, in which a hydrogen ion implantation layer 10HI is formed on the Si surface of a SiC single crystal substrate 10SB, is shown in Figure 6.

[0057] A cross-sectional view of a semiconductor substrate manufacturing method according to the second embodiment, in which a hydrogen ion implanted layer 10HI is weakened by annealing to form a single-crystal SiC thinned layer 10HE, and then a SiC epitaxial growth layer 12E is formed on the Si surface of the single-crystal SiC thinned layer 10HE, is shown in Figure 7.

[0058] A cross-sectional view of a structure obtained by manufacturing a semiconductor substrate according to a second embodiment, in which an adhesive layer 17PI is applied to the Si side of a SiC epitaxial growth layer 12E and a graphite substrate 19GS is attached, and then the SiC single crystal substrate 10SB is peeled off and separated via a weakened single crystal SiC thinning layer 10HE, is shown in Figure 8.

[0059] A cross-sectional view of a structure in which a semiconductor substrate manufacturing method according to the second embodiment is formed by smoothing the peeled surface of a single-crystal SiC thinning layer 10HE and then performing P ion implantation on the C-plane of the single-crystal SiC thinning layer 10HE to form a phosphorus ion implanted layer 10PI is shown in Figure 9.

[0060] A cross-sectional view of a semiconductor substrate manufacturing method according to a second embodiment is shown in Figure 10, in which the adhesive 17PI is removed, the laminate of single-crystal SiC thinning layer 10HE and SiC epitaxial growth layer 12E is separated from the graphite substrate 19GS, the separated laminate of single-crystal SiC thinning layer 10HE and SiC epitaxial growth layer 12E is mounted so that the Si surface is in contact with the carbon tray 20CT, the C surface is exposed with the C surface facing upward, and a SiC polycrystalline growth layer 18PC is formed on the same surface by CVD.

[0061] A cross-sectional view of the structure in which the carbon tray 20CT has been removed, according to the second embodiment of the semiconductor substrate manufacturing method, is shown in Figure 11.

[0062] (Ion implantation exfoliation method) In the semiconductor substrate manufacturing method according to the second embodiment, an ion implantation exfoliation method is applied. A thinned single-crystal SiC layer 10HE is formed from a SiC single-crystal substrate 10SB by the ion implantation exfoliation method. The ion implantation exfoliation method has the following steps.

[0063] (a) First, hydrogen ion implantation is performed on the C-plane of the hexagonal SiC single crystal substrate 10SB to form a hydrogen ion implanted layer 10HI to a predetermined depth.

[0064] (b) Next, when the annealing treatment is performed, the hydrogen ion implanted layer 10HI is weakened, and the thinned single-crystal SiC layer 10HE is formed. The embrittlement of the hydrogen ion implanted layer 10HI becomes the thinned single-crystal SiC layer 10HE. After hydrogen ion implantation, embrittlement thermal annealing is necessary to generate hydrogen microbubbles and make the thinned single-crystal SiC layer 10HE easier to fracture. When stress is applied, a delamination surface BP is formed within the thinned single-crystal SiC layer 10HE.

[0065] The second embodiment is a method for manufacturing a semiconductor substrate 1 having a single-crystal SiC thinned layer 10HE and a SiC epitaxial growth layer 12E on a SiC polycrystalline growth layer 18PC. The method includes the steps of thinning the surface of a hexagonal SiC single-crystal substrate 10SB by ion implantation exfoliation, epitaxially growing single-crystal SiC on the first surface of the thinned SiC single-crystal layer 13I, and directly growing a SiC polycrystalline growth layer 18PC on the second surface of the thinned SiC single-crystal layer 13I by CVD. Here, no substrate bonding method is used for bonding the interfaces of the first and second surfaces.

[0066] Furthermore, the method for manufacturing a semiconductor substrate according to the second embodiment includes a step of thinning the (0001)Si plane of a hexagonal SiC single crystal substrate 10SB by an ion implantation exfoliation method.

[0067] According to the second embodiment, a method for manufacturing a semiconductor substrate having a laminated structure of a SiC single crystal substrate 10SB and a SiC polycrystalline growth layer 18PC can be provided by combining an ion implantation exfoliation method and a CVD direct deposition technique, without joining the substrates.

[0068] The method for manufacturing a semiconductor substrate according to the second embodiment comprises the following steps: forming a hydrogen ion implantation layer 10HI on the Si surface of a SiC single crystal substrate 10SB; forming a SiC epitaxial growth layer 12E on the Si surface of the SiC single crystal substrate 10SB, and simultaneously embritting the hydrogen ion implantation layer 10HI to form a single crystal SiC thinning layer 10HE; attaching a temporary substrate to the Si surface of the SiC epitaxial growth layer 12E; peeling off the laminate of the single crystal SiC thinning layer 10HE and the SiC epitaxial growth layer 12E from the SiC single crystal substrate 10SB; smoothing the surface of the peeled single crystal SiC thinning layer 10HE; and forming a SiC polycrystalline growth layer 18PC on the surface of the smoothed single crystal SiC thinning layer 10HE.

[0069] Referring to the drawings, the method for manufacturing a semiconductor substrate according to the second embodiment will be described in detail below.

[0070] (G1) First, as shown in Figure 6, hydrogen ions for ion implantation exfoliation are implanted into the Si surface of the hexagonal SiC single crystal substrate 10SB to form a hydrogen ion implanted layer 10HI having a specified depth (approximately 1 μm). Here, the ion implantation conditions are, for example, an acceleration energy of approximately 100 keV and a dose of approximately 2.0 × 10⁻⁶. 17 / cm 2 It is to that extent.

[0071] (G2) Next, the hydrogen ion implanted layer 10HI is subjected to high-temperature treatment to embrittle it. After hydrogen ion implantation, embrittlement thermal annealing is necessary to generate hydrogen microbubbles and make the thinned single-crystal SiC layer 10HE easier to fracture.

[0072] (H) Next, as shown in Figure 7, a SiC epitaxial growth layer 12E is formed on the Si plane of the thinned single-crystal SiC layer 10HE by homoepitaxial growth using the CVD method.

[0073] (I) Next, as shown in Figure 8, the substrate structure of Figure 7 is removed from the CVD homoepitaxial growth furnace, and a temporary substrate is attached to the Si side of the SiC epitaxial growth layer 12E with adhesive 17PI in the laminate of the SiC single crystal substrate 10SB, the single crystal SiC thinning layer 10HE, and the SiC epitaxial growth layer 12E. The temporary substrate can be, for example, a graphite substrate 19GS or a sintered silicon substrate, or a silicon substrate. The adhesive layer 17PI can be, for example, an organic adhesive such as a polyimide-based adhesive. Alternatively, an organic adhesive such as an epoxy-based or acrylic-based adhesive may be used. A temporary substrate (graphite substrate 19GS) that is slightly larger than the SiC single crystal substrate 10SB has the advantage of keeping the wafer boat support marks outside the effective substrate area when inserted into the wafer boat groove of a batch-type vertical CVD furnace and aligned.

[0074] (J) Next, as shown in Figure 8, the thinned single-crystal SiC layer 10HE and the SiC epitaxial growth layer 12E, which are bonded to the graphite substrate 19GS, are peeled off and separated from the SiC single-crystal substrate 10SB.

[0075] (K1) Next, as shown in Figure 9, the delamination surface of the laminate of the single-crystal SiC thinning layer 10HE and the SiC epitaxial growth layer 12E bonded to the graphite substrate 19GS is sequentially smoothed by mechanical polishing and mechanical chemical polishing. As a result of the above process, the average surface roughness Ra of the C-plane of the single-crystal SiC thinning layer 10HE is, for example, about 1 nm or less.

[0076] (K2) On the other hand, the uneven structure of the thinned single-crystal SiC layer 10HE is exposed on the Si surface of the peeled-off SiC single-crystal substrate 10SB. The uneven structure of the thinned single-crystal SiC layer 10HE is smoothed by mechanical polishing and then mechanical-chemical polishing. As a result of the above process, the average surface roughness Ra of the Si surface of the SiC single-crystal substrate 10SB is, for example, about 1 nm or less. As a result, the SiC single-crystal substrate 10SB can be reused. The SiC single-crystal substrate 10SB becomes reusable.

[0077] (L) Next, as shown in Figure 9, phosphorus ions are implanted into the smoothed surface to reduce the electrical resistance of the laminated contact interface, forming a phosphorus ion implantation layer 10PI. Here, the depth of the phosphorus ion implantation layer 10PI is, for example, about 0.01 μm to 0.5 μm. As for the ion implantation conditions, the acceleration energy is, for example, about 10 keV to 180 keV, and the dose is, for example, about 4 × 10⁻⁶ 15 / cm 2 ~6×10 16 / cm 2 It is to that extent.

[0078] (M) Next, although not shown in the diagram, the adhesive 17PI is removed by wet etching or an organic solvent, and the laminate of the single-crystal SiC thinning layer 10HE and the SiC epitaxial growth layer 12E is separated from the graphite substrate 19GS.

[0079] (N) Next, as shown in Figure 10, the laminate of the separated single-crystal SiC thinned layer 10HE and the SiC epitaxial growth layer 12E is mounted so that the Si surface is in contact with the carbon tray 20CT, with the C surface facing upward and exposed. A SiC polycrystalline growth layer 18PC is deposited on this surface by CVD, and at the same time, activation and crystal damage recovery annealing are performed.

[0080] (O) Next, as shown in Figure 11, the laminate of the single-crystal SiC thinning layer 10HE, the SiC epitaxial growth layer 12E, and the SiC polycrystalline growth layer 18PC is separated from the carbon tray 20CT and the outer periphery and both sides of the substrate are processed to a predetermined shape and surface state. Note that the CVD apparatus for forming the SiC epitaxial growth layer 12E by homoepitaxial growth on the Si side of the single-crystal SiC thinning layer 10HE by the CVD method and the CVD apparatus for forming the SiC polycrystalline growth layer 18PC on the C side of the single-crystal SiC thinning layer 10HE by the CVD method may be the same CVD apparatus, or they may be configured as separate, dedicated apparatuses.

[0081] By following the above steps, the semiconductor substrate 1 according to the second embodiment can be formed.

[0082] In the second embodiment, a method for manufacturing a composite substrate without using a substrate bonding method is provided by combining thinning of a single-crystal SiC substrate by ion implantation exfoliation on the Si plane of a hexagonal single-crystal SiC substrate with direct growth of a polycrystalline SiC layer by CVD.

[0083] By directly depositing a polycrystalline SiC support layer onto a thinned single-crystal SiC layer on the Si surface of a single-crystal SiC substrate using ion implantation exfoliation, and then depositing the support layer using CVD, the bonding process between the single-crystal SiC layer and the polycrystalline SiC substrate is eliminated, simplifying the manufacturing process and reducing manufacturing costs.

[0084] The second embodiment is a method for manufacturing a SiC composite substrate having a single-crystal SiC epitaxial growth layer on a polycrystalline SiC substrate, wherein, on the (000-1)C plane of a hexagonal single-crystal SiC substrate, a polycrystalline SiC support layer is directly deposited on a single-crystal SiC layer obtained by thinning the surface of the single-crystal SiC substrate using an ion implantation exfoliation method, by thermal CVD, thereby eliminating substrate bonding between the single-crystal SiC layer and the polycrystalline SiC substrate, simplifying the manufacturing process and reducing manufacturing costs.

[0085] In the second embodiment, the following effects (1) to (6) can be obtained. (1) Because this method does not require substrate bonding, which is necessary for manufacturing composite substrates using conventional ion implantation delamination methods, it eliminates bonding defects and yield reductions due to voids caused by bonding. In addition, it reduces man-hours, fixed and variable cost losses due to defects, and improves productivity and quality. (2) Precise polishing to ensure bonding is no longer required, eliminating the high costs associated with defective products and increased processing costs, and enabling the provision of inexpensive SiC composite substrates. (3) By pre-implanting ions on one side of the contact surface between the SiC polycrystalline growth layer and the SiC epitaxial growth layer, and controlling high-concentration doping on the other side during film formation, the interfacial contact resistance can be reduced, thereby reducing the driving voltage specific to composite substrates. (4) The thermal CVD method allows for high-concentration autodoping during the deposition of the SiC polycrystalline growth layer, enabling the bulk electrical resistance to be reduced to a level comparable to that of single-crystal substrates fabricated by sublimation. (5) Of the two ion implantations to the C-plane of the SiC single crystal substrate, the first is hydrogen ion implantation for ion implantation exfoliation, and after ion implantation, brittle thermal annealing is required to generate hydrogen microbubbles and make it easier to break the thinned layer. The second ion implantation is P ion implantation to reduce the contact interface resistance (ohmic contact) between the SiC single crystal substrate and the SiC polycrystalline growth layer, and after implantation, activation thermal annealing is required to activate the P ions and improve the donor density. Since both of these annealing processes are achieved simultaneously by heating the substrate during deposition of the SiC polycrystalline growth layer by CVD, there is no need to perform these annealing processes separately, which reduces manufacturing costs. (6) In the second embodiment in which the Si surface is thinned by ion implantation exfoliation, since it is not necessary to put the SiC single crystal substrate itself into the CVD reaction chamber when depositing the SiC polycrystalline growth layer, the number of times the SiC single crystal substrate can be reused can be increased, thus enabling further cost reduction.

[0086] The semiconductor substrate according to this embodiment can be used, for example, in the manufacture of various SiC-based semiconductor devices. Below, examples of such devices will be described, including SiC-SBDs, SiC trench-gate (T:Trench) type MOSFETs, and SiC planar-gate type MOSFETs.

[0087] (SiC-SBD) As a semiconductor device fabricated using the semiconductor substrate according to the embodiment, the SiC-SBD21 comprises a semiconductor substrate 1 consisting of a SiC polycrystalline growth layer (CVD) 18PC and a SiC epitaxial growth layer 12E, as shown in Figure 12. A SiC single crystal layer 13I may be interposed between the SiC polycrystalline growth layer 18PC and the SiC epitaxial growth layer 12E. Here, the SiC single crystal layer 13I suppresses the expansion of the depletion layer within the SiC epitaxial growth layer 12E and facilitates the formation of ohmic contact with the SiC polycrystalline growth layer 18PC formed on the C-plane of the SiC epitaxial growth layer 12E. The SiC epitaxial growth layer 12E acts as a drift layer, the SiC single crystal layer 13I as a buffer layer, and the SiC polycrystalline growth layer 18PC as a substrate layer.

[0088] The SiC polycrystalline growth layer 18PC is n + Type (impurity density is, for example, approximately 1 × 10⁻⁶) 18 cm -3 ~Approx. 1×10 21 cm -3 The SiC epitaxial growth layer 12E is doped with n - Type (impurity density is, for example, approximately 5 × 10 14 cm -3 ~Approx. 5×10 16 cm -3 The SiC single crystal layer 13I is doped with a higher concentration of ) than the SiC epitaxial growth layer 12E.

[0089] Furthermore, the SiC epitaxial growth layer 12E may have one of the following crystal structures: 4H-SiC, 6H-SiC, or 2H-SiC.

[0090] Examples of n-type doping impurities that can be applied include N (nitrogen), P (phosphorus), and As (arsenic).

[0091] Examples of p-type doping impurities that can be applied include B (boron), Al (aluminum), and TMA.

[0092] The back surface ((000-1)C plane) of the SiC polycrystalline growth layer 18PC is provided with a cathode electrode 22 that covers its entire surface, and the cathode electrode 22 is connected to the cathode terminal K.

[0093] Furthermore, the surface 100 of the SiC epitaxial growth layer 12 (for example, the (0001)Si surface) is provided with contact holes 24 that expose a portion of the SiC epitaxial growth layer 12E as an active region 23, and a field insulating film 26 is formed in the field region 25 surrounding the active region 23.

[0094] The field insulating film 26 is made of SiO2 (silicon oxide), but may be made of other insulating materials such as silicon nitride (SiN). An anode electrode 27 is formed on this field insulating film 26, and the anode electrode 27 is connected to the anode terminal A.

[0095] A p-type JTE (Junction Termination Extension) structure 28 is formed near the surface 100 (surface layer) of the SiC epitaxial growth layer 12, in contact with the anode electrode 27. The JTE structure 28 is formed along the contour of the contact hole 24, spanning both the inside and outside of the contact hole 24 of the field insulating film 26.

[0096] (SiC-TMOSFET) As a semiconductor device fabricated using the semiconductor substrate according to the embodiment, the trench gate type MOSFET 31 comprises a semiconductor substrate 1 consisting of a SiC polycrystalline growth layer 18PC and a SiC epitaxial growth layer 12E, as shown in Figure 13. A SiC single crystal layer 13I may be interposed between the SiC polycrystalline growth layer 18PC and the SiC epitaxial growth layer 12E. Here, the SiC single crystal layer 13I suppresses the expansion of the depletion layer within the SiC epitaxial growth layer 12E and facilitates the formation of ohmic contact with the SiC polycrystalline growth layer 18PC formed on the C-plane of the SiC epitaxial growth layer 12E. The SiC epitaxial growth layer 12E acts as a drift layer, the SiC single crystal layer 13I as a buffer layer, and the SiC polycrystalline growth layer 18PC as a substrate layer.

[0097] The SiC polycrystalline growth layer 18PC is n + Type (impurity density is, for example, approximately 1 × 10⁻⁶) 18 cm -3 ~Approx. 1×10 21 cm -3 The SiC epitaxial growth layer 12E is doped with n - Type (impurity density is, for example, approximately 5 × 10 14 cm -3 ~Approx. 5×10 16 cm -3The SiC single crystal layer 13I is doped with a higher concentration of ) than the SiC epitaxial growth layer 12E.

[0098] Furthermore, the SiC epitaxial growth layer 12E may have one of the following crystal structures: 4H-SiC, 6H-SiC, or 2H-SiC.

[0099] Examples of n-type doping impurities that can be applied include N (nitrogen), P (phosphorus), and As (arsenic).

[0100] Examples of p-type doping impurities that can be applied include B (boron), Al (aluminum), and TMA.

[0101] The back surface ((000-1)C plane) of the SiC polycrystalline growth layer 18PC is provided with a drain electrode 32 that covers its entire surface, and the drain electrode 32 is connected to the drain terminal D.

[0102] Near the surface 100 ((0001)Si plane) of the SiC epitaxial growth layer 12E (surface layer), there are p-type impurities (impurity density is, for example, about 1 × 10⁻⁶). 16 cm -3 ~Approx. 1×10 19 cm -3 A body region 33 is formed. In the SiC epitaxial growth layer 12E, the portion on the SiC polycrystalline growth layer 18PC side relative to the body region 33 remains in the state of the SiC epitaxial growth layer RE, n - This is the drain region 34 (12E) of type [type].

[0103] A gate trench 35 is formed in the SiC epitaxial growth layer 12E. The gate trench 35 penetrates the body region 33 from the surface 100 of the SiC epitaxial growth layer 12E, and its deepest part reaches the drain region 34 (12E).

[0104] A gate insulating film 36 is formed on the inner surface of the gate trench 35 and on the surface 100 of the SiC epitaxial growth layer 12E, covering the entire inner surface of the gate trench 35. A gate electrode 37 is embedded in the gate trench 35 by filling the inside of the gate insulating film 36 with, for example, polysilicon. A gate terminal G is connected to the gate electrode 37.

[0105] The surface layer of the body region 33 forms part of the side surface of the gate trench 35 n + A source region 38 of type 38 is formed.

[0106] Furthermore, the SiC epitaxial growth layer 12 has p that penetrates from its surface 100 through the source region 38 and is connected to the body region 33. + Type (impurity density is, for example, approximately 1 × 10⁻⁶) 18 cm -3 ~Approx. 1×10 21 cm -3 A body contact area 39 is formed.

[0107] An interlayer insulating film 40 made of SiO2 is formed on the SiC epitaxial growth layer 12E. The source electrode 42 is connected to the source region 38 and the body contact region 39 via a contact hole 41 formed in the interlayer insulating film 40. A source terminal S is connected to the source electrode 42.

[0108] By generating a predetermined potential difference between the source electrode 42 and the drain electrode 32 (source-drain), and applying a predetermined voltage (a voltage equal to or greater than the gate threshold voltage) to the gate electrode 37, a channel can be formed near the interface between the gate insulating film 36 and the body region 33 by the electric field from the gate electrode 37. This allows current to flow between the source electrode 42 and the drain electrode 32, thereby turning on the SiC-TMOSFET 31.

[0109] (SiC planar gate type MOSFET) As a semiconductor device fabricated using the semiconductor substrate 1 according to the embodiment, the planar gate type MOSFET 51 comprises a semiconductor substrate 1 consisting of a SiC polycrystalline growth layer 18PC and a SiC epitaxial growth layer 12E, as shown in Figure 14. A SiC single crystal layer 13I may be interposed between the SiC polycrystalline growth layer 18PC and the SiC epitaxial growth layer 12E. Here, the SiC single crystal layer 13I suppresses the expansion of the depletion layer within the SiC epitaxial growth layer 12E and facilitates the formation of ohmic contact with the SiC polycrystalline growth layer 18PC formed on the C-plane of the SiC epitaxial growth layer 12E. The SiC epitaxial growth layer 12E acts as a drift layer, the SiC single crystal layer 13I as a buffer layer, and the SiC polycrystalline growth layer 18PC as a substrate layer.

[0110] The SiC polycrystalline growth layer 18PC is n + Type (impurity density is, for example, approximately 1 × 10⁻⁶) 18 cm -3 ~Approx. 1×10 21 cm -3 The SiC epitaxial growth layer 12 is doped with n - Type (impurity density is, for example, approximately 5 × 10 14 cm -3 ~Approx. 5×10 16 cm -3 ) is doped.

[0111] Furthermore, the SiC epitaxial growth layer 12 may have one of the following crystal structures: 4H-SiC, 6H-SiC, or 2H-SiC.

[0112] Examples of n-type doping impurities that can be applied include N (nitrogen), P (phosphorus), and As (arsenic).

[0113] Examples of p-type doping impurities that can be applied include B (boron), Al (aluminum), and TMA.

[0114] A drain electrode 52 is formed on the back surface ((000-1)C plane) of the SiC single crystal substrate 10SB, covering the entire surface, and a drain terminal D is connected to the drain electrode 52.

[0115] Near the surface 100 ((0001)Si plane) of the SiC epitaxial growth layer 12E (surface layer), there are p-type impurities (impurity density is, for example, about 1 × 10⁻⁶). 16 cm -3 ~Approx. 1×10 19 cm -3 The body region 53 of the SiC epitaxial growth layer 12E is formed in a well shape. The portion of the body region 53 on the SiC single crystal substrate 10SB side is maintained in the state after epitaxial growth, n - This is the drain region 54(12E) of type [type].

[0116] The surface layer of body region 53 is n + The source region 55 of the type is formed with a gap between it and the periphery of the body region 53.

[0117] Inside source region 55, p + Type (impurity density is, for example, approximately 1 × 10⁻⁶) 18 cm -3 ~Approx. 1×10 21 cm -3 A body contact region 56 is formed. The body contact region 56 penetrates the source region 55 in the depth direction and is connected to the body region 53.

[0118] A gate insulating film 57 is formed on the surface 100 of the SiC epitaxial growth layer 12E. The gate insulating film 57 covers the portion of the body region 53 that surrounds the source region 55 (the peripheral edge of the body region 53) and the outer edge of the source region 55.

[0119] A gate electrode 58, for example made of polysilicon, is formed on the gate insulating film 57. The gate electrode 58 faces the peripheral edge of the body region 53, with the gate insulating film 57 in between. The gate terminal G is connected to the gate electrode 58.

[0120] An interlayer insulating film 59 made of SiO2 is formed on the SiC epitaxial growth layer 12E. A source electrode 61 is connected to a source region 55 and a body contact region 56 via a contact hole 60 formed in the interlayer insulating film 59. A source terminal S is connected to the source electrode 61.

[0121] By generating a predetermined potential difference between the source electrode 61 and the drain electrode 52 (source-drain), and applying a predetermined voltage (a voltage equal to or greater than the gate threshold voltage) to the gate electrode 58, a channel can be formed near the interface between the gate insulating film 57 and the body region 53 by the electric field from the gate electrode 58. This allows current to flow between the source electrode 61 and the drain electrode 52, thereby turning on the planar gate type MOSFET 51.

[0122] Although this embodiment has been described above, it can also be implemented in other forms.

[0123] Furthermore, although not shown in the illustration, a MOS capacitor can also be manufactured using the semiconductor substrate 1 according to the embodiment. In MOS capacitors, yield and reliability can be improved.

[0124] Although not shown in the figures, bipolar transistors can also be manufactured using the semiconductor substrate 1 according to this embodiment. In addition, the semiconductor substrate 1 according to this embodiment can also be used to manufacture SiC-pn diodes, SiC IGBTs, SiC complementary MOSFETs, and the like. Furthermore, the semiconductor substrate 1 of this embodiment can be applied to other types of devices such as LEDs (light emitting diodes) and semiconductor optical amplifiers (SOAs).

[0125] (crystal planes) Figures 15A and 15B illustrate the crystal planes of SiC. The plan view in Figure 15A shows the Si plane 211 of a SiC wafer 200 on which a primary orientation flat 201 and a secondary orientation flat 202 have been formed. In the side view of Figure 15B, viewed from the [-1100] orientation, a Si plane 211 with the

[0001] orientation is formed on the upper surface, and a C plane 212 with the [000-1] orientation is formed on the lower surface.

[0126] As shown in Figure 16, the schematic bird's-eye view of the semiconductor substrate (wafer) 1 according to this embodiment includes a SiC polycrystalline growth layer 18PC and a SiC epitaxial growth layer 12E.

[0127] The thickness of the SiC polycrystalline growth layer 18PC is, for example, approximately 200 μm to approximately 500 μm, and the thickness of the SiC epitaxial growth layer 12E is, for example, approximately 4 μm to approximately 100 μm.

[0128] (Example of crystal structure) A schematic bird's-eye view of a unit cell of a 4H-SiC crystal applicable to the SiC epitaxial growth layer 12E is shown in Figure 17A, a schematic configuration of the two-layer portion of the 4H-SiC crystal is shown in Figure 17B, and a schematic configuration of the four-layer portion of the 4H-SiC crystal is shown in Figure 17C.

[0129] Furthermore, the schematic configuration of the unit cell of the 4H-SiC crystal structure shown in Figure 17A, viewed from directly above the (0001) plane, is represented as shown in Figure 18.

[0130] As shown in Figures 17A to 17C, the crystal structure of 4H-SiC can be approximated as a hexagonal system, with four carbon atoms bonded to one silicon atom. The four carbon atoms are located at the four vertices of a regular tetrahedron with the silicon atom at the center. Of these four carbon atoms, one silicon atom is positioned along the

[0001] axis relative to the carbon atom, and the other three carbon atoms are positioned along the [000-1] axis relative to the silicon atom. In Figure 17A, the off-angle θ is, for example, about 4 degrees or less.

[0131] The

[0001] axis and the [000-1] axis are aligned along the axial direction of the hexagonal prism, and the surface normalized to the

[0001] axis (the top surface of the hexagonal prism) is the (0001) surface (Si surface). On the other hand, the surface normalized to the [000-1] axis (the bottom surface of the hexagonal prism) is the (000-1) surface (C surface).

[0132] Furthermore, the directions perpendicular to the

[0001] axis and passing through non-adjacent vertices of the hexagonal prism when viewed from directly above the (0001) plane are the a1 axis [2-1-10], the a2 axis [-12-10], and the a3 axis [-1-120], respectively.

[0133] As shown in Figure 18, the direction passing through the vertex between the a1 axis and the a2 axis is the [11-20] axis, the direction passing through the vertex between the a2 axis and the a3 axis is the [-2110] axis, and the direction passing through the vertex between the a3 axis and the a1 axis is the [1-210] axis.

[0134] Between each of the six axes passing through each vertex of the hexagonal prism, the axes that are inclined at an angle of 30° with respect to each axis on either side, and that serve as the normals to each side of the hexagonal prism, are, in clockwise order from the space between the a1 axis and the [11-20] axis, the [10-10] axis, the [1-100] axis, the [0-110] axis, the [-1010] axis, the [-1100] axis, and the [01-10] axis. Each face (side of the hexagonal prism) normalized to these axes is a crystal plane perpendicular to the (0001) plane and the (000-1) plane.

[0135] The epitaxial growth layer 12E may comprise at least one or more types selected from the group consisting of group IV element semiconductors, group III-V compound semiconductors, and group II-VI compound semiconductors.

[0136] Furthermore, the SiC single crystal substrate 10SB and the SiC epitaxial growth layer 12E may be composed of any of the following materials: 4H-SiC, 6H-SiC, or 2H-SiC.

[0137] Furthermore, the SiC single crystal substrate 10SB and the SiC epitaxial growth layer 12E may also comprise at least one material other than SiC, selected from the group consisting of GaN, BN, AlN, Al2O3, Ga2O3, diamond, carbon, and graphite.

[0138] The semiconductor device comprising the semiconductor substrate according to the embodiment may include, in addition to SiC-based, GaN-based, AlN-based, or gallium oxide-based IGBTs, diodes, MOSFETs, or thyristors.

[0139] A semiconductor device comprising a semiconductor substrate according to an embodiment may have any of the following configurations: a one-in-one module, a two-in-one module, a four-in-one module, a six-in-one module, a seven-in-one module, an eight-in-one module, a twelve-in-one module, or a fourteen-in-one module.

[0140] According to the semiconductor substrate of the embodiment, instead of a high-cost SiC single-crystal substrate, for example, a low-cost SiC polycrystalline growth layer can be used as the substrate material.

[0141] [Other embodiments] As described above, several embodiments have been described, but the statements and drawings that constitute part of the disclosure are illustrative and should not be understood as limiting. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0142] Thus, this embodiment includes various other embodiments not described herein. [Industrial applicability]

[0143] The semiconductor substrate of this embodiment and the semiconductor device equipped with this semiconductor substrate can be used in various semiconductor module technologies such as IGBT modules, diode modules, and MOS modules (SiC, GaN, AlN, gallium oxide), and can be applied to a wide range of application fields, such as power modules for inverter circuits that drive electric motors used as power sources for electric vehicles (including hybrid vehicles), trains, and industrial robots, and power modules for inverter circuits that convert electricity generated by solar cells, wind turbines, and other power generation devices (especially private power generation devices) into electricity from the commercial power supply. [Explanation of symbols]

[0144] 1…Semiconductor substrate, 10SB…SiC single crystal substrate, 10HI…Hydrogen ion implantation layer, 10HE…Single crystal SiC thinning layer, 10PI…Phosphorus ion implantation layer, 12E…SiC epitaxial growth layer, 13I…SiC single crystal layer, 18PC…SiC polycrystalline growth layer, 19GS…Graphite substrate, 20CT…Carbon tray, 21…Semiconductor device (SiC-SBD), 22…Cathode electrode, 23…Active region, 24…Contact hole, 25…Field region, 26…Field insulating film, 27…Anode electrode, 28…JTE structure, 31…Semiconductor device (SiC-TMOSFET), 32, 52…Drain electrode, 33, 53 ...Body region, 34, 54...Drain region, 35...Gate trench, 36, 57...Gate insulating film, 37, 58...Gate electrode, 38, 55...Source region, 39, 56...Body contact region, 40, 59...Interlayer insulating film, 41, 60...Contact hole, 42, 61...Source electrode, 51...Semiconductor device (SiC-MOSFET), 100...Surface of SiC epitaxial growth layer, 200...SiC wafer, 201...Primary orientation flat, 202...Secondary orientation flat, 211, [S]...Si plane, 212, [C]...C plane, S...Source terminal, D...Drain terminal, G...Gate terminal, A...Anode terminal, K...Cathode terminal

Claims

1. A hexagonal SiC single crystal layer, A SiC epitaxial growth layer is disposed on the Si surface of the SiC single crystal layer, A SiC polycrystalline growth layer is disposed on the C plane facing the Si plane of the SiC single crystal layer. Equipped with, The SiC single crystal layer comprises a thinned single crystal SiC layer. The thinned single-crystal SiC layer comprises a first ion implantation layer, The aforementioned SiC single crystal layer comprises a second ion implantation layer, The SiC polycrystalline growth layer has an impurity density of 1 × 10 18 cm -3 ~1 x 10 21 cm -3 He is doped. Semiconductor substrate.

2. The semiconductor substrate according to claim 1, wherein the first ion implantation layer comprises a hydrogen ion implantation layer.

3. The semiconductor substrate according to claim 2, wherein the thinned single-crystal SiC layer comprises an embrittlement layer of the hydrogen ion implanted layer.

4. The semiconductor substrate according to claim 1, wherein the second ion implantation layer is disposed between the first ion implantation layer and the SiC polycrystalline growth layer.

5. The semiconductor substrate according to claim 1 or 4, wherein the second ion implantation layer comprises a phosphorus ion implantation layer.

6. The semiconductor substrate according to any one of claims 1 to 5, wherein the Si plane of the SiC single crystal layer is a plane in the [0001] orientation of 4H-SiC, and the C plane of the SiC single crystal layer facing the Si plane is a plane in the [000-1] orientation of 4H-SiC.

7. The semiconductor substrate according to any one of claims 1 to 6, wherein the SiC single crystal layer is reusable by peeling it off from the SiC epitaxial growth layer.

8. A semiconductor device comprising a semiconductor substrate according to any one of claims 1 to 7.

9. The semiconductor device according to claim 8, wherein the semiconductor device comprises at least one or more types selected from the group consisting of a SiC Schottky barrier diode, a SiC MOSFET, a SiC bipolar transistor, a SiC diode, a SiC thyristor, and a SiC insulated gate bipolar transistor.

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