Memory device

Abstract

To provide highly reliable storage devices. [Solution] On the side surface of the first conductor extending in the first direction, as viewed from the first conductor side, a first insulating The body, first semiconductor, second insulator, second semiconductor, and third insulator are arranged in that order. The electric body is connected via a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator. The first region overlapping with the second conductor, the first insulator, the first semiconductor, the second insulator, the second semiconductor, A second region is provided that overlaps with the third conductor via the third insulator. In the second region, the first A fourth conductor is placed between the insulator and the first semiconductor.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0003] Note that in this specification and the like, the semiconductor device generally refers to anything that can function by utilizing semiconductor characteristics. Therefore, semiconductor elements such as transistors and diodes, and circuits including semiconductor elements are semiconductor devices. In addition, display devices, light-emitting devices, lighting devices, electro-optical devices, memory devices, imaging devices, communication devices, and electronic devices may include semiconductor elements or semiconductor circuits

Background Art

[0004] In recent years, with the increase in the amount of data to be handled, semiconductor devices having a larger storage capacity have been demanded. In order to increase the storage capacity per unit area, it is effective to stack memory cells to form them (see Patent Document 1 and Patent Document 2). By stacking memory cells, the storage capacity per unit area can be increased according to the number of stacked memory cells In Patent Documents 3 and Patent Documents 4, memory devices using oxide semiconductors are disclosed. In Patent Document 5, a semiconductor memory using an oxide semiconductor as a charge storage layer is disclosed is present.

[0005] In addition, in Non-Patent Document 1, CAAC-IGZO is disclosed as a crystalline oxide semiconductor. is present. Also, in Non-Patent Document 1, the growth mechanism of CAAC-IGZO and the like are also disclosed. is present.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Non-Patent Documents

[0007]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] In Patent Document 1 and Patent Document 2, a plurality of memory elements (also referred to as memory cells) are stacked, and by connecting these in series, a memory cell array having a three-dimensional structure (memristor array) is formed. It forms a ring (also called a ring).

[0009] In Patent Document 1, a columnar semiconductor is in contact with an insulator having a charge storage layer. In Patent Document 2, a columnar semiconductor functions as a tunnel dielectric. It is in contact with an insulator. Both Patent Document 1 and Patent Document 2 describe the writing of information to a memory cell. The process is carried out by extracting and injecting charge through an insulator. Trap centers can form at the interface where semiconductors and insulators come into contact. Centers can capture electrons and alter the threshold voltage of a transistor. This could negatively impact the reliability of the storage device.

[0010] One embodiment of the present invention aims to provide a highly reliable storage device. One of the objectives of this invention is to provide a storage device with a large memory capacity. One of the objectives of this invention is to provide a memory device that occupies a small area. One of the objectives of this invention is to provide a memory device with low manufacturing costs. One aspect of this invention is to provide a highly reliable semiconductor device. One form of this invention aims to provide semiconductor devices with low manufacturing costs. One of the objectives of this invention is to provide a novel semiconductor device.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. The embodiment does not need to solve all of these problems. Other problems are addressed in the specification. This will become clear from the description in the drawings, claims, etc., and the specification, drawings, claims Based on these descriptions, it is possible to identify other issues besides those mentioned above. [Means for solving the problem]

[0012] One aspect of the present invention is a first conductor extending in a first direction, on the side surface of which, when viewed from the first conductor side, An insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in that order. This is a semiconductor device. It consists of a first conductor, a first insulator, a first semiconductor, a second insulator, and a second semiconductor. , and a first region overlapping with the second conductor via a third insulator, and the first insulator, first semiconductor, It has a second region that overlaps with the third conductor via a second insulator, a second semiconductor, and a third insulator. In the second region, a fourth conductor is present between the first insulator and the first semiconductor.

[0013] Another aspect of the present invention is a first conductor, a second conductor, a third conductor, a fourth conductor, and It comprises an insulator, a second insulator, a third insulator, a first semiconductor, and a second semiconductor, and the first The conductor extends in a first direction, and on the side surface of the first conductor extending in the first direction, the first insulator The first semiconductor is provided adjacent to the first insulator, and the second insulator is provided adjacent to the first semiconductor. The edge is provided adjacent to the first semiconductor, and the second semiconductor is provided adjacent to the second insulator, 3. The insulator is provided adjacent to the second semiconductor, and the first conductor has a first region and a second region. In the first region, the second conductor is provided adjacent to the third insulator, and in the second region The third conductor is provided adjacent to the third insulator, and in the second region, the fourth conductor is the first This is a memory device placed between an insulator and a first semiconductor.

[0014] In the first region, there is a first insulator, a second insulator, a third insulator, a first semiconductor, and a second semiconductor. It is preferable that each of the body is arranged in a concentric circle. In the second region, the first insulation Each of the body, second insulator, third insulator, first semiconductor, second semiconductor, and fourth conductor is It is preferable that they be arranged in concentric circles.

[0015] Furthermore, the first region can function as the first transistor. Also, the second region can function as the second transistor. It can function as a t. The first semiconductor is preferably an oxide semiconductor. The second semiconductor is an acid It is preferable that it be a synthetic semiconductor.

[0016] Another aspect of the present invention is a first conductor extending in a first direction and a second conductor extending in a second direction A body, a third conductor extending in a second direction, a fourth conductor, a first insulator, a second insulator, It has a third insulator, a first semiconductor, and a second semiconductor, and the first conductor and the second conductor intersect. At the first intersection and at the second intersection where the first conductor and the third conductor intersect, The first insulator overlaps with the first conductor, the first semiconductor overlaps with the first insulator, and the second insulator overlaps with the first semiconductor. The conductor overlaps, the second semiconductor overlaps with the second insulator, the third insulator overlaps with the second semiconductor, and At the intersection, the first semiconductor is a memory device that overlaps with the first insulator via the fourth conductor. ru.

[0017] At the first intersection, the first insulator, the second insulator, the third insulator, the first semiconductor, and the second semiconductor It is preferable that each of the conductors is arranged in a concentric circle. At the second intersection, the first Each of the insulator, second insulator, third insulator, first semiconductor, second semiconductor, and fourth conductor It is preferable that these are arranged in a concentric circle pattern.

[0018] Furthermore, the first intersection can function as the first transistor. Also, the second intersection can function as the second transistor. It can function as a ZISTA. [Effects of the Invention]

[0019] One embodiment of the present invention can provide a highly reliable storage device. In one embodiment, a storage device with a large memory capacity can be provided. This makes it possible to provide a storage device with a small footprint. Furthermore, according to one embodiment of the present invention, It is possible to provide a memory device with low manufacturing costs. Furthermore, according to one embodiment of the present invention, reliability High-performance semiconductor devices can be provided. Furthermore, according to one embodiment of the present invention, manufacturing costs can be reduced. It is possible to provide semiconductor devices with low noise. Furthermore, according to one embodiment of the present invention, a novel semiconductor device can be provided. We can provide the device.

[0020] Furthermore, the description of these effects does not preclude the existence of other effects. The embodiment does not need to have all of these effects. Other effects are described in the specification. This will become clear from the descriptions in the drawings and claims, and the specification, drawings, and claims will be clear from the description, drawings, and claims. It is possible to extract other effects from any of these descriptions. [Brief explanation of the drawing]

[0021] [Figure 1] Figure 1 is a perspective view of the storage device. [Figure 2] Figure 2 is a cross-sectional view of the memory device. [Figure 3] Figure 3 is a cross-sectional view of a memory string. [Figure 4] Figure 4 is a cross-sectional view of a memory string. [Figure 5] Figures 5A and 5B are cross-sectional views of the memory string. [Figure 6] Figures 6A and 6B are cross-sectional views of the memory string. [Figure 7] Figure 7A is a cross-sectional view of the memory element. Figure 7B is a perspective cross-sectional view of the memory element. [Figure 8] Figures 8A and 8B are cross-sectional views of the memory string. [Figure 9] Figures 9A to 9F are cross-sectional views of a memory string. [Figure 10] Figures 10A and 10B are cross-sectional views of the memory string. [Figure 11] Figure 11A illustrates the classification of IGZO crystal structures. Figure 11B illustrates the XRD spectrum of a CAAC-IGZO film. Figure 11C illustrates the micro-electron diffraction pattern of a CAAC-IGZO film. [Figure 12] Figures 12A to 12C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 13] Figures 13A to 13C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 14] Figures 14A to 14C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 15] Figures 15A to 15C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 16] Figures 16A to 16C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 17] Figures 17A to 17C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 18] Figures 18A to 18C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 19] Figures 19A to 19D are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 20] Figures 20A to 20C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 21]Figures 21A to 21C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 22] Figures 22A to 22C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 23] Figures 23A to 23C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 24] Figures 24A to 24C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 25] Figures 25A to 25C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 26] Figures 26A to 26C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 27] Figures 27A to 27C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 28] Figures 28A to 28C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 29] Figure 29 is a perspective view of the storage device. [Figure 30] Figure 30 is a cross-sectional view of the memory device. [Figure 31] Figure 31 is a cross-sectional view of a memory string. [Figure 32] Figures 32A to 32C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 33] Figures 33A to 33C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 34] Figures 34A to 34C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 35] Figures 35A to 35C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 36]Figures 36A to 36C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 37] Figures 37A to 37C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 38] Figures 38A to 38C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 39] Figures 39A to 39C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 40] Figures 40A to 40C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 41] Figures 41A to 41C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 42] Figures 42A to 42C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 43] Figures 43A to 43D are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 44] Figures 44A to 44C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 45] Figures 45A to 45C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 46] Figures 46A to 46C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 47] Figures 47A to 47C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 48] Figures 48A to 48C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 49] Figures 49A to 49C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 50]Figures 50A to 50C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 51] Figure 51 is a diagram illustrating an example of the configuration of an MOCVD apparatus. [Figure 52] Figure 52A is a schematic diagram of a multi-chamber type film deposition apparatus. Figure 52B is a cross-sectional view of the film deposition chamber. [Figure 53] Figure 53 illustrates an example of a memory string circuit configuration. [Figure 54] Figure 54 is an equivalent circuit diagram of the memory element MC. [Figure 55] Figure 55 illustrates an example of a memory string circuit configuration. [Figure 56] Figure 56 illustrates an example of a memory string circuit configuration. [Figure 57] Figure 57 illustrates an example of a memory string circuit configuration. [Figure 58] Figure 58 is a timing chart illustrating an example of a memory string write operation. [Figure 59] Figures 59A and 59B are circuit diagrams illustrating an example of memory string writing operation. [Figure 60] Figures 60A and 60B are circuit diagrams illustrating an example of memory string writing operation. [Figure 61] Figures 61A and 61B are circuit diagrams illustrating an example of memory string writing operation. [Figure 62] Figures 62A and 62B are circuit diagrams illustrating an example of memory string writing operation. [Figure 63] Figures 63A and 63B are timing charts illustrating an example of a memory string read operation. [Figure 64] Figures 64A and 64B are circuit diagrams illustrating an example of memory string read operation. [Figure 65] Figures 65A and 65B are circuit diagrams illustrating an example of memory string read operation. [Figure 66]Figures 66A and 66B illustrate the Id-Vg characteristics of a transistor. [Figure 67] Figure 67 illustrates an example of a memory string circuit configuration. [Figure 68] Figure 68 is a timing chart illustrating an example of a memory string write operation. [Figure 69] Figure 69 is a timing chart illustrating an example of a memory string read operation. [Figure 70] Figure 70 illustrates an example of a memory string circuit configuration. [Figure 71] Figure 71 illustrates an example of a memory string circuit configuration. [Figure 72] Figure 72 is a block diagram illustrating an example of a semiconductor device configuration. [Figure 73] Figures 73A to 73C are perspective views illustrating an example of a semiconductor device configuration. [Figure 74] Figure 74 is a cross-sectional view illustrating a semiconductor device according to one aspect of the present invention. [Figure 75] Figure 75 is a cross-sectional view illustrating a semiconductor device according to one aspect of the present invention. [Figure 76] Figure 76A is a schematic diagram of a semiconductor device. Figure 76B is a perspective view of the semiconductor device. [Figure 77] Figures 77A to 77E illustrate an example of a storage device. [Figure 78] Figures 78A to 78G are diagrams illustrating an example of an electronic device. [Modes for carrying out the invention]

[0022] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, its form and details may be changed in various ways. Those skilled in the art will readily understand that further modifications are possible. Therefore, the present invention can be implemented in the following forms. The interpretation is not limited to the description of the state. Furthermore, the structure of the invention described below... Furthermore, the same reference numeral is used across different drawings for parts that are identical or have similar functions. We will use it and omit the repetition of its explanation.

[0023] Furthermore, the position, size, and scope of each component shown in the drawings, etc., are intended to facilitate understanding of the invention. Therefore, it may not represent the actual location, size, or range. For this reason, disclosure is required. The invention is not necessarily limited to the location, size, scope, etc. disclosed in the drawings, etc. For example. In the actual manufacturing process, the resist mask may be unintentionally damaged by processes such as etching. While there may be some reduction in value, this is sometimes not reflected in the diagram for the sake of clarity.

[0024] Furthermore, in order to make the explanations easier to understand, some components are omitted from the drawings and other diagrams. It may happen.

[0025] Furthermore, in this specification, the terms "electrode" and "wiring" do not limit the functionality of these components. It is not fixed. For example, "electrode" can be used as part of "wiring". The reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes" and "wiring". This also includes cases where the "lines" are formed as a single unit.

[0026] Furthermore, in this specification, etc., "terminal" in an electrical circuit means an input or output of current, This refers to the part where pressure is input or output, or where signals are received or transmitted. In some cases, a portion of the wiring or electrodes may function as a terminal.

[0027] In this specification, the terms "above" and "below" refer to the relative positions of the constituent elements, specifically whether they are directly above or below. It is not limited to being below and in direct contact. For example, "electrode on insulating layer A" If the expression is "B", then it is not necessary for electrode B to be formed in direct contact with insulating layer A. Cases containing other components between marginal layer A and electrode B are not excluded.

[0028] Furthermore, the source and drain functions may differ when using transistors with different polarities, or when rotating In circuit operation, the direction of the current changes, and depending on the operating conditions, they can be swapped. Therefore, it is difficult to determine which is the source and which is the drain. In this specification, the terms source and drain may be used interchangeably. Let's assume that.

[0029] Furthermore, in this specification, "electrically connected" refers to both a direct connection and a "some kind of connection". This includes cases where it is connected via "something that has an electrical effect". "A device having an electrical function" is one that enables the exchange of electrical signals between connected objects. If so, there are no particular restrictions. Therefore, even when it is expressed as "electrically connected", In real-world circuits, there may be no physical connections, only prolonged wiring. .

[0030] Furthermore, in this specification and elsewhere, "parallel" means, for example, two straight lines that are at an angle of -10° or more and 10° or less. This refers to a state where objects are positioned at the following angles. Therefore, it also includes cases where the angle is between -5° and 5°. Furthermore, "perpendicular" and "orthogonal" refer to, for example, two lines that are at an angle of 80° or more but less than or equal to 100°. This refers to a state where objects are arranged at an angle. Therefore, it includes cases where the angle is between 85° and 95°.

[0031] Furthermore, in this specification and other documents, regarding count values ​​and measured values, or count values ​​or measured values, Regarding things, methods, and events that can be converted into quantitative values, the terms "identical," "same," and "equal" are used. Or, when we say "uniform," unless otherwise specified, it means plus or minus 20%. This includes errors.

[0032] Furthermore, in this specification, the terms "adjacent" and "proximity" refer to situations where the constituent elements are directly in contact. This does not limit the possibilities. For example, the expression "electrode B adjacent to insulating layer A" means that the insulating layer It is not necessary for the edge layer A and electrode B to be in direct contact; other structures can be formed between the insulating layer A and electrode B. Items containing constituent elements are not excluded.

[0033] Furthermore, voltage is the potential difference between a certain potential and a reference potential (e.g., ground potential or source potential). This often indicates that. Therefore, voltage and electric potential are often interchangeable. In this specification, unless otherwise specified, voltage and potential may be used interchangeably. It shall be considered as such.

[0034] Furthermore, even when the term "semiconductor" is used, if, for example, its conductivity is sufficiently low, it can be referred to as an "insulator." It possesses the following characteristics. Therefore, it is also possible to use it by replacing "semiconductor" with "insulator". In this case, the boundary between "semiconductors" and "insulators" is ambiguous, and a strict distinction between the two is difficult. Therefore, the terms "semiconductor" and "insulator" as used herein are interchangeable. It may be possible.

[0035] Furthermore, even when the term "semiconductor" is used, if, for example, its conductivity is sufficiently high, it can be referred to as a "conductor." It possesses the following characteristics. Therefore, it is also possible to use it by replacing "semiconductor" with "conductor". In this case, the boundary between "semiconductors" and "conductors" is ambiguous, and a strict distinction between the two is difficult. Therefore, the terms "semiconductor" and "conductor" as used herein are interchangeable. It may be possible.

[0036] Furthermore, in this specification, ordinal numbers such as "the first," "the second," etc., are used to avoid confusion of constituent elements. This is for visual inspection only and does not indicate any order or ranking, such as process order or layering order. Furthermore, even if an ordinal number is not attached to a term in this specification, the confusion of its constituent elements may occur. To avoid this, ordinal numbers may be added to the claims. Also, in this specification, etc. Even if a term is given an ordinal number in the patent claim, if a different ordinal number is used in the patent claim Ordinal numbers may be attached. Also, even if a term is used with an ordinal number in this specification, Ordinal numbers may be omitted in patent claims and other documents.

[0037] In this specification, the "on state" of a transistor refers to the source and This refers to a state where the drain can be considered electrically short-circuited (also called a "conductive state"). Furthermore, the "off state" of a transistor means that the source and drain of the transistor are electrically disconnected. This refers to a state in which a device can be considered to be conducting (also called a "non-conductive state").

[0038] Furthermore, in this specification, "on-current" refers to the current when the transistor is in the ON state and the source is connected to the transistor. It can also refer to the current flowing between the drains. Furthermore, "off-current" refers to the current flowing between the drains of a transistor. It can also refer to the current flowing between the source and drain when the circuit is in a faulty state.

[0039] Furthermore, in this specification, etc., the high power supply potential VDD (hereinafter simply referred to as "VDD", "H potential", etc.) (Also called "H") is the low power supply potential VSS (hereinafter simply referred to as "VSS", "L potential", etc.) It indicates a power supply potential that is higher than VDD (also called "L"). Also, VSS is a power supply potential that is higher than VDD. It also shows a low potential power supply potential. Furthermore, the ground potential (hereinafter simply referred to as "GND") The potential (also called the electric potential) can also be used as VDD or VSS. For example, VDD is grounded. In the case of potential, VSS is at a potential lower than the ground potential, and when VSS is at the ground potential, VDD is at a higher potential than the ground potential.

[0040] Furthermore, the transistors described herein, unless otherwise explicitly stated, are enhancement transistors. Let's assume it's a normally-off type n-channel field-effect transistor. Therefore, its equation is The voltage value (also called "Vth") shall be greater than 0V. Also, unless otherwise specified... Except in cases where, "supplying a high potential to the gate of a transistor" means "to supply a high potential to the gate of a transistor." It can be synonymous with "to turn on." Also, unless explicitly stated, "transition" "Supplying an inductive potential to the gate of a transistor" is synonymous with "turning the transistor off." There are cases where this is the case.

[0041] Furthermore, in this specification, etc., "gate" refers to part or all of the gate electrode and gate wiring. This refers to the gate wiring of at least one transistor and another transistor. This refers to wiring used to electrically connect poles or other wiring.

[0042] Furthermore, in this specification, etc., "source" refers to the source region, source electrode, and source wiring. This refers to part or all of something. The source region is the part of the semiconductor layer whose resistivity is below a certain value. It refers to a region. The source electrode refers to the conductive layer of the part connected to the source region. Source wiring refers to the source electrode of at least one transistor and another electrode or other wiring. This refers to the wiring used to electrically connect two things.

[0043] Furthermore, in this specification, etc., "drain" refers to the drain region, drain electrode, and drain This refers to part or all of the wiring. The drain region is a part of the semiconductor layer with constant resistivity. This refers to the region below a certain value. The drain electrode is the conductive layer of the part connected to the drain region. This refers to the drain wiring, which is the connection between the drain electrode of at least one transistor and another This refers to wiring used to electrically connect electrodes or other wiring.

[0044] Furthermore, in order to make the potential of wiring, electrodes, or conductors easier to understand in drawings and other diagrams, "H" indicates an H potential, or "L" indicates an L potential, adjacent to wiring, electrodes, or conductors. The following may be added: Also, for wiring, electrodes, or conductors where a potential change occurs, “H " or "L" may be enclosed in letters. Also, the transistor is in the off state. In some cases, an "×" symbol may be superimposed on the transistor in question.

[0045] Furthermore, generally speaking, "capacitance" refers to a configuration in which two electrodes face each other with an insulator (dielectric) in between. In this specification, the term "capacitive element" includes the case of the "capacitance" described above. In other words, in this specification, a "capacitive element" refers to a device in which two electrodes face each other across an insulator. Those with a matching configuration, those with a configuration in which two wires face each other with an insulator in between, This includes cases where two wires are arranged with an insulator in between.

[0046] Furthermore, in this specification, when the same reference numeral is used for multiple elements, we will not specifically distinguish them. When necessary, use identifiers such as "_1", "_2", "[n]", "[m,n]" in the code. Sometimes, a symbol is added to indicate the wiring. For example, the second wiring GL may be written as wiring GL[2]. It may be included.

[0047] (Embodiment 1) Figure 1 shows a perspective view of a storage device 100 according to one aspect of the present invention. The storage device 100 is a tertiary storage device. This is a memory device having a stacked structure. Figure 2 shows the area A1-A2 indicated by the dashed line in Figure 1. This is a cross-sectional view. Note that in Figure 1 and other figures, arrows are provided to indicate the X, Y, and Z directions. In some cases, the X, Y, and Z directions are mutually orthogonal. In this specification, one of the X, Y, or Z directions is referred to as the "first direction" or "first It is sometimes called the "first direction." The other one is also called the "second direction" or "second direction." In some cases, the remaining one is referred to as the "third direction" or "third way."

[0048] Figure 2 shows a cross-section in the XZ plane. As mentioned earlier, this is to make the explanation easier to understand. Therefore, in Figures 1 and 2, some of the components may be omitted.

[0049] <Example of storage device configuration> A storage device 100 according to one aspect of the present invention has a memory cell array 110. The array 110 has multiple memory strings 120. The memory strings 120 are arranged in the Z direction. They extend in the direction and are arranged in a matrix on the XY plane.

[0050] Figure 3 shows an example of a cross-sectional configuration of a memory string 120 according to one aspect of the present invention. Ring 120 is a structure in which multiple memory elements MC (also called "memory cells") are connected in series. It has the function. In this embodiment, the case in which five memory elements MC are connected in series is shown. The number of memory elements MC in the memory string 120 is not limited to 5. If n is the number of memory elements MC in the Moristring 120, then n is an integer greater than or equal to 2. Yes.

[0051] Furthermore, the memory string 120 consists of multiple conductors WWL, multiple conductors RWL, and a conductive The memory cell array 110 has a body SG and a conductor WWL, And the conductor SG extends in the X direction. Multiple conductors WWL and multiple conductors RWL are They are arranged in alternating layers with an insulator 123 in between. Conductor SG is made up of multiple conductors WW It is located below L and multiple conductive RWLs.

[0052] In Figure 3, the five memory elements MC are shown as memory element MC[1] to memory element MC[5]. . When explaining matters common to memory elements MC[1] to MC[5], simply It is labeled as "memory element MC". Other components include conductor WWL, conductor RWL, and insulator 123. The same applies to the constituent elements.

[0053] The memory string 120 is electrically connected to the memory element MC[1] by the transistor STr It has 1 and a transistor STr2 that is electrically connected to the memory element MC[5].

[0054] Conductors WWL, RWL, and SG extend beyond the memory cell array 110. It has a region where it is located. In addition, the conductor WWL, conductor RWL, and conductor SG are memory The cells are stacked in a stepped pattern on the outside of the cell array 110 (see Figures 1 and 2).

[0055] Figure 5A shows a cross-section of the area B1-B2, indicated by the dashed line in Figure 3, viewed from the Z direction. Figure 5B shows a cross-section of the area C1-C2, indicated by the dashed line, viewed from the Z direction. Figure 3 shows the area indicated by the dashed line. An enlarged view of the indicated region 105 is shown in Figure 7A. Figure 7A corresponds to a cross-sectional view of the memory element MC. .

[0056] The memory string 120 has a conductor 122 on a substrate 121. For example, an insulator can be used. Alternatively, an insulator 123[1] and a conductor S can be placed on the conductor 122. G, insulator 123[2], conductor RWL[1], insulator 123[3], conductor WWL[1 ], insulator 123[4], conductor RWL[2], insulator 123[5], conductor WWL[2 ], insulator 123[6], conductor RWL[3], insulator 123[7], conductor WWL[3 ], insulator 123[8], conductor RWL[4], insulator 123[9], conductor WWL[4 ], insulator 123

[10] , conductor RWL[5], insulator 123

[11] , conductor WWL [5] and an insulator 123

[12] (see Figure 3).

[0057] Furthermore, the memory string 120 consists of an insulator 123[1], a conductor SG, and an insulator 123[2]. ], conductor RWL[1], insulator 123[3], conductor WWL[1], insulator 123[4 ], conductor RWL[2], insulator 123[5], conductor WWL[2], insulator 123[6 ], conductor RWL[3], insulator 123[7], conductor WWL[3], insulator 123[8 ], conductor RWL[4], insulator 123[9], conductor WWL[4], insulator 123

[0010] , conductor RWL[5], insulator 123

[11] , conductor WWL[5], and insulator It has openings 141 (see Figure 4) which are formed by removing a portion of each of 123

[12] . Figure 4 is This is the same cross-sectional view as in Figure 3. However, to make the cross-sectional shape of the opening 141 easier to recognize, Figure 4 The components to be installed within the opening 141 are shown with dashed lines.

[0058] The opening 141 extends in the Z direction and reaches the conductor 122. Also, in the opening 141, The diameter of region 142 overlapping with the body RWL is larger than the diameter of region 143 overlapping with the conductor WWL. Therefore, the side surface of the opening 141 has an uneven shape.

[0059] Also, along the side of the opening 141, there is an insulator 124, a semiconductor 125, an insulator 126, and A semiconductor 127 is provided. The semiconductor 125 is on the side of the opening 141 via the insulator 124. It has an overlapping region. The insulator 126 has an opening through the semiconductor 125 and the insulator 124. It has a region that overlaps with the side of 141. The semiconductor 127 is an insulator 126, semiconductor 125 and It has a region that overlaps with the side of the opening 141 via the insulator 124. Also, the bottom of the opening 141 In this region, the semiconductor 125 has a region that is electrically connected to the conductor 122.

[0060] Furthermore, the memory string 120 has a conductor 130 that extends in the Z direction. 0 is located at or near the center of the opening 141. Also, the opening 1 of the conductor 130 An insulator 129 is provided in the region overlapping with 41. At the bottom of the opening 141, a conductor 130 is connected to the conductor 1 via the insulator 129, semiconductor 127, insulator 126, and semiconductor 125. It has a region that overlaps with 22. Also, in the region that overlaps with the conductor RWL, semiconductor 127 and A conductor 128 is provided between the insulators 129.

[0061] Between the conductor WWL and the conductor 130, from the conductor WWL side, there is an insulator 124 and a semiconductor 1 25, insulator 126, semiconductor 127, and insulator 129 are provided in that order (see Figure 5A). Between the conductive RWL and the conductor 130, from the conductor RWL side, there is an insulator 124 and a semiconductor 12 5. An insulator 126, a semiconductor 127, a conductor 128, and an insulator 129 are provided in that order. (See Figure 5B).

[0062] Figures 5A and 5B illustrate the cross-section (XY section) of one memory string 120. However, Figures 6A and 6B show an example where multiple memory strings 120 are provided. Multiple memory strings 120 may be arranged side by side along the X-axis, or along the Y-axis. They can be arranged in a row or in a matrix.

[0063] The memory element MC has transistors WTr and RTr (see Figure 7A). The region where the electrolytic body WWL and conductor 130 overlap functions as a transistor WTr. Then, the intersection of conductor WWL and conductor 130 functions as transistor WTr. At the intersection of the body WWL and the conductor 130, the insulator 129 is adjacent to the conductor 130, and the semiconductor Body 127 is adjacent to insulator 129. Also, insulator 126 is adjacent to semiconductor 127, and semiconductor Body 125 is adjacent to insulator 126. Also, insulator 124 is adjacent to semiconductor 125.

[0064] Conductor WWL acts as the gate electrode of transistor WTr, and conductor 130 is the transistor It functions as the back gate electrode of the STR. Also, a part of semiconductor 127 is a transient It functions as a semiconductor layer in which the channel of the transistor WTr is formed. The semiconductor layer on which the flannel is formed consists of an insulator 126, a semiconductor 125, and an insulator 124. It overlaps with the gate electrode (conductor WWL) through a portion of it. Note that in this embodiment, An example is shown where a portion of the conductor WWL functions as a gate electrode, but the gate electrode and conductor Each electrical WWL may be provided independently and electrically connected to it.

[0065] The region where the conductor RWL and conductor 130 overlap functions as the transistor RTr. In other words, the intersection of conductor RWL and conductor 130 functions as transistor RTr. Furthermore, a conductor 128 is provided at the intersection of the conductor RWL and the conductor 130. Similar to the intersection of conductor WWL and conductor 130, at the intersection of conductor RWL and conductor 130 In this case, the insulator 129, semiconductor 127, insulator 126, semiconductor 125, and insulator 1 Each of the 24 has a region that overlaps with each other in the direction perpendicular to the Z direction. However, At the intersection of the electric body RWL and the conductor 130, the conductor 12 is placed between the insulator 129 and the semiconductor 127. The presence of point 8 distinguishes it from the intersection of conductor WWL and conductor 130.

[0066] Conductor 128 functions as the gate electrode of transistor RTr. Also, conductor RWL is It functions as the back gate electrode of transistor RTr. Part of semiconductor 125 is the transistor It functions as a semiconductor layer in which the channel of the transistor RTr is formed. The semiconductor layer on which the channel is formed is connected to the gate electrode (conductor 128) via a portion of the insulator 126. ) overlaps with the semiconductor layer where the channel of transistor RTr is formed is insulator 12 It overlaps with the back gate electrode (conductor RWL) via a portion of 4. Note that in this embodiment, etc. Now, we have shown an example where a part of the conductive RWL functions as a back gate electrode, The gate electrode and the conductor RWL may be provided independently and electrically connected to each other. .

[0067] Furthermore, by dividing the memory string 120 along the Z-axis direction, it can be provided within the opening 141. This is preferable because it allows for an increase in the number of memory cells. Memory string 120 is Z When dividing along the axial direction, the conductive WWL and conductive RWL may also be divided.

[0068] Figure 8A shows the conductive WWL and memory string 120 arranged along the XZ plane. Figure 8B shows how the circuit is separated by the insulator 153, and the conductive RWL and memo The way the list ring 120 is divided by the insulator 153 provided along the XZ plane. Figure 8A is a modified example of the cross-section shown in Figure 5A. Figure 8B is a modified example of Figure 5A. This corresponds to a modified example of the cross-section shown in B. In Figure 8, etc., the end of the reference numeral of the divided components is It is labeled with either a or b.

[0069] As shown in Figure 8A, the region where the conductor WWLa and conductor 130a overlap is the transistor WT It functions as ra. Specifically, conductor WWLa, insulator 124a, semiconductor 125a, Region where insulator 126a, semiconductor 127a, insulator 129a, and conductor 130a overlap. The transistor WTra functions as the gate of the transistor WTra. The conductor WWLa is the gate of the transistor WTra. It functions as a back electrode, and the conductor 130a acts as the back electrode of transistor WTra. It works. Also, a portion of semiconductor 127a forms the channel of transistor WTra. It functions as a semiconductor layer. The semiconductor layer on which the channel of the transistor WTra is formed is Gate electricity via part of insulator 124a, part of semiconductor 125a, and part of insulator 126a It overlaps with the pole (conductor WWLa).

[0070] Furthermore, the region where conductor WWLb and conductor 130b overlap functions as transistor WTrb. Specifically, conductor WWLb, insulator 124b, semiconductor 125b, insulator 126b. The region where semiconductor 127b, insulator 129b, and conductor 130b overlap is a transistor. It functions as a WTrb. The conductor WWLb acts as the gate electrode of the transistor WTrb. The conductor 130b functions as the back gate electrode of transistor WTrb. A portion of semiconductor 127b is used as the semiconductor layer in which the channel of transistor WTrb is formed. It functions as follows: The semiconductor layer in which the channel of transistor WTrb is formed is insulator 124b A portion of the gate electrode (conductor WW) is connected via a part of semiconductor 125b and a part of insulator 126b. It overlaps with Lb.

[0071] As shown in Figure 8B, the region where the conductor RWLa and the conductor 130a overlap is transistor RT It functions as ra. Specifically, RWLa, insulator 124a, semiconductor 125a, insulator 126a, semiconductor 127a, conductor 128a, insulator 129a, and conductor 130a are It functions as a transistor RTra. The conductor RWLa is the gate of transistor RTra. It functions as an electrode. In addition, the conductor 130a is the back gate electrode of transistor RTra. It functions as follows: A portion of semiconductor 125a forms the channel of transistor RTra. It functions as a semiconductor layer. The semiconductor layer on which the channel of transistor RTra is formed is It overlaps with the gate electrode (conductor RWLa) via insulator 124a. Transistor RTra The semiconductor layer in which the channel is formed consists of a part of the insulator 126a, a part of the semiconductor 127a, and a conductive layer. Back gate electrode (conductor 130a) via part of the electrode 128a and part of the insulator 129a ) overlaps with this.

[0072] Furthermore, the region where conductor RWLb and conductor 130b overlap functions as transistor RTrb. Specifically, RWLb, insulator 124b, semiconductor 125b, insulator 126b, semiconductor Body 127b, conductor 128b, insulator 129b, and conductor 130b are in the transistor R It functions as a transistor (TRb). The conductor RWLb acts as the gate electrode of the transistor RTrb. In addition, conductor 130b functions as the back gate electrode of transistor RTrb. A portion of semiconductor 125b is used as the semiconductor layer in which the channel of transistor RTrb is formed. It functions as follows: The semiconductor layer in which the channel of transistor RTrb is formed is insulator 124b It overlaps with the gate electrode (conductor RWLb) via this. The channel of transistor RTrb is shaped The resulting semiconductor layer consists of a portion of the insulator 126b, a portion of the semiconductor 127b, and a portion of the conductor 128b. In part, it overlaps with the back gate electrode (conductor 130b) via a portion of the insulator 129b.

[0073] As described above, the conductor WWL, conductor RWL, and memory string 120 are separated. This allows the number of memory cells provided within the opening 141 to be doubled. The method of partitioning memory string 120 is not limited to the above. In Figures 8A and 8B, String 120 is divided by an insulator 153 that extends in the X-axis direction, as shown in Figure 9A and As shown in Figure 9B, the insulator 153 may be stretched in a direction different from the X-axis direction. Also, Figure 9 As shown in Figures C through 9F, the memory string 120 may be divided into three or more parts. Figure 9C Figure 9D shows an example of a memory string 120 divided into three parts, and Figure 9E shows an example of a memory string 120 divided into three parts. Figure 9F shows an example of a memory string 120 divided into four sections. At this time, the opening The number of memory cells located within 141 can be increased by three or four times, respectively.

[0074] In Figures 9A to 9F, the insulator 153 is the X-axis of the conductor WWL and the conductor RWL. It is preferable to arrange them so as not to obstruct directional conductivity.

[0075] Let me explain back gates here. Gates and back gates are the components of the semiconductor layer. They are arranged to overlap through the flannel formation region. The back gate functions similarly to a gate. It is possible to change the transistor threshold by changing the potential of the back gate. The value voltage can be changed. Either the gate or the back gate is the "first gate". If one is called the "first gate" and the other is called the "second gate" or "second gate" There is.

[0076] The gate and back gate are formed from a conductive layer or a semiconductor layer with low resistivity, To prevent the electric field generated outside the transistor from acting on the semiconductor layer where the channel is formed. It has the function of (especially the electrostatic shielding function against static electricity). That is, it has the function of ( This prevents the electrical characteristics of a transistor from fluctuating due to the influence of an electric field.

[0077] Furthermore, by controlling the potential of the back gate, the threshold voltage of the transistor can be controlled. This is possible. The potential of the back gate may be the same as the gate potential, or it may be the ground potential (GND). It may be an electric potential or any other electric potential.

[0078] The semiconductor layer in which the channels of transistors WTr and RTr are formed is single-layered. Crystalline semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, or amorphous semiconductors, either individually or in combination. They can be used together. Examples of semiconductor materials include silicon and germanium. These can be used. Also, silicon germanium, silicon carbide, gallium arsenide Compound semiconductors such as oxide semiconductors and nitride semiconductors may also be used. Transistor STr The same applies to transistors 1 and STr2.

[0079] Furthermore, the semiconductor layers used in the transistor may be stacked. When stacking semiconductor layers, Semiconductors having different crystalline states may be used, or different semiconductor materials may be used. It's okay to be there.

[0080] Transistor WTr, transistor RTr, transistor STr1, and transistor The semiconductor layer used in STr2 is preferably an oxide semiconductor containing a metal oxide. Transistors using metal oxides as semiconductor layers use amorphous silicon as the semiconductor layer. Compared to the transistor used, a higher field-effect mobility can be obtained. Also, polycrystalline silicon is semi-polycrystalline. In transistors using a conductive layer, there is a risk of grain boundaries forming in the semiconductor layer. This results in carrier capture, a decrease in transistor on-current, a decrease in field-effect mobility, etc. It is highly likely to cause this. On the other hand, as will be explained in more detail later, oxide semiconductors have clear grain boundaries. It is possible to realize a crystal structure in which no grain boundaries are observed, or a crystal structure with extremely few grain boundaries. Using such oxide semiconductors in the semiconductor layer results in high on-current and field-effect transfer. This is preferable because it enables the realization of transistors with good electrical characteristics, such as mobility.

[0081] Furthermore, in oxide semiconductors, especially crystalline oxide semiconductors such as CAAC-IGZO, Nanoclusters of several nanometers (e.g., 1-3 nm) with the c-axis oriented perpendicular to the surface being formed. —It has a distinctive structure in which they are connected to each other. Therefore, even within the opening that extends in the Z direction, This makes it possible to form a crystal structure in which no clear grain boundaries can be identified.

[0082] In particular, the WTr transistor has a semiconductor layer in which the channel is formed that contains a type of metal oxide. It is preferable that it is a transistor using an oxide semiconductor (also called an "OS transistor"). It seems so. Oxide semiconductors have a band gap of 2 eV or more, so the off-current is extremely low. i. When an OS transistor is used for the transistor WTr, the charge written to node ND It can retain data for a long period of time. The transistors that make up the memory element MC are OS transistors. When using this, the memory element MC can be called "OS memory". Memory string 120, which includes child memory cells, can also be called "OS memory." Device 100 can also be called "OS memory".

[0083] OS memory can be written to for more than a year, or even more than 10 years, even if the power supply is cut off. It can retain the information it has collected. Therefore, OS memory can be considered non-volatile memory. It's also possible.

[0084] Furthermore, because the amount of charge written to OS memory does not change easily over a long period of time, OS memory is binary ( It can store not only 1-bit information, but also multi-bit information.

[0085] Furthermore, since OS memory uses a method of writing electric charge to nodes via transistors, conventional This eliminates the need for the high voltage required in flash memory, and also enables high-speed writing operations. Furthermore, the erase operation performed before data rewriting in flash memory is performed in OS memory. It is unnecessary. Also, charge injection and extraction to the floating gate or charge trapping layer. Since this does not occur, the OS memory can perform virtually unlimited data write and read operations. Yes, it is possible. OS memory degrades less and is more reliable compared to conventional flash memory. Sex can be obtained.

[0086] Furthermore, the OS memory is either magnetoresistive memory (MRAM) or resistive random-access memory (ReRAM). ) and so on do not involve structural changes at the atomic level. Therefore, OS memory is magnetoresistive It offers superior rewrite endurance compared to Moly and resistive random-access memory.

[0087] Furthermore, OS transistors exhibit almost no increase in off-current even in high-temperature environments. Specifically, The off-current hardly increases even at ambient temperatures between 20°C and 200°C. However, the on-current does not easily decrease. The storage device, including the OS memory, operates even in high-temperature environments. This provides stability and high reliability. Furthermore, OS transistors have an insulating gap between the source and drain. The edge breakdown voltage is high. By using OS transistors in the transistors that make up the semiconductor device, This enables the creation of semiconductor devices that operate stably and reliably even in high-temperature environments.

[0088] The semiconductor 125 is preferably an n-type semiconductor. Also, the conductive WWL of semiconductor 127. The region overlapping with this is preferably an i-type or substantially i-type semiconductor. In this case, the tra WTr is an enhancement-type (normally-off) transistor. RTr is a depletion-type (normally-on) transistor.

[0089] Furthermore, semiconductors 125 and 127 may have the same material or different materials. It is also possible to do so. For example, semiconductor 125 and semiconductor 127 are each oxide semiconductors. This is also acceptable. Furthermore, semiconductors 125 and 127 are semiconductors having silicon. Alternatively, semiconductor 125 may be an oxide semiconductor, and semiconductor 127 may be a silicon-containing semiconductor. It may also be used as a conductor. Furthermore, semiconductor 125 may be a semiconductor containing silicon, and semiconductor 127 This may be an oxide semiconductor.

[0090] Figure 7B shows a perspective cross-sectional view of the memory element MC. Note that the structure of the memory element MC is explained for clarity. Therefore, the insulator 123 is omitted from Figure 7B.

[0091] Note that Figure 5A corresponds to the XY plane at or near the center of the transistor WTr, and Figure 5 B corresponds to the XY plane at or near the center of transistor RTr. (See Figure 5A and) In Figure 5B, when the cross-sectional shape of the conductor 130 is circular, the insulator 129 is the conductor 13 The semiconductor 127 is arranged concentrically around the outside of the insulator 129. Insulator 126 is provided concentrically outside semiconductor 127, and semiconductor 125 is provided concentrically outside insulator 1 26, and insulator 124 is provided concentrically outside semiconductor 125 and is provided. Conductor 128 is provided concentrically between insulator 129 and semiconductor 127 and is provided.

[0092] In addition, the cross-sectional shape of conductor 130 is not limited to circular. As shown in FIG. 10A, the cross-sectional shape of conductor 130 may be rectangular. Also, as shown in FIG. 10B, the cross-sectional shape of conductor 130 is three angular. Note that FIGS. 10A and 10B correspond to the cross-section of the portion B1-B 2 shown by the dashed-dotted line in FIG. 3 as viewed from the Z direction.

[0093] Note that the memory string 120 can also be referred to as a storage device, and the memory element MC can also be referred to as a storage device.

[0094] 〔Constituent materials of semiconductor device〕 Next, the constituent materials that can be used in the storage device 100 will be described.

[0095] [Substrate] The storage device 100 can be provided on a substrate. As the substrate, for example, an insulator substrate, a semi conductor substrate, or a conductor substrate may be used. As the insulator substrate, for example, a glass substrate , a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria-stabilized zirconia substrate etc.), a resin substrate, etc. are available. As the semiconductor substrate, for example, silicon, germani um-based semiconductor substrates, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide , indium phosphide, zinc oxide, gallium oxide, etc. are available. Furthermore, a semiconductor substrate having an insulating region inside the aforementioned semiconductor substrate, for example, SOI(S Examples include ilicon on insulator substrates. Examples of conductive substrates include graphite. These include substrates, metal substrates, alloy substrates, conductive resin substrates, etc., or substrates containing metallic nitrides. These include substrates, substrates containing metal oxides, and others. Furthermore, conductive or semiconductor materials can be added to insulating substrates. A substrate on which a body is provided, a semiconductor substrate on which a conductor or insulator is provided, a conductive substrate There are substrates on which semiconductors or insulators are provided. Or, elements are provided on these substrates. You may use the following. The elements provided on the substrate include capacitive elements, resistive elements, and switches. Examples include light-emitting elements, light-emitting elements, and memory elements.

[0096] [Insulator] Insulators include insulating oxides, nitrides, oxidized nitrides, nitride oxides, and metal oxides. Examples include metal oxides and nitrides, and metal nitride oxides.

[0097] In this specification, "oxide nitride" refers to a material in which the oxygen content is higher than the nitrogen content. It refers to a silicon material with a higher oxygen content than nitrogen. For example, "silicon oxidnitride" is a silicon material with a higher oxygen content than nitrogen. This indicates that. Furthermore, in this specification, "nitride oxide" refers to a substance with a higher nitrogen content than oxygen content. It refers to a material, and "aluminum nitride oxide" is an aluminum oxide with a higher nitrogen content than oxygen content. This shows the material.

[0098] For example, as transistors become smaller and more integrated, the gate insulator becomes thinner. Problems such as leakage current may occur in the insulator that functions as a gate insulator. By using igh-k material, the physical film thickness can be maintained while lowering the voltage during transistor operation. This becomes possible. On the other hand, the insulator that functions as an interlayer film uses a material with a low dielectric constant. Therefore, parasitic capacitance between wires can be reduced. Thus, depending on the function of the insulator... Then, you should select the materials.

[0099] Furthermore, insulators with high dielectric constants include gallium oxide, hafnium oxide, and zirconium oxide. Aluminium, an oxide containing aluminum and hafnium, an oxide containing aluminum and hafnium Oxidized nitrides, silicon and hafnium oxides, silicon and hafnium Examples include oxide nitrides having [a certain characteristic], or nitrides having silicon and hafnium.

[0100] Furthermore, insulators with low dielectric constants include silicon oxide, silicon oxide nitride, and silicon oxide nitride. Cone, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, carbon Silicon oxide with added elements and nitrogen, porous silicon oxide, or resins, etc. ru.

[0101] Furthermore, OS transistors have the function of suppressing the permeation of impurities such as hydrogen and oxygen. By surrounding it with an insulator, the electrical characteristics of the transistor can be stabilized. Examples of insulators that have the function of suppressing the permeation of impurities and oxygen include boron, Carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, aluminum Gon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, ha An insulator containing phenium or tantalum may be used in a single layer or in a multilayer configuration. It includes an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, such as a(V) oxide. Aluminum, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. Metal oxides such as aluminum nitride, silicon oxynitride, silicon nitride, etc. can be used. It is possible to use.

[0102] In addition, when an oxide semiconductor is used for the semiconductor 125 and / or the semiconductor 127, the insulator that functions as a gate insulator is preferably an insulator having a region containing oxygen that is desorbed by heating. For example, silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating is structured to be in contact with the semiconductor 125 and / or the semiconductor 127, and the oxygen deficiency of the semiconductor 125 and / or the semiconductor 127 can be compensated. .

[0103] [Conductor] As the conductor, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-described metal elements as components, or an alloy combining the above-described metal elements, etc. is preferably used. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. are preferably used. Also, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ​ Nitrides, ruthenium oxide, ruthenium nitride, strontium and ruthenium oxides Oxides containing lanthanum and nickel are conductive materials that are resistant to oxidation, or that absorb oxygen. It is preferable because it is a material that maintains conductivity even when impurity elements such as phosphorus are included. Highly electrically conductive semiconductors such as polycrystalline silicon and nickel silicides. You may also use lecithin.

[0104] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated manner. For example, the gold mentioned above A laminated structure may be formed by combining a material containing a group element with a conductive material containing oxygen. Furthermore, a laminated structure combining the aforementioned metal element-containing material and a nitrogen-containing conductive material. It may also be constructed as follows: a material containing the aforementioned metal element, a conductive material containing oxygen, and nitrogen A laminated structure may be formed by combining a conductive material containing with .

[0105] Furthermore, an oxide semiconductor, a type of metal oxide, is used in the channel formation region of the transistor. In this case, the conductor functioning as a gate electrode contains a material containing the aforementioned metal element, It is preferable to use a laminated structure that combines an oxygen-containing conductive material with [another material]. In this case, It is preferable to provide an oxygen-containing conductive material on the channel formation region side. By providing it on the channel-forming region side, oxygen released from the conductive material can be channeled into the channel-forming region It will become easier to supply to the region.

[0106] In particular, as a conductor that functions as a gate electrode, it is included in the oxide semiconductor in which the channel is formed. It is preferable to use a conductive material containing a metallic element and oxygen. Conductive materials containing metallic elements and nitrogen may be used. For example, titanium nitride, tantalum nitride. Conductive materials containing nitrogen, such as tungsten, may also be used. In addition, indium tin oxide and tungsten oxide may be used. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, and tungsten oxide. Indium oxide containing tungsten, indium tin oxide containing titanium oxide, indium zinc oxide Indium tin oxide with added silicon may also be used. Um gallium zinc oxide may also be used. By using such a material, the channel shape In some cases, hydrogen contained in the oxide semiconductor being formed can be captured. Alternatively, outward In some cases, it is possible to capture hydrogen that has entered from insulators and other materials.

[0107] [Oxide Semiconductors] As semiconductors 125 and 127, metal oxides (oxide semiconductors) that function as semiconductors. It is preferable to use a body. Below, the following applies to semiconductor 125 and semiconductor 127. Let's discuss oxide semiconductors.

[0108] The oxide semiconductor preferably contains at least one of indium or zinc. In particular, Preferably, it contains indium and zinc. In addition, aluminum, gas It is preferable that it contains lium, yttrium, tin, etc. Also, boron, titanium, Iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium One of the following materials is selected from: luminous, hafnium, tantalum, tungsten, magnesium, cobalt, etc. It may contain one or more species.

[0109] Here, the oxide semiconductor is an In-M-Zn oxide having indium, element M, and zinc. Let's consider the case where it is a substance. Note that element M is aluminum, gallium, yttrium, and One or more elements selected from tin. Other elements applicable to element M include: Boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, Cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt There are such cases. However, in some cases, it is acceptable to combine multiple of the aforementioned elements as element M. .

[0110] In this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxi They are sometimes collectively referred to as (de) metal oxides (met It may also be called al oxynitride.

[0111] [Classification of crystal structures] First, we will explain the classification of crystal structures in oxide semiconductors using Figure 11A. Figure 11A shows an oxide semiconductor, typically IGZO (a metal containing In, Ga, and Zn). This is a diagram illustrating the classification of the crystal structure of oxides.

[0112] As shown in Figure 11A, oxide semiconductors can be broadly classified into "Amorphous" It is divided into "Crystalline (crystalline)" and "Crystal (crystal)". They are classified as such. Also, among "Amorphous," there are completely amorp It includes hous. Also, within "Crystalline" there is CAAC(c-ax is-aligned crystalline), nc(nanocrystalli This includes ne), and CAC (cloud-aligned composite). Note that the classification of "Crystalline" includes single crystal, pol Y crystals and completely amorphous crystals are excluded. "Crystal" includes single crystal and poly cry It includes "stal".

[0113] The structures within the thick border shown in Figure 11A are "Amorphous" and "Cry It is an intermediate state between "stal (crystal)" and a new boundary region (New crystal This structure belongs to the line phase. In other words, this structure is energetically in It is completely different from the stable "Amorphous" or "Crystal" forms. This can be rephrased as a structure.

[0114] The crystal structure of the film or substrate is determined by X-ray diffraction (XRD). It can be evaluated using the (on) spectrum. Here, "Crystalline" GIXD (Grazing-Incidence) of CAAC-IGZO film, which is classified as such. The XRD spectrum obtained by the XRD measurement is shown in Figure 11B. Note that the GIXD method is used for thin films. This method is also called the Seemann-Bohlin method. Hereafter, the GIXD measurement shown in Figure 11B will be used. The XRD spectrum obtained is simply referred to as the XRD spectrum. Note that C shown in Figure 11B The composition of the AAC-IGZO film is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. Furthermore, the thickness of the CAAC-IGZO film shown in Figure 11B is 500 nm.

[0115] As shown in Figure 11B, the XRD spectrum of the CAAC-IGZO film clearly shows crystallinity. The peak shown is detected. Specifically, in the XRD spectrum of the CAAC-IGZO film, A peak indicating c-axis orientation is detected near 2θ = 31°. As shown in Figure 11B... The peaks near 2θ = 31° are asymmetrical with respect to the angle at which the peak intensity was detected.

[0116] Furthermore, the crystal structure of the film or substrate is determined by nano-beam diffraction (NBED). Diffraction patterns observed by electron diffraction (extremely low-voltage electrons) This can be evaluated using the sub-ray diffraction pattern (also called the sub-ray diffraction pattern). Diffraction of CAAC-IGZO film The pattern is shown in Figure 11C. Figure 11C shows an NBE with an electron beam incident parallel to the substrate. This is the diffraction pattern observed by D. Note that the CAAC-IGZO film shown in Figure 11C The composition is approximately In:Ga:Zn=4:2:3 [atomic ratio]. Also, the microelectron beam... In the diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0117] As shown in Figure 11C, the diffraction pattern of the CAAC-IGZO film shows multiple c-axis orientations. Spots of this nature are observed.

[0118] [Structure of oxide semiconductors] Note that oxide semiconductors may be classified differently from those shown in Figure 11A when considering their crystal structure. Yes, there are. For example, oxide semiconductors include single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. It can be divided into two parts. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS. And there is nc-OS. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors and pseudo-non-crystalline oxide semiconductors. crystalline oxide semiconductor (a-like OS: amorphous-like oxide) This includes semiconductors, amorphous oxide semiconductors, and so on.

[0119] Next, we will discuss the details of the aforementioned CAAC-OS, nc-OS, and a-like OS. Give an explanation.

[0120] [CAAC-OS] CAAC-OS has multiple crystalline regions, and these multiple crystalline regions are arranged with their c-axis in a specific direction. It is an oxide semiconductor that is oriented in a particular direction. Note that the specific direction refers to the thickness direction of the CAAC-OS film. The direction normal to the surface on which the CAAC-OS film is formed, or the direction normal to the surface of the CAAC-OS film. Furthermore, a crystalline region is a region in which the atomic arrangement has periodicity. If considered as an arrangement, a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-O S has a region in the ab-plane direction where multiple crystalline regions are connected, and this region is strained. This can sometimes occur. Note that strain refers to the deformation of the lattice arrangement in a region where multiple crystal regions are connected. Areas where the orientation of the grid arrangement changes between aligned regions and aligned regions with a different grid arrangement. This refers to the fact that CAAC-OS is c-axis oriented and has a clear orientation in the ab-plane direction. It is an oxide semiconductor that does not exist.

[0121] Each of the above multiple crystalline regions is composed of one or more minute crystals (with a maximum diameter of 10n It is composed of crystals that are less than m in size. If the crystalline region is composed of one minute crystal, The maximum diameter of the crystalline region is less than 10 nm. Furthermore, the crystalline region is composed of numerous tiny crystals. If this is the case, the size of the crystalline region may be around several tens of nanometers.

[0122] Furthermore, in In-M-Zn oxide, CAAC-OS contains indium (In) and acid A layer containing an element (hereinafter referred to as the In layer), and a layer containing the elements M, zinc (Zn), and oxygen (hereinafter referred to as the In layer). It tends to have a layered crystalline structure (also called a layered structure) in which (M,Zn) layers are stacked. Furthermore, indium and element M are mutually substitutable. Therefore, the (M,Zn) layer contains It may contain indium. Also, the In layer may contain element M. The In layer may also contain Zn. This layered structure can be seen, for example, in high-resolution TEM images. In this context, it is observed as a grid image.

[0123] When structural analysis of a CAAC-OS film is performed using, for example, an XRD instrument, the θ / 2θ skid is observed. Out-of-plane XRD measurements using a champ showed a peak indicating c-axis orientation at 2θ. It is detected at 31° or near that angle. Note that the position of the peak indicating c-axis orientation (value of 2θ) This may vary depending on the type and composition of the metal elements that make up CAAC-OS.

[0124] Furthermore, for example, in the electron diffraction pattern of a CAAC-OS film, multiple bright spots (spots) may be observed. ) is observed. Note that the difference between one spot and another is the incident electron beam that has passed through the sample. Observations are made at point-symmetric positions with respect to the spot (also called a direct spot) as the center of symmetry. ru.

[0125] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is a hexagonal lattice. While this is the basic principle, the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. Also, In the distortion described, there may be grid arrangements such as pentagons and heptagons. Note that CAAC- In OS, clear grain boundaries can be observed even near strain. It is not possible. In other words, the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This can be seen. This is because CAAC-OS has a dense arrangement of oxygen atoms in the ab-plane direction. Due to the absence of certain elements, or because the bond distance between atoms changes due to the substitution of metal atoms, This is thought to be because it allows for distortion to be tolerated.

[0126] Furthermore, a crystal structure in which clear grain boundaries can be observed is known as polycrystalline. It is called l). The grain boundaries become recombination centers, where carriers are trapped and the transistor is formed This is highly likely to cause a decrease in current, a decrease in field-effect mobility, etc. Therefore, a clear conclusion is reached. CAAC-OS, which lacks visible grain boundaries, has a crystal structure suitable for the semiconductor layer of transistors. It is one of the crystalline oxides. Note that CAAC-OS requires the presence of Zn. The configuration is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are In oxide It is preferable because it can suppress the generation of grain boundaries more effectively than other materials.

[0127] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less prone to a decrease in electron mobility caused by grain boundaries. Furthermore, the crystallinity of oxide semiconductors can decrease due to impurities or the formation of defects. Therefore, CAAC-OS is also an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Yes, that's correct. Therefore, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are highly heat-resistant and reliable. -OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors expands the degree of freedom in the manufacturing process. This becomes possible.

[0128] [nc-OS] nc-OS is used in minute regions (for example, regions between 1 nm and 10 nm, especially between 1 nm and 3 nm). It has periodicity in the atomic arrangement in the region of less than nm. In other words, nc-OS is minute It has crystals. The size of these minute crystals is, for example, between 1 nm and 10 nm. In particular, because they are between 1 nm and 3 nm in size, these minute crystals are also called nanocrystals. In nc-OS, no regularity is observed in the crystal orientation between different nanocrystals. Therefore, across the entire film... No orientation is observed. Therefore, nc-OS is a-like depending on the analytical method. It can sometimes be indistinguishable from OS or amorphous oxide semiconductors. For example, with respect to an nc-OS film, When performing structural analysis using an XRD device, out-of-pla scans using θ / 2θ scans are performed. In ne XRD measurements, no peak indicating crystallinity is detected. Furthermore, compared to nc-OS films... Electron diffraction using electron beams with probe diameters larger than nanocrystals (e.g., 50 nm or larger). When electron diffraction (also called limited-field diffraction) is performed, a diffraction pattern resembling a halo pattern can be observed. It is measured. On the other hand, for the nc-OS film, the size is close to or smaller than that of the nanocrystals. Electron diffraction (nanobeam electron diffraction) using an electron beam with a lobe diameter (e.g., 1 nm to 30 nm) Also called sub-ray diffraction, when this is performed, multiple particles are found within a ring-shaped region centered on the direct spot. In some cases, electron diffraction patterns with multiple spots observed may be obtained.

[0129] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. It is a conductor. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, it has a-like properties. OS has a higher hydrogen concentration in the membrane compared to nc-OS and CAAC-OS.

[0130] [Oxide semiconductor configuration] Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS is a material composition. Regarding.

[0131] [CAC-OS] CAC-OS refers to, for example, metal oxides in which the elements constituting the metal oxide are between 0.5 nm and 10 nm in size. Preferably, a composition of material that is unevenly distributed with a size of 1 nm to 3 nm or near that size. In addition, in the following, in a metal oxide, one or more metal elements are unevenly distributed, The region containing the metallic element is 0.5 nm to 10 nm, preferably 1 nm to 3 nm. The following state, where particles of similar or near-similar size are mixed, is also referred to as a mosaic or patchy appearance.

[0132] Furthermore, CAC-OS is a system where the material separates into a first region and a second region, resulting in a mosaic effect. This results in a cloud-like structure, where the first region is distributed within the membrane (hereinafter also referred to as a cloud-like structure). Therefore, CAC-OS is a mixture of the first region and the second region. It is a composite metal oxide having the following configuration.

[0133] Here, In for the metal elements constituting CAC-OS in In-Ga-Zn oxide The atomic ratios of Ga and Zn are expressed as [In], [Ga], and [Zn] respectively. To note, for example, in CAC-OS in In-Ga-Zn oxide, the first region is This is the region where [In] is greater than the [In] in the composition of the CAC-OS film. The second region is the region where [Ga] is greater than the [Ga] in the composition of the CAC-OS film. Yes. Or, for example, in the first region, [In] is greater than [In] in the second region. This is a region where the [Ga] is large and smaller than the [Ga] in the second region. In the second region, [Ga] is greater than [Ga] in the first region, and [In This is a region smaller than [In] in the first region.

[0134] Specifically, the first region mentioned above is mainly composed of indium oxide, indium zinc oxide, etc. This is the region. Furthermore, the second region mentioned above includes gallium oxide, gallium zinc oxide, etc. This is the region in which is the principal component. In other words, the first region described above is called the region in which In is the principal component. It can be replaced. Furthermore, the second region mentioned above can be rephrased as the region with Ga as the main component. It is possible.

[0135] Furthermore, a clear boundary may not be observed between the first region and the second region described above.

[0136] For example, in CAC-OS in In-Ga-Zn oxide, energy-dispersive X-ray spectroscopy is used. Law(EDX:Energy Dispersive X-ray spectrosco The EDX mapping obtained using py) shows the region with In as the main component (the first region) It has a structure in which a region mainly composed of ) and a region mainly composed of Ga (the second region) are unevenly distributed and mixed. This can be confirmed.

[0137] When CAC-OS is used in a transistor, the conductivity is due to the first region and the second region The insulating properties resulting from this work in a complementary manner to enable the switching function (On / The function to turn it off can be added to CAC-OS. In other words, CAC-OS is In part of the material, it has conductive properties, and in part of the material, it has insulating properties, and the whole material It has the function of a semiconductor. By separating the conductive function and the insulating function, dual This allows for maximizing the functionality of the transistor. Therefore, CAC-OS is used in transistors. As a result, high on-current (I on ), high field-effect mobility (μ), and good switching This enables the implementation of a specific action.

[0138] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention Oxide semiconductors include amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, and CA. It may have two or more of the following: C-OS, nc-OS, and CAAC-OS.

[0139] [Transistors containing oxide semiconductors] Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0140] By using the above oxide semiconductor in transistors, transistors with high field-effect mobility can be produced. It can be achieved. Furthermore, highly reliable transistors can be realized.

[0141] In the channel formation region of a transistor, an oxide semiconductor with a low carrier concentration is used. Preferred. For example, the carrier concentration in the channel formation region of an oxide semiconductor is 1 × 10⁻⁶. 18 c m -3 The following is preferable: 1 × 10 17 cm -3 It is more preferable that it be less than , less than 1×10 16 cm -3 is more preferably, and less than 1×10 13 cm -3 is more preferably, and less than 1×10 is more preferably. In addition, when reducing the carrier concentration of the oxide semiconductor film, the impurity 12 concentration in the oxide semiconductor film may be reduced and the density of defect levels may be reduced. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as high purity intrinsic or substantially high purity intrinsic. Note that an oxide semiconductor having a low carrier -3 concentration may be referred to as a high purity intrinsic or substantially high purity intrinsic oxide semiconductor. Further, being high purity intrinsic or substantially high purity intrinsic may be referred to as type i or substantially type i.

[0142]

[0142] In addition, an oxide semiconductor film that is high purity intrinsic or substantially high purity intrinsic may have a low density of trap levels because the density of defect levels is low .

[0143] In addition, the charge trapped in the trap levels of the oxide semiconductor may take a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics .

[0144] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like .

[0145] 〔impurities〕 Here, we will explain the effects of various impurities in oxide semiconductors.

[0146] In oxide semiconductors, if silicon or carbon, which are among the Group 14 elements, are present, the oxide Defect levels are formed in semiconductors. Therefore, in the channel formation region of oxide semiconductors... The concentration of silicon and carbon, and the silicon near the interface with the channel formation region of the oxide semiconductor. or carbon concentration (Secondary Ion Mass Spectrometry (SIMS) The concentration obtained by spectrometry is 2 × 10 18 ate / c m 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0147] Furthermore, if alkali metals or alkaline earth metals are present in the oxide semiconductor, defect levels are formed. And, it may generate carriers. Therefore, alkali metals or alkaline earth metals are included. Transistors using oxide semiconductors tend to exhibit normally-on characteristics. Therefore, alkali metals or alkali metals in the channel formation region of oxide semiconductors obtained by SIMS. The concentration of potassium earth metals is 1 × 10⁻⁶ 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0148] Furthermore, in oxide semiconductors, when nitrogen is present, electrons, which are carriers, are generated. The concentration increases, making it easier to convert to n-type. As a result, oxide semiconductors containing nitrogen become semiconductors. The transistor used tends to exhibit normally-on characteristics. Alternatively, in oxide semiconductors... If nitrogen is present, a trap level may be formed. As a result, the transistor Electrical properties may become unstable. For this reason, oxide semiconductors obtained by SIMS The nitrogen concentration in the channel formation region is 5 × 10 19 atoms / cm 3 Less than 5 ×10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 Below Below, more preferably 5 × 10 17 atoms / cm 3 Do the following:

[0149] Furthermore, the hydrogen contained in oxide semiconductors reacts with the oxygen bonded to the metal atoms to form water. This can sometimes form an oxygen vacancy. When hydrogen enters this oxygen vacancy, the electrons, which are carriers, In some cases, this can be generated. Also, some of the hydrogen combines with oxygen that is bonded to a metal atom, resulting in a It can generate electrons, which are rear electrons. Therefore, using an oxide semiconductor containing hydrogen... Transistors tend to exhibit normally-on characteristics. Therefore, the channel of oxide semiconductors It is preferable that the amount of hydrogen in the formation region is reduced as much as possible. Specifically, acid In the channel formation region of a ionized semiconductor, the hydrogen concentration obtained by SIMS is 1 × 10⁻⁶. 20 atoms / cm 3 Less than 5 × 10 19 atoms / cm 3 Less than, better Mashiku is 1 x 10 19 atoms / cm 3 Less than 5 × 10 18 Atom s / cm 3Less than 1 × 10 18 atoms / cm 3 Make it less than.

[0150] Using oxide semiconductors with sufficiently reduced impurities in the channel formation region of transistors. This allows for the provision of stable electrical characteristics.

[0151] [Other semiconductor materials] The semiconductor materials that can be used for semiconductors 125 and 127 are the oxide semiconductors described above. It is not limited to the body. Semiconductors 125 and 127 are semiconductors having a band gap. Body materials (semiconductor materials other than zero-gap semiconductors) may also be used. For example, silicon Semiconductors of any element, compound semiconductors such as gallium arsenide, and layered materials that function as semiconductors. Materials such as atomic layer materials, two-dimensional materials, etc., may also be used as semiconductor materials. In particular, It is preferable to use a layered material that functions as a semiconductor as a semiconductor material.

[0152] In this specification, the term "layered material" refers to a general term for a group of materials having a layered crystalline structure. The crystal structure consists of layers formed by covalent and ionic bonds, and van der Waals forces It is a layered structure in which layers are formed by bonds weaker than covalent or ionic bonds. The quality is high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions in this way and has high two-dimensional electrical conductivity in the channel formation region, It is possible to provide transistors with high current.

[0153] Layered materials include graphene, silicene, and chalcogenides. It is a compound containing chalcogens. Furthermore, chalcogens are a general term for elements belonging to Group 16. It contains oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of cogenides include transition metal chalcogenides and group 13 chalcogenides.

[0154] As semiconductors 125 and 127, for example, transition metal chalcoids that function as semiconductors. It is preferable to use a genide. Applicable transitions as semiconductor 125 and semiconductor 127 Specifically, examples of transfer metal chalcogenides include molybdenum sulfide (typically MoS2), and Molybdenum renide (typically MoSe2), molybdenum telluride (typically MoTe2) ), tungsten sulfide (typically WS2), tungsten selenide (typically WSe 2) Tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS 2) Hafnium selenide (typically HfSe2), zirconium sulfide (typically Z Examples include rS2 and zirconium selenide (typically ZrSe2).

[0155] <Example of a method for manufacturing a storage device> Next, an example of a method for manufacturing a memory device according to the present invention will be described with reference to Figures 12A to 28C. In Figures 12A to 28C, A is a top view seen from the Z direction, and B is Figures 12A to 28C show a cross-sectional view of the area indicated by the dashed line A1-A2. In each figure, C is a cross-sectional view of the area indicated by the dashed line A3-A4 in A. Also, Figure 1 9D is an enlarged cross-sectional view of the area enclosed by the dashed line in Figure 19B. In the manufacturing method, one memory storage has two memory elements MC (also called "two stages"). The memory string 120 is shown as an example, but this embodiment is not limited to this. It may have three or more memory elements MC. For example, the memory string 120 may have 32 More than 128 steps, preferably 64 steps or more, more preferably 256 steps or more. It is preferable to have more than one stage of memory elements MC.

[0156] First, a conductor 122 is formed on a substrate 121 having an insulating surface, and around the conductor 122, An insulator 132 is formed (see Figures 12A to 12C).

[0157] First, a conductive film is formed, and the conductive film is processed using lithography to form a conductor 122. Next, an insulating film is formed on the substrate 121 so as to cover the conductor 122. It is preferable to perform a planarization treatment on the surface of the conductor 122. It is preferable to polish the insulating film until it is removed. The insulator 132 is formed by the above method. This is possible, however, the method of forming the conductor 122 and the insulator 132 is not limited to this. No. Form an insulator 132 on the substrate 121 and remove any unnecessary parts of the insulator 132. Alternatively, grooves or openings may be formed, and the conductive material 122 may be embedded in these grooves or openings. The damascene method (single damascene method, dual damascene method) is a method for forming such conductive materials. ) is sometimes referred to as [this]. By the above method, the conductor 122 shown in Figures 12A to 12C is insulated. The structure of body 132 can be obtained.

[0158] The formation of conductors 122 and insulators 132 is done by sputtering, CVD, molecular beam epitaxy, etc. SIE (MBE: Molecular Beam Epitaxy), pulsed laser deposition (PLD: Pulsed Laser Deposition) method or ALD method, etc. It can be used to perform the task.

[0159] Furthermore, the CVD method is a plasma CVD (PECVD) method that utilizes plasma. Processed CVD (CVD), thermal CVD (TCVD) which utilizes heat. Method D) can be classified into methods such as photoCVD (Photo-CVD), which utilizes light. Depending on the source gas, the process can be performed using metal CVD (MCVD) or organometallic CVD. It can be divided into MOCVD (Metal Organic CVD) methods.

[0160] Plasma CVD can produce high-quality films at relatively low temperatures. Thermal CVD, on the other hand, uses plasma This film deposition method does not use plasma, thus minimizing plasma damage to the workpiece. Yes, for example, wiring, electrodes, and elements (transistors, capacitive elements, etc.) included in semiconductor devices. These can sometimes be charged up by receiving an electric charge from the plasma. In some cases, the accumulated electric charge can damage the wiring, electrodes, and components contained in semiconductor devices. Yes, it does. On the other hand, in the case of thermal CVD methods that do not use plasma, such plasma damage occurs. Therefore, the yield of semiconductor devices can be increased. In addition, with the thermal CVD method, film deposition is possible. Because no plasma damage occurs inside, a film with fewer defects can be obtained.

[0161] Furthermore, the ALD method is a film deposition method that can minimize plasma damage to the workpiece. Yes. Also, the ALD method does not cause plasma damage during film deposition, so it produces films with fewer defects. It can be obtained.

[0162] CVD and ALD are film deposition methods in which particles emitted from a target or other source are deposited. In contrast, this is a film formation method in which a film is formed by a reaction on the surface of the object being treated. This film formation method is less affected by the shape of the workpiece and has good step-level coverage. The ALD method has excellent step coverage and excellent thickness uniformity, so the aspect ratio It is suitable for coating surfaces with high apertures. However, the ALD method has a relatively slow film deposition rate. Because the deposition rate is slow, it is not suitable for use in combination with other film deposition methods that have a high deposition rate, such as CVD. It can be preferable in some cases.

[0163] The CVD and ALD methods allow control of the composition of the resulting film by adjusting the flow rate ratio of the source gas. This is possible. For example, in the CVD method and ALD method, the flow rate ratio of the raw material gas can be adjusted to any A film of a certain composition can be formed. Also, for example, in the CVD method and ALD method, the film is formed. By changing the flow rate ratio of the raw material gas, a film with a continuously changing composition is formed. This is possible. When forming a film while changing the flow rate ratio of the raw material gas, multiple deposition chambers can be used. Compared to the method used for film deposition, the time required for film deposition is reduced by eliminating the time spent on transport and pressure adjustment. This is possible. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0164] In lithography, the resist is first exposed through a photomask. Next, The exposed areas are removed or left intact using a developer to form a resist mask. By etching through the resist mask, a conductor, semiconductor, or insulator is obtained. These can be processed into desired shapes. For example, KrF excimer laser light, ArF excimer laser light Using kiserum laser light, EUV (Extreme Ultraviolet) light, etc. A resist mask can be formed by exposing the resist. Also, the substrate and the projection lens and A liquid immersion technique may be used, in which a liquid (e.g., water) is filled between the elements and exposed. Alternatively, the aforementioned method may be used. Instead of light, electron beams or ion beams may be used. When using a photomask, a photomask is not required. Note that to remove the resist mask, Dry etching treatment such as shings, wet etching treatment, dry etch After the etching process, a wet etching process is performed, or after the wet etching process, It can perform lye etching.

[0165] Alternatively, a hard mask made of an insulator or conductor may be used instead of a resist mask. When using a hard mask, an insulating film or conductive film that will serve as the hard mask material is formed on the conductive film. Then, a resist mask is formed on top of it, and the hard mask material is etched to create the desired shape. A hard mask can be formed in a specific shape.

[0166] This process can be carried out using either a dry etching method or a wet etching method. The ching method is suitable for micro-machining.

[0167] As a dry etching apparatus, a capacitively coupled plasma (CCP) system with parallel plate electrodes is used. Using a capacitively coupled plasma etching apparatus This is possible. A capacitively coupled plasma etching apparatus having parallel plate electrodes is a parallel plate type Alternatively, a configuration in which a high-frequency power supply is applied to one of the electrodes may be used. Alternatively, a configuration in which multiple different high-frequency power supplies are applied to the electrodes may be used. Alternatively, a configuration in which a high-frequency power supply of the same frequency is applied to each of the parallel plate electrodes. A configuration in which high-frequency power supplies of different frequencies are applied may also be used. Alternatively, a system with a high-density plasma source may be used. A dry etching apparatus can be used. Dry etching with a high-density plasma source. The device, for example, uses inductively coupled plasma (ICP). Plasma etching equipment and the like can be used.

[0168] When a hard mask is used for etching a conductive film, the etching process is performed using a hard mask. You can either remove the resist mask used for formation before proceeding, or leave the resist mask in place. You can proceed as is. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after etching the above conductive film. If the material for the mask does not affect subsequent processes, or can be used in subsequent processes, then it is not necessarily necessary to use a mask. There is no need to remove the code mask.

[0169] The conductive film that will become the conductor 122 is formed by sputtering, and the conductive film containing metal elements is created using the sputtering method. It is preferable to do so. Alternatively, it can be formed using the CVD method.

[0170] The surface of the insulator 132 is preferably planarized as needed. Chemical treatment can be performed using chemical mechanical polishing (CMP) or reflow methods.

[0171] Insulating film 123A, conductive film 134A, and conductive film are placed on the conductor 122 and the insulator 132. 136A is stacked alternately. In this embodiment, insulating film 123A is formed on the insulator 132. Then, a conductive film 134A is formed on the insulating film 123A, and the insulating film 123A is placed on the conductive film 134A. The following shows an example of forming a conductive film 136A on an insulating film 123A (Figures 12A to 12C). (See reference.) For the formation of conductive film 134A, conductive film 136A, and insulating film 123A, CVD The method can be used. Alternatively, the sputtering method may be used.

[0172] Conductor 122, conductive film 134A, and conductive film 136A are silicon with impurities added. Conductive materials such as condensate or metal can be used. The conductive film 136A is a post-processing material. In this process, selective etching of the conductor 122 and the conductive film 134A is necessary. For this reason, it is preferable that the conductive material is different from the conductive material of the conductive film 134A. On the other hand, the conductor 122 and the conductive film 134A may be made of the same material, or different materials. Materials may also be used. For example, silicon as the conductor 122, conductive film 134A, or conductive film 136A. When using, amorphous silicon or polysilicon can be used. To give the silicone conductivity, p-type or n-type impurities may be added. As conductive materials containing ions, silicides containing titanium, cobalt, or nickel are used. It can be used as the electrolytic body 122, the conductive film 134A, or the conductive film 136A. When using a metal material as the conductor 122, conductive film 134A, or conductive film 136A, aluminum nium, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tung Stainless steel, hafnium, vanadium, niobium, manganese, magnesium, zirconium, be Using a material containing one or more metallic elements selected from lylium, indium, ruthenium, etc. It is possible.

[0173] The insulator 132 and insulating film 123A are insulating oxides, nitrides, and oxidized nitrides. Materials such as nitrides, metal oxides, metal oxide nitrides, and metal nitrides can be used. Silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, and fluorine are added. Silicon oxide, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen Silicon oxide or resin with voids, aluminum oxide, gallium oxide, HA5 oxide Oxides containing nium, zirconium oxide, aluminum, and hafnium, aluminum Oxiditrides having silicon and hafnium, oxides having silicon and hafnium, Nitride oxides having silicon and hafnium or nitrides having silicon and hafnium Monsters and other such things can be used.

[0174] Furthermore, in this embodiment, there are six layers of insulating film 123A, three layers of conductive film 134A, and conductive film An example of forming two layers of 136A is shown, but the number of layers is not limited to this. Depending on the performance of the placement, each can be formed. Here, the number of layers of conductive film 134A If m is an integer greater than or equal to 2, then the number of layers of insulating film 123A is 2 × m, and the number of conductive films 136A is 2 × m. The number of layers is m-1. For example, m is 33 or more, preferably 65 or more, more preferably The value can be 129 or more, and more preferably 257 or more.

[0175] Next, a mask is formed on the insulating film 123A (not shown), insulating film 123A, conductive film 134 A and the conductive film 136A are processed using lithography to expose the conductor 122. A first opening is formed in this manner (see Figures 13A to 13C).

[0176] Next, isotropic etching is performed on the conductive film 136A, and the conductive film 136A in the first opening is removed. The side surface is set back from the side surfaces of the insulating film 123A and the conductive film 134A (Figures 14A to 14A) See Figure 14C.) As a result of this process, the diameter of the first opening that overlaps with the conductive film 136A is the diameter of the insulating film. The diameter of the first opening that overlaps with 123A and the diameter of the first opening that overlaps with conductive film 134A are larger. Therefore, irregularities are formed on the side surface of the first opening. Such processing requires gas, ra Isotropic etching by dry etching using dical or plasma, or using liquids Isotropic etching by wet etching can be used. The liquid used in etching is sometimes called etchant. Dry etching is used to create isotropic etching. When performing chipping, use a gas containing at least one of chlorine, bromine, and fluorine, radicals, and p Lazma or similar tools can be used. Isotropic etching is performed on the mass used to form the first opening. It is preferable to carry out the process without removing the cu. The first opening obtained by the above process is shown in Figure 4. This corresponds to the opening 141.

[0177] Next, an insulating film 124A is formed on the insulating film 123A and inside the first opening (Figure 15). See Figures A through 15C.) Note that in Figures 15B and 15C, the insulating film 124A is a single layer. The structure may have a layered structure. The insulating film 124A is processed by CVD or ALD. It can be formed using this method. In particular, by using the ALD method, grooves with a large aspect ratio can be formed. This is preferable because it allows for the formation of a film with uniform thickness even over openings. Alternatively, The insulating film 124A may be formed by combining the ALD method and the CVD method. If the film has a layered structure, each insulating film may be formed using the same film deposition apparatus, or different film deposition apparatuses may be used. It may be formed by a device.

[0178] The insulating film 124A formed by the above method has good coverage and conforms to the uneven shape of the first opening side surface. Insulating film 124A can also be formed against it. That is, insulating film 123A, conductive film 1 34A, and not only the sides of the conductive film 136A, but also a portion of the upper surface of the insulating film 123A, The insulating film 124A can be formed so as to be in contact with a portion of the lower surface.

[0179] Next, the insulating film 124A formed at the bottom of the first opening is removed to obtain the insulator 124. For removing film 124A, anisotropic etching is preferable. Since the insulating film 124A on 23A is also removed, the insulator 124 is only present on the side wall of the first opening. It is provided (see Figures 16A to 16C). Remove the insulating film 124A at the bottom of the first opening. This exposes the conductor 122 again.

[0180] Next, semiconductor film 125A, insulating film 126A, and semiconductor film 127A are placed inside the first opening. It forms (see Figures 17A to 17C).

[0181] The semiconductor film 125A, insulating film 126A, and semiconductor film 127A were produced by CVD or ALD. It can be formed using this method. In particular, by using the ALD method, grooves with a large aspect ratio can be formed. This is preferable because it allows for the formation of a film with uniform thickness even over openings. Alternatively, By combining the ALD method and the CVD method, semiconductor film 125A, insulating film 126A, and semiconductor Each of the films 127A may be formed. Furthermore, different film deposition methods and deposition equipment may be used for each film to be formed. A setting may also be used. For example, to form semiconductor film 125A and semiconductor film 127A, M It is preferable to use the OCVD method.

[0182] Next, a conductive film 128A is formed inside the first opening (see Figures 17A to 17C). The conductive film 128A comprises at least an insulator 124, a semiconductor film 125A, an insulating film 126A, and and are formed to fill the recesses of the conductive film 136A via the semiconductor film 127A. In that case, it is not necessarily required to fill the entire interior of the first opening. The conductive film 128A is CVD It can be formed using methods such as the ALD method. In particular, by using the ALD method, the aspect ratio Because it can form a film of uniform thickness even in grooves and openings with a large to-ratio, it is preferred. Alternatively, the conductive film 128A may be formed by combining the ALD method and the CVD method.

[0183] Semiconductor films 125A and 127A are oxide semiconductors having a CAAC structure. Preferably, semiconductor films 125A and 127A have an oxidation structure having a CAAC structure. In the case of a solid semiconductor, the c-axis of the semiconductor film 125A is within the first opening, and the surface to be formed It is oriented in the normal direction. At this time, the insulating film 123A and the conductive film 134 are separated by the insulator 124. A, and semiconductor films 125A and 127A located on the side of conductive film 136A The c-axis is oriented toward axis 182 shown in Figures 17A to 17C from the surface to be formed. Axis 182 can be called the central axis of the first opening. This allows the semiconductor located above to The c-axis of the body 125 and the semiconductor 127 are oriented toward axis 182 from the surface to be formed.

[0184] Next, the conductive film 128A is processed to form the conductor 128 (see Figures 18A to 18C). .) The conductive film 128A is processed using either isotropic etching or anisotropic etching. This is possible. In forming the conductive film 128A, as shown in Figures 17A to 17C, If the conductive film 128A fills the recess and the first opening is not completely filled, the conductive film 12 For processing 8A, isotropic etching is preferable. On the other hand, the recess and the first opening If the conductive film 128A is formed to fill the opening, anisotropic etching is used. Preferably, the conductive material 128 is formed inside the recess by the processing described above. It is possible.

[0185] Next, an insulating film 129A is formed inside the semiconductor film 127A and the conductor 128. Then, using the conductor 128 as a mask, a portion of the semiconductor film 127A is made highly resistive, creating a high-resistance region. (Type I region) is formed. As a method for forming a high-resistance region, a semiconductor is used via an insulating film 129A. If the film 127A is irradiated with microwaves 144 to remove the hydrogen contained in the semiconductor film 127A, Good. Also, if the microwave 144 irradiation is performed in an oxygen-containing atmosphere, the semiconductor film 127A This is preferable because oxygen is supplied to it. In this embodiment, an atmosphere containing oxygen and argon is used. Under ambient conditions, a portion of the semiconductor film 127A is exposed to microwaves 144 through the insulating film 129A. The semiconductor film 127A is irradiated to increase the resistance of region 146 (see Figures 19A to 19D). ).

[0186] Heat treatment may be performed here. The heat treatment is performed in a nitrogen-containing atmosphere at 200°C or higher for 50°C. It is preferable to perform the heat treatment at 0°C or below, or more preferably at 300°C to 400°C. The atmosphere used is not limited to those mentioned above, but includes at least one of nitrogen, oxygen, and argon. This can be done. Furthermore, the heat treatment may be carried out in a reduced pressure atmosphere or in an atmospheric pressure atmosphere. It's okay.

[0187] The heat treatment reduces the resistance of the semiconductor film 127A in contact with the conductor 128, and reduces the resistance of region 148. A resistive region (N-type region) can be formed. The semiconductor film 127A and the conductor 128 are in contact. By performing a heat treatment in this state, the interface between the conductor 128 and the semiconductor film 127A becomes conductive. A metal compound layer is formed containing the metal elements present in body 128 and the components of the semiconductor film 127A. In some cases, the formation of the metal compound layer results in the region in contact with the conductor 128. This is preferable because it reduces the resistance of the semiconductor film 127A. Also, the semiconductor film 127A contains Oxygen may be absorbed by the conductor 128. The semiconductor film 127A and the conductor 128 are in contact. By performing a heat treatment in this state, the semiconductor film 127A becomes even less resistive. This may be done before microwave treatment. The region 148 whose resistance has been reduced by the heat treatment is conductive. Because it is covered by body 128, it is not affected by microwave 144, and even after microwave processing, it remains low It can maintain a stable resistance value.

[0188] The carrier concentration in region 146 after the above microwave treatment and heat treatment is 1 × 10⁻⁶ 18 / cm 3 Less than 1 × 10 17 / cm 3 More preferably, 1 × 10 16 / cm 3 The following is preferable. Also, the carrier concentration in region 148 is 1 × 10⁻⁶. 18 / cm 3 Preferably, 1 × 10 19 / cm 3 More preferably, 1 × 10 20 / cm 3 It is preferable that the above conditions are met.

[0189] Next, a conductive film 130A is formed (see Figures 20A to 20C). The conductive film 130A is It can be formed using the CVD method or the ALD method. In particular, by using the ALD method, Because it can form a film of uniform thickness even on grooves and openings with a large spectral ratio. , which is preferable. Alternatively, the ALD method and the CVD method may be combined to form it.

[0190] Next, heat treatment is performed. The heat treatment is carried out in a nitrogen-containing atmosphere at a temperature between 200°C and 500°C. This process is preferably carried out at a temperature between 300°C and 400°C. (Atmosphere for heat treatment) This is not limited to the above, but can be carried out in an atmosphere containing at least one of nitrogen, oxygen, and argon. Furthermore, the heat treatment may be carried out in a reduced pressure atmosphere or in an atmospheric pressure atmosphere. .

[0191] Next, the conductive film 130A is removed using methods such as CMP until the surface of the insulating film 129A is exposed. Then, a conductor 130 is obtained (see Figures 21A to 21C). Note that the aforementioned heat treatment is This may be done after the formation of the conductive material 130.

[0192] Next, the semiconductor film 125A, insulating film 126A, semiconductor film 127A, and insulating film 129A are The semiconductor 125, insulator 126, oxide film 127B, and insulating film 129B are obtained by processing. (See Figures 22A to 22C.) The process can be performed using dry etching or wet etching. It can be used.

[0193] Next, the insulating film 123A, the conductive film 134A, and the conductive film 136A were processed, as shown in Figure 23B. Forms a stepped insulator 123B, conductor 134B, and conductor 136B. See Figures 23A to 23C. ) Insulating film 123A, conductive film 134A, and conductive film 136 In processing A, etching of insulating film 123A, conductive film 134A, and conductive film 136A By alternating between sculpting and mask slimming, the stepped insulator 123B and conductor 134 B and the conductor 136B can be formed.

[0194] Next, an insulator 150 is formed (see Figures 23A to 23C). The insulator 150 is CV It can be formed using method D. The insulator 150 can be formed using CMP or reflow. It is preferable that the surface is planarized.

[0195] Next, insulator 150, insulator 123B, conductor 134B, and conductor 136B are processed. An insulator 123, a conductor 134, and a conductor 136 are obtained. (See Figures 24A to 24C) Light. ).

[0196] Next, an insulator 152 is formed to fill the portion removed by the above processing (Figure 24). See A to Figure 24C. The insulator 152 can be formed using the CVD method or the ALD method. Yes, it is possible. In particular, by using the ALD method, even grooves and openings with large aspect ratios can be treated. This method is preferable because it allows for the formation of a film with uniform thickness. Alternatively, the ALD method and the CVD method. The insulator 152 may be formed by combining these. The insulator 152 can be formed by CMP or reflow. It is preferable that the material is flattened using a specific method.

[0197] Next, the oxide film 127B and the insulating film 129B are processed using lithography, and semi- A conductor 127 and an insulator 129 are obtained (see Figures 25A to 25C). This process is performed by a drill. The etching method or the wet etching method can be used.

[0198] Next, a conductor 154 is formed so as to overlap with a part of the semiconductor 125 via the insulator 126. (See Figures 26A to 26C.) Conductor 154 is insulator 126, insulator 150, A conductive film is formed on the insulator 152, and the conductive film is processed using lithography. This is obtained. Note that in Figure 26A, the conductor 154 is located on the dashed line A1-A2. However, in Figure 26B, the conductor 154 is shown with a dashed line.

[0199] Next, an insulating layer is placed over the conductor 154, insulator 126, insulator 150, and insulator 152. The edge 156 is formed (see Figures 27A to 27C). The insulator 156 is formed by CVD, A It can be formed using methods such as LD (Laser Discharge) or sputtering.

[0200] Next, insulator 156, insulator 126, insulator 129, semiconductor 127, and insulator 150 These are processed using lithography, and conductor 134, conductor 136, conductor 130, conductor A second opening is formed so that the electroluminescent body 154 and the semiconductor 125 are exposed. , formed on the stepped conductor 134 and the conductor 136 respectively (Figure See Figures 27A to 27C.

[0201] Next, a conductor 161 is electrically connected to the conductor 134 so as to be embedded in the second opening. Conductor 162 electrically connected to the electric body 136, Conductor 1 electrically connected to the conductor 130 63, Conductor 164, which is electrically connected to Conductor 154, and Semiconductor 125, which is electrically connected to Conductor 164, which is electrically connected to Semiconductor 125. Conductor 165, semiconductor 125 and semiconductor 127 are electrically connected by a conductor 166. (See Figures 28A to 28C.) Conductor 161, Conductor 162, Conductor 163, Conductor 164, conductor 165, and conductor 166 are formed using CVD or ALD methods. This is possible. In particular, by using the ALD method, grooves and openings with a large aspect ratio can be treated. This is preferable because it allows for the formation of a film with uniform thickness. Alternatively, the ALD method and CV The above conductor may be formed by combining method D. Also, conductor 161, conductor 162, Conductors 163, 164, 165, and 166 consist of multiple layers. It may have a layered structure. Conductor 161, Conductor 162, Conductor 163, Conductor 16 4. Conductors 165 and 166 are guided onto the insulator 156 and into the second opening. It can be formed by creating an electrical film and then removing the unwanted conductive film using CMP or the like. ru.

[0202] Next, conductor 171, which is electrically connected to conductor 161, and conductor 162, which are electrically connected to conductor 161. Conductors 172 and 163 are electrically connected to conductors 173 and 164. A conductor 174 to be connected, and a conductor 175 that is electrically connected to the conductor 165 are formed. (See Figures 28A to 28C.) Conductor 171, Conductor 172, Conductor 173, Conductor 174 and the conductor 175 form a conductive film on the insulator 156 and lithography is performed It can be formed by processing using a dry etching method or a wet etching method. You can use it.

[0203] Conductors 171, 161, and 134 are either conductor SG or conductor WWL. It functions as follows. Conductors 172, 162, and 136 are conductor RWLs. Conductors 173, 163, and 130 function as conductive BG. Conductors 174, 164, and 154 function as conductive SELs. Conductors 175 and 165 function as BLs. Through the above process, the memory device A structure can be created.

[0204] (Embodiment 2) In this embodiment, the storage device 100 is a modified version of the storage device 100 shown in Embodiment 1. A will be explained. Figure 29 shows a perspective view of a storage device 100A according to one aspect of the present invention. Figure 30 is a cross-sectional view of area A1-A2, indicated by the dashed line in Figure 29. For matters not explained in the form, refer to other embodiments, etc.

[0205] <Example of storage device configuration> The storage device 100A has a memory string 120s. The memory string 120s is The configuration of transistor STr2 is different from that of memory string 120. Figure 31 shows the memory string An example of the cross-sectional configuration of string 120s is shown. In memory string 120s, transistor S A conductor SEL, which functions as the gate electrode of Tr2, is provided on the insulator 123

[12] . It is. Also, the insulator 138 is provided on the conductor SEL. A part of the conductor 130 is It functions as the back gate electrode of the transistor STr2.

[0206] <Example of a method for manufacturing a storage device> Next, other examples of manufacturing methods for the storage device 100A will be described with reference to Figures 32A to 50C. In Figures 32A to 50C, A is a top view seen from the Z direction, and B is A is a cross-section of the area shown by the dashed line A1-A2. Also, C is a cross-section of A3-A4. This is a cross-sectional view of the area indicated by the dashed line in Figure 43B. This is a magnified cross-sectional view of the enclosed area. Note that this manufacturing method uses two stages of memory elements MC. One memory string 120s is given as an example, but this embodiment is not limited to this. The Moristring 120s may have three or more memory elements MC. For example, memo The listing 120s has 32 or more rows, preferably 64 or more rows, more preferably 128 rows. More preferably, the memory element MC has 256 or more stages.

[0207] First, similar to the example of the manufacturing method for the memory device 100, a conductive material 1 is placed on a substrate 121 having an insulating surface. 22, an insulator 132, an insulating film 123A, a conductive film 134A, and a conductive film 136A are formed. (See Figures 32A to 32C.)

[0208] Next, a conductive film 137A is formed on the uppermost insulating film 123A, and an insulating film 137A is formed on the conductive film 137A. A border film 138A is formed. The conductor 137A is formed using the same method as the conductive film 134A. It can be formed from the following materials. In addition, insulating film 138A can be formed using the same method as insulating film 123A. It can be used and formed from similar materials.

[0209] Next, a mask is formed on the insulating film 138A (not shown), insulating film 138A, conductive film 137 A, insulating film 123A, conductive film 134A, and conductive film 136A are coated using lithography. The material is then processed to form a first opening that exposes the conductor 122 (Figures 33A to 33A). See C. ).

[0210] Next, isotropic etching is performed on the conductive film 136A, and the conductive film 136A in the first opening is removed. The sides of the insulating film 123A, conductive film 134A, conductive film 137A, and insulating film 138A It is set back from the side (see Figures 34A to 34C). This process creates the conductive film 136 The diameter of the first opening that overlaps with A is such that insulating film 123A, conductive film 134A, conductive film 137A, and The diameter of each first opening that overlaps with the insulating film 138A becomes larger. An uneven surface is formed on the sides of the mouth.

[0211] Next, an insulating film 124A is formed on the insulating film 138A and inside the first opening (Figure 35). See Figures A through 35C.) Note that in Figures 35B and 35C, the insulating film 124A is a single layer. The structure may have a layered structure. The insulating film 124A is processed by CVD or ALD. It can be formed using this method. In particular, by using the ALD method, grooves with a large aspect ratio can be formed. This is preferable because it allows for the formation of a film with uniform thickness even over openings. Alternatively, The insulating film 124A may be formed by combining the ALD method and the CVD method. If the film has a layered structure, each insulating film may be formed using the same film deposition apparatus, or different film deposition apparatuses may be used. It may be formed by a device.

[0212] The insulating film 124A formed by the above method has good coverage and conforms to the uneven shape of the first opening side surface. Insulating film 124A can also be formed against it. That is, insulating film 123A, conductive film 1 34A, and not only the sides of the conductive film 136A, but also a portion of the upper surface of the insulating film 123A, The insulating film 124A can be formed so as to be in contact with a portion of the lower surface.

[0213] Next, the insulating film 124A formed at the bottom of the first opening is removed to obtain the insulator 124. For removing film 124A, anisotropic etching is preferable. Since the insulating film 124A on 38A is also removed, the insulator 124 is only present on the side wall of the first opening. (See Figures 36A to 36C.) The insulating film 124A at the bottom of the first opening is removed. This exposes the conductor 122 again.

[0214] Next, a semiconductor film 125A and an insulating film 126A are formed inside the first opening (Figure 37). See Figures A through 37C.

[0215] The semiconductor film 125A and the insulating film 126A are formed using CVD or ALD methods. This is possible. In particular, by using the ALD method, even grooves and openings with large aspect ratios can be treated. This is preferable because it allows for the formation of a film with uniform thickness. Alternatively, the ALD method and CVD The semiconductor film 125A and the insulating film 126A may be formed by combining these methods. Furthermore, different film deposition methods and equipment may be used for each film to be formed.

[0216] The semiconductor film 125A is preferably an oxide semiconductor having a CAAC structure. If film 125A is an oxide semiconductor having a CAAC structure, the c-axis of semiconductor film 125A is , within the first opening, it is oriented in the direction normal to the surface to be formed. At this time, the insulator 124 Through this, insulating film 138A, conductive film 137A, insulating film 123A, conductive film 134A, and The c-axis of the semiconductor film 125A located on the side of the electrode film 136A is shown in Figures 37A to 37C. It is oriented toward axis 182. As a result, the c-axis of the semiconductor 125 located above is shaped It is oriented from the surface toward axis 182.

[0217] Next, viewed from the Z direction, the conductive film 137A of the insulating film 126A and the semiconductor film 125A overlap. Remove the region. To remove the insulating film 126A and semiconductor film 125A in the region, First, a material 180 (also called a sacrificial layer) that can be easily removed in a later process is embedded inside the first opening. Formed to fit, a portion of material 180 is etched to the desired depth inside the first opening, etc. Remove by (see Figures 38A to 38C). Next, use the remaining material 180 as a mask. Then, the insulating film 126A and the semiconductor film 125A exposed by the etching are sequentially removed. Then, an insulator 126 and a semiconductor 125 are obtained (see Figures 39A to 39C). Remove material 180 (see Figures 40A to 40C).

[0218] Furthermore, even without removing a portion of the insulating film 126A and the semiconductor film 125A, the region can be treated as described above. If a transistor STr2 can be constructed, an insulating film 126A using material 180, and a semiconductor The step of removing the body film 125A can be omitted. At this time, between the conductor 137 and the semiconductor 127 A transistor S is provided with a semiconductor 125 via an insulator 124 and an insulator 126. Tr2 is formed.

[0219] Next, a semiconductor film 127A and a conductive film 128A are formed inside the first opening (Figure 41A). (See Figure 41C.)

[0220] First, the semiconductor film 127A is formed. The semiconductor film 127A is formed using CVD or ALD. It is possible to form grooves and openings with large aspect ratios, especially by using the ALD method. It is preferable because it can form a film of uniform thickness even on the part. Alternatively, ALD The semiconductor film 127A may be formed by combining the method and the CVD method.

[0221] The semiconductor film 127A is preferably an oxide semiconductor having a CAAC structure. If film 127A is an oxide semiconductor having a CAAC structure, the c-axis of semiconductor film 127A is , within the first opening, it is oriented in the direction normal to the surface to be formed. At this time, the insulator 124, The semiconductor 125, the insulator 126, etc., the insulating film 138A, the conductive film 137A, the insulating film 1 c of semiconductor film 127A located on the side of conductive film 134A, conductive film 136A The axis is oriented toward axis 182 shown in Figures 41A to 41C from the surface to be formed. Furthermore, the c-axis of the semiconductor 127 located above is oriented toward axis 182 from the surface to be formed.

[0222] Next, a conductive film 128A is formed (see Figures 41A to 41C). The conductive film 128A is At a minimum, the insulator 124, semiconductor film 125, insulating film 126, and semiconductor film 127A It is sufficient that the second is formed to fill the recesses of the conductive film 136A, and it is not necessarily the second It is not necessary to fill the entire opening. The conductive film 128A is shaped using CVD or ALD methods. This can be achieved. In particular, by using the ALD method, grooves and openings with large aspect ratios can be created. This is preferable because it allows for the formation of a film with uniform thickness. Alternatively, the ALD method. The conductive film 128A may also be formed by combining this with the CVD method.

[0223] Next, the conductive film 128A is processed to form the conductor 128 (see Figures 42A to 42C). .) The conductive film 128A is processed using either isotropic etching or anisotropic etching. This is possible. In forming the conductive film 128A, as shown in Figures 41A to 41C, If the conductive film 128A fills the recess and the opening is not completely filled, the conductive film 128A For processing, isotropic etching is preferable. Meanwhile, the recesses and openings are filled. When a conductive film 128A is formed in this manner, it is preferable to use anisotropic etching. i. By processing as described above, a conductor 128 can be formed inside the recess.

[0224] Next, using the conductor 128 as a mask, a portion of the semiconductor film 127A is made highly resistive, creating a high-resistance region. (Type I region) is formed. As a method for forming the high-resistance region, the semiconductor film 127A is microwaved. Irradiation with 144°C can remove the hydrogen contained in the semiconductor film 127A. Alternatively, microwaves can be used. When irradiation with 144 is performed in an oxygen-containing atmosphere, oxygen is supplied to the semiconductor film 127A, Preferred. In this embodiment, the semiconductor film 1 is prepared in an atmosphere containing oxygen and argon. A portion of 27A is irradiated with microwaves 144, so as not to overlap with the conductor 128 of the semiconductor film 127A. The resistance of region 146 is increased (see Figures 43A to 43D).

[0225] Heat treatment may be performed here. The heat treatment is performed in a nitrogen-containing atmosphere at 200°C or higher for 50°C. It is preferable to perform the heat treatment at 0°C or below, or more preferably at 300°C to 400°C. The atmosphere used is not limited to those mentioned above, but includes at least one of nitrogen, oxygen, and argon. This can be done. Furthermore, the heat treatment may be carried out in a reduced pressure atmosphere or in an atmospheric pressure atmosphere. It's okay.

[0226] The heat treatment reduces the resistance of the region (region 148) of the semiconductor film 127A that is in contact with the conductor 128. This allows for the formation of a low-resistance region (N-type region). The semiconductor film 127A and the conductor 1 By performing a heat treatment while 28 is in contact, the interface between the conductor 128 and the semiconductor film 127A The metal compound layer includes the metal elements present in the conductor 128 and the components of the semiconductor film 127A. It may be formed. When the metal compound layer is formed, the conductor 128 and the semiconductor film 1 In the region where 27A is in contact, the resistance of the semiconductor film 127A is reduced, which is preferable. In some cases, the conductor 128 may absorb oxygen contained in the semiconductor film 127A. By performing a heat treatment while 7A and the conductor 128 are in contact, the region of the semiconductor film 127A 148 results in lower resistance. This heat treatment may be performed before microwave treatment. The region 148, which has been made less resistive by this principle, is covered by the conductor 128, so microwave 14 It is unaffected by factor 4 and can maintain a low resistance value even after microwave processing.

[0227] The carrier concentration in region 146 after the above microwave treatment and heat treatment is 1 × 10⁻⁶ 18 / cm 3 Less than 1 × 10 17 / cm 3 More preferably, 1 × 10 16 / cm 3 The following is preferable. Also, the carrier concentration in region 148 is 1 × 10⁻⁶. 18 / cm 3 Preferably, 1 × 10 19 / cm 3 More preferably, 1 × 10 20 / cm 3 It is preferable that the above conditions are met.

[0228] Next, an insulating film 129A is formed to cover the semiconductor film 127A and the conductor 128, and insulating film 1 A conductive film 130A is formed to cover 29A (see Figures 44A to 44C). Insulating film 129 A and conductive film 130A can be formed using CVD or ALD methods. In particular, AL By using the D method, a film with uniform thickness can be formed even for grooves and openings with large aspect ratios. This is preferable because it can be achieved. Alternatively, it can be formed by combining the ALD method and the CVD method. You may do so.

[0229] Furthermore, the formation of the high-resistance region by the above microwave treatment and the heat treatment are performed on the insulating film 129A This may be performed after the formation of the conductive film 130A but before the formation of the conductive film 130A.

[0230] Next, heat treatment is performed. The heat treatment is carried out in a nitrogen-containing atmosphere at a temperature between 200°C and 500°C. This process is preferably carried out at a temperature between 300°C and 400°C. (Atmosphere for heat treatment) This is not limited to the above, but can be carried out in an atmosphere containing at least one of nitrogen, oxygen, and argon. Furthermore, the heat treatment may be carried out in a reduced pressure atmosphere or in an atmospheric pressure atmosphere. .

[0231] Next, the conductive film 130A is removed using methods such as CMP until the surface of the insulating film 129A is exposed. Then, a conductor 130 is obtained (see Figures 45A to 45C). Note that the aforementioned heat treatment is This may be done after the formation of the conductive material 130.

[0232] Next, the semiconductor film 127A and the insulating film 129A are processed to form the semiconductor 127 and the insulator 129 is obtained (see Figures 46A to 46C). This process can be performed by dry etching or wet etching. An etching method can be used. In this case, the semiconductor 125 and the semiconductor that are electrically connected 127 can be formed.

[0233] Next, insulating film 138A, conductive film 137A, insulating film 123A, conductive film 134A, and conductive The film 136A is processed to form a stepped insulator 138B, a conductor 137B, as shown in Figure 47B. Insulator 123B, conductor 134B, and conductor 136B are formed (Figures 47A to 4) See 7C. ) Insulating film 138A, conductive film 137A, insulating film 123A, conductive film 134A, In processing the conductive film 136A, insulating film 138A, conductive film 137A, insulating film 123A Etching of conductive film 134A and conductive film 136A and mask slimming are performed alternately. By doing so, the stepped insulator 138B, conductor 137B, insulator 123B, and conductor 134 B and the conductor 136B can be formed.

[0234] Next, an insulator 150 is formed (see Figures 47A to 47C). The insulator 150 is CV It can be formed using method D. The insulator 150 can be formed using CMP or reflow. It is preferable that the surface is planarized.

[0235] Next, insulator 150, insulator 138B, conductor 137B, insulator 123B, conductor 134 B and the conductor 136B are processed to create the insulator 138, conductor 137, insulator 123, and conductive Body 134 and conductor 136 are obtained. (See Figures 48A to 48C.)

[0236] Next, an insulator 152 is formed to fill the portion removed by the above processing (Figure 48). See A to Figure 48C. The insulator 152 can be formed using the CVD method or the ALD method. Yes, it is possible. In particular, by using the ALD method, even grooves and openings with large aspect ratios can be treated. This method is preferable because it allows for the formation of a film with uniform thickness. Alternatively, the ALD method and the CVD method. The insulator 152 may be formed by combining these. The insulator 152 can be formed by CMP or reflow. It is preferable that the material is flattened using a specific method.

[0237] Next, covering the conductor 130, insulator 129, insulator 150, and insulator 152 is an insulating layer. A border 156 is formed (see Figures 49A to 49C). The insulator 156 is formed by CVD, A It can be formed using methods such as LD (Laser Discharge) or sputtering.

[0238] Next, insulators 156, 150, 129, and 138 are subjected to lithography. Processed using the E method, conductor 134, conductor 136, conductor 130, conductor 137, A second opening is formed to expose semiconductor 127. The second opening is formed in a stepped shape. Formed on the conductor 134 and conductor 136 respectively (Figures 49A to 49A) See 9C. ).

[0239] Next, a conductor 161 is electrically connected to the conductor 134 so as to be embedded in the second opening. Conductor 162 electrically connected to the electric body 136, Conductor 1 electrically connected to the conductor 130 63, Conductor 164, which is electrically connected to Conductor 137, and Semiconductor 127, which is electrically connected to Conductor 164, which is electrically connected to Semiconductor 127. Conductor 165 is formed (see Figures 50A to 50C). Conductor 161, Conductor 162 Conductors 163, 164, and 165 are shaped using CVD or ALD methods. This can be achieved. In particular, by using the ALD method, grooves and openings with large aspect ratios can be created. This is preferable because it allows for the formation of a film with uniform thickness. Alternatively, the ALD method. The above conductor may be formed by combining the CVD method with the conductor 161. 162, conductor 163, conductor 164, and conductor 165 are laminated structures consisting of multiple layers. It may have a structure. Conductor 161, Conductor 162, Conductor 163, Conductor 164, The conductor 165 forms a conductive film on the insulator 156 and inside the second opening, and CMP It can be formed by removing unwanted conductive films using methods such as the above.

[0240] Next, conductor 171, which is electrically connected to conductor 161, and conductor 162, which are electrically connected to conductor 161. Conductors 172 and 163 are electrically connected to conductors 173 and 164. A conductor 174 to be connected, and a conductor 175 that is electrically connected to the conductor 165 are formed. (See Figures 50A to 50C.) Conductor 171, Conductor 172, Conductor 173, Conductor 174 and the conductor 175 form a conductive film on the insulator 156 and lithography is performed It can be formed by processing using a dry etching method or a wet etching method. You can use it.

[0241] Conductors 171, 161, and 134 are either conductor SG or conductor WWL. It functions as follows. Conductors 172, 162, and 136 are conductor RWLs. Conductors 173, 163, and 130 function as conductive BG. Conductors 174, 164, and 137 function as conductive SELs. Conductors 175 and 165 function as BLs. Through the above process, the semiconductor is formed. Device 200A can be manufactured.

[0242] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0243] (Embodiment 3) In this embodiment, an MOCVD apparatus that can be used for forming oxides and the like, and a film formation method using the MOCVD method will be described with reference to FIGS. 51 and 52.

[0244] <MOCVD Apparatus and Film Formation Method Using MOCVD Method> In the MOCVD method, a liquid raw material (also referred to as a precursor, a precurser, or a metal precurser) is vaporized using a vaporizer and introduced into a chamber to form a film. The liquid precurser is held in a cylinder 1041 (cylinders 1041A to 1041D) for each precurser. A gas 1042 is supplied into the cylinder 1041 holding the precurser used for film formation. As the gas 1042, an inert gas such as helium, argon, or nitrogen can be used. The supply of the gas 1042 can be controlled by a valve 1043, and the inside of a desired cylinder 1 041 can be pressurized. By pressurizing the inside of the cylinder 1041, the liquid precurser can be supplied to the vaporizer 1044. The supply of the gas 1042 can be performed for one cylinder 1041, or can be performed simultaneously for two or more cylinders 1041. Also, in FIG. 51, an example in which four cylinders 1041 are connected to the MOCVD apparatus is shown, but the present embodiment is not limited to this. The cylinder 1041 may be one or more.

[0245] By forming a film using a plurality of precursers, films having different compositions can be formed. For example, a precurser containing indium is held in the cylinder 1041A, a precurser containing gallium is held in the cylinder 1041B, a precurser containing zinc is held in the cylinder 1041C, and the gas 1042 is simultaneously supplied to the cylinders 1041A to 1C. This allows for the formation of films containing indium, gallium, and zinc. Further details are available. As will be described later, the vaporized precursor is mixed with a reaction gas containing oxygen, and then deposited in the deposition chamber 1008 Alternatively, by supplying to 1009, the wafer held in the deposition chamber 1008 or 1009 Oxides containing indium, gallium, and zinc can be formed on 1012.

[0246] The precursor supplied to the vaporizer 1044 is first supplied to the dispersion unit 1045. When precursors are used in film formation, these precursors are mixed in the dispersion section 1045. It is preferable that gas 1046 is supplied to the dispersion section at this time. This is sometimes called the primary carrier gas. Gas 1046 is a precursor, or mixed with it. It is used to supply the precursor from the dispersion section 1045 to the vaporization section 1048. Gas 1 As O46, inert gases such as helium, argon, and nitrogen can be used.

[0247] The precursor, or a mixture of precursors, is heated and vaporized in the vaporization section 1048. The vaporized precursor is supplied towards valve 1049 by gas 1047. Gas 1047 is sometimes called a secondary carrier gas. Examples of gases 1047 include helium and algonine. Inert gases such as nitrogen can be used.

[0248] Until the supply of vaporized precursor and secondary carrier gas stabilizes, the precursor, It is preferable not to supply the secondary carrier gas to the deposition chamber 1008 or 1009, but to exhaust it. It is so. At this time, by closing valve 1049a and opening valve 1049b, the pre-cycle It can exhaust the carburetor and secondary carrier gas.

[0249] Once the supply of vaporized precursor and secondary carrier gas is stable, valve 1049a Open and close valve 1049b. The precursor and secondary carrier gas enter the deposition chamber 10 By supplying to 08 or 1009, a desired film is formed on the wafer 1012. It is possible.

[0250] As described above, by exhausting the precursor and secondary carrier gas before they stabilize, A desired amount of precursor, or a desired mixing ratio of precursor, is deposited into deposition chamber 1008 or 1009. A carrier can be supplied. The precursor and secondary carrier gas can be discharged before they stabilize. By doing so, it is possible to form a film of a desired quality or desired thickness on the wafer 1012. This is desirable because it improves the uniformity of the formed film.

[0251] Furthermore, the precursor and secondary carrier gas that have passed through valve 1049a are supplied with gas 105 0 may be mixed in. As gas 1050, for example, reaction gas such as oxidizing gas or nitriding gas. It is preferable to use a oxidizing gas. Oxygen, ozone, etc., can be used as the oxidizing gas. Furthermore, nitrogen, nitrous oxide, nitrogen dioxide, ammonia, etc., are used as nitriding gases. The supply of gas 1050 can be controlled by valve 1051. Alternatively, a mass flow controller or the like may be provided to control the supply amount of gas 1050.

[0252] Here, the precursor vaporized by the vaporization unit 1048 liquefies or solidifies due to temperature changes. There is a risk that this may happen. For example, in cases where powders of the components contained in the precursor are generated due to solidification. There is a fit. Therefore, the piping from the vaporization section 1048 to the film formation chamber 1008 or 1009, It is preferable to heat the membrane chamber 1008, the film deposition chamber 1009, and the exhaust piping. The heating temperature of the exhaust piping is preferably higher than the heating temperature in the vaporization section. The heating temperatures of 1008 and the deposition chamber 1009 affect the film quality, film uniformity, and deposition rate. The implementer can make decisions as appropriate, taking these factors into consideration.

[0253] As described above, the film deposition method using a vaporized precursor allows for the determination of film thickness and film quality. It is possible to form a highly uniform film. Furthermore, even on surfaces with irregularities, the surface coverage rate is high. The ratio is high, especially in openings with a large aspect ratio, relative to the bottom and sides of the opening. It is possible to form a film with high uniformity in quality and thickness.

[0254] Here, as an example of an apparatus capable of forming films using the MOCVD method, we have a film deposition apparatus 100. An example of configuration 0 will be explained using Figures 52A and 52B. Figure 52A shows a multi-cha Figure 52B is a schematic diagram of a vacuum-type film deposition apparatus 1000, and is a cross-sectional view of the film deposition chamber 1008. .

[0255] <Example of a film deposition apparatus configuration> The film deposition apparatus 1000 includes a cassette chamber 1002, an alignment chamber 1004, and a transport chamber 100 6, deposition chamber 1008, deposition chamber 1009, cooling chamber 1010, and transport arm 10 It has 14 and the transport arm 1014 which can transport the wafer 1012. Here, cassette chamber 1002, alignment chamber 1004, film deposition chamber 1008, film deposition chamber 10 09. The cooling chamber 1010 is connected to the transport chamber 1006. This connects to the film deposition chamber. Continuous film deposition can be performed in 1008 and the deposition chamber 1009 without exposure to the atmosphere. Furthermore, it is possible to prevent impurities from being mixed into the film. Also, at the interface between the substrate and the film, and at each film Contamination of the interface is reduced, resulting in a clean interface.

[0256] The cassette chamber 1002 can accommodate a cassette having multiple wafers 1012. The cassette can be placed one or more times. The cassette is carried by the transport arm 1014. The wafer 1012 is removed from the cassette chamber 1002, and after processing such as film deposition, it is returned to the cassette chamber 1002. It's returned to Nozomi's cassette.

[0257] In the alignment chamber 1004, the position of the wafer 1012 on the transport arm 1014 is adjusted. The wafer 1012 removed from the cassette chamber 1002 is deposited in the deposition chamber 1008, or 1 It is preferable to perform position adjustment before transporting to 009. Also, after processing such as film formation, the cassette Position adjustment may be performed before returning the wafer 1012 to chamber 1002.

[0258] In deposition chambers 1008 and 1009, film deposition is performed on wafer 1012.

[0259] In the cooling chamber 1010, wafers processed in the deposition chamber 1008 or deposition chamber 1009 are processed. Temperature control is performed in 1012. For example, this is done in deposition chamber 1008 or deposition chamber 1009. When processing is carried out in a heated atmosphere, in order to suppress the rapid cooling of the heated wafer 1012, It is preferable to adjust the temperature in the ring chamber 1010 and then transport the contents to the cassette chamber 1002. It's nice.

[0260] Note that the cassette room 1002, alignment room 1004, transport room 1006, and film deposition room 1008 The deposition chamber 1009 and the cooling chamber 1010 have their dew points controlled to prevent moisture from adhering to them. It is preferable to fill it with an inert gas (such as nitrogen gas) that has been filled, and to maintain a reduced pressure. is desirable.

[0261] In addition, an MOCVD apparatus can be used in the film formation chambers 1008 and 1009. Further, it may be configured to use a film forming apparatus other than the ALD apparatus in either the film formation chamber 1008 or the film formation chamber 1009. The film forming apparatus used in the film formation chambers 1008 and 1009 For example, there are a sputtering apparatus, a PECVD apparatus, a TCVD apparatus, an ALD apparatus, etc. etc. There is.

[0262] In addition, the film forming apparatus 1000 has a cassette chamber 1002, an alignment chamber 1004, a transfer chamber 10 06, a film formation chamber 1008, a film formation chamber 1009, and a cooling chamber 1010. However, the present invention is not limited to this. The film formation chamber of the film forming apparatus 1000 may be configured to have three or more, or a configuration may be added with a processing chamber for performing heat treatment or plasma treatment. In addition, the film forming apparatus 1000 may be a single wafer type, or may be a batch type for forming films on a plurality of substrates at once. It may be.

[0263] <MOCVD apparatus> Next, the configuration when an MOCVD apparatus is used as the film formation chamber 1008 will be described with reference to FIG. 52B. The film formation chamber 1008 has a bottom outer wall 1021, a side outer wall 1022, and an upper outer wall 1023. A raw material inlet 1025 and a shower plate 10 24 are provided on the upper outer wall 1023. A gate valve 1028 for loading and unloading the wafer 1012 is provided on the side outer wall 1022. An exhaust portion 1026, an exhaust valve 1 027, and a stage 1029 are provided on the bottom outer wall 1021. Note that the bottom outer wall 1021, the side outer wall 1022, 027, and a stage 1029 are provided. Furthermore, the upper outer wall 1023 is provided with a heater for controlling the temperature during film formation. Preferred. Note that the bottom outer wall 1021, the side outer wall 1022, and the upper outer wall 1023 must It does not need to be provided independently. For example, the bottom outer wall 1021, the side outer wall 1022, The upper outer wall 1023 may be integrally formed. Also, the bottom outer wall 1021 and the side The outer wall 1022 may be integrally formed, and the upper outer wall 1023 may function as a lid.

[0264] The gas containing the precursor vaporized by the vaporization unit 1048 enters the film deposition chamber from the raw material inlet 1025. 1008 is introduced and, via shower plate 1024, wafer 1 on stage 1029 It is supplied to 012. The supplied gas deposits on wafer 1012, forming a film. The gases not used in film formation, and the excess gases, are discharged from the exhaust section 1026 to the film deposition chamber 1008. The exhaust is released outside.

[0265] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0266] (Embodiment 4) This embodiment describes the circuit configuration and operation of the memory string 120, which is a storage device. To clarify, Figure 53 shows an example of the circuit configuration of the memory string 120. The circuit configuration example can also be applied to the memory string 120s. Therefore, in this embodiment... And, you can read "memory string 120" as "memory string 120s". can.

[0267] <Example of a memory string circuit configuration> Figure 53 shows the circuit configuration when the number of memory elements MC in the memory string 120 is n = 5. An example is shown. As described in the above embodiment, the memory element MC is a transistor WTr It also has a transistor RTr.

[0268] Furthermore, in equivalent circuit diagrams, etc., it should be explicitly stated that the transistor is an OS transistor. For this reason, the "OS" is sometimes added to the circuit symbol for a transistor. Similarly, A Si transistor (a transistor that uses silicon in the semiconductor layer where the channel is formed) In order to clearly indicate that it is a transistor, the letter "Si" is sometimes added to the circuit symbol for a transistor. In Figure 53, transistors WTr and RTr are OS transistors. This indicates that...

[0269] Figure 54 shows the equivalent circuit diagram of the memory element MC. It can be expressed by replacing capacitance Cs and transistor Tr. The terminal is electrically connected to the conductor WWL via capacitance Cs.

[0270] In Figure 53, the transistor WTr included in the memory element MC[1] is shown as transistor WTr[ [1] is shown, and the transistor RTr included in the memory element MC[1] is represented as transistor RTr[ 1] is indicated. Therefore, the memory string 120 shown in Figure 53 is a transistor WT r[1] to transistor WTr[5], and transistor RTr[1] to transistor It has a stRTr[5]. Also, the memory string 120 shown in Figure 53 is a transient It has transistor STr1 and transistor STr2. The memory string 120 is NAND It is a type of memory device.

[0271] NAND type storage devices that include OS memory are called "OS NAND type" or "OS NAND It is also called a "type of memory device." Furthermore, it has a configuration in which multiple OS memories are stacked in the Z direction. S NAND type storage device is called "3D OS NAND type" or "3D OS NAND It is also called a "type of memory device."

[0272] Either the source or drain of transistor RTr[1] is connected to the source of transistor STr1. One of the sockets or drains is electrically connected, and the other is connected to the socket of transistor RTr[2] It is electrically connected to either the source or the drain of transistor WTr[1]. One side of the drain is electrically connected to the gate of transistor RTr[1], and the other side is connected to the transistor It is electrically connected to either the source or drain of the transistor WTr[2]. The back gate of the transistor RTr[1] is electrically connected to the conductor RWL[1]. The gate of the WTr[1] is electrically connected to the conductor WWL[1]. Also, the transistor The back gate of the transistor [1] is electrically connected to the conductor BG. The source or drain of STr1 is electrically connected to the conductor 122, and the gate is connected to the conductor It is electrically connected to the SG (Spark Generator).

[0273] Furthermore, either the source or the drain of transistor RTr[5] [4] is electrically connected to the other of the source or drain of transistor STr2 The source or drain of transistor RTr[5] is electrically connected. The terminal is electrically connected to either the source or the drain of transistor WTr[5]. The source or drain of transistor WTr[5] is the other of transistor STr2 It is electrically connected to either the drain or the casing of the transistor RTr[5]. The gate is electrically connected to the conductor RWL[5]. The gate of transistor WTr[5] is It is electrically connected to the conductor WWL[5]. Also, the backgear of the transistor WTr[5] The terminal is electrically connected to the conductive BG. Also, the source or terminal of transistor STr2. The other end of the rain is electrically connected to conductor BL, and the gate is electrically connected to conductor SEL. It can be done.

[0274] If the memory string 120 has n memory elements MC, the 1st and nth memory elements In the i-th memory element MC[i] (where i is an integer between 1 and n), excluding MC, Either the source or drain of transistor RTr[i] is connected to the source of transistor RTr[i-1]. The other end is electrically connected to the drain or the other end of transistor RTr[i+1] The gate of transistor RTr[i] is electrically connected to either the source or the drain. It is electrically connected to either the source or the drain of transistor WTr[i]. The source or drain of transistor WTr[i] is connected to transistor WTr[i+1]. It is electrically connected to either the source or drain of transistor RTr[i]. The gate of transistor WTr[i] is electrically connected to the conductor RWL[i]. The terminal is electrically connected to the conductor WWL[i]. Also, the terminal of transistor WTr[i] The gate is electrically connected to the conductive backing (BG).

[0275] Also, the gate of transistor RTr and the source or drain of transistor WTr The node at which the two sides are electrically connected is defined as node ND. That is, the transistor RTr[i] The gate is electrically connected to either the source or the drain of transistor WTr[i]. Let the node be denoted as node ND[i]. In Figure 53, node ND is included in memory element MC[1]. This is indicated as node ND[1].

[0276] Transistors STr1 and STr2 are, for example, OS transistors. It may be a Si transistor, or it may be a Si transistor. Transistor STr1 and Transis One of the STr2 transistors may be an OS transistor and the other a Si transistor. In a case where both transistor WTr and transistor RTr are formed with OS transistors In this case, transistors STr1 and STr2 are also formed from OS transistors. This is preferable. By providing semiconductor materials for use in transistors, the productivity of semiconductor devices can be increased. It can improve.

[0277] Furthermore, an OS transistor is used for the WTr transistor, and a Si transistor is used for the RTr transistor. A zista may be used. An OS transistor is used as the transistor WTr, and the transistor Equivalent circuit diagram of memory string 120 when using a Si transistor as RTr. This is shown in Figure 55.

[0278] When forming the transistor RTr with a Si transistor, the semiconductor 125 is, for example, polycrystalline. Silicon can be used. When forming a WTr transistor with an OS transistor, For example, CAAC-IGZO can be used for conductor 127.

[0279] Furthermore, as shown in Figure 56, depending on the purpose or application, the transistor WTr may be used A Si transistor may be used, and an OS transistor may be used as the transistor RTr. Furthermore, as shown in Figure 57, depending on the purpose or application, the transistor WTr and Si transistors may be used for both transistors RTr. When using Si transistors for both transistors STr1, Furthermore, it is preferable to use a Si transistor for transistor STr2 as well.

[0280] <Example of memory string operation> Next, we will explain an example of the operation of the memory string 120 shown in Figure 53.

[0281] [Writing operation] In this embodiment, an H potential is written to memory element MC[1] and memory element MC[3]. An example of operation when writing an L potential to another memory element MC is explained. Figure 58 shows the writing operation. This is a timing chart for explanation. Figures 59A to 62B illustrate the writing operation. This is the circuit diagram. Note that symbols not shown in Figures 59A to 62B are shown in Figure 53. These are some things to consider.

[0282] Initially, an L potential is written to memory element MC[1] through memory element MC[5]. It shall be so. Also, conductors WWL[1] to WWL[5], conductors RWL[1] To conductor RWL[5], conductor SEL, conductor BG, conductor BL, conductor SG, and Assume that an L potential is supplied to the conductor 122. Furthermore, the potential supplied to the conductor BG is By adjusting it, the threshold of transistor RTr can be controlled. To make it a normally-on type transistor, the potential supplied to the conductive BG is adjusted as appropriate. That's good too.

[0283] [Period T1] During period T1, the conductors WWL[1] to WWL[5], conductor BL, and A high potential is supplied to the electrostatic SEL (see Figure 59A). Then, nodes ND[1] to Node 59[1] The potential of ND[5] becomes the H potential.

[0284] [Period T2] During period T2, an L potential is supplied to the conductor WWL[1] (see Figure 59B). , transistor WTr[1] turns off, and the charge written to node ND[1] It is retained. Here, a charge corresponding to the H potential is retained.

[0285] [Period T3] During period T3, an L potential is supplied to the conductor BL (see Figure 59B). Then, the node The potential of ND[2] through node ND[5] becomes L potential. In this case, transistor RTr [2] The gate of transistor RTr[5] is also at an L potential, but transistor RTr is Because it is a normally-on type transistor, the transistor RTr[2] or the transistor RTr[5] does not go into the off state.

[0286] [Period T4] During period T4, an L potential is supplied to the conductor WWL[2] (see Figure 60A). , the transistor WTr[2] turns off, and the charge written to node ND[2] It is retained. Here, a charge corresponding to the L potential is retained.

[0287] [Period T5] During period T5, a high potential is supplied to the conductor BL (see Figure 60B). Then, the node [3] or node [5] becomes the H potential.

[0288] [Period T6] During period T6, an L potential is supplied to the conductor WWL[3] (see Figure 61A). , the transistor WTr[3] turns off, and the charge written to node ND[3] It is retained. Here, a charge corresponding to the H potential is retained.

[0289] [Period T7] During period T7, an L potential is supplied to the conductor BL (see Figure 61B). Then, the node The potentials at ND[4] and node ND[5] become L potential.

[0290] [Period T8] During period T8, an L potential is supplied to the conductor WWL[4] (see Figure 62A). , the transistor WTr[4] turns off, and the charge written to node ND[4] It is retained. Here, a charge corresponding to the L potential is retained.

[0291] [Period T9] During period T9, the conductor BL remains at L potential. Therefore, the potential of node ND[5] It remains at the L potential.

[0292] [Period T10] During period T10, an L potential is supplied to the conductor WWL[5] (see Figure 62B). Then, transistor WTr[5] turns off, and the charge written to node ND[5] This is maintained. Here, a charge corresponding to the L potential is maintained. Also, L is maintained in the conductor SEL. Supply an electric potential.

[0293] In this way, information can be written to the memory element MC.

[0294] Furthermore, information is written to the i-th memory element MC (excluding i=1) among the multiple memory elements MC. If this is the case, the write operation for the first i-1 memory elements MC will be omitted. This is possible. For example, if you want to write information to memory element MC[4], you can write to memory element MC[1 It is not necessary to perform an information writing operation to the memory element MC[3]. Thus, the write operations from period T1 to period T6 shown in this embodiment can be omitted. Therefore, the time required for writing to the memory device and the power consumption can be reduced.

[0295] [Read operation] An example of the read operation of the memory string 120 in the above circuit configuration will be explained. Initially, A high potential is maintained in memory element MC[1] and memory element MC[3], and memory element MC[2] Assume that an L potential is maintained in memory element MC[4] and memory element MC[5]. Also, conductors WWL[1] to WWL[5], conductors RWL[1] to R WL[5], conductor SEL, conductor BG, conductor BL, conductor SG, and conductor 122 Assume that an L potential is supplied. Figures 63A and 63B illustrate the readout operation. This is a timing chart. Figures 64A, 64B, 65A, and 65B are readouts. This is a circuit diagram to explain the operation. Note that Figures 64A, 64B, 65A, and For symbols and other details not listed in 65B, please refer to Figure 53, etc.

[0296] ≪When the holding potential is H potential≫ First, we will explain the read operation of the memory element MC[3] in which the H potential is maintained.

[0297] [Period T11] During period T11, the conductors RWL[1] to RWL[5] and SEL A high potential is supplied to it (see Figure 64A). Then, transistor STr2 turns on. As a result, the semiconductor 125 of the transistor RTr and the conductor BL become electrically connected. In this state, the conductor BL and semiconductor 125 are precharged with a high potential, and both are in a floating state. I'll do that.

[0298] Here, we will explain the Id-Vg characteristics of the transistor. (Figures 66A and 66B) This is a diagram illustrating the Id-Vg characteristics of a transistor. (Horizontal axis of Figures 66A and 66B) The vertical axis shows the gate voltage (Vg), and the vertical axis shows the drain current (Id). Figure 66A shows the normally occurring voltage. - The Id-Vg characteristics of an off-type transistor are shown, and Figure 66B shows the Id-Vg characteristics of a normally-on type transistor. This shows the Id-Vg characteristics of the device.

[0299] The H potential is a higher potential than the L potential. If the L potential is 0V, then the H potential is a positive voltage. In a normally-off type transistor, the channel resistance value (s) when Vg is at low potential (0V) is... The resistance between the drain and the outlet is extremely high, so Id hardly flows. Also, Vg is high. At this level, the channel resistance decreases and Id increases (see Figure 66A).

[0300] In normally-on transistors, the channel resistance is small even when Vg is at an inductive potential. Compared to a Marie-off type transistor, more Id flows. Also, Vg becomes high potential. This further reduces the channel resistance and increases Id (see Figure 66B).

[0301] Since transistor RTr is a normally-on type transistor, the potential of the conductor RWL is Even if the conductor remains at an L potential, precharging of semiconductor 125 is possible. However, By supplying a high potential to the RWL, the channel resistance of transistor RTr is further reduced. Yes. Therefore, the time and power consumption required for precharging can be reduced.

[0302] [Period T12] During period T12, an L potential is supplied to the conductor RWL[3] (see Figure 64B). A high potential is maintained in ND[3]. Therefore, the potential of the conductor RWL[3] is low. Even at this position, the channel resistance of transistor RTr[3] is L-voltage to node ND[3]. It is smaller than when the position is preserved.

[0303] [Period T13] During period T13, a high potential is supplied to the conductor SG, turning on transistor STr1. (See Figure 65A.) Then, conductor BL and conductor 122 become electrically connected. Conductive RWL[1], Conductive RWL[2], Conductive RWL[4], and Conductive RWL [5] Since an H potential is supplied to transistor RTr[1], transistor RTr [2], transistor RTr[4], and channel resistance of transistor RTr[5] This becomes small regardless of the potential of node ND. Also, as mentioned above, the conductor RWL[3] Although an L potential is supplied to node ND[3], an H potential is held at node ND[3], so The channel resistance of the inverter RTr[3] is small. Therefore, floating The potential of the conductor BL, which is in the state of low potential, changes rapidly from high potential to low potential (see Figure 63A).

[0304] [Period T14] During period T14, an L potential is supplied to the conductor SEL, conductor RWL, and conductor SG. (See Figure 65B.)

[0305] ≪When the holding potential is L potential≫ Next, the read operation of the memory element MC[2], which holds an L potential, will be described. When reading out the information (potential) held in the memory element MC[2], in period T12 , the potential of the conductor RWL[2] is set to L potential (see Figure 63B). At this time, node ND[ Since an L potential is maintained in [2], the channel resistance of transistor RTr[2] is NO This is greater than when the H potential is maintained at ND[2].

[0306] Next, during period T13, a high potential is supplied to the conductor SG, and the conductors BL and 122 are... To make it conduction. At this time, because the channel resistance of transistor RTr[2] is large, The potential of the electrostatic body BL changes gradually from high potential to low potential.

[0307] Thus, during period T13, the conductor RWL corresponding to the memory element MC to be read out By setting the potential to an L potential and detecting the potential change of the conductor BL, the data is stored in the memory element MC. You can access the information that is being shared.

[0308] <Variation> Figure 67 shows the circuit configuration of memory string 120A, which is a modified version of memory string 120. For example, memory string 120A has a transistor STr connected to memory string 120. It has a circuit configuration with the addition of 3.

[0309] In the memory string 120A shown in Figure 67, the source of transistor RTr[5] or The other side of the drain is not one of the source or drain of transistor STr2, Connect electrically to either the source or drain of transistor STr3. The source or drain of STr3 is electrically connected to the conductor BL. The gate of transistor STr2 is electrically connected to the conductor WSEL, and transistor STr Gate 3 is electrically connected to the conductor RSEL.

[0310] Figure 68 is a timing chart illustrating the write operation of memory string 120A. Figure 69 is a timing chart illustrating the read operation of memory string 120A. That is the case.

[0311] In memory string 120A, a high potential is supplied to the conductor WSEL during the write operation, It supplies an L potential to the RSEL (electrical component). It also supplies an L potential to the WSEL (conductor) during readout operations. This supplies a high potential to the conductor RSEL. Therefore, during the write operation, the transistor ST When r2 is turned on, transistor STr3 is turned off. During readout operation, Transistor STr2 turns off, and transistor STr3 turns on. Conductor B When writing or reading information via L, a dedicated transistor is used for each. The information transmission path can be switched. Therefore, the operation of the memory becomes stable, and the memory This can increase its reliability.

[0312] Also, memory string 120, memory string 120A, and the memory string described later In ring 120B and other devices, during operations other than writing, the conductor BG is at a potential higher than L. It is preferable to supply a low potential (also called "LL potential"). LL potential to the conductor BG. By supplying this, the transistor WTr can be more reliably turned off. This allows information written to node ND to be retained for a longer period of time.

[0313] Also, memory string 120, memory string 120A, and the memory string described later In ring 120B and other devices, a potential higher than the L potential is supplied to the conductor BG during the writing operation. It may be supplied. For example, a high potential may be supplied to the conductive BG during the writing operation. During operation, supplying a high potential to the conductor BG reduces the resistance of semiconductor 127. This can increase the writing speed.

[0314] Furthermore, as shown in Figure 70, the source or drain of transistor STr2 is conductive Electrically connect to the body WBL and conduct the other of the source or drain of transistor STr3. The RBL body may be electrically connected. During writing operations, information is written via the conductive WBL. During the write operation, information is read via the conductive RBL. By providing dedicated conductive elements BL for both the input and read operations, the operation of the memory device becomes more stable. This can improve the reliability of storage devices.

[0315] The memory string 120B shown in Figure 71 has a transistor S connected to the memory string 120A. The circuit configuration includes an additional Tr4. One of the sources or drains of transistor STr4. One side is electrically connected to either the source or drain of transistor WTr[1], and the other side The side is electrically connected to the conductor WBL[2]. The gate of transistor STr4 is a conductor. It is electrically connected to WSEL[2].

[0316] Furthermore, in memory string 120B, the gate of transistor STr2 is a conductor WSEL. [1] is electrically connected to and the other of the source or drain of transistor STr2 is conductive It is electrically connected to the body WBL[1]. Note that, as shown in Figure 67, transistor ST The circuit configuration may also involve electrically connecting r2 and transistor STr3 with the conductor BL. .

[0317] Memory string 120B writes information to conductor WBL[1] and conductor WBL [2] This can be done from both sides. Therefore, the speed of information writing can be increased. Furthermore, it becomes possible to more reliably supply the electric charge corresponding to the information being written.

[0318] Also, when writing information to the i-th memory element MC, if i is close to n, the conductor WBL[ By writing information from side 1, the information of memory elements MC from the 1st to i-1th element is written. The writing operation can be omitted. Also, if i is close to 1, the conductor WBL[2] side By writing information, the writing operation of information to memory elements MC from the i+1th to the nth element is performed. The process can be omitted. In memory string 120B, the time required for the write operation This allows for further reduction in power consumption.

[0319] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0320] (Embodiment 5) In this embodiment, an example configuration of a semiconductor device 200 including a storage device 100 will be described. In addition, storage device 100A may be used instead of storage device 100. Unless otherwise specified, storage device 100A can be used instead of storage device 100. It shall be assumed that...

[0321] Figure 72 shows a block diagram illustrating an example configuration of a semiconductor device 200 according to one aspect of the present invention. The semiconductor device 200 shown in 72 includes a drive circuit 210 and a memory array 220. The memory array 220 has one or more storage devices 100. In Figure 72, the memory array 2 The diagram shows an example having multiple storage devices 100 arranged in a matrix.

[0322] The drive circuit 210 includes PSW241 (power switch), PSW242, and peripheral circuit 2 It has 15. Peripheral circuit 215 is peripheral circuit 211 (Row Decoder), control It includes a roll circuit 212 (Control Circuit) and a voltage generation circuit 228. The semiconductor device 200 includes a memory array 220, PSW241, 242, and peripheral circuits. Elements with various functions such as path 211, control circuit 212, and voltage generation circuit 228 Or it has circuits, etc. Therefore, the semiconductor device 200 is a system or subsystem. It may also be called that.

[0323] In the semiconductor device 200, each circuit, each signal, and each voltage are selected and discarded as necessary. This is possible. Alternatively, other circuits or other signals may be added. Signal BW, signal CE, signal GW, signal CLK, signal WAKE, signal ADDR, signal WDA, signal PON1 Signal PON2 is an external input signal, and signal RDA is an external output signal. CLK is the clock signal.

[0324] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip-in signal. The signal GW is a global write enable signal, and the signal BW is a global write enable signal. The write enable signal. The ADDR signal is the address signal. The WDA signal is the write enable signal. This is the written data, and signal RDA is the read data. Signal PON1, signal PON2 These are signals for power gating control. Note that signals PON1 and PON2 are... It may also be generated by the troll circuit 212.

[0325] The control circuit 212 has a logic control function that controls the overall operation of the semiconductor device 200. It is a logic circuit. For example, a control circuit uses signals CE, GW, and BW to logic. The system performs calculations to determine the operating mode of the semiconductor device 200 (e.g., write operation, read operation). Determine. Alternatively, the control circuit 212 controls the peripheral so that this operating mode is performed. Generates control signals for circuit 211.

[0326] The voltage generation circuit 228 has the function of generating a negative voltage. The signal WAKE is the power of the signal CLK. It has the function of controlling the input to the pressure generation circuit 228. For example, when the WAKE signal is high level... When a signal is applied, the signal CLK is input to the voltage generation circuit 228. This generates a negative voltage.

[0327] The peripheral circuit 211 is used to write and read data to and from the storage device 100. This is the circuit. The peripheral circuit 211 is a row decoder 221, row Decoder 222 (Column Decoder), Row Driver 223 (Row Driver) ver), Column Driver 224, Input Circuit 225 ut Cir.), output circuit 226 (Output Cir.), sense amplifier 227 ( It has a sense amplifier.

[0328] The row decoder 221 and column decoder 222 have the function of decoding the signal ADDR. The row decoder 221 is a circuit for specifying the row to access, and the column decoder 222 This is a circuit for specifying the column to access. The row driver 223 controls the row decoder 22 It has the function of selecting the wiring WL specified by 1. The column driver 224 stores data in storage. Function to write to 100, function to read data from memory device 100, read data It has functions such as holding.

[0329] The input circuit 225 has the function of holding the signal WDA. The data held by the input circuit 225 The output is sent to the column driver 224. The output data from the input circuit 225 is sent to the storage device 100. This is the data (Din) to be written. The column driver 224 read it from the storage device 100. The data (Dout) is output to the output circuit 226. The output circuit 226 retains Dout. It has the function of holding. In addition, the output circuit 226 outputs Dout to the outside of the semiconductor device 200. It has the function of performing an action. The data output from output circuit 226 is the RDA signal.

[0330] PSW241 has the function of controlling the supply of VDD to peripheral circuit 215. PSW242 It has the function of controlling the supply of VHM to the row driver 223. Here, semiconductor device The high power supply voltage of 200 is VDD, and the low power supply voltage is GND (ground potential). Also, V HM is a high supply voltage used to raise the word line to a high level, and is higher than VDD. The on / off state of PSW241 is controlled by signal PON1, and by signal PON2. The on / off state of PSW242 is controlled. In Figure 72, in peripheral circuit 215, VDD The number of power domains supplied is set to 1, but it can be multiple. In this case, A power switch should be provided for each power domain.

[0331] The drive circuit 210 and the memory array 220 may be provided on the same plane. Also, as shown in Figure 73A The drive circuit 210 and the memory array 220 may be arranged in a stacked manner. By stacking the memory array 220, the signal propagation distance can be shortened. Furthermore, as shown in Figure 73B, multiple memory arrays 220 are stacked on top of the drive circuit 210. That's fine.

[0332] Furthermore, as shown in Figure 73C, the memory array 220 is located on the upper and lower layers of the drive circuit 210. A memory module may be provided. In Figure 73C, one memory module is provided on the upper and lower layers of the drive circuit 210. This shows an example of providing a rear array 220. The drive circuit 210 is used with multiple memory arrays 220. By arranging them in a sandwich-like manner, the signal propagation distance can be further shortened. A memory array 220 is stacked on top of the path 210, and a drive circuit 210 is stacked on the lower layer Each layer of the memory array 220 only needs to be one or more. The number of stacked memory arrays 220 and the memory arrays stacked below the drive circuit 210 It is preferable that the number 220 is equal.

[0333] <Example of cross-sectional configuration of a semiconductor device> Figure 74 shows an example of the cross-sectional configuration of the semiconductor device 200 shown in Figure 73A. Figure 75 shows a portion of the semiconductor device 200 shown in Figure 73A. Figure 75 shows an example of a cross-sectional configuration when 200 is replaced with semiconductor device 200A. This shows a portion of 200A.

[0334] In Figure 74, the drive circuit 210 includes transistors 301, 302, and This refers to transistor 303. Note that transistors 301 and 3 02 functions as part of the sense amplifier 304. Transistor 303 is also column selector. It functions as a switch. Specifically, the conductor BL included in the memory array 220 is Electrically connect to either the source or drain of transistor 301. The gate of the transistor is electrically connected to either the source or the drain of transistor 302, The gate of transistor 302 is electrically connected to the other side of the source and drain of transistor 301. Connect to the transistor 301. Also, connect to one of the source and drain of transistor 301 and the transistor The source and drain of 302 are transistors that function as column selection switches. It is electrically connected to either the source or drain of 303. This connects to semiconductor device 200. The layout area can be reduced. Note that Figure 74 shows one memory string. This example shows a configuration with 7 memory elements MC. However, one memory string is used. The number of memory elements MCs provided in a single memory string is not limited to this. The number of memory elements MC may be 32, 64, 128, or 200 or more.

[0335] The conductor BL of the memory array 220 is embedded in insulators 726 and 722, etc. Conductors 752, 705, 714, and 715 are formed in such a manner. , via the sense amplifier 304 and transistor 303 which functions as a column selection switch It is electrically connected to it. Note that the circuits and transistors of the drive circuit 210 are, for example, Yes, and it is not limited to the circuit configuration or transistor structure. In addition to the above, control circuits, The configuration of the semiconductor device 200, including decoders, line drivers, source line drivers, input / output circuits, etc. Depending on the driving method, appropriate circuits and transistors can be provided.

[0336] Transistors 301, 302, and 303 are located on substrate 311. These are semiconductors provided therein, each consisting of a conductor 316, an insulator 315, and a part of the substrate 311. Region 313, and low-resistance region 314a which functions as a source region or drain region, and has a low-resistance region 314b. Note that, as shown in Figure 74, one low-resistance region is The source region or drain region of transistors 301 and 302 Furthermore, it may be shared as the source or drain area of ​​the other system.

[0337] Transistors 301, 302, and 303 form a channel. The resulting semiconductor region 313 (part of the substrate 311) has a convex shape. The sides and top surface of 13 are covered by a conductor 316 via an insulator 315. It is present. Furthermore, the conductor 316 may be made of a material that adjusts the work function. Transistor 301, transistor 302, and transistor 303 utilize the protrusions of the semiconductor substrate. It is also called a FIN type transistor because it uses this feature. Furthermore, the upper part of the convex part is in contact with the convex part. It may have an insulator that functions as a mask for forming the part. Also, here it is a semi The example shown involves processing a portion of a conductive substrate to form a protrusion, but the example also shows how to process an SOI substrate to create a protrusion. A semiconductor film having the following properties may be formed.

[0338] Transistors 301, 302, and 303 are each p-type Either a channel type or an n-channel type is acceptable, but transistor 301 and the transistor It is preferable that each of the 302 transistors has a different polarity.

[0339] The region where the channel of the semiconductor region 313 is formed, the region near it, the source region, or the do In the low-resistance region 314a and low-resistance region 314b, which are rain regions, silico It is preferable that the semiconductor contains semiconductors such as silicon-based semiconductors, and it is preferable that it contains single-crystal silicon. Alternatively, Ge (germanium), SiGe (silicon germanium), GaAs (galvanium) It may also be formed from materials containing arginine, GaAlAs (gallium aluminum arsenide), etc. By applying stress to the crystal lattice and changing the lattice spacing, silicon with controlled effective mass is produced. The configuration used may also be used. Alternatively, by using GaAs and GaAlAs, etc., the transient Transistor 301, transistor 302, and transistor 303 are HEMT (High El It can also be called an ectron (Mobility Transistor).

[0340] Low-resistance regions 314a and 314b are semiconductor regions applied to semiconductor region 313. In addition to the main material, elements that impart n-type conductivity, such as arsenic and phosphorus, or p-type conductivity, such as boron. It contains elements that impart conductivity.

[0341] Insulator 315 is connected to transistors 301, 302, and 303 It functions as a gate insulating film.

[0342] The conductor 316, which functions as a gate electrode, is a component that imparts n-type conductivity, such as arsenic or phosphorus. Semiconductor materials such as silicon containing elements that impart p-type conductivity, such as boron or other elements. Conductive materials such as metallic materials, alloy materials, or metal oxide materials can be used.

[0343] Furthermore, since the work function is determined by the material of the conductor, changing the material of the conductor will result in... The voltage can be adjusted. Specifically, the conductive material can be titanium nitride or tantalum nitride. It is preferable to use the following material. Furthermore, in order to achieve both conductivity and embedding properties, the conductive material It is preferable to use metal materials such as tansten or aluminum as laminates, and especially tansten. Using gusten is preferable in terms of heat resistance.

[0344] Furthermore, an insulator 317, which functions as an etch stopper, is provided above the conductor 316. It is preferable that the sides of the insulator 315 have an insulating layer that functions as a spacer. It is preferable that a rim 318 is provided. Provide insulators 317 and 318. As a result, the low-resistance region 314a and the low-resistance region 314b are electrically connected to the conductor 328. The region can be determined in a self-consistent manner. Therefore, the low resistance region 314a, and the low resistance region An alignment error occurred when forming an opening to expose a portion of the anti-region 314b. Even so, an opening can be formed to expose the intended area. By forming a conductor 328 in the formed opening, a low-resistance region 314a and a low-resistance region are created. A good contact with reduced contact resistance is obtained between region 314b and conductor 328. The low-resistance region 314a and the low-resistance region 314b formed in this manner are conductive The contact with body 328 is sometimes called self-aligned contact. Also, the insulator 317 and the conductor 316 are electrically connected so as to be embedded in the insulator 322. An electric unit 329 may be provided.

[0345] An insulator covers transistors 301, 302, and 303. 320, insulator 322, insulator 324, insulator 326, and insulator 327 are stacked in order. It is provided as such.

[0346] As insulators 320, 322, 324, 326, and 327 For example, silicon oxide, silicon nitride oxide, silicon nitride oxide, silicon nitride oxide, silicon oxide Aluminum oxide nitride, aluminum nitride oxide, aluminum nitride, etc. Just be there.

[0347] The insulator 322 smooths out the step created by the transistor 301 and other components located below it. It may also function as a planarizing film that flattens. For example, the upper surface of the insulator 322 is flat To improve flatness, the surface is planarized using chemical mechanical polishing (CMP) or similar methods. It's okay to be there.

[0348] Furthermore, the insulator 324 receives memory signals from the substrate 311 or transistor 301, etc. A barrier film is used in the region where I-220 is provided to prevent the diffusion of hydrogen and impurities. It is preferable that they be present.

[0349] As an example of a film that has barrier properties against hydrogen, for example, silica nitride formed by CVD. A semiconductor element can be used. Here, a semiconductor element having an oxide semiconductor such as a memory element MC can be used. The diffusion of hydrogen may degrade the properties of the semiconductor element. Therefore, the memory element It is preferable to use a film that suppresses hydrogen diffusion between the MC and transistor 301, etc. Specifically, a membrane that suppresses hydrogen diffusion is a membrane that releases less hydrogen.

[0350] The amount of hydrogen desorbed can be analyzed, for example, using a thermodynamic desorption gas analysis (TDS) method. For example, the amount of hydrogen desorption from insulator 324 is determined in TDS analysis when the film surface temperature is 5 In the range of 0°C to 500°C, the amount of desorption converted to hydrogen atoms is per unit area of ​​insulator 324. Convert to units, 10 x 10 15 atoms / cm 2 The following is preferably 5 × 10 15 at oms / cm 2 The following is acceptable.

[0351] Furthermore, it is preferable that insulators 326 and 327 have a lower dielectric constant than insulator 324. For example, the relative permittivity of insulator 326 and insulator 327 is preferably less than 4, and 3 Less than is preferable. Also, for example, the relative permittivity of insulator 326 and insulator 327 is less than The relative permittivity of the edge body 324 is preferably 0.7 times or less, and more preferably 0.6 times or less. By using a material with low capacitance as the interlayer film, parasitic capacitance between wiring can be reduced.

[0352] Also, insulators 320, 322, 324, 326, and 327 The memory array 220 is electrically connected to conductors 328, 329, and conductors 330 etc. are embedded. Note that conductors 328, 329, and 330 It functions as a plug or wiring. In some cases, conductive materials may have multiple structures grouped together and assigned the same designation. In such cases, the wiring and the plug that electrically connects to the wiring may be a single integrated unit. Furthermore, when a portion of the conductor functions as wiring, and when a portion of the conductor functions as a plug... In some cases, this may be the case.

[0353] The materials of each plug and wiring (conductor 328, conductor 329, and conductor 330, etc.) Conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials. It can be used in a single layer or in a laminated form. Tungsten and other materials that offer both heat resistance and conductivity. It is preferable to use high-melting-point materials such as molybdenum, and it is also preferable to use tungsten. It is preferable to form it with a low-resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using resistive conductive materials.

[0354] A wiring layer may be provided on the insulator 327 and the conductor 330. For example, as shown in Figure 74 Insulators 350, 352, and 354 are arranged in a sequential stack. Furthermore, a conductor 356 is formed on insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring. It can be provided using the same material as conductors 328, 329, and 330. Cut.

[0355] For example, insulator 350 has a barrier property against hydrogen, similar to insulator 324. It is preferable to use an insulator. Furthermore, the conductor 356 has barrier properties against hydrogen. It is preferable that it contains a conductor. In particular, the insulator 350 having barrier properties against hydrogen is preferable. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, The transistor 301 and the memory element MC can be separated by a barrier layer, This can suppress the diffusion of hydrogen from ZISTA 301 and other sources to the memory element MC.

[0356] For example, tantalum nitride can be used as a conductor that has barrier properties against hydrogen. This is good. Also, by laminating tantalum nitride and highly conductive tungsten, the wiring can be It is possible to suppress the diffusion of hydrogen from transistor 301, etc., while maintaining conductivity. In this case, the tantalum nitride layer, which has barrier properties against hydrogen, acts as a barrier against hydrogen. It is preferable that the structure is in contact with an insulating material 350 having properties.

[0357] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, as shown in Figure 74 Insulators 360, 362, and 364 are arranged in a sequential stack. Furthermore, a conductor 366 is formed on insulators 360, 362, and 364. The conductor 366 functions as a plug or wiring. It can be provided using the same material as conductors 328, 329, and 330. Cut.

[0358] For example, insulator 360 has a barrier property against hydrogen, similar to insulator 324. It is preferable to use an insulator. Furthermore, the conductor 366 has barrier properties against hydrogen. It is preferable that it contains a conductor. In particular, the insulator 360 having barrier properties against hydrogen is preferable. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, The transistor 301 and the memory element MC can be separated by a barrier layer, This can suppress the diffusion of hydrogen from ZISTA 301 and other sources to the memory element MC.

[0359] An insulator 722 is provided on the insulator 364 and the conductor 366, and further insulator 722 Above it, a memory array 220 is provided. Between insulator 364 and insulator 722 Alternatively, a barrier film made of the same material as the insulator 324 may be provided.

[0360] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0361] (Embodiment 6) In this embodiment, Figures 76A and 76B are used to show a semiconductor in which the storage device of the present invention is mounted. An example of a chip 1200, a type of conductive device, is shown. The chip 1200 contains multiple circuits ( The system is implemented. In this way, multiple circuits (systems) are integrated onto a single chip. The combined technologies are referred to as System on Chip (SoC). There is a match.

[0362] As shown in Figure 76A, the chip 1200 is a CPU 1211, a GPU 1212, or Multiple analog arithmetic units 1213, one or more memory controllers 1214, one or It has multiple interfaces 1215, one or more network circuits 1216, etc. .

[0363] The chip 1200 is provided with bumps (not shown), and as shown in Figure 76B, The first side of the Printed Circuit Board (PCB) 1201 and Connect. Also, multiple bumps 1202 are provided on the back surface of the first face of PCB1201. It is connected to the motherboard 1203.

[0364] Motherboard 1203 includes storage devices such as DRAM 1221 and flash memory 1222. A semiconductor may be provided as the flash memory 1222. It is preferable to use a device. The semiconductor device shown in the above embodiment is a flash memory 1 By using it in 222, the storage capacity of flash memory 1222 can be increased. .

[0365] CPU1211 preferably has multiple CPU cores. Also, GPU1212 is It is preferable to have multiple GPU cores. Also, CPU1211 and GPU12 Each of the 12 components may have memory to temporarily store data. Alternatively, the CPU Even if memory common to both 1211 and GPU1212 is provided on chip 1200 Good. Also, the GPU1212 is suitable for parallel computation of large amounts of data, such as image processing and sum-of-products. It can be used for calculations. The GPU1212 is equipped with image processing circuits and multiply-accumulate circuits. This makes it possible to perform image processing and multiply-accumulate operations with low power consumption.

[0366] Furthermore, because the CPU1211 and GPU1212 are located on the same chip, C The wiring between PU1211 and GPU1212 can be shortened, and from CPU1211 Data transfer to GPU1212, CPU1211, and the memory of GPU1212 Data transfer between them, and after calculations on GPU1212, from GPU1212 to CPU121 The result of the calculation to 1 can be transferred at high speed.

[0367] The analog processing unit 1213 includes an A / D (analog / digital) conversion circuit and a D / A (digital) conversion circuit. It has one or both of the analog / analog conversion circuits. Also, the analog arithmetic unit 1213 The above-described sum-of-accumulate circuit may be provided.

[0368] The memory controller 1214 is a circuit that functions as a controller for the DRAM 1221. It also has a circuit that functions as an interface for the flash memory 1222.

[0369] Interface 1215 is for display devices, speakers, microphones, cameras, controllers It has an interface circuit for connecting to external devices such as rollers. The controller is a mouse This includes keyboards, game controllers, etc. USB (Universal Serial Bus), HDMI (Registered Trademark) (Hi-Fi) Using gh-Definition Multimedia Interface, etc. It is possible.

[0370] The network circuit 1216 connects to a LAN (Local Area Network), etc. It has a network circuit for connection. It also has a circuit for network security. It may have.

[0371] The above circuit (system) can be formed on chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, increasing the manufacturing process will not increase the number of circuits. This eliminates the need for additional components, allowing for the low-cost production of Chip 1200.

[0372] PCB1201 equipped with chip 1200 having GPU1212, DRAM1221 The motherboard 1203, which is equipped with flash memory 1222, has a GPU module It can be called 1204.

[0373] The GPU module 1204 has a chip 1200 that uses SoC technology, It can reduce the size. Also, because it excels at image processing, smartphones Mobile devices such as phones, tablets, laptops, portable game consoles, etc. It is preferable to use it in strip-type electronic devices. Also, in multiply-accumulate circuits using the GPU1212. More specifically, deep neural networks (DNNs), convolutional neural networks ( CNN, Recurrent Neural Network (RNN), Autoencoder, Deep Boltzmann It can implement techniques such as DVM (Deep Belief Network) and DBN (Deep Belief Network). Therefore, the chip 1200 is the AI ​​chip, or the GPU module 1204 is the AI ​​system module. It can be used as a liter.

[0374] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. It is possible.

[0375] (Embodiment 7) This embodiment describes an application example of a semiconductor device using the memory device shown in the previous embodiment. Let me explain. The storage device shown in the above embodiment is a memory card (for example, an SD card), U Various removable storage devices such as SB memory and SSD (Solid State Drive) This can be applied to the following. Figures 77A to 77E show several configurations of removable storage devices. An example is schematically shown. For example, the semiconductor device shown in the above embodiment is packaged It is processed into memory chips and used in various storage devices and removable memory.

[0376] Figure 77A is a schematic diagram of a USB memory device. The USB memory device 1100 consists of a casing 1101 and a cable. It has a 1102, a USB connector 1103, and a circuit board 1104. The circuit board 1104 is It is housed in the enclosure 1101. For example, the circuit board 1104 contains a memory chip 1105, The controller chip 1106 is installed. The memory chip 1105 and others are implemented as described above. A storage device or semiconductor device shown in the form can be incorporated.

[0377] Figure 77B is a schematic diagram of the external appearance of an SD card, and Figure 77C is a schematic diagram of the internal structure of an SD card. This is a diagram. The SD card 1110 consists of the housing 1111, connector 1112, and circuit board 1113. It has. The circuit board 1113 is housed in the housing 1111. For example, the circuit board 1113 has, A memory chip 1114 and a controller chip 1115 are mounted on circuit board 111. By also providing a memory chip 1114 on the back side of 3, the capacity of the SD card 1110 can be increased. This is possible. Furthermore, a wireless chip with wireless communication capabilities may be provided on the substrate 1113. This allows wireless communication between the host device and the SD card 1110 to control the memory chip. This enables reading and writing of data to the 1114. The device can incorporate a storage device or semiconductor device as shown in the embodiment.

[0378] Figure 77D is a schematic diagram of the external appearance of an SSD, and Figure 77E is a schematic diagram of the internal structure of an SSD. The SSD1150 has a housing 1151, a connector 1152, and a circuit board 1153. The board 1153 is housed in the casing 1151. For example, the board 1153 has memory chips. 1154, memory chip 1155, and controller chip 1156 are installed. Memory chip 1155 is the work memory of controller chip 1156, for example DO An SRAM chip can be used. A memory chip 1154 is also provided on the back side of the circuit board 1153. This allows you to increase the capacity of the SSD1150. A storage device or semiconductor device as shown in the embodiment can be incorporated.

[0379] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0380] (Embodiment 8) Figures 78A to 78G show an electric device equipped with a storage device or semiconductor device according to one aspect of the present invention. Here are some specific examples of sub-devices.

[0381] <Electronic Equipment and Systems> A memory device or semiconductor device according to one aspect of the present invention can be mounted on various electronic devices. Yes, it can. Examples of electronic devices include, for example, information terminals, computers, smartphones, and electronic devices. Book terminals, television equipment, digital signage: Electronic signboards, large game machines such as pachinko machines, digital cameras, digital video cameras, Digital photo frames, mobile phones, portable game consoles, recording and playback devices, navigation systems Examples include systems and sound reproduction devices. Note that, here, "computer" refers to a tablet. In addition to laptop computers, notebook computers, and desktop computers, This includes large computers such as server systems.

[0382] An electronic device according to one aspect of the present invention may have an antenna. The antenna receives a signal. This allows the display unit to show images, information, etc. Also, electronic equipment can be used as an antenna and If a secondary battery is present, the antenna may be used for contactless power transmission.

[0383] An electronic device according to one aspect of the present invention includes sensors (force, displacement, position, velocity, acceleration, angular velocity, rotational speed). Distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, electric current, voltage, power, (Includes functions for measuring radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation) It's okay to do so.

[0384] An electronic device according to one aspect of the present invention can have various functions. For example, various information ( Functions to display still images, videos, text images, etc. on the display unit, touch panel function, calendar A function to display the date or time, and to run various software (programs). Functions include wireless communication and the ability to read programs or data recorded on a recording medium. They may possess abilities such as [specific abilities / skills].

[0385] [Information terminal] Using a storage device or semiconductor device according to one aspect of the present invention, the process of a microcontroller A memory device for holding gram data can be formed. Therefore, according to one aspect of the present invention, The cross-controller chip can be made smaller.

[0386] Figure 78A illustrates a mobile phone (smartphone), a type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102, and an input interface The device features a touch panel on the display unit 5102 and buttons on the housing 5101. This is achieved by using a miniaturized microcontroller according to one aspect of the present invention. This allows for effective use of the limited space inside the mobile phone. Also, the mobile phone's storage A storage device according to one aspect of the present invention may be used for the storage. This allows for a larger storage capacity per unit area.

[0387] Figure 78B shows the notebook-type information terminal 5200. The information terminal comprises a main unit 5201, a display unit 5202, and a keyboard 5203. According to one aspect of the present invention, by using a miniaturized microcontroller, a notebook computer can be used. This allows for effective use of the limited space inside the information terminal. Furthermore, it allows for efficient use of the limited space inside the notebook-type information terminal. A storage device according to one aspect of the present invention may be used for the storage. This allows for a larger storage capacity per unit area.

[0388] In the above, smartphones and notebook computers were used as examples of electronic devices. As shown in Figures 78A and 78B respectively, smartphones and notebook information terminals External information terminals can be used. This includes smartphones and notebook computers. Examples of information terminals include PDAs (Personal Digital Assistants). Examples include ant, desktop information terminals, and workstations.

[0389] [Game console] Figure 78C shows a portable game console 5300, which is an example of a game console. Portable game console 5 300 consists of casing 5301, casing 5302, casing 5303, display unit 5304, and connection unit 530. 5. It has operation keys 5306, etc. Housing 5302 and housing 5303 are housing 5301 It can be removed from the housing 5301. The connection part 5305 provided on the housing 5301 can be connected to another housing By attaching it to the body (not shown), the video output to the display unit 5304 can be displayed on another video device. Output can be sent to (not shown). At this time, housing 5302 and housing 5303 Each of these can function as a control unit. This allows multiple players to play simultaneously. The game can be played. The circuit boards of cabinets 5301, 5302, and 5303 are A memory device or semiconductor device according to one aspect of the present invention is incorporated into a chip or the like. It can be placed inside.

[0390] Figure 78D also shows a home console 5400, which is an example of a game console. The stationary game console 5400 can be connected to controller 5402 wirelessly or via a wired connection. ru.

[0391] In one aspect of the present invention, a game console such as a portable game console 5300 or a home game console 5400 is provided. By using a miniaturized microcontroller, the limited space inside the game console can be utilized. This can be effectively utilized. Furthermore, in one aspect of the present invention, the storage of a portable game console can be used. The storage device or semiconductor device may be used. This allows for a larger storage capacity per unit area.

[0392] Figures 78C and 78D show examples of game consoles, including a handheld game console and a home console. Although the machine is shown in the illustration, a game machine to which a microcontroller according to one aspect of the present invention is applied is this The invention is not limited to the above. A game machine to which a microcontroller according to one aspect of the present invention is applied includes: For example, arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) Examples include pitching machines for batting practice installed in sports facilities.

[0393] [Large computer] A storage device or semiconductor device according to one aspect of the present invention can be applied to a large computer. can.

[0394] Figure 78E shows an example of a large computer, the Supercomputer 5500. Yes. Figure 78F shows the rack-mount type computer 5 of the supercomputer 5500. This is a diagram of 502.

[0395] The supercomputer 5500 consists of rack 5501 and multiple rack-mount computers. It has 5502 and, in addition, multiple computers 5502 are stored in rack 5501. Furthermore, the computer 5502 is provided with multiple circuit boards 5504, and the present invention is placed on these circuit boards. A microcontroller according to one embodiment of the present invention can be mounted. By using standardized microcontrollers, the limited space of a large computer can be utilized. It can be used effectively. Furthermore, in one aspect of the present invention, it can be used in the storage of a large computer. The storage device or semiconductor device may be used. This allows for a larger storage capacity per unit area.

[0396] Figures 78E and 78F illustrate a supercomputer as an example of a large-scale computer. However, a large computer to which a microcontroller according to one aspect of the present invention is applied is The present invention is not limited to the application of a microcontroller according to one aspect of the present invention to a large computer. Examples of data sources include computers (servers) that provide services, and large-scale general-purpose computers. Examples include computers (mainframes).

[0397] [electric appliances] Figure 78G shows an example of an electrical appliance, the electric refrigerator-freezer 5800. The storage unit 5800 includes a casing 5801, a door for the refrigerator compartment 5802, a door for the freezer compartment 5803, and the like.

[0398] A storage device or semiconductor device according to one aspect of the present invention is applicable to an electric refrigerator 5800. It is also possible to use a miniaturized electric refrigerator 5800 according to one aspect of the present invention. By applying a microcontroller, the limited space in electric refrigerators and freezers can be utilized effectively. It can be used for this purpose.

[0399] I explained electric refrigerators as an example of electrical appliances, but other electrical appliances include: For example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cooktops, and hob. Heating and cooling appliances including heaters, air conditioners, washing machines, dryers, audio equipment Examples include casual equipment.

[0400] The electronic devices described in this embodiment, their functions, and their effects may differ from those of other electronic devices. This can be combined with the description as appropriate.

[0401] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible. [Explanation of symbols]

[0402] 100: Memory device, 105: Region, 110: Memory cell array, 120: Memostring G, 121: Substrate, 122: Conductor, 123: Insulator, 124: Insulator, 125: Semiconductor 126: Insulator, 127: Semiconductor, 128: Conductor, 129: Insulator, 130: Conductor , 141:Aperture, 142:Area, 143:Area

Claims

1. A first conductor having a region that functions as the first gate electrode of a first transistor, A second conductor having a region that functions as the first electrode of a capacitive element, A third conductor having a region that functions as the first gate electrode of the second transistor, A fourth conductor having a region that functions as the second gate electrode of the second transistor, A first insulator having a region that functions as the first gate insulating film of the first transistor, A second insulator having a region that functions as a second gate insulating film of the first transistor and a region that functions as a second gate insulating film of the second transistor, A third insulator having a region that functions as the first gate insulating film of the second transistor, The fourth insulator and, A first semiconductor having a channel formation region of the first transistor, The second semiconductor has a region that functions as the second gate electrode of the first transistor and the second electrode of the capacitive element, and a channel formation region of the second transistor. The first conductor extends perpendicularly to the upper surface of the substrate, In the first top view, the side surface of the first conductor has a region in contact with the first insulator. In the first top view, the side surface of the first insulator has a region in contact with the first semiconductor, In the first top view, the side surface of the first semiconductor has a region in contact with the second insulator. In the first top view, the side surface of the second insulator has a region in contact with the second semiconductor, In the first top view, the side surface of the second semiconductor has a region in contact with the third insulator. In the first top view, the side surface of the third insulator has a region in contact with the second conductor. In the second top view, the side surface of the first conductor has a region in contact with the first insulator. In the second top view, the side surface of the first insulator has a region in contact with the fourth conductor. In the second top view, the side surface of the fourth conductor has a region in contact with the first semiconductor, In the second top view, the side surface of the first semiconductor has a region in contact with the second insulator. In the second top view, the side surface of the second insulator has a region in contact with the second semiconductor, In the second top view, the side surface of the second semiconductor has a region in contact with the third insulator. In a second top view, the side surface of the third insulator has a region in contact with the third conductor.

2. The first semiconductor is an oxide semiconductor, The second semiconductor is an oxide semiconductor. The storage device according to claim 1.

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