Schmitt circuit
The Schmitt circuit addresses chattering issues by integrating signal detection and delay circuits to filter noise, ensuring stable output signals despite impedance mismatches and reflected noise.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- SEIKO INSTR INC
- Filing Date
- 2026-03-17
- Publication Date
- 2026-05-19
AI Technical Summary
Conventional Schmitt circuits experience chattering in their output when connected to a communication bus that is not impedance-matched, leading to potential device malfunctions due to superimposed reflected noise.
The Schmitt circuit incorporates a first and second signal detection circuit, an RS latch circuit, and a selection signal generation circuit with a delay mechanism to filter out reflected noise, ensuring stable output signals without chattering.
The circuit effectively suppresses chattering even when input signals have superimposed noise, maintaining stable output performance.
Smart Images
Figure 2026083421000001_ABST
Abstract
Description
Technical Field
[0005]
[0001] The present invention relates to a Schmitt circuit.
Background Art
[0002] When the input terminal of a conventional Schmitt circuit is connected to a communication bus or the like that is not impedance - matched, reflected noise may be superimposed on the input signal. And when an input signal with superimposed reflected noise is input to the conventional Schmitt circuit, chattering may occur in the output of the Schmitt circuit, which may cause malfunction of the device. (See, for example, Patent Document 1).
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] An object of the present invention is to provide a Schmitt circuit that does not cause chattering in the output of the Schmitt circuit even when the input terminal is connected to a communication bus or the like that is not impedance - matched and reflected noise is superimposed on the input signal.
Means for Solving the Problems
[0005] The Schmitt circuit of the present invention comprises a first signal detection circuit, a second signal detection circuit, a latch circuit, a selection signal generation circuit, a first input terminal, and a first output terminal, wherein the first signal detection circuit has a second input terminal, a first selection signal input terminal, and a second output terminal, the first input terminal being connected to the second input terminal, the first selection signal input terminal being connected to the selection signal generation circuit, and the second output terminal being connected to one input of the latch circuit, the second signal detection circuit has a third input terminal, a second selection signal input terminal, and a third output terminal, the first input terminal being connected to the third input terminal, the second selection signal input terminal being connected to the selection signal generation circuit, and the third output terminal being connected to the other input of the latch circuit, the latch circuit being connected to the selection signal generation circuit and the output terminal, and the selection signal generation circuit having a delay circuit. [Effects of the Invention]
[0006] Even if reflected noise is superimposed on the input signal, chattering will not occur at the output of the Schmitt circuit. [Brief explanation of the drawing]
[0007] [Figure 1] This is a circuit diagram showing an example of a Schmitt circuit according to the first embodiment of the present invention. [Figure 2] This figure shows an example of the input and output waveforms of a Schmitt circuit according to the first embodiment of the present invention. [Figure 3] This figure shows another example of the input and output waveforms of the Schmitt circuit according to the first embodiment of the present invention. [Figure 4] This figure shows another example of the input and output waveforms of the Schmitt circuit according to the first embodiment of the present invention. [Figure 5] This figure shows another example of the input and output waveforms of the Schmitt circuit according to the first embodiment of the present invention. [Figure 6] This is a circuit diagram showing an example of a Schmitt circuit according to a second embodiment of the present invention. [Figure 7]This is a circuit diagram showing an example of a Schmitt circuit according to a third embodiment of the present invention. [Figure 8] This figure shows an example of the input and output waveforms of a Schmitt circuit according to a third embodiment of the present invention. [Figure 9] This figure shows another example of the input and output waveforms of a Schmitt circuit according to a third embodiment of the present invention. [Modes for carrying out the invention]
[0008] [First Embodiment]
[0009] A first embodiment of the present invention will be described below with reference to the drawings. Figure 1 is a circuit diagram showing an example of a Schmitt circuit 1 according to this embodiment.
[0010] The configuration of the Schmitt circuit 1 of this embodiment will now be described. The Schmitt circuit 1 of this embodiment includes a first signal detection circuit 100, a second signal detection circuit 110, an RS latch circuit 120, a selection signal generation circuit 130, inverters 150 and 151, an input terminal IN, and an output terminal OUT.
[0011] The first signal detection circuit 100 includes a first P-channel MOS transistor (hereinafter referred to as a PMOS transistor) 101, a second PMOS transistor 102, a first N-channel MOS transistor (hereinafter referred to as an NMOS transistor) 103, a second NMOS transistor 104, an input terminal 105, a selection signal input terminal 106, and an output terminal 107.
[0012] The second signal detection circuit 110 includes a third PMOS transistor 111, a fourth PMOS transistor 112, a third NMOS transistor 113, a fourth NMOS transistor 114, an input terminal 115, a selection signal input terminal 116, and an output terminal 117.
[0013] The RS latch circuit 120 includes a first NOR circuit 121, a second NOR circuit 122, a first input terminal 123, a second input terminal 124, and an output terminal 125.
[0014] The selection signal generation circuit 130 includes an input terminal 131, an output terminal 132, and an internal delay circuit 140.
[0015] The connections of the Schmitt circuit in this embodiment will now be described. Input terminal IN is connected to input terminal 105 of the first signal detection circuit 100 and input terminal 115 of the second signal detection circuit 110. Output terminal 107 of the first signal detection circuit 100 is connected to the first input terminal 123 of the RS latch circuit 120 via inverter 150. Output terminal 117 of the second signal detection circuit 110 is connected to the second input terminal 124 of the RS latch circuit 120. Output terminal 125 of the RS latch circuit 120 is connected to input terminal 131 of the selection signal generation circuit 130 and output terminal OUT via inverter 151. Output terminal 132 of the selection signal generation circuit 130 is connected to selection signal input terminal 106 of the first signal detection circuit 100 and selection signal input terminal 116 of the second signal detection circuit 110.
[0016] The connection of the first signal detection circuit 100 will be described. The input terminal 105 of the first signal detection circuit 100 is connected to the gate terminal of the second PMOS transistor 102 and the gate terminal of the first NMOS transistor 103. The selection signal input terminal 106 of the first signal detection circuit 100 is connected to the gate terminal of the first PMOS transistor 101 and the gate terminal of the second NMOS transistor 104. The source terminals of the first PMOS transistor 101 and the second PMOS transistor 102 are connected to the VDD terminal. The source terminal of the first NMOS transistor 103 is connected to the drain terminal of the second NMOS transistor 104. The source terminal of the second NMOS transistor 104 is connected to the GND terminal. The drain terminals of the first PMOS transistor 101, the second PMOS transistor 102, and the first NMOS transistor 103 are connected to the output terminal 107 of the first signal detection circuit 100.
[0017] The connection of the second signal detection circuit 110 will be described. The input terminal 115 of the second signal detection circuit 110 is connected to the gate terminal of the fourth PMOS transistor 112 and the gate terminal of the fourth NMOS transistor 114. The selection signal input terminal 116 of the second signal detection circuit 110 is connected to the gate terminal of the third PMOS transistor 111 and the gate terminal of the third NMOS transistor 113. The source terminal of the third PMOS transistor 111 is connected to the VDD terminal, and the drain terminal is connected to the source terminal of the fourth PMOS transistor 112. The source terminals of the third NMOS transistor 113 and the fourth NMOS transistor 114 are connected to the GND terminal. The drain terminals of the fourth PMOS transistor 112, the third NMOS transistor 113, and the fourth NMOS transistor 114 are connected to the output terminal 117 of the second signal detection circuit 110.
[0018] The connection of the RS latch circuit 120 will be described. The first input terminal of the first NOR circuit 121 is connected to the first input terminal 123 of the RS latch circuit 120, the second input terminal is connected to the output terminal of the second NOR circuit 122, and the output terminal is connected to the output terminal 125 of the RS latch circuit 120 and the first input terminal of the second NOR circuit 122. The second input terminal of the second NOR circuit 122 is connected to the second input terminal 124 of the RS latch circuit 120.
[0019] Referring to FIGS. 2 to 5, the operation of the Schmitt circuit 1 of this embodiment will be described. FIGS. 2 to 5 show that the horizontal axis is time and the vertical axis is voltage. FIG. 2(a) shows an example of the signal VIN input to the input terminal IN. FIG. 2(b) shows the signal SETX at the output terminal 107 of the first signal detection circuit 100, FIG. 2(c) shows the signal SET obtained by inverting the signal SETX with the inverter 150. FIG. 2(d) shows the signal RST at the output terminal 117 of the second signal detection circuit 110. FIG. 2(e) shows the signal SELECT at the output terminal 132 of the selection signal generation circuit 130. FIG. 2(f) shows the signal DOX at the output terminal 125 of the RS latch circuit 120, and FIG. 2(g) shows the signal VOUT at the output terminal OUT obtained by inverting the signal DOX with the inverter 151. For FIGS. 3 to 5, (a) to (g) show an example of the same signal.
[0020] The voltage VIH shown in Figure 2(a) represents the threshold voltage of the first signal detection circuit 100. The voltage VIL represents the threshold voltage of the second signal detection circuit 110. Voltage VIH > Voltage VIL. The threshold voltage VIH of the first signal detection circuit 100 is determined by the size ratio of the second PMOS transistor 102 and the first NMOS transistor 103. Similarly, the threshold voltage VIL of the second signal detection circuit 110 is determined by the size ratio of the fourth PMOS transistor 112 and the fourth NMOS transistor 114. Assuming the channel length L of the MOS transistors is the same, the threshold voltage is higher when the channel width W of the PMOS transistor is greater than the channel width W of the NMOS transistor, and lower when the channel width W of the PMOS transistor is less than the channel width W of the NMOS transistor. For example, the voltage VIH can be set to > voltage VIL by making the channel width W of the second PMOS transistor 102 larger than the channel width W of the first NMOS transistor 103, and the channel width W of the fourth PMOS transistor 112 smaller than the channel width W of the fourth NMOS transistor 114. Note that this is just one example, and the threshold voltage may also be set by adjusting parameters other than the channel width W.
[0021] [Explanation of normal operation]
[0022] The operation of the first signal detection circuit 100 will be explained with reference to Figures 2 and 3. Figure 2 shows the state in which the signal VIN rises from a low level to a high level. The signal VIN shown in Figure 2(a) starts rising from time T0 and rises above the voltage VIH at time T2. The signal VIN is applied from the input terminal IN to the input terminal 105 of the first signal detection circuit 100. When the signal SELECT input to the selection signal input terminal 106 is at a high level from time T0 to time T7 as shown in Figure 2(e), and the signal VIN shown in Figure 2(a) is input to the input terminal 105, the signal SETX output from the output terminal 107 falls from a high level to a low level at time T2 as shown in Figure 2(b). When the signal SELECT falls to a low level at time T7 after the delay time Delay, the signal SETX rises from a low level to a high level at time T7.
[0023] The first signal detection circuit 100 outputs a high-level signal SETX from output terminal 107 if the signal VIN applied to input terminal 105 is lower than the voltage VIH, and outputs a low-level signal SETX from output terminal 107 if the voltage is higher than VIH. The first signal detection circuit 100 outputs a high-level signal SETX from output terminal 107 regardless of the voltage of the signal VIN applied to input terminal 105 when the signal SELECT is low.
[0024] Figure 3 shows the state in which the signal VIN falls from a high level to a low level. The signal VIN shown in Figure 3(a) begins to fall from time T10 and falls below the voltage VIL at time T12. The signal VIN is applied from the input terminal IN to the input terminal 105 of the first signal detection circuit 100. When the signal SELECT input to the selection signal input terminal 106 is at a low level from time T10 to time T17 as shown in Figure 3(e), and the signal VIN shown in Figure 3(a) is input to the input terminal 105, the signal SETX output from the output terminal 107 remains at a high level from time T10 to time T17 as shown in Figure 3(b). When the signal SELECT rises to a high level at time T17 after the delay time Delay, the signal SETX remains at a high level at time T17.
[0025] The operation of the second signal detection circuit 110 will be explained with reference to Figures 2 and 3. The signal VIN shown in Figure 2(a) is applied from the input terminal IN to the input terminal 115 of the second signal detection circuit 110. When the signal SELECT input to the selection signal input terminal 116 is at a high level from time T0 to time T7 as shown in Figure 2(e), and the signal VIN shown in Figure 2(a) is input to the input terminal 115, the signal RST output from the output terminal 117 remains at a low level from time T0 to time T7 as shown in Figure 2(d). When the signal SELECT falls to a low level at time T7 after the delay time Delay, the signal RST remains at a low level at time T7 and does not change.
[0026] The signal VIN shown in Figure 3(a) is applied from the input terminal IN to the input terminal 115 of the second signal detection circuit 110. When the signal SELECT input to the selection signal input terminal 116 is at a low level from time T10 to time T17 as shown in Figure 3(e), and the signal VIN shown in Figure 3(a) is input to the input terminal 115, the signal RST output from the output terminal 117 rises from a low level to a high level at time T12 as shown in Figure 3(d). When the signal SELECT rises to a high level at time T17 after the delay time Delay, the signal RST falls from a high level to a low level at time T17.
[0027] The second signal detection circuit 110 outputs a low-level signal RST from the output terminal 117 if the signal VIN applied to the input terminal 115 is higher than the voltage VIL, and outputs a high-level signal RST from the output terminal 117 if the signal VIN applied to the input terminal 115 is lower than the voltage VIL. The second signal detection circuit 110 outputs a low-level signal RST from the output terminal 117 regardless of the voltage of the signal VIN applied to the input terminal 115, when the signal SELECT is at a high level.
[0028] The operation of the RS latch circuit 120 will be explained with reference to Figures 2 and 3. RS latch circuit 120 In The signal SETX is inverted by the inverter 150, resulting in the signal SET, which is input to the first input terminal 123 of the RS latch circuit 120. The signal RST is input to the second input terminal 124 of the RS latch circuit 120, and the signal DOX is output from the output terminal 125 of the RS latch circuit 120. Figure 2 shows the state in which the signal VIN rises from a low level to a high level. The signal SET shown in Figure 2(c) rises from a low level to a high level at time T2 and falls from a high level to a low level at time T7. but The signal RST shown in Figure 2(d) remains at a low level from time T0 to time T7. The signal DOX shown in Figure 2(f) falls from a high level to a low level at time T2. but The signal VOUT at the output terminal OUT shown in Figure 2(g) rises from a low level to a high level over time T2. The RS latch circuit was explained as an example of a latch circuit, but it is not limited to the RS latch circuit; any latch circuit with equivalent functionality, such as a JK latch circuit, may be used.
[0029] Figure 3 shows the state in which the signal VIN falls from a high level to a low level. The signal RST shown in Figure 3(d) rises from a low level to a high level at time T12 and falls from a high level to a low level at time T17. butThe signal SET shown in Figure 3(c) remains at a low level from time T10 to time T17. The signal DOX shown in Figure 3(f) rises from a low level to a high level at time T12. but The signal VOUT at the output terminal OUT, shown in Figure 3(g), falls from a high level to a low level at time T12.
[0030] The operation of the selection signal generation circuit 130 will be explained with reference to Figures 2 and 3. In The signal DOX is input to the input terminal 131 of the selection signal generation circuit 130, and the signal SELECT is output from the output terminal 132 of the selection signal generation circuit 130. The selection signal generation circuit 130 has an internal delay circuit 140. After the input signal DOX changes, the signal SELECT changes after a delay time of Delay by the delay circuit 140. When the signal DOX shown in Figure 2(f) falls at time T2, the signal SELECT shown in Figure 2(e) falls at time T7 after the delay time of Delay. When the signal DOX shown in Figure 3(f) rises at time T12, the signal SELECT shown in Figure 3(e) rises at time T17 after the delay time of Delay.
[0031] The selection signal generation circuit 130 can be configured using a combination of logic circuits, an ASIC, or a programmable single-chip microcontroller, as long as it operates in this manner. The delay time of the internal delay circuit 140 is set to be longer than the noise of the reflected signal expected from the signal wiring length, and shorter than the pulse width of the input signal.
[0032] In this embodiment, when the signal VIN input to the input terminal IN shown in Figure 2(a) rises above a voltage VIH higher than the voltage VIL at time T2, the signal VOUT output from the output terminal OUT shown in Figure 2(g) rises from a low level to a high level at time T2. Also, in this embodiment, when the signal VIN at the input terminal IN shown in Figure 3(a) falls below a voltage VIL lower than the voltage VIH at time T12, the signal VOUT at the output terminal OUT shown in Figure 3(g) falls from a high level to a low level at time T12.
[0033] [Explanation of operation when a signal with superimposed reflected noise is input]
[0034] Referring to Figures 4 and 5, the operation when a signal VIN with superimposed reflected noise is input to the input terminal IN of the Schmitt circuit 1 of this embodiment will be explained. Figure 4(a) shows the state in which the signal VIN with superimposed reflected noise rises from a low level to a high level. The signal VIN shown in Figure 4(a) has superimposed reflected noise and begins to rise at time T20, rises above voltage VIH at time T22, falls above voltage VIH at time T23, falls above voltage VIL at time T24, rises above voltage VIL at time T25, and rises above voltage VIH at time T26.
[0035] The operation of the first signal detection circuit 100 will be explained with reference to Figure 4. The signal VIN is applied from the input terminal IN to the input terminal 105 of the first signal detection circuit 100. When the signal SELECT input to the selection signal input terminal 106 is at a high level from time T20 to time T27 as shown in Figure 4(e), and the signal VIN shown in Figure 4(a) is input to the input terminal 105, the signal SETX output from the output terminal 107 falls from a high level to a low level at time T22, rises from a low level to a high level at time T23, and falls from a high level to a low level at time T26, as shown in Figure 4(b). When the signal SELECT falls to a low level at time T27 after the delay time Delay, the signal SETX rises from a low level to a high level at time T27.
[0036] The operation of the second signal detection circuit 110 will be explained with reference to Figure 4. The signal VIN is applied from the input terminal IN to the input terminal 115 of the second signal detection circuit 110. When the signal SELECT input to the selection signal input terminal 116 is at a high level from time T20 to time T27 as shown in Figure 4(e), and the signal VIN shown in Figure 4(a) is input to the input terminal 115, the signal RST output from the output terminal 117 remains at a low level from time T20 to time T27 as shown in Figure 4(d). When the signal SELECT falls to a low level at time T27 after the delay time Delay, the signal RST remains at a low level at time T27 and does not change.
[0037] The operation of the RS latch circuit 120 will be explained with reference to Figure 4. The signal SET shown in Figure 4(c) rises from a low level to a high level at time T22, and falls from a high level to a low level at time T23. but Then, at time T26, it rises from a low level to a high level, and at time T27, it falls from a high level to a low level. but The signal RST shown in Figure 4(d) remains at a low level from time T20 to time T27. The signal DOX shown in Figure 4(f) falls from a high level to a low level at time T22. but The signal VOUT at the output terminal OUT shown in Figure 4(g) rises from a low level to a high level at time T22. The operation of the selection signal generation circuit 130 will be explained with reference to Figure 4. When the signal DOX shown in Figure 4(f) falls at time T22, the signal SELECT shown in Figure 4(e) falls at time T27 after the delay time Delay.
[0038] In this embodiment, even when the Schmitt circuit 1 receives a signal VIN, as shown in Figure 4(a), which rises above voltage VIH, then falls below voltage VIL, and then rises above voltage VIH again, as input to the input terminal IN, no chattering occurs in the signal VOUT output from the output terminal OUT.
[0039] Figure 5(a) shows the state in which the signal VIN, which has reflected noise superimposed on it, falls from a high level to a low level. The signal VIN shown in Figure 5(a) has reflected noise superimposed on it, starts rising at time T30, falls above voltage VIL at time T32, rises above voltage VIL at time T33, rises above voltage VIH at time T34, falls above voltage VIH at time T35, and falls below voltage VIL at time T36.
[0040] The operation of the first signal detection circuit 100 will be explained with reference to Figure 5. The signal VIN shown in Figure 5(a) is applied from the input terminal IN to the input terminal 105 of the first signal detection circuit 100. When the signal SELECT input to the selection signal input terminal 106 is at a low level from time T30 to time T37 as shown in Figure 5(e), and the signal VIN shown in Figure 5(a) is input to the input terminal 105, the signal SETX output from the output terminal 107 remains at a high level from time T30 to time T37 as shown in Figure 5(b). When the signal SELECT falls to a low level at time T37 after the delay time Delay, the signal SETX remains at a high level at time T37 and does not change.
[0041] The operation of the second signal detection circuit 110 will be explained with reference to Figure 5. The signal VIN is applied from the input terminal IN to the input terminal 115 of the second signal detection circuit 110. When the signal SELECT, which is input to the selection signal input terminal 116, is at a low level from time T30 to time T37 as shown in Figure 5(e), and the signal VIN, shown in Figure 5(a), is input to the input terminal 115, the signal RST, which is output from the output terminal 117, rises from a low level to a high level at time T32, falls from a high level to a low level at time T33, and rises from a low level to a high level at time T36, as shown in Figure 5(d). When the signal SELECT falls to a low level at time T37 after the delay time Delay, the signal RST falls from a high level to a low level at time T37.
[0042] The operation of the RS latch circuit 120 will be explained with reference to Figure 5. The signal SET shown in Figure 5(c) remains at a low level from time T30 to time T37. The signal RST shown in Figure 5(d) rises from a low level to a high level at time T32, and falls from a high level to a low level at time T33. but Then, at time T36, it rises from a low level to a high level, and at time T37, it falls from a high level to a low level. but The signal DOX shown in Figure 5(f) rises from a low level to a high level at time T32. but The signal VOUT at the output terminal OUT shown in Figure 5(g) falls from a high level to a low level at time T32. The operation of the selection signal generation circuit 130 will be explained with reference to Figure 5. When the signal DOX shown in Figure 5(f) rises at time T32, the signal SELECT shown in Figure 5(e) rises at time T37 after the delay time Delay.
[0043] In this embodiment, even when the signal VIN shown in Figure 5(a), which drops below voltage VIL, then rises above voltage VIH, and then drops below voltage VIL again, is input to the input terminal IN of the Schmitt circuit 1, no chattering occurs in the signal VOUT output from the output terminal OUT.
[0044] As described above, the Schmitt circuit 1 of this embodiment operates as a Schmitt circuit that does not cause chattering, whether the signal VIN on which the reflected noise is superimposed is rising or falling.
[0045] [Second Embodiment]
[0046] A second embodiment of the present invention will be described below with reference to the drawings. Figure 6 is a circuit diagram showing an example of a Schmitt circuit 1a according to this embodiment. The same reference numerals are used for the same components as in the first embodiment, and their descriptions are omitted.
[0047] The Schmitt circuit 1a of this embodiment includes a first signal detection circuit 100, a second signal detection circuit 110, an RS latch circuit 120, a second selection signal generation circuit 130a, inverters 150, 151, and 152, a fifth NMOS transistor 153, an input terminal IN, an output terminal OUT, and an enable input terminal EN.
[0048] The difference between the configuration of the Schmitt circuit 1a of this embodiment and the Schmitt circuit 1 of the first embodiment is that the Schmitt circuit 1a of this embodiment includes an enable input terminal EN, an inverter 152, a fifth NMOS transistor 153, and a second selection signal generation circuit 130a instead of the selection signal generation circuit 130. The second selection signal generation circuit 130a includes an input terminal 131, a third output terminal 133, a fourth output terminal 134, an enable terminal 135, and an internal delay circuit 140.
[0049] The connections of the Schmitt circuit 1a in this embodiment will now be described. The enable input terminal EN is connected to the enable terminal 135 of the second selection signal generation circuit 130a and to the gate terminal of the fifth NMOS transistor 153 via the inverter 152. The third output terminal 133 of the second selection signal generation circuit 130a is connected to the selection signal input terminal 106 of the first signal detection circuit 100. The fourth output terminal 134 of the second selection signal generation circuit 130a is connected to the selection signal input terminal 116 of the second signal detection circuit 110. The drain terminal of the fifth NMOS transistor 153 is connected to the output terminal 125 of the RS latch circuit 120 and to the input terminal 131 of the second selection signal generation circuit 130a. The source terminal of the fifth NMOS transistor 153 is connected to the GND terminal.
[0050] The operation of the Schmitt circuit 1a in this embodiment will now be described.
[0051] [Explanation of operation when the enable signal is high level]
[0052] The operation of the Schmitt circuit 1a in this embodiment when a high-level signal is input to the enable input terminal EN will now be described. When a high-level signal is input to the enable input terminal EN, a low-level signal is input to the gate terminal of the fifth NMOS transistor 153 via the inverter 152, and a high-level signal is input to the enable terminal 135 of the second selection signal generation circuit 130a. The fifth NMOS transistor 153 is turned off. When the signal DOX is input to the input terminal 131 of the second selection signal generation circuit 130a, after a delay time by the delay circuit 140, the second selection signal generation circuit 130a outputs a SELECT1 signal from the third output terminal 133 and a SELECT2 signal from the fourth output terminal 134. The SELECT1 and SELECT2 signals when the enable signal is high level are the same as the SELECT signal in the first embodiment. The operation of the Schmitt circuit 1a in this embodiment when the enable signal is high level is the same as the Schmitt circuit 1 in the first embodiment.
[0053] [Explanation of operation when the enable signal is low level]
[0054] The operation when a low-level signal is input to the enable input terminal EN of the Schmitt circuit 1a of this embodiment will now be described. When a low-level signal is input to the enable input terminal EN, a high-level signal is input to the gate terminal of the fifth NMOS transistor 153 via the inverter 152, and a low-level signal is input to the enable terminal 135 of the second selection signal generation circuit 130a. The fifth NMOS transistor 153 turns ON.
[0055] When a low-level signal is input to the enable terminal 135 of the second selection signal generation circuit 130a, it outputs a low-level signal SELECT1 from the third output terminal 133 and a high-level signal SELECT2 from the fourth output terminal 134. The low-level signal SELECT1 is input to the selection signal input terminal 106 of the first signal detection circuit 100. Regardless of the signal input to the input terminal 105, the first signal detection circuit 100 outputs a high-level signal SETX from the output terminal 107. The high-level signal SELECT2 is input to the selection signal input terminal 116 of the second signal detection circuit 110. Regardless of the signal input to the input terminal 115, the second signal detection circuit 110 outputs a low-level signal RST from the output terminal 117 of the second signal detection circuit 110.
[0056] RS latch circuit 120 In A low-level SET signal is input to the first input terminal 123 from the output terminal 107 of the first signal detection circuit 100 via the inverter 150, and a low-level RST signal is input to the second input terminal 124 from the output terminal 117 of the second signal detection circuit 110. The output of the output terminal 125 of the RS latch circuit 120 holds the voltage level of the previous output signal. Meanwhile, the output terminal 125 of the RS latch circuit 120 is connected to the GND terminal by the fifth NMOS transistor 153. The output terminal OUT via the inverter 151 always outputs a high-level signal VOUT. In this embodiment, the fifth NMOS transistor 153 acts as a switch that connects the output terminal 125 of the RS latch circuit 120 to the GND terminal.
[0057] The second selection signal generation circuit 130a can be configured using a combination of logic circuits, an ASIC, or a programmable single-chip microcontroller, as long as it operates in this manner. The delay time of the internal delay circuit 140 is set to be longer than the noise of the reflected signal expected from the signal wiring length, and shorter than the pulse width of the input signal.
[0058] As described above, the Schmitt circuit 1a of this embodiment operates in the same way as the Schmitt circuit 1 of the first embodiment when a high-level signal is input to the enable input terminal EN, and outputs a high-level signal VOUT from the output terminal OUT regardless of the signal at the input terminal IN when a low-level signal is input to the enable input terminal EN.
[0059] [Third Embodiment]
[0060] A third embodiment of the present invention will be described below with reference to the drawings. Figure 7 shows an example of a Schmitt circuit 1b according to this embodiment. circuit This is a diagram. The same reference numerals are used for components that are the same as in the first embodiment, and their descriptions are omitted.
[0061] The configuration of the Schmitt circuit 1b of this embodiment will now be described. The Schmitt circuit 1b of this embodiment includes a third signal detection circuit 100a, a fourth signal detection circuit 110a, an RS latch circuit 120, a third selection signal generation circuit 130b, an inverter 151, an input terminal IN, and an output terminal OUT.
[0062] The third signal detection circuit 100a includes a fifth signal detection circuit 160, a first AND circuit 163, an input terminal 105a, a selection signal input terminal 106a, and an output terminal 107a. The input terminal 105a is connected to the input terminal 161 of the fifth signal detection circuit 160. The output terminal 162 of the fifth signal detection circuit 160 is connected to the first input terminal of the first AND circuit 163. The selection signal input terminal 106a is connected to the second input terminal of the first AND circuit 163.
[0063] The fourth signal detection circuit 110a includes a sixth signal detection circuit 170, a second AND circuit 173, an input terminal 115a, a selection signal input terminal 116a, and an output terminal 117a. The input terminal 115a is connected to the input terminal 171 of the sixth signal detection circuit 170. The output terminal 172 of the sixth signal detection circuit 170 is connected to the first input terminal of the second AND circuit 173. The selection signal input terminal 116a is connected to the second input terminal of the second AND circuit 173. The third selection signal generation circuit 130b includes an input terminal 131, a fifth output terminal 136, and a sixth output terminal 137.
[0064] The connections of the Schmitt circuit 1b in this embodiment will now be described. Input terminal IN is connected to input terminal 105a of the third signal detection circuit 100a and input terminal 115a of the fourth signal detection circuit 110a. Output terminal 107a of the third signal detection circuit 100a is connected to the first input terminal 123 of the RS latch circuit 120. Output terminal 117a of the fourth signal detection circuit 110a is connected to the second input terminal 124 of the RS latch circuit 120. Output terminal 125 of the RS latch circuit 120 is connected to input terminal 131 of the third selection signal generation circuit 130b and output terminal OUT via inverter 151. Fifth output terminal 136 of the third selection signal generation circuit 130b is connected to selection signal input terminal 106a of the third signal detection circuit 100a. Sixth output terminal 137 of the third selection signal generation circuit 130b is connected to selection signal input terminal 116a of the fourth signal detection circuit 110a.
[0065] The operation of the Schmitt circuit 1b in this embodiment will be explained with reference to Figures 8 and 9. Figure 8(a) shows a state in which the signal VIN, which has reflected noise superimposed on it, rises from a low level to a high level. The signal VIN shown in Figure 8(a) has reflected noise superimposed on it, starts rising at time T40, rises above voltage VIL at time T41, rises above voltage VIH at time T42, falls above voltage VIH at time T43, falls above voltage VIL at time T44, rises above voltage VIL at time T45, and rises above voltage VIH at time T46. Here, voltage VIH is the threshold voltage of the fifth signal detection circuit, and voltage VIL is the threshold voltage of the sixth signal detection circuit. 。 The relationship between voltage VIH and voltage VIL is such that voltage VIH > voltage VIL.
[0066] As shown in Figure 8(b), the third signal detection circuit 100a outputs a high-level DET1 signal from output terminal 107a when the voltage at input terminal 105a exceeds voltage VIH, and a low-level DET1 signal when the voltage falls below VIH. As shown in Figure 8(c), the fourth signal detection circuit 110a outputs a low-level DET2 signal from output terminal 117a when the voltage at input terminal 115a exceeds voltage VIL, and a high-level DET2 signal when the voltage falls below VIL.
[0067] When the signal DOX is input to the input terminal 131, the third selection signal generation circuit 130b outputs, after a delay time by the delay circuit 140, a signal SELECT3 with the same voltage level as the signal DOX from the fifth output terminal 136, and a signal SELECT4 which is the inverted version of the signal DOX from the sixth output terminal.
[0068] When the signal VIN shown in Figure 8(a) is input to the input terminal IN, the third signal detection circuit 100a outputs a signal DET1 from the output terminal 107a, as shown in Figure 8(b), which rises to a high level at time T42, falls to a low level at time T43, and rises to a high level at time T46. The fourth signal detection circuit 110a outputs a signal DET2 from the output terminal 117a, as shown in Figure 8(c), which falls to a low level at time T41, rises to a high level at time T44, and falls to a low level at time T45.
[0069] Assuming that the signal DOX at the output terminal 125 of the RS latch circuit 120 is initialized to a high level, the third selection signal generation circuit 130b generates a high-level signal SELECT3 from the fifth output terminal 136 between time T40 and time T47, which is the same level as the signal DOX as shown in Figure 8(d), and a sixth of The RS latch circuit 120 outputs a low-level signal SELECT4, which is the inverted signal DOX as shown in Figure 8(e), from its output terminal. The RS latch circuit 120 receives the signal DET1 from the third signal detection circuit 100a at its first input terminal 123, and a low-level signal from the fourth signal detection circuit 110a at its second input terminal 124. The RS latch circuit 120 outputs a signal DOX that falls at time T42, as shown in Figure 8(f), from its output terminal 125. The third selection signal generation circuit 130b outputs the signals SELECT3 and SELECT4, which are inverted at time T47 after a delay time Delay by the delay circuit 140. The Schmitt circuit 1b of this embodiment outputs a signal VOUT from its output terminal OUT, which is the inverted signal DOX as shown in Figure 8(g), from its output terminal OUT.
[0070] Figure 9(a) shows the state in which the signal VIN, which has reflected noise superimposed on it, falls from a high level to a low level. The signal VIN shown in Figure 9(a) has reflected noise superimposed on it, and starts to rise at time T50, falls above voltage VIH at time T51, falls above voltage VIL at time T52, rises above voltage VIL at time T53, rises above voltage VIH at time T54, falls above voltage VIH at time T55, and falls above voltage VIL at time T56.
[0071] When the signal VIN shown in Figure 9(a) is input to the input terminal IN, the third signal detection circuit 100a outputs a signal DET1 from the output terminal 107a, as shown in Figure 9(b), which falls to a low level at time T51, rises to a high level at time T54, and falls to a low level at time T55. The fourth signal detection circuit 110a outputs a signal DET2 from the output terminal 117a, as shown in Figure 9(c), which rises to a high level at time T52, falls to a low level at time T53, and rises to a high level at time T56.
[0072] The third selection signal generation circuit 130b generates a low-level signal SELECT3 from the fifth output terminal 136 between time T50 and time T57, which is the same level as the signal DOX from time T50 to time T52 as shown in Figure 9(d), and the sixth of The RS latch circuit 120 outputs a high-level signal SELECT4, which is the inverted version of signal SELECT3 as shown in Figure 9(e), from its output terminal. The RS latch circuit 120 receives a low-level signal from the third signal detection circuit 100a at its first input terminal 123, and a signal DET2 from the fourth signal detection circuit 110a at its second input terminal 124. The RS latch circuit 120 outputs a signal DOX, which rises at time T52, from its output terminal 125, as shown in Figure 9(f). The third selection signal generation circuit 130b outputs signals SELECT3 and SELECT4, which are inverted at time T57 after a delay time Delay by the delay circuit 140. The Schmitt circuit 1b of this embodiment outputs a signal VOUT, which is the inverted version of signal DOX by the inverter 151, from its output terminal OUT, as shown in Figure 9(g).
[0073] In addition, the Schmitt circuit 1b in this embodiment can also be configured as a Schmitt circuit equipped with an enable input terminal EN, similar to the Schmitt circuit 1a in the second embodiment.
[0074] As explained above, according to the Schmitt circuit of the present invention, even if the input terminal of the Schmitt circuit is connected to a signal line that is not impedance-matched, and an input signal superimposed with reflection noise due to impedance mismatch is input, it is possible to output an output signal without chattering. [Explanation of Symbols]
[0075] 1, 1a, 1b, Schmitt circuit 100, 100a, 110, 110a, signal detection circuit 120. RS latch circuit 130, 130a, 130b, Select signal generation circuit 140. Delay Circuit 150, 151, 152, Inverter 153. N-channel MOS transistor 163, 173, AND gate IN, Input terminal OUT, output terminal EN, Enable terminal
Claims
1. It comprises a first signal detection circuit, a second signal detection circuit, a latch circuit, a selection signal generation circuit, a first input terminal, a first output terminal, a switch connected to the output terminal of the latch circuit, and an enable input terminal. The first input terminal is connected to the second input terminal of the first signal detection circuit and the third input terminal of the second signal detection circuit. The outputs of the first signal detection circuit and the second signal detection circuit are connected to the inputs of the latch circuit, respectively. The output of the latch circuit is connected to the input of the selection signal generation circuit and to the first output terminal. The selection signal generation circuit has a delay circuit and outputs a selection signal with a delay time due to the delay circuit in response to changes in the output signal of the latch circuit to the first selection signal input terminal of the first signal detection circuit and the second selection signal input terminal of the second signal detection circuit. The first and second signal detection circuits alternately switch between a first state, in which they detect voltage changes of the signal input to the first input terminal and change the output based on the selection signal, and a second state, in which they fix the output to a specific logic level regardless of the voltage of the input signal. The enable input terminal is connected to the selection signal generation circuit and the switch, The selection signal generation circuit, when a low-level signal is input to the enable input terminal, causes the first signal detection circuit to output a high-level signal and the second signal detection circuit to output a low-level signal. The aforementioned switch is connected between the output terminal and the GND terminal of the latch circuit, and is turned on when a low-level signal is input to the enable input terminal, thereby creating conductivity between the output terminal and the GND terminal of the latch circuit.
2. The Schmitt circuit according to claim 1, wherein the latch circuit is an RS latch circuit.
3. The Schmitt circuit according to claim 1 or 2, wherein the switch is an NMOS transistor having a gate terminal connected to the enable input terminal via an inverter.