Semiconductor device, method for manufacturing the same, and semiconductor epitaxial wafer

Abstract

The present invention provides a semiconductor device that improves the mobility of p-type channels. [Solution] The semiconductor device comprises a first SiC layer 1d having first and second regions R1 and R2, a second 3C-SiC SiC layer 4d provided on the main surface of the first SiC layer, a first transistor P-HFET provided on the second SiC layer and having a first electrode group including a first gate electrode 10G positioned between a first source electrode 10S and a first drain electrode 10D, a first AlN nitride semiconductor layer 5d provided on the main surface in the first region, a second nitride semiconductor layer 6d provided on the first nitride semiconductor layer, a third nitride semiconductor layer 7d provided on the second nitride semiconductor layer and having a larger band gap than the second nitride semiconductor layer, and a second transistor GaN-HEMT provided on the third nitride semiconductor layer and having a second electrode group including a second gate electrode 9G positioned between a second source electrode 9S and a second drain electrode 9D.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device, a method for manufacturing the same, and a semiconductor epitaxial wafer. [Background technology]

[0002] Technologies are also advancing to realize channels with higher mobility by using complementary GaN integrated circuits, which stack nitrides with different band gaps on a GaN substrate, and by utilizing two-dimensional electron gas (2DEG) and two-dimensional hole gas (2DHG) generated by heterostructures that utilize polarization effects. As a result, the development of integrated circuits that combine n-type and p-type complementary transistors is progressing, and improvements in power conversion efficiency and switching speed are expected. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2015-37190 Public Relations [Patent Document 2] Japanese Patent Publication No. 2024-35252 Public Relations [Non-patent literature]

[0004] [Non-Patent Document 1] Generation and transportation mechanisms for two-dimensional hole gases in GaN / AlGaN / GaN double heterostructures, Akira Nakajima, Pucheng Liu, Masahiko Ogura, Toshiharu Makino, Kuniyuki Kakushima, Shin-ichi Nishizawa, Hiromichi Ohashi, Satoshi Yamasaki, and Hiroshi Iwai, Journal of Applied Physics 115, 153707 (2014); doi: 10.1063 / 1.4872242 [Non-Patent Document 2] First Demonstration of a Monolithic SiC Power IC Integrating a Vertical MOSFET with a CMOS Gate Buffer, Mitsuo Okamoto, Atsushi Yao, Hiroshi Sato, Shinsuke Harada, The 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD); doi: 10.23919 / ISPSD50666.2021.9452262 [Disclosure of the Invention] [Problems that the invention aims to solve]

[0005] However, in conventional complementary heterojunction transistors, the mobility of the p-type channel in particular is low, which hinders the improvement of overall device performance. To solve this problem, there is a need to develop heterojunction structures using materials with higher mobility, as well as new device structures.

[0006] This disclosure aims to provide a semiconductor device that improves the mobility of a p-type channel. [Means for solving the problem]

[0007] To achieve the above objective, the semiconductor device in this disclosure comprises: a first SiC layer of 4H-SiC or 6H-SiC having a (0001) main surface and having a first region and a second region; a second SiC layer of 3C-SiC provided on the main surface in the first region of the first SiC layer; a first transistor provided on the second SiC layer and having a first electrode group including a first gate electrode disposed between a first source electrode and a first drain electrode; a first AlN nitride semiconductor layer provided on the main surface in the second region of the first SiC layer; a second nitride semiconductor layer provided on the first nitride semiconductor layer; a third nitride semiconductor layer provided on the second nitride semiconductor layer and having a larger band gap than the second nitride semiconductor layer; and a second transistor provided on the third nitride semiconductor layer and having a second electrode group including a second gate electrode disposed between a second source electrode and a second drain electrode. [Effects of the Invention]

[0008] The semiconductor device of this disclosure provides a complementary transistor with improved p-channel mobility, and an integrated circuit integrating the same. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a cross-sectional view of the laminated structure 100 during the manufacturing stage of a semiconductor device according to Embodiment 1. [Figure 2] Figure 2 is a cross-sectional view of the laminated structure 200 during the manufacturing stage of the semiconductor device according to Embodiment 1. [Figure 3] Figure 3 is a cross-sectional view of the laminated structure 300 during the manufacturing stage of the semiconductor device according to Embodiment 1. [Figure 4] Figure 4 is a cross-sectional view of the laminated structure 400 during the manufacturing stage of the semiconductor device according to Embodiment 1. [Figure 5] Figure 5 is a cross-sectional view of the semiconductor device according to Embodiment 1. [Figure 6] Figure 6 is an equivalent circuit diagram of the semiconductor device according to Embodiment 1. [Figure 7] Figure 7 is a cross-sectional view of the laminated structure 500 during the manufacturing stage of the semiconductor device according to Embodiment 2. [Figure 8] Figure 8 is a cross-sectional view of the stacked structure 600 during the manufacturing stage of the semiconductor device according to Embodiment 2. [Figure 9] Figure 9 is a cross-sectional view of the laminated structure 700 during the manufacturing stage of the semiconductor device according to Embodiment 2. [Figure 10] Figure 10 is a cross-sectional view of a semiconductor device according to Embodiment 2. [Figure 11] Figure 11 is a cross-sectional view of the stacked structure 900 during the manufacturing stage of a semiconductor epitaxial wafer according to Embodiment 3. [Figure 12] Figure 12 is a cross-sectional view of the stacked structure 1000 during the manufacturing stage of a semiconductor epitaxial wafer according to Embodiment 3. [Figure 13] Figure 13 is a cross-sectional view of a semiconductor epitaxial wafer according to Embodiment 3. [Figure 14] Figure 14 shows the XRD spectrum of a semiconductor epitaxial wafer according to Embodiment 3. [Figure 15] Figure 15 shows the XRD spectrum of a semiconductor epitaxial wafer according to Embodiment 3. [Figure 16] Figure 16 is an AFM image of the AlGaN layer according to Embodiment 3. [Figure 17] Figure 17 is a cross-sectional view of the semiconductor device according to Embodiment 4. [Figure 18] Figure 18 is a graph showing the characteristics evaluation of the embodiment of the device according to Embodiment 4. [Figure 19] Figure 19 is a graph showing the characterization of the semiconductor device according to Embodiment 4. [Modes for carrying out the invention]

[0010] The semiconductor device, its manufacturing method, and semiconductor epitaxial wafer described herein will be explained below with reference to the drawings. While preferred embodiments of the semiconductor device, its manufacturing method, and semiconductor epitaxial wafer described herein will be explained below, the invention is not limited thereto, and various modifications and improvements are possible based on the knowledge of those skilled in the art.

[0011] The following embodiments or examples refer to the accompanying drawings. Identical reference symbols (e.g., numbers and / or letters) in different drawings may indicate the same or similar elements.

[0012] When used in this disclosure, terms indicating that one element (e.g., a layer, region, and / or substrate) is “on” or “over” another element may indicate that the element may be “directly on” or “indirectly above” another element, with or without intervening elements. Furthermore, when used in this disclosure, terms indicating that one element is “directly on” or “directly over” another element may indicate that there are no intervening elements between them.

[0013] <Embodiment 1> A semiconductor device of Embodiment 1 and its manufacturing method will be described with reference to Figures 1 to 6.

[0014] A method for manufacturing the semiconductor device A of Embodiment 1 will be described.

[0015] (Method of manufacturing semiconductor device A of Embodiment 1) (Manufacturing process for laminated structure 100) The laminated structure 100 is n + On type 4H-SiC substrate 1, n - Type 4H-SiC epitaxial layer 2, 4H-SiC epitaxial layer 3, 3C-SiC epitaxial layer 4, AlN epitaxial layer 5, In a Al b Gac An N (0≦a≦1, 0≦b≦1, 0≦c≦1, a + b + c = 1) epitaxial layer 6, In p Al q Ga r An N (0≦p≦1, 0≦q≦1, 0≦r≦1, p + q + r = 1) epitaxial layer 7 is formed by sequentially stacking them. In the present specification, the "layer" includes, in addition to the generally known meaning, a "substrate" and a "layer formed on the substrate".

[0016] (Step S11: n + Fabrication of the n-type 4H-SiC substrate 1) n + In fabricating the n-type 4H-SiC substrate 1, an n + type 4H-SiC single crystal substrate is prepared. An n + type 4H-SiC single crystal substrate has an off-plane specified by a predetermined direction and a predetermined off-angle with respect to the main surface (0001) plane as the stacking plane. The predetermined direction is, for example, a direction within the range of ±15 degrees from the <01-20> direction. The predetermined off-angle is an angle within the range of 0.5 degrees or more and 8.0 degrees or less with respect to the main surface (0001) plane. Note that, an n + type 6H-SiC single crystal substrate may be used instead of the n + type 4H-SiC single crystal substrate.

[0017] Note that, an n + type 4H-SiC single crystal substrate is, for example, mechanically and chemically polished with respect to a commercially available 4-inch n + type 4H-SiC ingot cut out therefrom to have an off-plane specified by the above direction and off-angle. By this polishing treatment, the roughness of the substrate surface is reduced, and a smooth surface suitable for epitaxial growth and device formation is obtained. Further, the surface of the substrate is cleaned, and impurities such as organic substances and oxide films are removed.

[0018] Next, an n + etching treatment is performed on the type 4H-SiC single crystal substrate. The etching treatment is performed, for example, using a thermal etching method. Specifically, an n +A type 4H-SiC single crystal substrate is placed inside the reactor of a thermal chemical vapor deposition (CVD) apparatus. + The etching process is performed by setting the temperature of the type 4H-SiC single crystal substrate to a range of 1500°C to 1700°C, supplying hydrogen as the etching gas, and maintaining the pressure inside the reactor at 20kPa to 100kPa by evacuating the system. The etching time is in the range of 1 minute to 2 hours. High-temperature hydrogen etching produces n + The off-plane (stack surface) of the type 4H-SiC single crystal substrate is prepared. This allows n + A type 4H-SiC substrate 1 is formed.

[0019] n + By providing an off-plane on a type 4H-SiC single crystal substrate, step-flow growth is promoted during the subsequent crystal growth process, making it easier to form a homogeneous layer with fewer crystal defects. The step structure of the off-plane is an important factor in the growth of the epitaxial layer. When epitaxial growth is performed on a 4H-SiC substrate, the off-plane is used as the crystal growth surface, resulting in a uniform layer with good crystallinity.

[0020] Note that n + A drain electrode is provided on the opposite side of the laminated surface of the type 4H-SiC substrate 1. + By using the type 4H-SiC substrate 1, the on-resistance of the entire device can be reduced, and the operating efficiency of the device can be improved while maintaining high-power switching performance and high breakdown voltage performance. In particular, the n to which the drain electrode is connected + The region of the type 4H-SiC substrate 1 plays a crucial role in the current path and is essential for achieving stable operation even in high-temperature environments.

[0021] (Step S12:n - Formation of type 4H-SiC epitaxial layer 2 (drift layer) Using the thermal CVD method, n + On the off-surface (layer surface) of the type 4H-SiC substrate 1, n - A type 4H-SiC epitaxial layer 2 is formed.

[0022] First, n + The 4H-SiC substrate 1 is set to the growth temperature. A carrier gas is supplied to prepare for transporting the raw material gas onto the substrate. The raw material gas and dopant gas are supplied to start the reaction. The reaction is carried out while evacuating the reactor to maintain a predetermined pressure.

[0023] Table 1 shows n - This shows the growth conditions for type 4H-SiC epitaxial layer 2.

[0024] [Table 1]

[0025] n + A type 4H-SiC substrate 1 is heated to a predetermined temperature. Hydrogen is supplied to the reactor as a carrier gas. To advance the growth reaction, a raw material gas consisting of, for example, SiH4 (silane) and C3H8 (propane) is supplied. SiH4 (silane) is used as a silicon source, and Si atoms are deposited on the substrate. C3H8 (propane) is used as a carbon source, and C atoms form SiC crystals together with Si atoms. At the same time, nitrogen (N2) gas is introduced as a dopant, and n - An epitaxial layer with n-type characteristics is formed. Nitrogen is supplied to supply electrons into the substrate and adjust the n-type carrier concentration. The carrier concentration is, for example, 1 × 10⁻⁶. 16 cm -3 This is set to n + n - A type 4H-SiC epitaxial layer 2 is formed. - The type 4H-SiC epitaxial layer 2 has a thickness of, for example, 10 μm, but is not limited to this. For example, n - The thickness range of the type 4H-SiC epitaxial layer 2 may be between 5 μm and 50 μm, taking into consideration device performance and crystal growth optimization.

[0026] Furthermore, the growth temperature is not limited to 1600°C. For example, it may be adjusted within the range of 1500°C to 1700°C. The reaction pressure in the reactor during the reaction is not limited to 25kPa. Taking into consideration that if the reaction pressure is too high, crystal defects are likely to occur, and if it is too low, growth will be insufficient, it may be adjusted within the range of 20kPa to 100kPa. Also, steps S11 and S12 are n + The process may be carried out continuously by adjusting the temperature and pressure inside the furnace of the thermal CVD apparatus without removing the type 4H-SiC single crystal substrate from the apparatus.

[0027] (Process S13: Formation of 4H-SiC epitaxial layer 3 (insulating layer / semi-insulating layer)) Using the thermal CVD method, n - A 4H-SiC epitaxial layer 3 is formed on top of a type 4H-SiC epitaxial layer 2. Table 2 shows the growth conditions for the 4H-SiC epitaxial layer 3.

[0028] [Table 2]

[0029] Hydrogen is supplied to the reactor as a carrier gas. To advance the growth reaction, a raw material gas consisting of, for example, SiH4 (silane) and C3H8 (propane) is supplied. SiH4 (silane) is used as a silicon source, and Si atoms are deposited on the substrate. C3H8 (propane) is used as a carbon source, and C atoms form SiC crystals together with Si atoms. As a result, n - A 4H-SiC epitaxial layer 3 is formed on top of a type 4H-SiC epitaxial layer 2. The grown 4H-SiC epitaxial layer 3 is so-called semi-insulating, meaning it has a resistivity of 1 × 10⁻⁶. 5It has insulating properties of Ωcm or more. The grown 4H-SiC epitaxial layer 3 has a thickness of, for example, 4 μm, but is not limited to this. For example, the thickness range of the 4H-SiC epitaxial layer 3 may be 0.5 μm to 20 μm. Within this range, a thinner thickness is preferable because it allows for higher productivity and lower production costs, while a thicker thickness is preferable because it suppresses the influence of the drive voltage of the SiC-MOSFET 103 provided in the third region on the channel potential of the GaN-HEMT 102 and P-HFET 101 provided in the first and second regions.

[0030] Furthermore, in order to form a depletion region to suppress the influence of the driving voltage of the SiC-MOSFET103 on the channel potential of the GaN-HEMT102 and P-HFET101 provided in the first and second regions, n - A p-type 4H-SiC epitaxial layer may be further provided between the type 4H-SiC epitaxial layer 2 and the 4H-SiC epitaxial layer 3.

[0031] The growth temperature is not limited to 1600°C. For example, it may be adjusted within the range of 1500°C to 1700°C. The reaction pressure in the reactor during the reaction is not limited to 25kPa. Taking into consideration that too high a reaction pressure can easily cause crystal defects, and too low a pressure can result in insufficient growth, it may be adjusted within the range of 20kPa to 100kPa.

[0032] The 4H-SiC epitaxial layer 3 may be mechanically and chemically polished so that it has an off-plane as a laminated surface, which is specified by a predetermined direction and a predetermined off-angle with respect to the main surface (0001). The predetermined direction is, for example, a direction within ±15 degrees from the <01-10> direction. The predetermined off-angle is an angle in the range of 0 degrees to 1.0 degrees with respect to the main surface (0001). This polishing process facilitates the suppression of crystal defects in the 3C-SiC epitaxial layer 4 provided on the 4H-SiC epitaxial layer 3. Furthermore, the surface of the substrate is cleaned to remove impurities such as organic matter and oxide films.

[0033] (Process S14: 3C-SiC epitaxial layer 4) A 3C-SiC epitaxial layer 4 is formed on top of a 4H-SiC epitaxial layer 3 using thermal CVD. Table 3 shows the growth conditions for the 3C-SiC epitaxial layer 4.

[0034] [Table 3]

[0035] Hydrogen is supplied to the reactor as a carrier gas. To advance the growth reaction, a raw material gas consisting of, for example, SiH4 (silane) and C3H8 (propane) is supplied. SiH4 (silane) is used as a silicon source, and Si atoms are deposited on the substrate. C3H8 (propane) is used as a carbon source, and C atoms, together with Si atoms, form a SiC crystal. As a result, a 3C-SiC epitaxial layer 4 is formed on the 4H-SiC epitaxial layer 3. The grown 3C-SiC epitaxial layer 4 has a thickness of, for example, 50 nm, but is not limited to this. For example, the thickness range of the 3C-SiC epitaxial layer 4 may be between 10 nm and 200 nm, taking into consideration device performance and crystal growth optimization.

[0036] The growth temperature is not limited to 1400°C. For example, it may be adjusted within the range of 1300°C to 1500°C. The reaction pressure in the reactor during the reaction is not limited to 25kPa. Taking into consideration that too high a reaction pressure can easily cause crystal defects, and too low a pressure can result in insufficient growth, it may be adjusted within the range of 10kPa to 100kPa.

[0037] (Process S15: AlN epitaxial layer 5 (insulator)) A nitride semiconductor AlN epitaxial layer 5 is formed on a 3C-SiC epitaxial layer 4 using thermal CVD. Table 4 shows the growth conditions for the AlN epitaxial layer 5.

[0038] [Table 4]

[0039] Hydrogen is supplied to the reactor as a carrier gas. To advance the growth reaction, a raw material gas consisting of TMA (trimethylaluminum) and NH3 (ammonia) is supplied. TMA is used as the aluminum source and NH3 is used as the nitrogen source, and AlN crystals are deposited on the substrate. This forms an AlN epitaxial layer 5 on top of the 3C-SiC epitaxial layer 4. The grown AlN epitaxial layer 5 has a thickness of, for example, 50 nm, but is not limited to this. The thickness range of the AlN epitaxial layer 5 may be between 10 nm and 1000 nm, taking into consideration device performance and crystal growth optimization.

[0040] The growth temperature is not limited to 1200°C. For example, it may be adjusted within the range of 1000°C to 1400°C. If the temperature is too low, the decomposition of the raw material gas will be insufficient, reducing growth efficiency and slowing the formation of the epitaxial layer, so 1000°C is set as the critical lower limit. High-temperature growth makes it easier for defects to form in the crystal and also increases the risk of coarse grain growth, so optimization of the growth conditions is necessary. 1400°C is set as the critical upper limit. The reaction pressure in the reactor is not limited to 15kPa. Taking into consideration that if the reaction pressure is too high the growth rate will be too fast and if it is too low the growth will be insufficient, it may be adjusted within the range of 10kPa to 100kPa. When the reaction pressure is low, there are fewer defects and impurities in the crystal, improving crystal quality, but the growth rate slows down and production efficiency decreases, so 10kPa is set as the critical lower limit. While higher reaction pressures improve crystal growth rates, they also increase the likelihood of coarse grains forming on the growth surface and the risk of defects occurring within the crystal. Therefore, 100 kPa is set as the critical upper limit.

[0041] (Step S16:In a Al b Ga c N epitaxial layer 6: n-type channel layer) Using thermal CVD, a nitride semiconductor, In, is deposited on the AlN epitaxial layer 5. a Al b Ga c N epitaxial layer 6 is formed. Table 5 shows In a Al b Ga c This shows the growth conditions for N epitaxial layer 6 (0≦a≦1, 0≦b≦1, 0≦c≦1, a+b+c=1).

[0042] [Table 5]

[0043] Hydrogen is supplied to the reactor as a carrier gas. TMI (trimethylindium), TMG (trimethylgallium), TMA (trimethylaluminum), and NH3 are supplied as raw material gases to advance the growth reaction. If a=0, TMI is not supplied. If b=0, TMA is not supplied. If c=0, TMG is not supplied. TMI (trimethylindium) is used as an indium source. TMG (trimethylgallium) is used as a gallium source. TMA is used as an aluminum source. NH3 is used as a nitrogen source. These gases cause In to grow on top of the AlN epitaxial layer 5. a Al b Ga c N epitaxial layer 6 is formed. a Al b Ga c The N epitaxial layer 6 has a thickness of, for example, 1000 nm.

[0044] The In content can be adjusted depending on the device's application and required characteristics. A higher In content results in a narrower band gap and improved electron mobility. The In composition ratio a is set within the range of 0 to 0.5.

[0045] The Al content can be adjusted depending on the device's application and required characteristics. A higher Al content results in a wider band gap, making it suitable for high-temperature operation and high-voltage devices. Typically, the Al composition ratio b is set within the range of 0 to 0.5.

[0046] The Ga content can be adjusted depending on the device's application and required characteristics. Increasing the Ga content narrows the band gap and improves electron mobility. The Ga composition ratio c is set, for example, within the range of 0.1 to 1.0. The composition ratios of In, Al, and Ga (a, b, c) are controlled by adjusting the flow ratios of TMI, TMA, and TMG.

[0047] Furthermore, In functions as an n-type channel layer. a Al b Ga c The thickness of the N epitaxial layer 6 is not limited to 1000 nm. For example, it may be adjusted within the range of 500 nm to 3000 nm. 500 nm is the critical lower limit to maintain the fast response of the n-type channel while improving gate controllability. 3000 nm is the critical upper limit to maintain appropriate gate control while ensuring carrier mobility and current drive capability.

[0048] In a Al b Ga cThe growth temperature of the N epitaxial layer 6 is not limited to 1000°C. For example, it may be adjusted within the range of 1000°C to 1250°C. If the temperature is too low, the decomposition of the raw material gas will be insufficient, reducing growth efficiency and slowing the growth rate of the epitaxial layer, so 1000°C is set as the critical lower limit. High-temperature growth makes it easier for defects to form in the crystal and also increases the risk of coarse grain growth, so 1250°C is set as the critical upper limit. The reaction pressure in the reactor is not limited to 15kPa. Taking into consideration that if the reaction pressure is too high the growth rate will be too fast and if it is too low the growth will be insufficient, it may be adjusted within the range of 10kPa to 100kPa. When the reaction pressure is low, there are fewer defects and impurities in the crystal, improving crystal quality, but the growth rate slows down and production efficiency decreases, so 10kPa is set as the critical lower limit. While higher reaction pressures improve crystal growth rates, they also increase the likelihood of coarse grains forming on the growth surface and the risk of defects occurring within the crystal. Therefore, 100 kPa is set as the critical upper limit.

[0049] (Step S17:In p Al q Ga r Formation of N epitaxial layer 7) Using the thermal CVD method, In a Al b Ga c On top of the N epitaxial layer 6, there is a nitride semiconductor called In p Al q Ga r It forms an N epitaxial layer 7. Table 6 shows In p Al q Ga r This shows the growth conditions for the N epitaxial layer 7 (0≦p≦1, 0≦q≦1, 0≦r≦1, p+q+r=1).

[0050] [Table 6]

[0051] Hydrogen is supplied to the reactor as the carrier gas. To advance the growth reaction, TMI (trimethylindium), TMG (trimethylgallium), TMA (trimethylaluminum), and NH3 are supplied as source gases. When p = 0, TMI is not supplied. When q = 0, TMA is not supplied. When r = 0, TMG is not supplied. With these gases, In a Al b Ga c An In p Al q Ga r N epitaxial layer 7 is provided on the In p Al q Ga r N epitaxial layer 6. The bandgap of the In a Al b Ga c N epitaxial layer 7 is larger than that of the In p Al q Ga r N epitaxial layer 6. The In p Al q Ga r N epitaxial layer 7 has a thickness of, for example, 25 nm. Note that source electrodes, gate electrodes, and drain electrodes can be formed on the In

[0052] Note that the thickness of the In p Al q Ga r N epitaxial layer 7 is not limited to 25 nm. For example, it may be adjusted within the range of 10 nm or more and 100 nm or less. To enhance the electric field control, 10 nm is the critical lower limit. To improve the current driving ability, 100 nm is the critical upper limit.

[0053] Note that the In p Al q Ga rThe growth temperature of the N epitaxial layer 7 is not limited to 1200°C. For example, it may be adjusted within the range of 1000°C to 1250°C. If the temperature is too low, the decomposition of the raw material gas will be insufficient, reducing growth efficiency and slowing the growth rate of the epitaxial layer, so 1000°C is set as the critical lower limit. High-temperature growth makes it easier for defects to form in the crystal and also increases the risk of coarse grain growth, so 1250°C is set as the critical upper limit. The reaction pressure in the reactor is not limited to 15kPa. Taking into consideration that if the reaction pressure is too high the growth rate will be too fast and if it is too low the growth will be insufficient, it may be adjusted within the range of 10kPa to 100kPa. When the reaction pressure is low, there are fewer defects and impurities in the crystal, improving crystal quality, but the growth rate slows down and production efficiency decreases, so 10kPa is set as the critical lower limit. While higher reaction pressures improve crystal growth rates, they also increase the likelihood of coarse grains forming on the growth surface and the risk of defects occurring within the crystal. Therefore, 100 kPa is set as the critical upper limit.

[0054] (Manufacturing process for laminated structure 200) The laminated structure 200 is formed by processing the laminated structure 100 using lithography. As shown in Figure 2, the laminated structure 200 has a first region R1 corresponding to a GaN-HEMT (High Electron Mobility Transistor), a second region R2 corresponding to a P-HFET (P-channel Heterojunction Field Effect Transistor), and a third region R3 corresponding to a SiC-MOSFET.

[0055] (Process S21: First dry etching process) In order to mask the first region R1 and expose the 3C-SiC epitaxial layer 4 in the second region R2 and the third region R3, the layer stacked on top (In p Al q Ga r N epitaxial layer 7, In a Al b Gac Remove the N epitaxial layer 6 and the AlN epitaxial layer 5). Using photolithography, remove the uppermost In layer in the first region R1. p Al q Ga r A photoresist is applied to the top layer of In to protect the N epitaxial layer 7. p Al q Ga r The N epitaxial layer 7 is applied to the surface and then exposed and developed.

[0056] The first dry etching step is a process that uses gas to react with and remove solid materials. For example, plasma etching or RIE (reactive ion etching) techniques may be used. Dry etching involves the ionization or chemical reaction of gas to remove In in the second region R2 and the third region R3. p Al q Ga r N epitaxial layer 7, In a Al b Ga c The N epitaxial layer 6 and the AlN epitaxial layer 5 are removed.

[0057] (Process S22: Second dry etching process) Next, a photoresist is used as a mask on the upper layers of the first region R1 and the second region R2, and dry etching is performed to expose the 4H-SiC epitaxial layer 3 in the third region.

[0058] (Process S23: Third dry etching process) In the third region where the 4H-SiC epitaxial layer 3 is exposed, SiO2 is used as a mask and dry etching is performed, n - A portion of the molded 4H-SiC epitaxial layer 2 is exposed to form an opening 20 in the 4H-SiC epitaxial layer 3. Dry etching can be performed using CHF3 or CHCl3 gas.

[0059] (Process S24: Fourth dry etching process) Next, using a photoresist as a mask, dry etching is performed to form a recess 13 in the 3C-SiC epitaxial layer 4, and further, In a Al b Ga c A recess 14 is formed in the N epitaxial layer 7. Dry etching can be performed using CHF3 or CHCl3 gas.

[0060] The laminated structure 200 is formed through steps S21 to S24. The laminated structure 200 is formed by dividing the laminated structure 100 into three regions corresponding to three transistor structures.

[0061] By forming recesses 13 and 14, the two-dimensional carriers directly beneath those areas are depleted, allowing the transistor to operate normally-off.

[0062] Recesses 13 and 14 are the regions where the gate electrodes of the P-HFET and GaN-HEMT are formed, respectively. These recess structures control current by depleting the carriers beneath the gate. When recesses 13 and 14 are formed, the carriers in the region beneath the gate electrode enter a "depleted state." This means that there are not enough carriers, or that they are unable to move easily. Due to this depleted state, no current flows in the channel unless a gate voltage is applied, thus realizing normally-off operation. Normally-on operation refers to a state in which a transistor flows current even when no voltage is applied to the gate. In contrast, in normally-off operation, no current flows unless a voltage is applied to the gate. In the P-HFET, hole carriers are the main mobile carriers. Recess 13 depletes the holes directly beneath the gate electrode, thus realizing a normally-off state in which no current flows unless an appropriate voltage is applied to the gate. In the GaN-HEMT, electron carriers are the main mobile carriers. Similarly, recess 14 depletes the electron carriers, resulting in normally-off operation where no current flows until voltage is applied to the gate electrode.

[0063] Furthermore, the threshold voltage can be adjusted by adjusting the depth of recesses 13 and 14. The threshold voltage (Vth) is the minimum gate voltage required for current to begin flowing in a transistor (switching to ON). In FETs and HEMTs, the threshold voltage determines whether the device operates on or off, so Vth is an important basic characteristic parameter of the device. A high Vth is advantageous for maintaining a state where current is difficult to flow when the transistor is in the OFF state. On the other hand, a low Vth is suitable for low-voltage driven devices because it improves switching speed and efficiency.

[0064] The threshold voltage fluctuates in the negative direction for p-type channels (P-HFET101) and in the positive direction for n-type channels (GaN-HEMT102) as the recess deepens. This fluctuation allows the threshold voltage to be adjusted as needed.

[0065] Normally-off operation is crucial in complementary transistors. In the basic operation of complementary transistors, it is desirable that no current flows when no gate voltage is applied to either the P-type or N-type transistor (for example, when the switch is not flipped), i.e., when the transistor is in an off state. To achieve this, it is essential that both the P-type and N-type transistors operate normally-off. Because the device automatically turns off when no gate voltage is applied, this characteristic of avoiding unnecessary power consumption contributes to the power-saving characteristics of complementary transistors. If either the P-type or N-type transistor in a complementary transistor operates normally-off, current will flow even when no gate voltage is applied. This results in wasted power consumption even in standby or non-switching states, compromising the low power consumption characteristic of complementary transistors.

[0066] In view of the above, the depth and width of the recess 13 having a bottom for forming the gate electrode of the P-HFET and the recess 14 having a bottom for forming the gate electrode of the GaN-HEMT are set by the threshold voltage (Vth), current drive capability, operating frequency, etc.

[0067] (Manufacturing process for laminated structure 300) The laminated structure 300 is n in the third region R3 of the laminated structure 200. - P is present in the 4H-SiC epitaxial layer 2. + Region and N + It is formed by defining a region.

[0068] (Step S30:P + Region 18 and N + Formation of region 19) First, n - A photoresist mask is formed on the surface of the type 4H-SiC epitaxial layer 2, and ion implantation and annealing treatment are performed on the region exposed through the opening 20, thereby P + Regions 18 and N + Forms region 19. P + Area 18 contains aluminum in 5 × 10 18 atoms / cm 3 Ion implantation is performed at a concentration such that the depth direction has a width of, for example, 100 nm. + Region 19 contains phosphorus in 1 × 10⁻⁶ units. 20 atoms / cm 3 Ion implantation is performed at a concentration such that the depth direction is, for example, 50 nm wide. Next, the implanted ions are activated by annealing in an argon (Ar) atmosphere at 1100°C for 20 minutes.

[0069] (Manufacturing process for laminated structure 400) (Step S41: Formation of oxide film 15) An oxide film 15 is formed within the opening 20 in the third region R3. First, SiO2 is deposited to a thickness of 80 nm on the exposed surface within the opening 20 using plasma CVD. Next, unwanted portions are removed by wet etching with BHF using a photoresist mask. The SiO2 remaining in the area protected by the mask is formed as the oxide film 15. The oxide film 15 (e.g., SiO2) functions as an insulating layer between the gate electrode and the semiconductor layer and is provided to control the channel by the field effect.

[0070] (Step S42: Formation of gate electrode 12) In the third region R3, the surface of the oxide film 15 is first cleaned in order to form the gate electrode 12. Next, a material such as polycrystalline silicon or a metallic material (e.g., titanium, aluminum, tungsten) is deposited onto the oxide film 15 using the CVD method. After deposition, the pattern of the gate electrode 12 is formed using photolithography and etching techniques. Through this process, a gate electrode 12 having a predetermined shape and thickness is formed on the oxide film 15.

[0071] (Step S43: Formation step of ohmic electrode 8, ohmic electrode 10, and ohmic electrode 11) To sequentially form ohmic electrodes 8 (drain electrode 8), 10 (drain electrode 10D and source electrode 10S), and 11 (source electrode 11), a photoresist mask is patterned using photolithography. Next, a metallic material (e.g., nickel, aluminum, gold) is deposited onto the target area using vacuum deposition. After deposition, the metal film is removed along with unwanted photoresist using the lift-off method to form the patterns of ohmic electrodes 8, 10, and 11. Subsequently, the formed ohmic electrodes are annealed at a temperature of 950°C for 2 minutes. This annealing process creates good ohmic properties at the electrode-semiconductor interface, resulting in ohmic electrodes 8, 10, and 11 that have low resistance and enable stable current injection.

[0072] (Process S44: Process for forming the ohmic electrode 9) To form the ohmic electrode 9 (drain electrode 9D and source electrode 9S), photolithography is used to pattern the photoresist and create a mask in the desired area. Then, a metal material (e.g., nickel, aluminum, gold, etc.) is deposited onto the target area using vacuum deposition. Once deposition is complete, the photoresist and unwanted metal film are removed using the lift-off method to form the shape of the ohmic electrode 9.

[0073] After electrode formation, the electrodes are annealed at 800°C for 1 minute. This annealing process creates good ohmic contact at the metal-semiconductor interface, resulting in low contact resistance. This completes the ohmic electrode 9, enabling efficient current injection and stable operation.

[0074] (Process S45: Formation process of gate electrodes 16 and 17) To form gate electrodes 16 and 17, photolithography is used to pattern a photoresist and create a mask over the desired area. Then, a metallic material such as nickel, aluminum, or polycrystalline silicon is deposited onto the target area using a vacuum deposition method. After deposition is complete, the lift-off method is used to remove the unwanted metal film along with the photoresist, forming the patterns for gate electrodes 16 and 17. This process ensures that gate electrodes 16 and 17 are formed within the recess 14. p Al q Ga r These structures are formed on the N epitaxial layer 7 and the 3C-SiC epitaxial layer 4 within the recess 13, respectively, completing the structure necessary for controlling the transistor's electric field.

[0075] (Semiconductor device A) Figure 5 is a cross-sectional view of semiconductor device A according to this embodiment 1. Semiconductor device A includes a P-HFET 101 as a P-type transistor, a GaN-HEMT 102 as an N-type transistor, and an N-type SiC-MOSFET 103 whose gate is controlled according to the output voltage Vout from the P-HFET 101 and the GaN-HEMT 102.

[0076] (P-HFET101) The P-HFET101 consists of a 4H-SiC epitaxial layer 3, a 3C-SiC epitaxial layer 4 provided on top of the 4H-SiC epitaxial layer 3, a gate electrode 17 provided at the bottom of the recess of the 3C-SiC epitaxial layer 4, and a drain electrode 10D and a source electrode 10S provided on either side of the recess.

[0077] The 3C-SiC epitaxial layer 4 has 2DHG extending along the heterointerface with the 4H-SiC epitaxial layer 3.

[0078] The P-HFET101 and GaN-HEMT102 are configured to not electrically influence each other by an AlN epitaxial layer 5. The P-HFET101 and SiC-MOSFET103 are configured to not electrically influence each other by a 4H-SiC epitaxial layer 3.

[0079] (GaN-HEMT102) GaN-HEMT102 consists of an AlN epitaxial layer 5 and an In layer provided on top of the AlN epitaxial layer 5. a Al b Ga c N epitaxial layer 6 and In a Al b Ga c In provided on the N epitaxial layer 6 p Al q Ga r N epitaxial layer 7 and In p Al q Ga r It consists of a gate electrode 16 provided at the bottom of the recess of the N epitaxial layer 7, and a drain electrode 9D and a source electrode 9S provided so as to sandwich the recess.

[0080] In a Al b Ga c N epitaxial layer 6 is In p Al q Ga r It has a 2DEG that extends along the interface with the N epitaxial layer 7. The 2DEG is In a Al b Ga c N epitaxial layer 6 and In p Al q Ga r It is formed due to the difference in band gap and degree of polarization with the N epitaxial layer 7.

[0081] (SiC-MOSFET103) The SiC-MOSFET103 is a power MOSFET with a so-called N-type DMOS (Double-diffused Metal-Oxide-Semiconductor) structure, achieving high voltage resistance and high switching efficiency by using SiC material. The N-type DMOS structure reduces on-resistance and enables high-speed switching by manufacturing the region necessary for channel formation using double diffusion technology. The SiC-MOSFET103 is n + Type 4H-SiC substrate 1 and n - Type 4H-SiC epitaxial layer 2 and P + Region 18 and N + The device comprises a region 19, a source electrode 11, a drain electrode 8, an oxide film 15, and a gate electrode 12.

[0082] n + The type 4H-SiC substrate 1 is the support substrate for the entire device and supports the N-type drift layer, which has high conductivity.

[0083] n - Type 4H-SiC epitaxial layer 2 is n + This is a drift region provided on the type 4H-SiC substrate 1, which functions to ensure the device's breakdown voltage performance. This region provides resistance to maintain a high voltage when current flows from the drain 8 to the source 11.

[0084] P + Region 18 is a P-type body region located below the gate electrode 12, and in the switching operation of the MOSFET, it forms a channel in response to the voltage applied to the gate electrode 12, controlling the flow of current from the drain 8 to the source 11. The channel is located below the gate electrode 12, and is P-type. + It is formed at the edge of region 18.

[0085] N + Region 19 will serve as the source region and become the electron injection point. Source and P +The PN junction formed between the body regions reduces leakage current in the off state.

[0086] The source electrode 11 is N + It is connected to region 19 and forms a terminal for current to flow out of the device.

[0087] The drain electrode 8 is n + It is connected to the type 4H-SiC substrate 1 and forms a terminal into which current flows.

[0088] The oxide film 15 is formed by the gate electrode 12 and n - This insulating layer is provided between the 4H-SiC epitaxial layer 2 and the gate voltage, and functions to efficiently transmit the electric field formed by the gate voltage.

[0089] The gate electrode 12 is provided on the oxide film 15 and functions to control the switching of the MOSFET. When a gate voltage is applied, P + An electron channel is formed in region 18, allowing electrons to flow from the source to the drain.

[0090] (Equivalent circuit) Figure 6 shows an equivalent circuit 100 of semiconductor device A according to Embodiment 1. The equivalent circuit 100 includes a P-HFET 101 as a P-type transistor, a GaN-HEMT 102 as an N-type transistor, and a SiC-MOSFET 103 whose gate is controlled according to the output voltage Vout from the P-HFET 101 and the GaN-HEMT 102.

[0091] (P-HFET101) The P-HFET 101 has its source electrode 10S connected to the power supply voltage VDD and its drain electrode 10D connected to the output voltage Vout. The gate electrode 17 is connected to the input signal Vin, and the on / off state of the P-HFET 101 is controlled according to the value of Vin. When the input signal Vin is "low" (e.g., logic level "0"), the P-HFET 101 is in the ON state, and when the input signal Vin is "high" (logic level "1"), the P-HFET 101 is in the OFF state.

[0092] In the off state, Vin is in the "high" state (logic level "1"), so no current flows between the source and drain. In other words, no movement of the 2DHG occurs.

[0093] When the P-HFET 101 is ON, Vin is in a "low" state (logic level "0"), and the gate voltage of the P-HFET 101 becomes low, causing current to flow between the source and drain. As a result, the P-HFET 101 conducts current from the source electrode to the drain electrode, and the output voltage Vout is set to the power supply voltage VDD. When the P-HFET 101 is turned ON, 2DHG moves from the source to the drain. As a result, current flows from the source electrode 10S to the drain electrode 10D, and the output voltage Vout is set to the power supply voltage VDD.

[0094] (GaN-HEMT102) The GaN-HEMT102 has its source electrode 9S connected to ground potential VSS and its drain electrode 9D connected to output voltage Vout. The gate electrode 16 is connected to the input signal Vin, and the on / off state of the GaN-HEMT102 is controlled according to the value of Vin. When the input signal Vin is "high" (logic level "1"), the GaN-HEMT102 is turned on, and when the input signal Vin is "low" (logic level "0"), the GaN-HEMT102 is turned off.

[0095] In the off state, Vin is in a "low" state (logic level "0"), so the gate voltage of the GaN-HEMT102 is relatively low compared to the source voltage VSS, and no channel is formed. Therefore, no current flows between the source and drain. In other words, no 2DEG movement occurs.

[0096] When the device is ON, the input signal Vin is in a "high" state (logic level "1"), and the gate voltage of the GaN-HEMT102 becomes relatively high relative to the source voltage VSS, forming a channel and allowing current to flow between the source and drain. That is, 2DEG at the interface moves from the source to the drain (current moves from the drain to the source). As a result, the output voltage Vout is set to the ground potential VSS.

[0097] (SiC-MOSFET103) The SiC-MOSFET 103 has its source electrode 11 connected to ground potential Vs and its drain electrode 8 connected to drain voltage Vd. The gate electrode 12 is connected to the output voltage Vout, and the on / off state of the SiC-MOSFET 103 is controlled according to the value of the output voltage Vout.

[0098] When a gate voltage is applied to the gate electrode 12 of the SiC-MOSFET 103, and the SiC-MOSFET 103 turns on, a channel is formed. In this state, the SiC-MOSFET 103 has low on-resistance, so the voltage drop between the drain (Vd) and source (Vs) becomes very small. Therefore, the drain voltage Vd of the SiC-MOSFET 103 is almost the same as the ground potential Vs. In reality, a small voltage drop Vds occurs, but it depends on the on-resistance and is a small value. When the SiC-MOSFET 103 is on, if a load is connected to the drain voltage Vd, the potential on the load side will be the ground potential Vs.

[0099] When a gate voltage is applied to the gate electrode 12 of the SiC-MOSFET 103, and the SiC-MOSFET 103 turns off, the channel closes and current stops flowing. In this case, the drain voltage Vd of the SiC-MOSFET 103 is the potential on the load side, that is, the voltage applied to the load. If a high voltage is applied to the load, a high voltage will be maintained at the drain terminal 8 of the SiC-MOSFET 103. In this state, the SiC-MOSFET 103 has blocked the current (channel), and almost no drain current flows.

[0100] The equivalent circuit 100 of semiconductor device A according to Embodiment 1 is applicable to power electronics and switching power supplies. This circuit combines the low power consumption characteristics of a push-pull structure consisting of a P-type transistor P-HFET 101 and an N-type transistor GaN-HEMT 102, or a CMOS structure, with the high power control capability of a SiC-MOSFET 103. Based on a CMOS inverter, the SiC-MOSFET 103 is controlled through P-type and N-type transistors, resulting in a design that can handle high-voltage and high-current applications. This improves power conversion efficiency and suppresses switching losses, achieving highly reliable and efficient operation, making it applicable, for example, to renewable energy conversion devices and power management systems for electric vehicles.

[0101] In general, the difference in carrier mobility between p-type and n-type transistors in complementary circuits can have various impacts on the circuit's performance and design.

[0102] (Difference in mobility between n-type and p-type) Generally, the mobility of an n-type channel is higher than that of a p-type channel. This difference in mobility means that, when driven by the same voltage, an N-type transistor operates faster than a P-type transistor. This can cause problems in balancing complementary circuits.

[0103] (Impact of switching speeds) Complementary circuits process digital signals using a pair of N-type and P-type transistors. However, N-type transistors have higher mobility, resulting in faster switching speeds, while P-type transistors tend to lag behind. This imbalance limits the overall switching speed of the circuit. In high-speed digital circuits and high-frequency applications, the delay of the P-type transistor can become a bottleneck, potentially degrading the overall circuit performance.

[0104] (Transistor size imbalance) To compensate for the difference in mobility, P-type transistors are typically designed to be larger than N-type transistors. This is because the lower mobility of the p-type channel requires a larger channel area to supply the same current.

[0105] (Impact on power consumption) Due to their low mobility, P-type transistors require a larger size to achieve the same switching speed, which increases their capacitance. As a result, the amount of charge charged and discharged during switching increases, leading to increased switching losses. This effect is particularly significant at high frequencies, leading to increased power consumption. Furthermore, the slow mobility of the p-type channel means that the circuit may be affected by switching delays, potentially reducing power efficiency.

[0106] To address these problems caused by the difference in mobility between n-type and p-type transistors, according to semiconductor device A of Embodiment 1 of this disclosure, the P-HFET, which functions as a p-type transistor, utilizes 2DHG generated at the interface between the 4H-SiC epitaxial layer 3 and the 3C-SiC epitaxial layer 4. The 2DHG generated at the interface between 3C-SiC and 4H-SiC exhibits higher hole mobility compared to existing SiC devices. Specifically, the hole mobility at 293K is 30 cm². 2 It has a / Vs value and exhibits higher performance than conventional devices.

[0107] (Presence of high-mobility carriers) The 2DHG generated at the 3C-SiC and 4H-SiC interface exhibits higher Hall mobility compared to existing SiC devices. This improves the current density and switching speed of the device, enabling more efficient device design. Specifically, the Hall mobility at 293K is 30 cm². 2 It has a / Vs value, indicating higher performance than conventional devices.

[0108] The semiconductor device A of Embodiment 1 of this disclosure can provide the following effects.

[0109] (Effect 1: Improved switching speed due to increased mobility of p-type channels) 3C-SiC / 4H-SiC junctions using 2DHG exhibit higher hole mobility than conventional SiC devices. This improves the switching speed of p-type channels, bringing the switching speed of p-type transistors closer to that of N-type transistors, and potentially mitigating the switching speed imbalance in complementary circuits.

[0110] (Effect 2: Reduction in transistor size) By realizing a high-mobility p-type channel, it may be possible to achieve equivalent current drive capability with smaller transistors compared to conventional p-type transistors. This reduces the need to make p-type transistors larger than n-type transistors, potentially improving the imbalance in transistor sizes. Furthermore, the reduction in size contributes to a reduction in chip area and manufacturing costs, potentially enabling highly integrated circuit designs.

[0111] (Effect 3: Reduced power consumption) High Hall mobility allows for faster switching speeds in P-type transistors, thus reducing switching losses. This reduces the amount of charge and discharge during switching, potentially lowering power consumption. In particular, it suppresses the increase in power consumption during high-frequency operation, improving energy efficiency and preventing a decrease in power efficiency.

[0112] As described above, by utilizing the high hole mobility provided by 2DHG generated at the interface between 3C-SiC and 4H-SiC, problems caused by the low mobility of p-type channels in complementary circuits can be improved. This leads to improved performance of the complementary circuit as a whole, including increased switching speed of p-type transistors, reduced size of p-type transistors, and lower power consumption, making it particularly applicable in applications requiring operation at high frequencies and high temperatures.

[0113] <Embodiment 2> The semiconductor device A according to Embodiment 1 was oriented to have a stacked structure comprising a 3C-SiC epitaxial layer 4 between a 4H-SiC epitaxial layer 3 and an AlN epitaxial layer 5. The semiconductor device B according to Embodiment 2 is oriented to have a different configuration of the 3C-SiC epitaxial layer 4 compared to Embodiment 1.

[0114] A method for manufacturing the semiconductor device B according to Embodiment 2 will be described using Figures 7 to 10.

[0115] (Laminated structure 500) (Step S51:n + (Formation of 4H-SiC substrate 1) Since this is the same as step S11 of Embodiment 1, the details will be omitted. Note that a 6H-SiC single crystal substrate may be used instead of a 4H-SiC single crystal substrate.

[0116] (Step S52:n + Formation of 4H-SiC epitaxial layer 2) Since this is the same as step S12 in Embodiment 1, the details will be omitted.

[0117] (Step S53: Formation of 4H-SiC epitaxial layer 3) Since this is the same as step S13 in Embodiment 1, the details will be omitted.

[0118] (Step S54: Formation of 3C-SiC epitaxial layer 4) Since this is the same as step S14 in Embodiment 1, the details will be omitted.

[0119] (Process S55: Formation of a partially exposed surface of the 4H-SiC epitaxial layer 3) First, a portion of the 3C-SiC epitaxial layer 4 is removed by dry etching. CHF3 or CHCl3 gas can be used for dry etching. Here, the region of the 3C-SiC epitaxial layer 4 to be etched is the region for growing the AlN epitaxial layer 5. Next, an SiO2 film is deposited over the entire surface. Then, wet etching is performed using a photoresist as a mask to remove the SiO2 film formed on areas other than the 3C-SiC epitaxial layer 4, exposing a portion of the 4H-SiC epitaxial layer 3.

[0120] (Step S56: Formation of AlN epitaxial layer 5) An AlN epitaxial layer 5 is grown on a partially exposed surface of the 4H-SiC epitaxial layer 3. In this growth process, a single-crystal AlN epitaxial layer 5 is epitaxially grown on the 4H-SiC epitaxial layer 3, and polycrystalline AlN is formed on the SiO2 film on the 3C-SiC epitaxial layer 4. Next, the SiO2 layer formed on the 3C-SiC epitaxial layer 4 is removed using hydrofluoric acid, thereby simultaneously removing the polycrystalline AlN. The formation of the AlN epitaxial layer 5 itself is the same as in step S15 of Embodiment 1, so the details are omitted.

[0121] (Step S57: Formation of the exposed surface of the AlN epitaxial layer 5) Next, an SiO2 film is formed over the entire surface again. Using a photoresist as a mask, the SiO2 formed on surfaces other than the 3C-SiC epitaxial layer 4 is removed by wet etching, exposing the AlN epitaxial layer 5.

[0122] (Step S58:In a Al b Ga c Formation of N-epitaxial layer 6) On the exposed surface of the AlN epitaxial layer 5, In a Al b Ga cThe N epitaxial layer 6 is grown. During this growth process, single crystal In is grown on the exposed surface of the AlN epitaxial layer 5. a Al b Ga c The N epitaxial layer 6 is epitaxially grown. On the SiO2 film on the 3C-SiC epitaxial layer 4, In a Al b Ga c N does not grow.

[0123] (Step S59:In p Al q Ga r (Formation of N epitaxial layer 7) Next, In a Al b Ga c In on the N epitaxial layer 6 p Al q Ga r An N epitaxial layer 7 is provided. On the SiO2 film on the 3C-SiC epitaxial layer 4, In p Al q Ga r N does not grow.

[0124] (Laminated structure 600) Figure 8 is a cross-sectional view of the laminated structure 600 according to Embodiment 2. In the laminated structure 600, recesses 13, recesses 14, and openings 20 are provided, similar to the laminated structure 200 according to Embodiment 1. The laminated structure 600 according to Embodiment 2 is formed from the laminated structure 500 by the same process as the laminated structure 200 according to Embodiment 1, so the details are omitted.

[0125] (Laminated structure 700) Figure 9 is a cross-sectional view of the laminated structure 700 according to Embodiment 2. The laminated structure 700 according to Embodiment 2 is formed from the laminated structure 600 by the same process as the laminated structure 300 according to Embodiment 1, so details are omitted.

[0126] (Laminated structure 800) Figure 10 is a cross-sectional view of the laminated structure 800 according to Embodiment 2. The laminated structure 800 according to Embodiment 2 is formed from the laminated structure 700 by the same process as the laminated structure 400 according to Embodiment 1, so the details are omitted.

[0127] When comparing semiconductor device A according to Embodiment 1 with semiconductor device B according to Embodiment 2, the following points differ.

[0128] The difference is that in semiconductor device A according to Embodiment 1, the AlN epitaxial layer 5 (insulating layer) is provided on the 3C-SiC epitaxial layer 4 as shown in Figure 5, whereas in semiconductor device B according to Embodiment 2, the AlN epitaxial layer 5 (insulating layer) is provided on the 4H-SiC epitaxial layer 3 as shown in Figure 10. Semiconductor device A according to Embodiment 1 does not require selective growth in the manufacturing process. Therefore, the manufacturing cost of semiconductor device A according to Embodiment 1 is lower than that of semiconductor device B according to Embodiment 2. Semiconductor device B according to Embodiment 2 provides In a Al b Ga c Below the GaN-HEMT102B having the N epitaxial layer 6, there is no 3C-SiC epitaxial layer 4 providing 2DHG. In other words, 2DHG and 2DEG do not overlap in the height direction of the semiconductor device. Therefore, it is considered that the adverse effect of 2DHG on the GaN-HEMT102B characteristics can be suppressed. Thus, in semiconductor device B according to Embodiment 2, carrier interference between 2DHG and 2DEG is suppressed compared to semiconductor device A according to Embodiment 1.

[0129] <Embodiment 3> Figure 11 is a cross-sectional view of the stacked structure 900 during the manufacturing process of the semiconductor epitaxial wafer C shown in Figure 13. Figure 12 is a cross-sectional view of the stacked structure 1000, in which an additional epitaxial layer is provided on top of the stacked structure 900 of Figure 11.

[0130] The semiconductor epitaxial wafer C according to Embodiment 3 is formed by sequentially stacking a 3C-SiC epitaxial layer 4c, an AlN epitaxial layer 5c, a GaN epitaxial layer 6c, and an AlGaN epitaxial layer 7c on a 4H-SiC substrate 1c.

[0131] (Method for manufacturing semiconductor epitaxial wafer C) (Step S11C: 4H-SiC substrate 1c) To fabricate the 4H-SiC substrate 1c, a 4H-SiC single crystal substrate is prepared. The 4H-SiC single crystal substrate has an off-plane as a laminated surface, which is specified by a predetermined direction and a predetermined off-angle relative to the main plane (0001). The predetermined direction is, for example, a direction within ±15 degrees from the <01-10> direction. The predetermined off-angle is an angle in the range of 0 degrees to 1.0 degrees relative to the main plane (0001). The 4H-SiC single crystal substrate is prepared by mechanically and chemically polishing a substrate cut from, for example, a commercially available 4-inch 4H-SiC ingot so that it has an off-plane specified by the above direction and off-angle. This polishing process reduces the roughness of the substrate surface, resulting in a smooth surface suitable for epitaxial growth and device formation. Furthermore, the substrate surface is cleaned to remove impurities such as organic matter and oxide films. The 4H-SiC single crystal substrate is so-called semi-insulating, meaning it has a resistivity of 1 × 10⁻⁶. 5 It has insulating properties of Ωcm or more. Alternatively, a 6H-SiC single crystal substrate may be used instead of a 4H-SiC single crystal substrate.

[0132] Next, the 4H-SiC single crystal substrate is subjected to etching. The etching process is carried out, for example, using a thermal etching method. Specifically, the 4H-SiC single crystal substrate is placed in the reaction furnace of a thermal CVD apparatus. The temperature of the 4H-SiC single crystal substrate is set to a range of 1280°C to 1470°C, and the pressure inside the reaction furnace is maintained at 5kPa to 50kPa by supplying hydrogen as the etching gas and applying a vacuum, while the etching process is carried out. The etching process time is in the range of 1 minute to 2 hours. Hydrogen etching prepares the off-surface (layer surface) of the 4H-SiC single crystal substrate. This forms the 4H-SiC substrate 1c.

[0133] As shown in Figure 11, a 3C-SiC epitaxial layer 4c is laminated on a 4H-SiC substrate 1c. This process is the same as the manufacturing process for the 3C-SiC epitaxial layer 4 in Embodiment 1, so the details are omitted.

[0134] As shown in Figure 12, an AlN epitaxial layer 5c, a GaN epitaxial layer 6c, and an AlGaN epitaxial layer 7c are sequentially laminated on a 3C-SiC epitaxial layer 4c. The manufacturing process for these layers is the same as in Embodiment 1, so details are omitted.

[0135] Figure 13 shows a cross-sectional view of a semiconductor epitaxial wafer C. As shown in Figure 13, the semiconductor epitaxial wafer C comprises a 4H-SiC(0001) substrate 1c, a 3C-SiC epitaxial layer 4c, an AlN epitaxial layer 5c, a GaN epitaxial layer 6c, and an AlGaN epitaxial layer 7c.

[0136] (4H-SiC substrate 1c) The 4H-SiC substrate 1c has a wide bandgap (approximately 3.26 eV), resulting in excellent resistance to operation in high-temperature and high-voltage environments. Furthermore, its critical electric field strength is very high at approximately 3 MV / cm, giving it superior voltage resistance compared to silicon of the same volume, making it suitable for power devices. In addition, its high thermal conductivity of approximately 4.9 W / cm·K allows for efficient dissipation of heat generated during device operation, enabling stable operation even in high-power devices requiring thermal management. These characteristics allow the 4H-SiC substrate 1c to be a chemically stable substrate, enabling the construction of long-life and highly reliable semiconductor devices.

[0137] (3C-SiC epitaxial layer 4c) The 3C-SiC epitaxial layer 4c is provided on the 4H-SiC substrate 1c, thereby generating 2DHG at the heterointerface. This 2DHG is formed by the two-dimensional confinement of hole carriers at the heterointerface between the 4H-SiC substrate 1c and the 3C-SiC epitaxial layer 4c. Because this 2DHG has higher mobility than conventional structures, it contributes to improved device performance and is particularly effective in applications requiring high-speed switching and high-frequency operation. Thus, the combination of the 3C-SiC epitaxial layer 4c and the 4H-SiC substrate 1c can provide excellent characteristics in next-generation high-performance power devices and high-frequency devices that achieve high hole mobility.

[0138] (AlN epitaxial layer 5c) The AlN epitaxial layer 5c is provided on the 3C-SiC epitaxial layer 4c and functions as an insulating buffer layer that electrically insulates the 3C-SiC epitaxial layer 4c and the GaN epitaxial layer 6c. The AlN epitaxial layer 5c has high electrical insulation properties, preventing unwanted leakage current and charge transfer between the 3C-SiC epitaxial layer 4c and the GaN epitaxial layer 6c, and preventing electrical interference between the upper and lower layers. In addition, the AlN epitaxial layer 5 of Embodiment 1 may be used instead of the AlN epitaxial layer 5c.

[0139] Furthermore, because the AlN epitaxial layer 5c has a wide bandgap, it exhibits stable insulation performance even in high-voltage and high-temperature environments, and improves the reliability and operational stability of the device by suppressing unwanted current and potential fluctuations that may occur between the upper and lower epitaxial layers.

[0140] Furthermore, the high thermal conductivity of AlN improves the overall heat dissipation of the device, resulting in a structure that can withstand long-term high-load operation. In addition, the AlN epitaxial layer 5c suppresses island-like growth, thereby suppressing the occurrence of crystal defects and improving the crystal quality of the GaN epitaxial layer 6c.

[0141] (GaN epitaxial layer 6c) The GaN epitaxial layer 6c generates a 2DEG at its interface with the AlGaN epitaxial layer 7c. This 2DEG is formed based on the bandgap difference between the GaN epitaxial layer 6c and the AlGaN epitaxial layer 7c, and high electron mobility is achieved by confining electron carriers in a high density in two dimensions. As a result, the device can operate at high speed and exhibits characteristics suitable for applications requiring high frequency performance and high power efficiency. Note that the In Embodiment 1 a Al b Ga c An N epitaxial layer 6 may also be used.

[0142] Furthermore, since 2DEG occurs naturally without doping, the manufacturing process can be simplified. In addition, 2DEG can operate stably even in high-temperature environments, demonstrating excellent performance in power devices and devices that require high-temperature operation.

[0143] (AlGaN epitaxial layer 7c) The AlGaN epitaxial layer 7c functions as a direct contact layer for the source electrode, drain electrode, and gate electrode, and also functions as a layer for adjusting the 2DEG concentration in conjunction with the GaN epitaxial layer 6c. The AlGaN epitaxial layer 7c efficiently connects to each electrode, ensuring current flow while reducing resistance at the interface with the electrodes, thereby improving switching speed and device responsiveness. It also functions to control the band gap and adjust the 2DEG concentration by adjusting the ratio of Al to Ga. Specifically, increasing the Al content expands the band gap and increases the 2DEG concentration, while increasing the Ga proportion suppresses the 2DEG concentration. By adjusting the band gap in this way, the characteristics of the device can be optimized, and performance during high-frequency operation and high-voltage driving can be improved. The band gap of the AlGaN epitaxial layer 7c is larger than the band gap of the GaN epitaxial layer 6c. p Al q Ga r An N epitaxial layer 7 may also be used.

[0144] Figure 14 shows X-ray diffraction (XRD) data, illustrating the crystallinity evaluation results for a GaN epitaxial layer providing 2DEG. The horizontal axis represents the 2θ angle, ranging from 16.60 to 17.60 degrees. This range relates to the interplane spacing and provides information about the material's crystal structure. The vertical axis represents the X-ray scattering intensity, showing the intensity of the diffracted X-rays. The peak position is 17.161 degrees, which corresponds to a specific crystal plane. The peak width is 0.174 degrees, known as the full width at half maximum (FWHM), an indicator of crystal quality and the presence or absence of defects. A narrower FWHM indicates higher crystallinity, while a wider FWHM indicates the presence of defects in the crystal. Regarding asymmetry, a value of 1.01 is shown, confirming that the peak is nearly symmetrical. CuKα rays (wavelength 1.5405980 Å) were used for the measurement. As shown in Figure 14, the sharp and symmetrical peaks indicate that the crystallinity of the GaN epitaxial layer is relatively high.

[0145] Figure 15 shows the X-ray diffraction (XRD) spectrum, where peaks corresponding to different epitaxial layers are observed. From this spectrum, a peak corresponding to the 4H-SiC substrate 1c is first identified, which is a characteristic peak corresponding to the crystal structure of 4H-SiC. Next, a shoulder structure associated with the 3C-SiC epitaxial layer 4c is observed, confirming that the 3C-SiC epitaxial layer is located on the 4H-SiC substrate. This shoulder structure reflects the difference in the crystal lattice unique to 3C-SiC. Furthermore, a peak corresponding to the GaN epitaxial layer 6c is observed, indicating the crystallinity of GaN. The position and intensity of this peak suggest that the GaN layer has high-quality crystallinity. In addition, a peak corresponding to the AlGaN epitaxial layer 7c is also observed, which reflects the crystal structure of the AlGaN layer. Through the analysis of this XRD spectrum, the crystallinity and structural properties of each epitaxial layer were evaluated, and it was confirmed that each layer possesses a crystalline structure.

[0146] Figure 16 shows an AFM (atomic force microscope) image of the top layer, the AlGaN epitaxial layer 7c. In this image, the horizontal and vertical axes cover a range of 2.0 μm, and the maximum surface height is 5.0 nm. The image shows a certain periodic pattern on the surface, as well as numerous minute irregularities. These irregularities reflect the surface roughness of the grown AlGaN layer, and the difference between the highest and lowest points is very small at 5.0 nm, indicating that the surface is generally smooth. However, some small pit-like features are observed, which may indicate localized surface defects or heterogeneity during the growth process. Analysis of this AFM image confirms that the AlGaN epitaxial layer 7c is generally smooth with relatively low surface roughness, indicating that a high-quality epitaxial layer is formed during device manufacturing.

[0147] <Embodiment 4> Figure 17 is a cross-sectional view of a semiconductor device D according to Embodiment 4. The semiconductor device D comprises a semiconductor device 102D which is a GaN-HEMT in a first region R1 and a semiconductor device 101D which is a P-HFET in a second region R2.

[0148] The first SiC substrate 1d is, for example, a 4H-SiC substrate or a 6H-SiC substrate, and has an off-plane as a laminated surface, which is specified by a predetermined direction and a predetermined off-angle with respect to the main surface (0001). The predetermined direction is, for example, a direction within ±15 degrees from the <01-10> direction. The predetermined off-angle is an angle in the range of 0 degrees or more and 1.0 degrees or less with respect to the main surface (0001).

[0149] The second SiC layer 4d is a 3C-SiC layer provided on the first SiC substrate 1d and has a first region and a second region. The thickness of the first region is greater than or equal to the thickness of the second region. The second SiC layer 4d may be the 3C-SiC epitaxial layer 4 of Embodiment 1.

[0150] The first semiconductor layer 5d is, for example, an AlN epitaxial layer with a thickness of 50 nm, and is provided on the first region of the second SiC layer 4d. The first semiconductor layer 5d may also be the AlN epitaxial layer 5 of Embodiment 1.

[0151] The second semiconductor layer 6d is, for example, a GaN epitaxial layer with a thickness of 1 μm, and is provided on the first semiconductor layer 5d. The second semiconductor layer 6d is the In of Embodiment 1 a Al b Ga c It may also be an N epitaxial layer 6.

[0152] The third semiconductor layer 7d is, for example, Al with a thickness of 25 nm. 0.2 Ga 0.8 It is an N epitaxial layer and is provided on the second semiconductor layer 6d. The third semiconductor layer 7d is the In of Embodiment 1. p Al q Ga r It may also be an N epitaxial layer 7.

[0153] The first electrode group (9D, 9G, 9S), consisting of the drain electrode 9D, gate electrode 9G, and source electrode 9S, is formed on the third semiconductor layer 7d and is an electrode for driving the semiconductor device 102D, which is a GaN-HEMT. The gate electrode 9G may be placed within a recess provided in the third semiconductor layer 7d.

[0154] The second electrode group (10D, 10G, 10S), consisting of the drain electrode 10D, gate electrode 10G, and source electrode 10S, is formed on the second SiC layer 4d and is an electrode for driving the semiconductor device 101D, which is a P-HFET. The gate electrode 10G may be placed within a recess provided in the second SiC layer 4d.

[0155] The semiconductor device 102D is configured to be driven using 2DEG, which extends along the first interface between the third semiconductor layer 7d and the second semiconductor layer 6d, via the first electrode group (9D, 9G, 9S).

[0156] The semiconductor device 101D is configured to be driven using 2DHG, which extends along the second interface between the first SiC substrate 1d and the second SiC layer 4d, via a second electrode group (10D, 10G, 10S).

[0157] According to the semiconductor device D of Embodiment 3, the 2DHG generated at the interface between 3C-SiC and 4H-SiC exhibits a higher hole mobility compared to existing SiC devices. Specifically, the hole mobility at 293K is 30 cm². 2 It has a Vs value and shows higher performance than conventional devices, and can improve hole mobility compared to conventional devices.

[0158] Figure 18 is a graph showing the output characteristics of the GaN-HEMT102D. The horizontal axis represents the drain voltage Vd, ranging from 0V to 16V, which is the voltage between the drain and source of the GaN-HEMT102D. The vertical axis shows the drain current Id on a logarithmic scale, representing the magnitude of the current flowing through the device. The numerical range is from 0A to approximately 0.01A (10mA). Figure 18 includes data for different gate-source voltage Vg values ​​(0V, -1V, -2V, -3V, -4V). Each curve shows the behavior of the drain current at different gate voltages. At a gate voltage of 0V, the device exhibits the maximum drain current, and as the gate voltage Vg shifts to the negative, the drain current decreases. This indicates that the gate voltage controls the gate current. At low gate voltages, the drain current is suppressed, and above a certain drain voltage, the current reaches the saturation region.

[0159] Figure 19 shows a characteristic evaluation graph (SiC-TLM) of the P-HFET101D based on the TLM (Transfer Length Method). This technique is used to evaluate contact resistance and resistance characteristics at different inter-electrode distances (pitches). The vertical axis of the graph shows current (I) in amperes, and shows the behavior of very small currents in the range from -0.0005A to 0.0005A. The horizontal axis shows voltage (V) in volts, in the range from -1.5V to 1.5V. Each data set shows the relationship between current and voltage at different inter-electrode distances, namely "40μm", "25μm", "15μm", and "8μm". The data for pitches "25μm" and "15μm" almost overlap.

[0160] At each pitch, the relationship between current and voltage is nearly linear, suggesting that ohmic contact is formed in the SiC device. That is, an ohmic characteristic where current is proportional to voltage is observed, which is important for evaluating the quality of contact resistance in SiC devices. In particular, the current increases and the slope becomes steeper as the pitch decreases (8 μm). This indicates a tendency for contact resistance to decrease as the pitch decreases.

[0161] This graph shows the current-voltage characteristics of SiC devices at different inter-electrode distances, providing important information for evaluating the quality of ohmic contacts. It has been confirmed that contact resistance is pitch-dependent, suggesting that decreasing pitch increases current and reduces contact resistance.

[0162] (Note 1) A first SiC layer of 4H-SiC or 6H-SiC having a (0001) main surface and a first region and a second region, In the first region of the first SiC layer, a second SiC layer of 3C-SiC is provided on the main surface, A first transistor having a first electrode group including a first gate electrode provided on the second SiC layer and positioned between a first source electrode and a first drain electrode, In the second region of the first SiC layer, a first AlN nitride semiconductor layer is provided on the main surface, A second nitride semiconductor layer is provided on the first nitride semiconductor layer, A third nitride semiconductor layer is provided on the second nitride semiconductor layer and has a larger band gap than the second nitride semiconductor layer, A second transistor having a second electrode group including a second gate electrode provided on the third nitride semiconductor layer and positioned between the second source electrode and the second drain electrode, A semiconductor device equipped with a semiconductor device.

[0163] (Note 2) The semiconductor device according to Addendum 1, wherein a 3C-SiC layer is further provided between the main surface of the second region of the first SiC layer and the first nitride semiconductor layer.

[0164] (Addendum 3) The second SiC layer has a two-dimensional hole gas extending along a first interface with the first SiC layer, The second nitride semiconductor layer has a two-dimensional electron gas extending along a second interface with the third nitride semiconductor layer. The semiconductor device according to Addendum 1 or 2.

[0165] (Addendum 4) The second nitride semiconductor layer is In a Al b Ga c N (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, 0 ≦ c ≦ 1, a + b + c = 1), The third nitride semiconductor layer is In p Al q Ga r N (0 ≦ p ≦ 1, 0 ≦ q ≦ 1, 0 ≦ r ≦ 1, p + q + r = 1). The semiconductor device according to Addenda 1 to 3.

[0166] (Addendum 5) The second SiC layer has a first recess structure, The first gate electrode is disposed within the first recess structure. The semiconductor device according to Addenda 1 to 4.

[0167] (Addendum 6) The third nitride semiconductor layer has a second recess structure, The second gate electrode is disposed within the second recess structure. The semiconductor device according to Addenda 1 to 5.

[0168] (Addendum 7) Having a main surface on the (0001) plane, a SiC substrate of 4H-SiC or 6H-SiC, A third SiC layer of 4H-SiC or 6H-SiC provided on the main surface of the SiC substrate, A vertical power transistor is provided in a third region, which is a part of the third SiC layer, and has a main current path from the third SiC layer in the thickness direction of the SiC substrate, A first wiring configuration comprising a p-type first transistor and an n-type second transistor, which constitute a complementary drive circuit, The system includes a second wiring that connects the output of the complementary drive circuit to the input gate of the power transistor, The first SiC layer is provided on a region of the third SiC layer that does not overlap with the third region. Semiconductor devices as described in Appendix 1 to 6.

[0169] (Note 8) A step of providing a first SiC layer of 4H-SiC or 6H-SiC having a (0001) main surface and a first region and a second region, A step of providing a second 3C-SiC SiC layer on the main surface in the first region of the first SiC layer, A step of providing a first transistor having a first electrode group including a first gate electrode disposed between a first source electrode and a first drain electrode on the second SiC layer, A step of providing a first AlN nitride semiconductor layer on the main surface in the second region of the first SiC layer, A step of providing a second nitride semiconductor layer on the first nitride semiconductor layer, A step of providing a third nitride semiconductor layer having a larger band gap than the second nitride semiconductor layer on the second nitride semiconductor layer, The process includes providing a second transistor having a second electrode group including a second gate electrode disposed between a second source electrode and a second drain electrode on the third nitride semiconductor layer, A method for manufacturing a semiconductor device.

[0170] (Note 9) A step of providing a SiC substrate having a (0001) main surface and being 4H-SiC or 6H-SiC, A step of providing a third SiC layer of 4H-SiC or 6H-SiC on the main surface of the SiC substrate, A step of providing a vertical power transistor having a main current path in the thickness direction of the SiC substrate from the third SiC layer in a third region which is a part of the third SiC layer, A step of providing a first wiring that constitutes a complementary drive circuit using the first p-type transistor and the second n-type transistor, The process includes providing a second wire that connects the output of the complementary drive circuit to the input gate of the power transistor, The first SiC layer is provided on a region of the third SiC layer that does not overlap with the third region. The method for manufacturing a semiconductor device as described in Appendix 8.

[0171] (Note 10) (0001) It has a main surface of the (0001) plane and a first SiC layer of 4H-SiC or 6H-SiC, A second SiC layer of 3C-SiC is provided on the main surface of the first SiC layer, A first AlN nitride semiconductor layer is provided on the second SiC layer, A second nitride semiconductor layer is provided on the first nitride semiconductor layer, A third nitride semiconductor layer is provided on the second nitride semiconductor layer and has a larger band gap than the second nitride semiconductor layer, Equipped with, The second SiC layer has a two-dimensional hole gas extending along the first interface with the first SiC layer. The second nitride semiconductor layer has a two-dimensional electron gas extending along the second interface with the third nitride semiconductor layer. Semiconductor epitaxial wafer.

[0172] The matters described in the claims are not limited to the exemplary embodiments and can be modified and improved in various ways without departing from the spirit and scope of the invention. [Explanation of Symbols]

[0173] 1 n + Type 4H-SiC substrate 2 n -Type 4H-SiC epitaxial layer 3 4H-SiC epitaxial layer 4 3C-SiC epitaxial layer 5 AlN epitaxial layer 6 In a Al b Ga c N epitaxial layer 7 In p Al q Ga r N epitaxial layer 13, 14, recesses 15 Oxide film 20 Opening 101 P-HFET 102 GaN-HEMT 103 SiC-MOSFET

Claims

1. A first SiC layer of 4H-SiC or 6H-SiC having a (0001) main surface and a first region and a second region, In the first region of the first SiC layer, a second SiC layer of 3C-SiC is provided on the main surface, A first transistor having a first electrode group including a first gate electrode provided on the second SiC layer and positioned between a first source electrode and a first drain electrode, In the second region of the first SiC layer, a first AlN nitride semiconductor layer is provided on the main surface, A second nitride semiconductor layer provided on the first nitride semiconductor layer, A third nitride semiconductor layer is provided on the second nitride semiconductor layer and has a larger band gap than the second nitride semiconductor layer, A second transistor having a second electrode group including a second gate electrode disposed between a second source electrode and a second drain electrode, provided on the third nitride semiconductor layer, A semiconductor device equipped with a semiconductor device.

2. The semiconductor device according to claim 1, wherein a 3C-SiC layer is further provided between the main surface of the second region of the first SiC layer and the first nitride semiconductor layer.

3. The second SiC layer has a two-dimensional hole gas extending along the first interface with the first SiC layer. The second nitride semiconductor layer has a two-dimensional electron gas extending along the second interface with the third nitride semiconductor layer. The semiconductor device according to claim 1.

4. The second nitride semiconductor layer is In ａ Al ｂ Ga ｃ N is (0 ≤ a ≤ 1, 0 ≤ b ≤ 1, 0 ≤ c ≤ 1, a + b + c = 1), The third nitride semiconductor layer is In ｐ Al ｑ Ga ｒ N is (0 ≤ p ≤ 1, 0 ≤ q ≤ 1, 0 ≤ r ≤ 1, p + q + r = 1), The semiconductor device according to claim 1.

5. The second SiC layer has a first recess structure, The first gate electrode is located within the first recess structure. The semiconductor device according to claim 1.

6. The third nitride semiconductor layer has a second recess structure, The second gate electrode is located within the second recess structure. The semiconductor device according to claim 1.

7. (0001) A SiC substrate having a main surface of the (0001) plane, and 4H-SiC or 6H-SiC, A third SiC layer of 4H-SiC or 6H-SiC is provided on the main surface of the SiC substrate, A vertical power transistor is provided in a third region, which is a part of the third SiC layer, and has a main current path from the third SiC layer in the thickness direction of the SiC substrate, A first wiring configuration comprising a p-type first transistor and an n-type second transistor, which constitute a complementary drive circuit, The system includes a second wiring that connects the output of the complementary drive circuit to the input gate of the power transistor, The semiconductor device according to claim 1, wherein the first SiC layer is provided on a region of the third SiC layer that does not overlap with the third region.

8. (0001) A step of providing a first SiC layer of 4H-SiC or 6H-SiC having a main surface of the (0001) plane and a first region and a second region, A step of providing a second 3C-SiC SiC layer on the main surface in the first region of the first SiC layer, A step of providing a first transistor having a first electrode group including a first gate electrode disposed between a first source electrode and a first drain electrode on the second SiC layer, A step of providing a first AlN nitride semiconductor layer on the main surface in the second region of the first SiC layer, The process of providing a second nitride semiconductor layer on the first nitride semiconductor layer, A step of providing a third nitride semiconductor layer having a larger band gap than the second nitride semiconductor layer on the second nitride semiconductor layer, The process includes providing a second transistor having a second electrode group including a second gate electrode disposed between a second source electrode and a second drain electrode on the third nitride semiconductor layer, A method for manufacturing a semiconductor device.

9. (0001) A step of providing a SiC substrate having a main surface of the (0001) plane, which is 4H-SiC or 6H-SiC, A step of providing a third SiC layer of 4H-SiC or 6H-SiC on the main surface of the SiC substrate, A step of providing a vertical power transistor having a main current path in the thickness direction of the SiC substrate from the third SiC layer in a third region which is a part of the third SiC layer, A step of providing a first wiring that constitutes a complementary drive circuit using the first p-type transistor and the second n-type transistor, The process includes providing a second wire that connects the output of the complementary drive circuit to the input gate of the power transistor, The method for manufacturing a semiconductor device according to claim 8, wherein the first SiC layer is provided on a region of the third SiC layer that does not overlap with the third region.

10. (0001) It has a main surface of the (0001) plane and a first SiC layer of 4H-SiC or 6H-SiC, A second SiC layer of 3C-SiC is provided on the main surface of the first SiC layer, A first AlN nitride semiconductor layer is provided on the second SiC layer, A second nitride semiconductor layer provided on the first nitride semiconductor layer, A third nitride semiconductor layer is provided on the second nitride semiconductor layer and has a larger band gap than the second nitride semiconductor layer, Equipped with, The second SiC layer has a two-dimensional hole gas extending along the first interface with the first SiC layer. The second nitride semiconductor layer has a two-dimensional electron gas extending along the second interface with the third nitride semiconductor layer. Semiconductor epitaxial wafer.

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