Method for manufacturing semiconductor wafers for bonding, method for manufacturing composite substrates, and semiconductor wafers for bonding

Abstract

The present invention provides a method for manufacturing semiconductor wafers for bonding and a method for manufacturing composite substrates that allow for easy removal of knife edges. [Solution] An annular groove 12 is formed on one side of a flattened wafer 11, concentric with the outer circumference of the wafer 11 and having a predetermined width and depth. Subsequently, the inside of the groove 12 is filled with oxide to obtain a bonding semiconductor wafer 21 for bonding to a support substrate 22. Then, the side of the bonding semiconductor wafer 21 with the groove 21 formed thereon is bonded to the support substrate 22, and subsequently, the unnecessary portion is removed using the annular groove 22 (oxide) as a boundary to obtain a composite substrate 41 from which the knife edge has been easily removed.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor wafer for bonding to be bonded to a support substrate, a method for manufacturing a composite substrate, and a semiconductor wafer for bonding.

Background Art

[0002] In recent years, it has been considered to create three-dimensional devices by forming laminated wafers in which semiconductor wafers are laminated, and to improve functions, capacities, processing capabilities, and the like.

[0003] And, in the step of forming the laminated wafer, for example, a semiconductor wafer for bonding having substantially the same thickness is laminated on a lower support substrate, and this semiconductor wafer for bonding is thinned from the upper surface side (front surface side) in order to improve heat dissipation or to enable further lamination of another semiconductor wafer thereon.

[0004] However, since the outer peripheral end surface (chamfered surface) of the semiconductor wafer for bonding is formed in a trapezoidal cross-section or an arcuate cross-section, as described above, when grinding from the upper surface side until it becomes thin, it becomes an acute angle shape like the blade of a knife (knife edge), and as a result, it is easily chipped. Further, when a chip occurs on the outer peripheral end surface, cracks enter from there, and the quality of the laminated wafer deteriorates. Furthermore, in the case where the quality of the laminated wafer is significantly deteriorated, the laminated wafer cannot be used.

[0005] In order to improve such deterioration of the quality of the laminated wafer, that is, in order to suppress cracking and chipping of the outer peripheral end surface of the semiconductor wafer for bonding, in Cited Document 1, a laminated wafer is disclosed in which the outer peripheral end surface shape of the semiconductor wafer for bonding is devised so that no knife edge occurs before bonding. Specifically, before bonding the semiconductor wafer for bonding to the support substrate, the end portion of the semiconductor wafer for bonding is ground so as not to generate a knife edge.

Prior Art Documents

[0006] [Patent Document 1] Japanese Patent Publication No. 2021-027062 [Overview of the project] [Problems that the invention aims to solve]

[0007] However, as described in Reference 1, in cases where the edges of the bonding semiconductor wafer are ground before bonding it to the support substrate, there is a problem in that the manufacturing process becomes complicated, requiring grinding of the edges with a special grinding wheel and a special cleaning device that matches the edge shape.

[0008] The present invention has been made in view of the above problems, and aims to provide a method for manufacturing a semiconductor wafer for bonding, a method for manufacturing a composite substrate, and a semiconductor wafer for bonding that can easily remove knife edges without degrading quality. [Means for solving the problem]

[0009] The present invention relates to a method for manufacturing a semiconductor wafer for bonding, which is a method for manufacturing a semiconductor wafer for bonding to a support substrate, and is characterized by comprising: a groove formation step of forming an annular groove on one side of the semiconductor wafer that is concentric with the outer circumference of the semiconductor wafer and has a predetermined width and depth; and an oxidation atmosphere heat treatment step of performing a heat treatment on the semiconductor wafer having the groove in an oxygen atmosphere to cover the surface of the semiconductor wafer with an oxide film and fill the inside of the annular groove with oxide. Furthermore, this manufacturing method further comprises an inert atmosphere heat treatment step of performing a heat treatment on the semiconductor wafer having the groove formed in the groove formation step in an inert atmosphere to form an annular cavity inside the groove by the heat treatment, and the oxidation atmosphere heat treatment step is performed after the inert atmosphere heat treatment step.

[0010] Furthermore, this manufacturing method includes a first cleaning step of performing HF cleaning on the semiconductor wafer covered with the oxide film to remove the oxide film, and an exposure step of polishing or etching the surface on the semiconductor wafer where the groove portion is formed after the oxide film removal until the oxide is exposed. As a result, a bonding semiconductor wafer with the oxide exposed on the wafer surface can be obtained for bonding to a support substrate.

[0011] Another invention relates to a method for manufacturing a semiconductor wafer for bonding, which is a method for manufacturing a semiconductor wafer for bonding to a support substrate, and is characterized by comprising: a groove formation step of forming an annular groove on one side of the semiconductor wafer that is concentric with the outer circumference of the semiconductor wafer and has a predetermined width and depth; and an oxidation atmosphere heat treatment step of performing heat treatment on the semiconductor wafer having the groove in an oxygen atmosphere to cover the surface of the semiconductor wafer with an oxide film and to fill the inside of the annular groove with oxide. Furthermore, this manufacturing method includes a first cleaning step of performing HF cleaning on the surface of the semiconductor wafer covered with the oxide film other than the surface on which the groove is formed, and removing the oxide film from the cleaned portion. As a result, a semiconductor wafer for bonding to a support substrate can be obtained in which the surface on which the groove is formed is covered with an oxide film layer.

[0012] In the method for manufacturing a semiconductor wafer for bonding according to these inventions, the groove portion preferably has a depth of 0.1 μm to 50 μm from the surface of the semiconductor wafer, a width of 50 nm to 200 nm, and is formed at a position 0.1 mm to 10.0 mm inward from the outer circumference of the semiconductor wafer. Furthermore, the shape of the groove portion preferably has a cross-sectional shape perpendicular to the surface of the semiconductor wafer that is elliptical, rectangular, L-shaped, or arc-shaped.

[0013] Furthermore, in the method for manufacturing a semiconductor wafer for bonding according to these inventions, the heat treatment in the oxidation atmosphere heat treatment step is preferably carried out under heat treatment conditions in an oxygen atmosphere, with a heating rate of 1 to 20°C / min, a cooling rate of 1 to 20°C / min, and maintaining a maximum temperature of 1000 to 1400°C for a predetermined time, or under heat treatment conditions in an oxygen atmosphere, with a heating rate of 20 to 150°C / min, a cooling rate of 20 to 150°C / min, and maintaining a maximum temperature of 1200 to 1400°C for a predetermined time.

[0014] Furthermore, in the method for manufacturing semiconductor wafers for bonding according to these inventions, the heat treatment in the inert atmosphere heat treatment step is preferably carried out under heat treatment conditions in an inert atmosphere, with a heating rate of 1 to 20°C / min, a cooling rate of 1 to 20°C / min, and maintaining a maximum temperature of 1000 to 1400°C for a predetermined time.

[0015] Therefore, a semiconductor wafer for bonding manufactured by the above-described method for manufacturing a semiconductor wafer for bonding is a semiconductor wafer for bonding with a diameter of 150 mm or more on which oxygen precipitates that serve as gettering sites are formed, wherein an annular groove portion is formed on one side that is concentric with the outer circumference of the wafer and has a predetermined width and depth, the groove portion has a depth of 0.1 μm to 50 μm from the surface of the wafer and a width of 50 nm to 200 nm, is formed at a position 0.1 mm to 10.0 mm inward from the outer circumference of the wafer, and furthermore, the interior of the groove portion has a structure filled with oxide.

[0016] Furthermore, a semiconductor wafer for bonding manufactured by the above-described method for manufacturing a semiconductor wafer for bonding is a semiconductor wafer for bonding with a diameter of 150 mm or more on which oxygen precipitates that serve as gettering sites are formed, wherein an annular groove portion is formed on one side that is concentric with the outer circumference of the wafer and has a predetermined width and depth, the groove portion has a depth of 0.1 μm to 50 μm from the surface of the wafer and a width of 50 nm to 200 nm, is formed at a position 0.1 mm to 10.0 mm inward from the outer circumference of the wafer, and furthermore, the inside of the groove portion is filled with oxide, and the surface on which the groove portion is formed is covered with an oxide film layer.

[0017] The present invention relates to a method for manufacturing a composite substrate, characterized by comprising a bonding step of bonding the groove-side surface of a bonding semiconductor wafer manufactured by the above-described method for manufacturing a bonding semiconductor wafer to a support substrate, and a composite substrate manufacturing step of removing unnecessary portions other than the region surrounded by oxide filling the annular groove formed in the bonding semiconductor wafer.

[0018] Specifically, the composite substrate manufacturing process includes a thinning step of grinding or peeling the surface of the bonding semiconductor wafer where grooves are not formed until the oxide is exposed, and a second cleaning step of performing HF cleaning on the bonding semiconductor wafer after the thinning step to remove the oxide filling the annular grooves. Note that, in the thinning step, when peeling the surface of the bonding semiconductor wafer where grooves are not formed until the oxide is exposed, it is preferable to first form an embrittlement layer on the bonding semiconductor wafer using an ion implantation separation method or laser light, and then peel from the embrittlement layer.

[0019] According to the above-described method for manufacturing semiconductor wafers for bonding and for manufacturing composite substrates, knife edges can be easily removed without degrading quality. [Effects of the Invention]

[0020] According to the method for manufacturing a semiconductor wafer for bonding and the method for manufacturing a composite substrate according to the present invention, the knife edge can be easily removed without degrading the quality.

Brief Description of the Drawings

[0021] [Figure 1] FIG. 1 is a schematic diagram showing the manufacturing process of the first embodiment of the method for manufacturing a semiconductor wafer for bonding and the method for manufacturing a composite substrate according to the present invention. [Figure 2] FIG. 2 is a diagram showing an example of the formation position of the groove portion. [Figure 3] FIG. 3 is a diagram showing an example of the groove shape. [Figure 4] FIG. 4 is a diagram showing an example of the heat treatment of the first embodiment. [Figure 5] FIG. 5 is a schematic diagram showing the manufacturing process of the second embodiment of the method for manufacturing a semiconductor wafer for bonding and the method for manufacturing a composite substrate according to the present invention. [Figure 6] FIG. 6 is a diagram showing an example of the heat treatment of the second embodiment.

Embodiments for Carrying Out the Invention

[0022] Hereinafter, the method for manufacturing a semiconductor wafer for bonding, the method for manufacturing a composite substrate, and embodiments of the semiconductor wafer for bonding according to the present invention will be described in detail based on the drawings. Note that the present invention is not limited by this embodiment. Also, in the specification and drawings of the present application, elements that can be similarly described may be denoted by the same reference numerals, and redundant description may be omitted.

[0023] <Outline of the Manufacturing Method> The present invention provides a semiconductor wafer manufacturing method for bonding and a semiconductor substrate manufacturing method, which uses a semiconductor wafer with a diameter of 150 mm or more obtained by performing a well-known planarization process that includes a slicing step of cutting a semiconductor wafer from a semiconductor single crystal ingot, a lapping step of roughly polishing to a certain thickness while removing cutting damage formed during slicing, an etching step of removing fine distortions and scratches introduced in the lapping step by chemical etching, and a chemical polishing (CP) step of performing a highly flat, mirror-like finish by dissolving with a polishing solution.

[0024] Assuming the planarization process described above is performed, the present invention provides a method for manufacturing a semiconductor wafer for bonding, in which an annular groove is formed on one side of the planarized semiconductor wafer, concentric with the outer circumference of the semiconductor wafer and having a predetermined width and depth, and then the inside of the groove is filled with oxide. Here, for example, the inside of the groove is filled with oxide by performing a heat treatment such as RTO (Raped Thermal Oxidation) or batch annealing in an oxygen atmosphere on the semiconductor wafer in which the annular groove has been formed. Through such a process, a semiconductor wafer for bonding to a support substrate can be obtained.

[0025] Furthermore, in the method for manufacturing a composite substrate according to the present invention, the grooved surface of the semiconductor wafer for bonding obtained by the above-described method for manufacturing a semiconductor wafer for bonding is bonded to a support substrate, and then the unwanted portion is removed using the annular groove (oxide) as a boundary. For example, the semiconductor wafer for bonding is thinned by grinding the area from the surface of the semiconductor wafer where no groove is formed to where the oxide is exposed (part of the unwanted portion), and then the knife edge (the remaining unwanted portion) formed by thinning is separated by removing the oxide embedded in the groove. Through such processing, a composite substrate from which the knife edge has been easily removed can be obtained.

[0026] <First Embodiment> Next, an embodiment (first embodiment) of the method for manufacturing a bonded semiconductor wafer and a composite substrate according to the present invention will be specifically described with reference to the drawings. Figure 1 is a schematic diagram showing the manufacturing process of the first embodiment of the method for manufacturing a bonded semiconductor wafer and a composite substrate according to the present invention.

[0027] In this embodiment, a silicon wafer will be used as an example of a semiconductor wafer to describe the method for manufacturing a bonded semiconductor wafer and a composite substrate according to the present invention.

[0028] In the first embodiment, a silicon wafer 11 (hereinafter sometimes simply referred to as wafer 11) shown in Figure 1(a) is obtained by first performing a well-known planarization process including the slicing process, lapping process, etching process, and CP process described above (planarization process).

[0029] Next, an annular groove 12 is formed on one side of the wafer 11 using techniques such as semiconductor lasers or dry etching. The groove is concentric with the outer circumference of the wafer 11 and has a predetermined width and depth (groove formation process: see Figure 1(b)). Figure 2 shows an example of the groove formation position. In this embodiment, the groove 12 is formed at a depth of 0.1 μm to 50 μm from the surface of the wafer 11, a width of 50 nm to 200 nm, and at a position 0.1 mm to 10.0 mm inward from the outer circumference. Figure 3 shows an example of the groove shape. The shape of the groove 12 is such that the cross-sectional shape perpendicular to the surface of the wafer 11 is, for example, an ellipse, rectangle, L-shape, or arc shape, as shown in Figures 3(a) to (d). Note that the cross-sectional shape is not limited to Figures 3(a) to (d) and may be other cross-sectional shapes.

[0030] Next, the wafer 11 after groove 12 formation is subjected to heat treatment under inert atmosphere conditions with a heating rate of 1 to 20°C / min, a cooling rate of 1 to 20°C / min, and a maximum temperature of 1000 to 1400°C maintained for a predetermined time (inert atmosphere heat treatment process: see Figure 1(c)). In the inert atmosphere heat treatment process of this embodiment, for example, batch annealing is performed using a batch-type heat treatment apparatus.

[0031] Figure 4 shows an example of the heat treatment of the first embodiment, with the vertical axis representing temperature (°C) and the horizontal axis representing time (sec). In Figure 4, the inert atmosphere heat treatment process is indicated by section X. In this inert atmosphere heat treatment process, for example, by maintaining the highest attainable temperature T1 for a predetermined time t1, silicon atoms are reconfigured in the groove 12 opening of the wafer 11, and a lid is formed in the groove 12. As a result, an annular cavity 13 is formed inside the groove 12 of the wafer 11.

[0032] In the inert atmosphere heat treatment process, the holding time at the highest temperature can be appropriately set according to the cross-sectional shape, width, and depth of the groove 12. However, in order to form a lid on the groove 12, it is desirable to perform the heat treatment with a holding time of 0.5 hours or more at the highest temperature. Furthermore, from the viewpoint of productivity, it is desirable to set the holding time at the highest temperature to 4 hours or less.

[0033] Next, the wafer 11 after the inert atmosphere heat treatment process is subjected to heat treatment under an oxygen atmosphere with a heating rate of 1 to 20°C / min, a cooling rate of 1 to 20°C / min, and a maximum temperature of 1000 to 1400°C maintained for a predetermined time (oxidizing atmosphere heat treatment process: see Figure 1(d)). In the oxidizing atmosphere heat treatment process of this embodiment, for example, batch annealing is performed using a batch-type heat treatment apparatus.

[0034] Furthermore, in Figure 4, the oxidizing atmosphere heat treatment process is indicated by section Y. In this oxidizing atmosphere heat treatment process, for example, by maintaining the maximum temperature T2 for a predetermined time t2, the surface of the wafer 11 is covered with an oxide film 14 (SiO2), and the annular cavity 13 is filled with SiO2 oxide. That is, an annular SiO2 layer 15 with a depth of 0.1 μm to 50 μm from the surface of the wafer 11 is formed inside the cavity 13. In addition, this heat treatment forms oxygen precipitates that serve as gettering sites in a region of several μm on the surface of the wafer 11.

[0035] In this embodiment, batch annealing is performed in the oxidizing atmosphere heat treatment process as described above, but this is not the only method. For example, if the groove 12 (cavity 13) is small, the cavity 13 can also be filled with SiO2 by heat treatment using an RTP (rapid thermal process) apparatus.

[0036] Furthermore, the heat treatment conditions for the oxidation atmosphere heat treatment process are not limited to those described above. For example, the wafer 11 after the inert atmosphere heat treatment process may be subjected to heat treatment under an oxygen atmosphere with a heating rate of 20 to 150°C / min, a cooling rate of 20 to 150°C / min, and a maximum temperature of 1200 to 1400°C maintained for a predetermined time.

[0037] Furthermore, in the oxidizing atmosphere heat treatment process of this embodiment, the holding time at the maximum temperature can be appropriately set according to the cross-sectional shape, width, and depth of the groove 12. However, in order to fill the cavity 13 with oxide, it is desirable to perform the heat treatment with a holding time of 30 seconds or more at the maximum temperature, and it is even more desirable to perform the heat treatment with a holding time of 60 seconds or more at the maximum temperature. Also, from the viewpoint of productivity, it is desirable to set the holding time at the maximum temperature to 4 hours or less.

[0038] Next, the wafer 11 covered with the oxide film 14 is cleaned with HF (hydrofluoric acid) to remove the oxide film 14 (first cleaning step: see Figure 1(e)). Here, only the oxide film 14 formed on the surface of the wafer 11 is removed, and the SiO2 (SiO2 layer 15) filling the void 13 is left intact.

[0039] Then, the side of the wafer 11 facing the cavity 13 after oxide film removal (the side where the groove 12 was formed in the groove formation process) is polished or etched until the SiO2 filling the cavity 13 (the annular SiO2 layer 15) is exposed, that is, until the cover formed on the groove 12 in the inert atmosphere heat treatment process is gone (exposure process: see Figure 1(f)). This yields a semiconductor wafer 21 for bonding with the annular SiO2 layer 15 exposed.

[0040] Next, the side of the semiconductor wafer 21 for bonding obtained by the exposure process, where the SiO2 layer 15 is exposed (the side facing the groove 12), is bonded to, for example, a support substrate 22 which is a semiconductor wafer, to produce a bonded substrate 31 (bonding process: see Figure 1(g)).

[0041] Finally, using the SiO2 layer 15 of the bonding semiconductor wafer 21 constituting the bonding substrate 31 as a boundary, the unwanted portions other than the region surrounded by the annular SiO2 layer 15 (the first unwanted portion 23 and the second unwanted portion 24 described later) are removed to obtain the desired composite substrate 41 (composite substrate manufacturing process: corresponding to the thinning process and the second cleaning process described later).

[0042] Specifically, the surface of the bonding semiconductor wafer 21 constituting the bonding substrate 31 where the SiO2 layer 15 is not formed (the surface where the groove portion 12 is not formed) is ground down until the annular SiO2 layer 15 is exposed, or peeled off so that the annular SiO2 layer 15 is exposed. In other words, the first unnecessary portion 23 is removed by thinning the bonding semiconductor wafer 21 (thinning process: see Figure 1(h)). As a result, a knife edge (second unnecessary portion 24) is formed on the outer periphery of the remaining bonding semiconductor wafer 21 due to the thinning of the wafer bevel, and the remaining bonding semiconductor wafer 21 is divided into an outer periphery side and a central side with the annular SiO2 layer 15 as the boundary (see Figure 1(h)).

[0043] Furthermore, when the annular SiO2 layer 15 is exposed during the thinning process, the SiO2 layer 15 acts as a column, making it possible to flatten the region surrounded by the annular SiO2 layer 15 while suppressing sagging (edge ​​sagging) at the outer periphery.

[0044] Furthermore, in the thinning process, when peeling off a side of the bonding semiconductor wafer 21 where the SiO2 layer 15 is not formed so that the SiO2 layer 15 is exposed, an embrittlement layer is formed on the bonding semiconductor wafer 21 in advance using an ion implantation separation method or laser light, and the peeling is performed from that embrittlement layer.

[0045] Then, the semiconductor wafer 21 for bonding from which the first unwanted portion 23 has been removed is subjected to HF cleaning to remove the annular SiO2 layer 15 (second cleaning step: see Figure 1(i)). This makes it possible to remove the knife edge (second unwanted portion 24) by a wet process alone without grinding the knife edge, and to obtain the desired composite substrate 41 from which the unwanted portion has been removed.

[0046] Furthermore, the semiconductor wafer material (raw material) used in this embodiment is not limited to silicon (Si), but may also be germanium (Ge), selenium (Se), gallium arsenide (GaAs), silicon carbide (SiC), indium phosphide (InP), gallium nitride (GaN), synthetic diamond (C), etc.

[0047] Furthermore, the support substrate 22 used in this embodiment is not limited to a semiconductor wafer, but any substrate (for example, a glass substrate) can be used.

[0048] Furthermore, in the thinning process of this embodiment, the surface of the bonding semiconductor wafer 21 where the SiO2 layer 15 is not formed is thinned until the SiO2 layer 15 is exposed. However, if polishing is stopped just before the SiO2 layer 15 is exposed, for example, the knife edge can be retained by the thin silicon film even after the subsequent second cleaning process. In this state, the knife edge is only connected by a thin silicon film, meaning it can be easily peeled off with little force. This makes it possible to peel off the knife edge while suppressing damage to the grinding wheel used for polishing.

[0049] As described above, the manufacturing process of this embodiment includes a groove formation step of forming an annular groove 12 on one side of the wafer 11 that is concentric with the outer circumference of the wafer 11 and has a predetermined width and depth, and an oxidation atmosphere heat treatment step of performing heat treatment on the wafer 11 having the groove 12 in an oxygen atmosphere to cover the surface of the wafer 11 with an oxide film 14 and fill the inside of the annular groove 12 with oxide.

[0050] Furthermore, the manufacturing process of this embodiment further includes an inert atmosphere heat treatment step in which the wafer 11, which has grooves 12 formed by the groove formation step, is heat-treated in an inert atmosphere to form an annular cavity 13 inside the grooves 12 by heat treatment, and the above oxidation atmosphere heat treatment step is performed after the inert atmosphere heat treatment step.

[0051] Furthermore, the manufacturing process of this embodiment includes a first cleaning step of performing HF cleaning on the wafer 11 covered with the oxide film 14 to remove the oxide film 14, and an exposure step of polishing or etching the surface on the wafer 11 where the groove portion 12 is formed after the oxide film 14 has been removed until the oxide is exposed. As a result, a bonding semiconductor wafer 21 with the oxide exposed on the wafer surface can be obtained for bonding to a support substrate 22.

[0052] Furthermore, the manufacturing process of this embodiment includes a bonding step of joining the groove-side surface of the bonding semiconductor wafer 21 manufactured by the above-described steps to the support substrate 22, and a composite substrate manufacturing step of removing unnecessary portions other than the region surrounded by oxide filling the annular groove 12 formed in the bonding semiconductor wafer 21.

[0053] Specifically, the composite substrate manufacturing process involves a thinning step in which the surface of the bonding semiconductor wafer 21 where grooves 12 are not formed is ground or peeled off to expose oxide, and a second cleaning step in which HF cleaning is performed on the bonding semiconductor wafer 21 after the thinning step to remove the oxide filling the annular grooves 12. This makes it possible to easily obtain a composite substrate 41 from which the knife edge has been removed without degrading the quality.

[0054] The bonding semiconductor wafer 21 manufactured by the manufacturing process of this embodiment described above is a bonding semiconductor wafer with a diameter of 150 mm or more on which oxygen precipitates that serve as gettering sites are formed, and an annular groove 12 is formed on one side that is concentric with the outer circumference of the wafer and has a predetermined width and depth, the groove 12 has a depth of 0.1 μm to 50 μm from the wafer surface and a width of 50 nm to 200 nm, and is formed at a position 0.1 mm to 10.0 mm inward from the outer circumference of the wafer, and furthermore, the inside of the groove 12 has a structure filled with oxide.

[0055] <Second Embodiment> Next, a second embodiment of the method for manufacturing a bonded semiconductor wafer and a composite substrate according to the present invention will be specifically described with reference to the drawings. Figure 5 is a schematic diagram showing the manufacturing process of the second embodiment of the method for manufacturing a bonded semiconductor wafer and a composite substrate according to the present invention.

[0056] In this embodiment, similar to the first embodiment described above, a silicon wafer will be used as an example of a semiconductor wafer to explain the method for manufacturing a bonded semiconductor wafer and a composite substrate according to the present invention.

[0057] In the second embodiment, similar to the first embodiment, a well-known planarization process including the slicing, lapping, etching, and CP processes described above is first performed to obtain the wafer 11 shown in Figure 5(a) (planarization process).

[0058] Next, a groove formation process similar to that of the first embodiment is performed to form an annular groove 12 on one side of the wafer 11 that is concentric with the outer circumference of the wafer 11 and has a predetermined width and depth (groove formation process: see Figure 5(b)). The formation position and shape of the groove 12 are the same as in the first embodiment (see Figures 2 and 3).

[0059] Next, the wafer 11 after the groove formation process is subjected to heat treatment under heat treatment conditions in an oxygen atmosphere, with a heating rate of 1 to 20°C / min, a cooling rate of 1 to 20°C / min, and maintaining a maximum temperature of 1000 to 1400°C for a predetermined time (oxidizing atmosphere heat treatment process: see Figure 5(c)). In the oxidizing atmosphere heat treatment process of this embodiment, for example, batch annealing is performed using a batch-type heat treatment apparatus.

[0060] Figure 6 shows an example of the heat treatment of the second embodiment, with the vertical axis representing temperature (°C) and the horizontal axis representing time (sec). In Figure 6, the oxidizing atmosphere heat treatment process is indicated by section Z. In this oxidizing atmosphere heat treatment process, for example, by maintaining the highest attainable temperature T3 for a predetermined time t3, the surface of the wafer 11 is covered with an oxide film 14 (SiO2). At this time, an annular SiO2 layer 15 with a depth of 0.1 μm to 50 μm from the surface of the wafer 11 is also formed in the groove 12. In addition, this heat treatment forms oxygen precipitates that serve as gettering sites in a surface region of several μm on the wafer 11.

[0061] In this embodiment, batch annealing is performed in the oxidizing atmosphere heat treatment process as described above, but this is not the only method. For example, if the groove 12 is small, the inside of the groove 12 can also be filled with SiO2 by heat treatment using an RTP device.

[0062] Furthermore, the heat treatment conditions are not limited to those described above. For example, the wafer 11 after the groove formation process may be subjected to heat treatment under an oxygen atmosphere with a heating rate of 20 to 150°C / min, a cooling rate of 20 to 150°C / min, and a maximum temperature of 1200 to 1400°C maintained for a predetermined time.

[0063] Furthermore, in the oxidizing atmosphere heat treatment process of this embodiment, the holding time at the maximum temperature can be appropriately set according to the cross-sectional shape, width, and depth of the groove 12. However, in order to fill the groove 12 with oxide, it is desirable to perform the heat treatment with a holding time of 30 seconds or more at the maximum temperature, and it is even more desirable to perform the heat treatment with a holding time of 60 seconds or more at the maximum temperature. Also, from the viewpoint of productivity, it is desirable to set the holding time at the maximum temperature to 4 hours or less.

[0064] Next, HF cleaning is performed on the wafer 11 covered with the oxide film 14, excluding the surface where the groove portion 12 is formed, to remove the oxide film 14 from the cleaned areas (first cleaning step: see Figure 5(d)). Specifically, only the oxide film formed on the surface opposite to the surface where the groove portion 12 is formed and on the outer peripheral surface (wafer bevel) of the wafer 11 is removed, while the oxide film (SiO2) covering the surface where the groove portion 12 is formed and the SiO2 filling the inside of the groove portion 12 (SiO2 layer 15) are left intact. This results in a bonding semiconductor wafer 21a in which the surface where the groove portion 12 is formed is covered with a silicon oxide film layer 16.

[0065] Next, the side of the semiconductor wafer 21a for bonding obtained by the first cleaning step that is covered with the silicon oxide film layer 16 (the side facing the groove portion 12) is bonded to, for example, a support substrate 22 which is a semiconductor wafer, to obtain a bonded substrate 31a (bonding step: see Figure 5(e)). That is, the bonded substrate 31a has a structure in which the semiconductor wafer 21a for bonding and the support substrate 22 are bonded via the silicon oxide film layer 16 (bonding layer).

[0066] In this embodiment, the bonding layer is described as a silicon oxide film layer, but it is not limited to this. For example, it is possible to remove only the silicon oxide film layer 16 by HF cleaning and form a silicon nitride film layer, an organic adhesive layer, a titanium layer, or a titanium oxide film layer as the bonding layer by CVD (Chemical Vapor Deposition) or PVD (Physical Vapor Deposition).

[0067] Finally, using the SiO2 layer 15 of the bonding semiconductor wafer 21a constituting the bonding substrate 31a as a boundary, the unwanted portions other than the region surrounded by the annular SiO2 layer 15 (the first unwanted portion 23 and the second unwanted portion 24 described later) are removed to obtain the desired composite substrate 41a (composite substrate manufacturing process: corresponding to the thinning process and the second cleaning process described later).

[0068] Specifically, the surface of the bonding semiconductor wafer 21a constituting the bonding substrate 31a where the SiO2 layer 15 is not formed (the surface where the groove portion 12 is not formed) is ground down until the SiO2 layer 15 is exposed, or peeled off so that the SiO2 layer 15 is exposed. In other words, the first unnecessary portion 23 is removed by thinning the bonding semiconductor wafer 21a (thinning process: see Figure 5(f)). As a result, a knife edge (second unnecessary portion 24) is formed on the outer periphery of the remaining bonding semiconductor wafer 21a due to the thinning of the wafer bevel, and the remaining bonding semiconductor wafer 21a is divided into an outer periphery side and a central side with the annular SiO2 layer 15 as the boundary.

[0069] Furthermore, when the SiO2 layer 15 is exposed during the thinning process, it acts as a column, making it possible to flatten the region surrounded by the annular SiO2 layer 15 while suppressing sagging (edge ​​sagging) at the outer edge.

[0070] In the thinning process, when peeling off a side of the bonding semiconductor wafer 21a where the SiO2 layer 15 is not formed so that the SiO2 layer 15 is exposed, an embrittlement layer is formed on the bonding semiconductor wafer 21a in advance using an ion implantation separation method or laser light, and the peeling is performed from that embrittlement layer.

[0071] Then, the semiconductor wafer 21a for bonding from which the first unwanted portion 23 has been removed is subjected to HF cleaning to remove the annular SiO2 layer 15 (second cleaning step: see Figure 5(g)). This makes it possible to remove the knife edge (second unwanted portion 24) by a wet process alone without grinding the knife edge, and to obtain the desired composite substrate 41a (SOI: Silicon-On-Insulator Wafer) from which the unwanted portion has been removed.

[0072] As described above, the manufacturing process of this embodiment includes a groove formation step of forming an annular groove 12 on one side of the wafer 11 that is concentric with the outer circumference of the wafer 11 and has a predetermined width and depth, and an oxidation atmosphere heat treatment step of performing heat treatment on the wafer 11 having the groove 12 in an oxygen atmosphere to cover the surface of the wafer 11 with an oxide film 14 and fill the inside of the annular groove 12 with oxide.

[0073] Furthermore, the manufacturing process of this embodiment further includes a first cleaning step in which HF cleaning is performed on surfaces other than the surface on which the groove portion 12 is formed on the wafer 11 covered with the oxide film 14, and the oxide film is removed from the cleaned portion. As a result, a bonding semiconductor wafer 21a can be obtained in which the surface on which the groove portion 12 is formed is covered with an oxide film (silicon oxide film layer 16) for bonding to a support substrate 22.

[0074] Furthermore, the manufacturing process of this embodiment includes a bonding step of bonding the groove-side surface of the bonding semiconductor wafer 21a manufactured by the above-described steps to the support substrate 22, and a composite substrate manufacturing step of removing unnecessary portions other than the region surrounded by oxide filling the annular groove 12 formed in the bonding semiconductor wafer 21a.

[0075] Specifically, the composite substrate manufacturing process involves a thinning step in which the surface of the bonding semiconductor wafer 21a where grooves 12 are not formed is ground or peeled off to expose oxide, and a second cleaning step in which HF cleaning is performed on the bonding semiconductor wafer 21a after the thinning step to remove the oxide filling the annular grooves 12. This makes it possible to easily obtain a composite substrate 41a with the knife edge removed without degrading the quality.

[0076] The bonding semiconductor wafer 21a manufactured by the manufacturing process of this embodiment described above is a bonding semiconductor wafer with a diameter of 150 mm or more on which oxygen precipitates that serve as gettering sites are formed, and an annular groove 12 is formed on one side that is concentric with the outer circumference of the wafer and has a predetermined width and depth, the groove 12 has a depth of 0.1 μm to 50 μm from the wafer surface and a width of 50 nm to 200 nm, and is formed at a position 0.1 mm to 10.0 mm inward from the outer circumference of the wafer, and furthermore, the inside of the groove 12 is filled with oxide and the surface on which the groove 12 is formed is covered with an oxide film layer.

[0077] It should be noted that the present invention is not limited to the first and second embodiments described above. The above embodiments are illustrative, and any configuration that is substantially identical to the technical idea described in the claims and achieves similar effects is included within the technical scope of the present invention. [Examples]

[0078] Next, the method for manufacturing a semiconductor wafer for bonding and a composite substrate according to the present invention will be further described based on examples. However, the present invention is not limited to the following examples.

[0079] <Example 1> After obtaining a silicon single crystal ingot grown by the CZ method, five silicon wafers with a diameter of 300 mm were prepared by performing a well-known planarization process including slicing, lapping, etching, and CP processes.

[0080] Next, on one side of the silicon wafer, grooves were formed by dry etching, creating concentric grooves extending 1 mm from the outer edge, with a width of 100 nm and a depth of 10 μm, and a rectangular cross-section (groove formation process).

[0081] Next, the grooved silicon wafer was heat-treated in an Ar atmosphere with a heating rate of 5°C / min, a cooling rate of 5°C / min, and a maximum temperature of 1200°C with a holding time of 1 hr (inert atmosphere heat treatment process) to form an annular cavity inside the silicon wafer. Then, after cooling down to 700°C, the wafer was further heat-treated in an oxygen atmosphere with a heating rate of 5°C / min, a cooling rate of 5°C / min, and a maximum temperature of 1300°C with a holding time of 1 hr (oxidizing atmosphere heat treatment process) to cover the silicon wafer with an oxide film and form an annular SiO2 layer with a depth of 10 μm from the silicon wafer surface. In Example 1, batch annealing was performed using a batch-type heat treatment apparatus.

[0082] Next, the silicon wafer covered with an oxide film was subjected to HF cleaning with a 5% by mass hydrofluoric acid purified water solution for 15 seconds (first cleaning step) to remove the oxide film. Here, only the oxide film covering the silicon wafer was removed, leaving the SiO2 layer intact.

[0083] Next, the silicon wafer with the SiO2 layer remaining was polished on both sides to a thickness of 7 μm, and then the side with the SiO2 layer was polished on one side to a thickness of 0.5 μm (exposure process). This resulted in a semiconductor wafer for bonding with the SiO2 layer exposed on the surface of the silicon wafer.

[0084] Next, the side of the semiconductor wafer for bonding with the exposed SiO2 layer was bonded to a silicon wafer that would serve as a support substrate (bonding process) to produce a bonded substrate.

[0085] Next, the side of the semiconductor wafer for bonding that does not have an SiO2 layer was ground down (thinning process) until the SiO2 layer was exposed (i.e., until the thickness of the semiconductor wafer for bonding was 10 μm), creating a knife edge on the outer periphery of the remaining semiconductor wafer.

[0086] Finally, the bonded semiconductor wafers that had developed knife edges were subjected to HF cleaning for 30 seconds with a 10% by mass hydrofluoric acid solution (second cleaning step) to remove the annular SiO2 layer. As a result, five composite substrates of Example 1 with the knife edges removed were obtained.

[0087] <Example 2> In Example 2, the composite substrate was manufactured under the same conditions and procedures as in Example 1, except as described below. • Heat treatment conditions for the inert atmosphere heat treatment process → Maximum temperature reached 1200℃・Holding time 4hr • Heat treatment conditions for the oxidizing atmosphere heat treatment process → Maximum temperature reached 1000℃・Holding time 1hr

[0088] <Example 3> In Example 3, the composite substrate was manufactured under the same conditions and procedures as in Example 1, except as described below. • Heat treatment conditions for the inert atmosphere heat treatment process → Maximum temperature reached 1200℃・Holding time 0.5hr • Heat treatment conditions for the oxidizing atmosphere heat treatment process → Maximum temperature reached 1350℃・Holding time 1hr

[0089] <Example 4> In Example 4, the composite substrate was manufactured under the same conditions and procedures as in Example 1, except as described below. • Heat treatment conditions for the oxidizing atmosphere heat treatment process → Maximum temperature reached 1300℃・Holding time 4hr

[0090] <Example 5> In Example 5, the composite substrate was manufactured under the same conditions and procedures as in Example 1, except as described below. • Heat treatment conditions for the oxidizing atmosphere heat treatment process → Maximum temperature reached 1300℃・Holding time 0.5hr

[0091] <Example 6> After obtaining a silicon single crystal ingot grown by the CZ method, five silicon wafers with a diameter of 300 mm were prepared by performing a well-known planarization process including slicing, lapping, etching, and CP processes.

[0092] Next, on one side of the silicon wafer, grooves were formed by laser processing, creating concentric circles extending 5 mm from the outer edge, with a width of 200 nm and a depth of 10 μm, and a rectangular cross-section (groove formation process).

[0093] Next, the grooved silicon wafer was heat-treated in an oxygen atmosphere under the following heat treatment conditions: heating rate of 5°C / min, cooling rate of 5°C / min, and maximum temperature reached of 1300°C with a holding time of 1 hr (oxidizing atmosphere heat treatment process). This covered the silicon wafer with an oxide film and formed an annular SiO2 layer with a depth of 10 μm within the grooves. In Example 6, batch annealing was performed using a batch-type heat treatment apparatus.

[0094] Next, the silicon wafer covered with an oxide film, excluding the surface where grooves were formed, was subjected to HF cleaning with a 5% by mass hydrofluoric acid purified water solution for 25 seconds (first cleaning step) to remove the oxide film from the cleaned areas. That is, the oxide film covering the surface where grooves were formed and the SiO2 layer inside the grooves were left intact. This resulted in obtaining a semiconductor wafer for bonding in which the surface where grooves were formed was covered with an oxide film.

[0095] Next, the oxide-covered surface of the semiconductor wafer for bonding was joined to a silicon wafer that would serve as the support substrate (bonding process) to produce a bonded substrate.

[0096] Next, the uncovered side of the semiconductor wafer for bonding was ground down (thinning process) until the SiO2 layer was exposed (i.e., until the thickness of the semiconductor wafer for bonding was 10 μm), creating a knife edge on the outer periphery of the remaining semiconductor wafer for bonding.

[0097] Finally, the bonded semiconductor wafers that had developed knife edges were subjected to HF cleaning for 30 seconds with a 10% by mass hydrofluoric acid solution (second cleaning step) to remove the annular SiO2 layer. As a result, five composite substrates of Example 6 with the knife edges removed were obtained.

[0098] <Example 7> In Example 7, the composite substrate was manufactured under the same conditions and procedures as in Example 6, except as described below. • Groove width → 50nm

[0099] <Example 8> In Example 8, the composite substrate was manufactured under the same conditions and procedures as in Example 6, except as described below. • Groove width → 100nm • Groove depth → 0.1 μm

[0100] <Example 9> In Example 9, the composite substrate was manufactured under the same conditions and procedures as in Example 6, except as described below. • Groove width → 100nm • Groove depth → 50 μm

[0101] <Example 10> In Example 10, the composite substrate was manufactured under the same conditions and procedures as in Example 1, except as described below. • Groove width → 50nm • Groove depth → 0.2 μm • Heat treatment conditions for the oxidizing atmosphere heat treatment process → Cooling rate 50℃ / min, maximum temperature reached 1300℃・Holding time 60sec

[0102] <Comparative Example 1> In Comparative Example 1, the composite substrate was manufactured under the same conditions and process as in Example 1, except as described below. • Heat treatment conditions for the oxidizing atmosphere heat treatment process → Maximum temperature reached 900℃・Holding time 1hr

[0103] <Comparative Example 2> In Comparative Example 2, the composite substrate was manufactured under the same conditions and process as in Example 1, except as described below. • Groove width → 300nm • Heat treatment conditions for the inert atmosphere heat treatment process → Maximum temperature reached 900℃・Holding time 1hr

[0104] <Comparative Example 3> In Comparative Example 3, the composite substrate was manufactured under the same conditions and process as in Example 1, except as described below. • Groove depth → 60 μm • Heat treatment conditions for the oxidizing atmosphere heat treatment process → Maximum temperature reached 900℃・Holding time 1hr

[0105] <Comparative Example 4> In Comparative Example 4, the composite substrate was manufactured under the same conditions and process as in Example 6, except as described below. • Groove depth → 60 μm

[0106] <Rating> Table 1 shows the evaluations of Examples 1 to 10 and Comparative Examples 1 to 4. For Examples 1 to 10, a composite substrate was obtained in which knife edges generated on the semiconductor wafer for bonding could be easily removed, and thinning was achieved with a shape that was less prone to chipping on the outer edge (Evaluation: ○).

[0107] [Table 1]

[0108] In Comparative Example 1, the maximum temperature reached during the oxidizing atmosphere heat treatment was low, so sufficient oxide could not be formed inside the grooves. As a result, the knife edge formed at the end damaged the inner bonding wafer during the thinning process (Evaluation: ×). Similarly, in Comparative Example 2, the maximum temperature reached during the inert atmosphere heat treatment was low, so a lid could not be sufficiently formed over the groove openings. As a result, the subsequent HF cleaning removed even the oxide inside the grooves (Evaluation: ×). In Comparative Example 3, similar to Comparative Example 1, the maximum temperature reached during the oxidizing atmosphere heat treatment was low, so sufficient oxide could not be formed inside the grooves. As a result, the knife edge formed at the end damaged the inner bonding wafer during the thinning process (Evaluation: ×). Furthermore, in Comparative Example 4, the groove depth was large at 60 μm, so sufficient oxide could not be formed inside the grooves. As a result, the knife edge formed at the end damaged the inner bonding wafer during the thinning process (Evaluation: ×). [Explanation of Symbols]

[0109] 11. Silicon wafer (wafer) 12 grooves 13 Cavity 14 Oxide film 15 SiO2 layer 16 Silicon oxide layer 21, 21a Semiconductor wafers for bonding 22 Support substrate 23. First unnecessary part 24. Second unnecessary part 31, 31a Bonded board 41, 41a Composite substrate

Claims

1. A method for manufacturing a semiconductor wafer for bonding to a support substrate, A groove formation step of forming an annular groove on one side of a semiconductor wafer that is concentric with the outer circumference of the semiconductor wafer and has a predetermined width and depth, An oxidizing atmosphere heat treatment step is performed on the semiconductor wafer having the groove portion in an oxygen atmosphere to cover the surface of the semiconductor wafer with an oxide film and to fill the inside of the annular groove portion with oxide, including, A method for manufacturing semiconductor wafers for bonding, characterized by the features described above.

2. An inert atmosphere heat treatment step is performed on the semiconductor wafer in which grooves have been formed by the groove formation step, in which an annular cavity is formed inside the grooves by the heat treatment. It further includes, The aforementioned oxidizing atmosphere heat treatment step is performed after the aforementioned inert atmosphere heat treatment step. The method for manufacturing a semiconductor wafer for bonding according to claim 1.

3. A first cleaning step involves performing HF cleaning on a semiconductor wafer covered with the aforementioned oxide film to remove the oxide film, An exposure step is performed in which the surface on which the groove portion is formed in the semiconductor wafer after the oxide film has been removed is polished or etched until the oxide is exposed, Further including, The method for manufacturing a semiconductor wafer for bonding according to feature 2.

4. A first cleaning step involves performing HF cleaning on surfaces of a semiconductor wafer covered with the aforementioned oxide film, other than the surface on which the groove portion is formed, to remove the oxide film from the cleaned portion. Further including, The method for manufacturing a semiconductor wafer for bonding according to claim 1.

5. The groove portion has a depth of 0.1 μm to 50 μm from the surface of the semiconductor wafer, a width of 50 nm to 200 nm, and is formed at a position 0.1 mm to 10.0 mm inward from the outer edge of the semiconductor wafer. The method for manufacturing a semiconductor wafer for bonding according to claim 1.

6. The shape of the groove is such that the cross-sectional shape perpendicular to the surface of the semiconductor wafer is elliptical, rectangular, L-shaped, or arc-shaped. The method for manufacturing a semiconductor wafer for bonding according to claim 1.

7. The heat treatment in the aforementioned oxidizing atmosphere heat treatment step is carried out under heat treatment conditions in an oxygen atmosphere, with a heating rate of 1 to 20°C / min, a cooling rate of 1 to 20°C / min, and maintaining a maximum temperature of 1000 to 1400°C for a predetermined time. The method for manufacturing a semiconductor wafer for bonding according to claim 1.

8. The heat treatment in the aforementioned oxidation atmosphere heat treatment step is carried out under heat treatment conditions in an oxygen atmosphere, with a heating rate of 20 to 150°C / min, a cooling rate of 20 to 150°C / min, and maintaining a maximum temperature of 1200 to 1400°C for a predetermined time. The method for manufacturing a semiconductor wafer for bonding according to claim 1.

9. The heat treatment in the aforementioned inert atmosphere heat treatment step is carried out under heat treatment conditions in an inert atmosphere, with a heating rate of 1 to 20°C / min, a cooling rate of 1 to 20°C / min, and maintaining a maximum temperature of 1000 to 1400°C for a predetermined time. The method for manufacturing a semiconductor wafer for bonding according to feature 2.

10. A bonding step of bonding the groove-side surface of a bonded semiconductor wafer manufactured by the method for manufacturing a bonded semiconductor wafer according to claim 3 or claim 4 to a support substrate, A composite substrate manufacturing process that removes unwanted portions other than the region surrounded by oxide filling the annular groove formed in the aforementioned semiconductor wafer for bonding, including, A method for manufacturing a composite substrate, characterized by the above.

11. The aforementioned composite substrate manufacturing process is: A thinning step in which the surface of the semiconductor wafer for bonding that does not have grooves formed is ground until the oxide is exposed, or peeled off so that the oxide is exposed, A second cleaning step involves performing HF cleaning on the semiconductor wafer for bonding after the thinning step has been carried out to remove oxides filling the annular grooves, including, A method for manufacturing a composite substrate according to claim 10.

12. In the thinning process, when peeling off the surface of the bonding semiconductor wafer where no grooves are formed so that the oxide is exposed, an embrittlement layer is formed on the bonding semiconductor wafer in advance using an ion implantation separation method or laser light, and the peeling is performed from the embrittlement layer. A method for manufacturing a composite substrate according to feature 11.

13. A semiconductor wafer for bonding with a diameter of 150 mm or more, on which oxygen precipitates that serve as gettering sites are formed, An annular groove is formed on one side, concentric with the outer circumference of the wafer and having a predetermined width and depth. The groove portion has a depth of 0.1 μm to 50 μm from the surface of the wafer, a width of 50 nm to 200 nm, and is formed at a position 0.1 mm to 10.0 mm inward from the outer edge of the wafer. The groove has a structure in which the inside is filled with oxide. A semiconductor wafer for bonding, characterized by the following features.

14. The surface on which the groove portion is formed is covered with an oxide film layer, The semiconductor wafer for bonding according to feature 13.

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