Capacitive sensor detection circuit

Abstract

This invention provides a capacitive sensor detection circuit that converts the output signal, which responds to changes in capacitance, into a continuous signal over time. [Solution] A capacitive sensor detection circuit 20 used in a sensor element 10 comprising a movable electrode 100 that is displaced, a first electrode 121 that outputs a signal corresponding to the change in a first capacitance Cs1 that changes due to the displacement of the movable electrode 100, and a second electrode 122 that outputs a signal corresponding to the change in a second capacitance Cs2 that changes due to the displacement of the movable electrode 100, includes a control unit 70 that acquires a first input signal Vin1 and a second input signal Vin2, and outputs a signal to a first capacitor 61 and a second capacitor 62 that has a feedback amplitude Vcnt that brings the amplitudes of the first input signal Vin1 and the second input signal Vin2, whose frequency and phase correspond to the frequency and phase of the modulated signal S, close to zero, and whose frequency corresponds to the frequency of the modulated signal and whose phase is inverse to the phase of the modulated signal.

Description

Technical Field

[0001] The present disclosure relates to a capacitive sensor detection circuit.

Background Art

[0002] Conventionally, as described in Non-Patent Document 1, a detection circuit for a capacitive sensor that detects acceleration from a change in capacitance that changes due to displacement of an electrode is known. This detection circuit includes a fully differential amplifier that outputs a signal corresponding to the change in capacitance, and a feedback amplifier that controls the input voltage of the fully differential amplifier to a predetermined voltage.

Prior Art Documents

Patent Documents

[0003]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the detection circuit described in Non-Patent Document 1, since the feedback amplifier sets the input voltage of the fully differential amplifier to a predetermined voltage, the input voltage of the fully differential amplifier is reset. While the input voltage of the fully differential amplifier is reset, the signal output from the fully differential amplifier does not include a signal corresponding to acceleration, so the signal becomes discontinuous with respect to time.

[0005] An object of the present disclosure is to provide a capacitive sensor detection circuit that makes an output signal corresponding to a change in capacitance a continuous signal with respect to time. [Means for solving the problem]

[0006] The invention described in claim 1 is a capacitive sensor detection circuit used in a sensor element (10) comprising a displaceable movable electrode (100), a first electrode (121) that outputs a signal corresponding to the change in a first capacitance (Cs1) between the movable electrode which changes due to the displacement of the movable electrode, and a second electrode (122) that outputs a signal corresponding to the change in a second capacitance (Cs2) between the movable electrode which changes due to the displacement of the movable electrode, wherein a modulated signal (S), which is a signal having input amplitude (Vm), frequency and phase, is used with respect to the movable electrode A fully differential amplifier (24) having a signal generation unit (22) that outputs to the poles, a first input terminal (241) connected to the first electrode, a second input terminal (242) connected to the second electrode, a first output terminal (251) that outputs a signal corresponding to the first input signal (Vin1) input to the first input terminal and the second input signal (Vin2) input to the second input terminal, and a second output terminal (252) that outputs a signal corresponding to the first input signal and the second input signal, and the first input terminal and the first output terminal The capacitive sensor detection circuit comprises: a first feedback capacitor (31) connected to the child; a second feedback capacitor (32) connected to the second input terminal and the second output terminal; a calculation unit (50) that calculates a value related to the displacement of the movable electrode based on a first output signal (Vout1) which is a signal output from the first output terminal and a second output signal (Vout2) which is a signal output from the second output terminal; a first capacitor (61) connected between the first electrode and the first input terminal; a second capacitor (62) connected between the second electrode and the second input terminal; and a control unit (70) that acquires the first input signal and the second input signal and outputs a signal to the first and second capacitors that has a feedback amplitude (Vcnt) that brings the amplitudes of the first and second input signals, whose frequency and phase correspond to the frequency and phase of the modulated signal, close to zero, and whose frequency corresponds to the frequency of the modulated signal and whose phase is opposite to the phase of the modulated signal.

[0007] Furthermore, the invention described in claim 9 is a capacitive sensor detection circuit used in a sensor element (10) comprising a displaceable movable electrode (100), a first electrode (121) that outputs a signal corresponding to the change in a first capacitance (Cs1) between the movable electrode which changes due to the displacement of the movable electrode, and a second electrode (122) that outputs a signal corresponding to the change in a second capacitance (Cs2) between the movable electrode which changes due to the displacement of the movable electrode, wherein a modulated signal (S) having input amplitude (Vm), frequency and phase can be used. A fully differential amplifier (24) having a signal generation unit (22) that outputs to the dynamic electrode, a first input terminal (241) connected to the first electrode, a second input terminal (242) connected to the second electrode, a first output terminal (251) that outputs a signal corresponding to the first input signal (Vin1) input to the first input terminal and the second input signal (Vin2) input to the second input terminal, and a second output terminal (252) that outputs a signal corresponding to the first input signal and the second input signal, and the first input terminal and the first output The capacitive sensor detection circuit comprises: a first feedback capacitor (31) connected to a force terminal; a second feedback capacitor (32) connected to a second input terminal and a second output terminal; a calculation unit (50) that calculates a value relating to the displacement of the movable electrode based on a first output signal (Vout1) output from the first output terminal and a second output signal (Vout2) output from the second output terminal; a first capacitor (61) connected between the first electrode and the first input terminal; a second capacitor (62) connected between the second electrode and the second input terminal; and a control unit (70) that acquires the first output signal and the second output signal and outputs a signal to the first and second capacitors that has a feedback amplitude (Vcnt) that brings the amplitudes of the first and second output signals, whose frequency and phase correspond to the frequency and phase of the modulated signal, close to zero, and whose frequency corresponds to the frequency of the modulated signal and whose phase is opposite to the phase of the modulated signal.

[0008] As a result, the amplitudes of the first input signal and the second input signal, whose frequency and phase correspond to the frequency and phase of the modulated signal, continuously approach zero. Therefore, there is no need to provide a reset period for the first and second input signals. Consequently, the output signal from the fully differential amplifier, which corresponds to the changes in the first and second capacitances, becomes a continuous signal with respect to time.

[0009] The reference numerals in parentheses attached to each component indicate an example of the correspondence between that component and the specific components described in the embodiments described later. [Brief explanation of the drawing]

[0010] [Figure 1] A diagram showing the configuration of a sensor element using the capacitive sensor detection circuit of the first embodiment. [Figure 2] Circuit diagram of a capacitive sensor detection circuit. [Figure 3] This diagram shows the modulated signal from the signal generation unit of a capacitive sensor detection circuit. [Figure 4] This diagram shows the output common-mode feedback circuit of a fully differential amplifier in a capacitive sensor detection circuit. [Figure 5] Block diagram of the control unit of the capacitive sensor detection circuit. [Figure 6] Circuit diagram of the control unit. [Figure 7] A diagram showing the signals output from the control unit. [Figure 8] Circuit diagram of the control unit in the capacitive sensor detection circuit of the second embodiment. [Figure 9] Circuit diagram of the capacitive sensor detection circuit of the third embodiment. [Figure 10] This figure shows the input common-mode feedback circuit of the full differential amplifier in the capacitive sensor detection circuit of the fourth embodiment. [Figure 11] Circuit diagram of a capacitive sensor detection circuit. [Figure 12] Circuit diagram of the control unit for a capacitive sensor detection circuit. [Figure 13]Circuit diagram of the control unit in the capacitive sensor detection circuit of the fifth embodiment. [Figure 14] Circuit diagram of the capacitive sensor detection circuit of the sixth embodiment.

Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are denoted by the same reference numerals, and their descriptions are omitted.

[0012] (First Embodiment) The capacitive sensor detection circuit of this embodiment is used for the sensor element 10 as shown in FIG. 1, and makes the output signal corresponding to the change in capacitance into a continuous signal with respect to time. First, the sensor element 10 will be described.

[0013] The sensor element 10 includes a movable electrode 100, a first elastic part 101, a first fixing part 111, a second elastic part 102, a second fixing part 112, a first electrode 121, and a second electrode 122.

[0014] The movable electrode 100 is displaced by being accelerated or receiving pressure. One end of the first elastic part 101 is connected to the movable electrode 100 in the direction in which the movable electrode 100 is displaced. The other end of the first elastic part 101 is connected to the first fixing part 111 in the direction in which the movable electrode 100 is displaced. The first fixing part 111 is fixed to a housing or the like not shown. One end of the second elastic part 102 is connected to the side of the movable electrode 100 opposite to the first elastic part 101 in the direction in which the movable electrode 100 is displaced. The other end of the second elastic part 102 is connected to the second fixing part 112 in the direction in which the movable electrode 100 is displaced. The second fixing part 112 is fixed to a housing or the like not shown. Therefore, when the movable electrode 100 is displaced, the first elastic part 101 and the second elastic part 102 are elastically deformed to generate a restoring force. By this restoring force, the position of the displaced movable electrode 100 returns to its original position.

[0015] The first electrode 121 is connected to the portion of the movable electrode 100 that is connected to the first elastic portion 101 and faces the direction in which the movable electrode 100 is displaced. Also, when the movable electrode 100 is displaced, the distance between the first electrode 121 and the movable electrode 100 changes, so the first capacitance Cs1 changes. Therefore, the first electrode 121 and the movable electrode 100 serve as a variable capacitor, as shown in FIG. 2. Note that the first capacitance Cs1 is the capacitance between the first electrode 121 and the movable electrode 100.

[0016] Returning to FIG. 1, for example, when the movable electrode 100 is displaced toward the first electrode 121, the distance between the first electrode 121 and the movable electrode 100 decreases, so the first capacitance Cs1 increases. Furthermore, the first electrode 121 outputs a signal corresponding to the change in the first capacitance Cs1.

[0017] The second electrode 122 is connected to the portion of the movable electrode 100 that is connected to the second elastic portion 102 and faces the direction in which the movable electrode 100 is displaced. Thus, the second electrode 122 faces the opposite side of the movable electrode 100 from the first electrode 121. Also, when the movable electrode 100 is displaced, the distance between the second electrode 122 and the movable electrode 100 changes, so the second capacitance Cs2 changes. Therefore, the second electrode 122 and the movable electrode 100 serve as a variable capacitor, as shown in FIG. 2. Note that the second capacitance Cs2 is the capacitance between the second electrode 122 and the movable electrode 100.

[0018] Returning to FIG. 1, for example, when the movable electrode 100 is displaced toward the first electrode 121, the distance between the second electrode 122 and the movable electrode 100 increases, so the second capacitance Cs2 decreases. Therefore, when the movable electrode 100 is displaced, the change in the second capacitance Cs2 is opposite to the change in the first capacitance Cs1. Furthermore, the second electrode 122 outputs a signal corresponding to the change in the second capacitance Cs2.

[0019] Furthermore, here, the first capacitance Cs1 when the movable electrode 100 is not displaced is considered to be the same as the second capacitance Cs2 when the movable electrode 100 is not displaced, and is therefore referred to as Cs0. Note that "same" includes the manufacturing tolerance range.

[0020] As described above, the sensor element 10 is configured as described. Next, the configuration of the capacitive sensor detection circuit used in the sensor element 10 will be explained.

[0021] As shown in Figure 2, the capacitive sensor detection circuit 20 is an ASIC and includes a signal generation unit 22, a fully differential amplifier 24, a first feedback capacitor 31, a first feedback resistor 41, a second feedback capacitor 32, and a second feedback resistor 42. Furthermore, the capacitive sensor detection circuit 20 includes a calculation unit 50, a first parasitic capacitor 51, a second parasitic capacitor 52, a first capacitor 61, a second capacitor 62, and a control unit 70. ASIC stands for Application Specific Integrated Circuit.

[0022] The signal generation unit 22 modulates the signal by including a modulator. The signal generation unit 22 also outputs the modulated signal to the movable electrode 100. The signal output by the signal generation unit 22 is a signal having an input amplitude Vm, frequency, and phase, and is, for example, a square wave as shown in Figure 3. However, the signal output by the signal generation unit 22 is not limited to a square wave, and may be a triangular wave, sawtooth wave, sine wave, etc.

[0023] Here, the signal output from the signal generation unit 22 to the movable electrode 100 is defined as the modulated signal S. The inverse phase signal Sinv is defined as a signal whose amplitude is the input amplitude Vm, whose frequency is the same as the frequency of the modulated signal S, and whose phase is opposite to the phase of the modulated signal S.

[0024] Returning to Figure 2, the signal generation unit 22 outputs the modulated signal S and the inverse phase signal Sinv to the control unit 70, which will be described later.

[0025] The fully differential amplifier 24 has a first input terminal 241, a second input terminal 242, a first output terminal 251, and a second output terminal 252.

[0026] The first input terminal 241 is a non-inverting input terminal and is connected to the first electrode 121. Furthermore, the signal from the first electrode 121 is input to the first input terminal 241.

[0027] The second input terminal 242 is an inverting input terminal and is connected to the second electrode 122. The signal from the second electrode 122 is input to the second input terminal 242.

[0028] Here, the signal input to the first input terminal 241 is denoted as the first input signal Vin1. The signal input to the second input terminal 242 is denoted as the second input signal Vin2.

[0029] The first output terminal 251 outputs signals corresponding to the first input signal Vin1 and the second input signal Vin2.

[0030] The second output terminal 252 outputs signals corresponding to the first input signal Vin1 and the second input signal Vin2.

[0031] Furthermore, the signal output from the first output terminal 251 is designated as the first output signal Vout1, and the signal output from the second output terminal 252 is designated as the second output signal Vout2.

[0032] The fully differential amplifier 24 includes an output common-mode feedback circuit 260 as shown in Figure 4. Therefore, the voltage is controlled so that half of the voltage related to the sum of the first output signal Vout1 and the second output signal Vout2, i.e., (Vout1 + Vout2) / 2, becomes a predetermined voltage. This predetermined voltage is determined through experiments, simulations, etc.

[0033] Returning to Figure 2, one end of the first feedback capacitor 31 is connected to the first input terminal 241. The other end of the first feedback capacitor 31 is connected to the first output terminal 251.

[0034] One end of the second feedback capacitor 32 is connected to the second input terminal 242. The other end of the second feedback capacitor 32 is connected to the second output terminal 252.

[0035] One end of the first feedback resistor 41 is connected to the first input terminal 241 and one end of the first feedback capacitor 31. The other end of the first feedback resistor 41 is connected to the first output terminal 251 and the other end of the first feedback capacitor 31.

[0036] One end of the second feedback resistor 42 is connected to the second input terminal 242 and one end of the second feedback capacitor 32. The other end of the second feedback resistor 42 is connected to the second output terminal 252 and the other end of the second feedback capacitor 32.

[0037] Here, let the capacitance of the first feedback capacitor 31 be the first feedback capacitance Cf1. Let the capacitance of the second feedback capacitor 32 be the second feedback capacitance Cf2. Let the electrical resistance of the first feedback resistor 41 be the first resistor Rf1. Let the electrical resistance of the second feedback resistor 42 be the second resistor Rf2.

[0038] Furthermore, the first feedback capacitance Cf1 is considered to be the same as the second feedback capacitance Cf2, and is therefore denoted as Cf. Thus, Cf1 = Cf2 = Cf. Also, the first resistor Rf1 is considered to be the same as the second resistor Rf2, and is therefore denoted as Rf. Thus, Rf1 = Rf2 = Rf.

[0039] The calculation unit 50 acquires the first output signal Vout1 and the second output signal Vout2. Furthermore, the calculation unit 50 calculates the displacement of the movable electrode 100 based on the acquired first output signal Vout1 and second output signal Vout2. The calculation unit 50 also calculates the acceleration and pressure of the movable electrode 100 from the calculated displacement of the movable electrode 100. In this way, the calculation unit 50 calculates the acceleration and pressure of a detection target (not shown) that displaces together with the movable electrode 100. Note that the acceleration and pressure of the movable electrode 100 correspond to values ​​related to the displacement of the movable electrode 100.

[0040] One end of the first parasitic capacitor 51 is connected between the first electrode 121 and the first input terminal 241. The other end of the first parasitic capacitor 51 is connected to ground.

[0041] One end of the second parasitic capacitor 52 is connected between the second electrode 122 and the second input terminal 242. The other end of the second parasitic capacitor 52 is connected to ground.

[0042] One end of the first capacitor 61 is connected between the first electrode 121 and the first input terminal 241. The other end of the first capacitor 61 is connected to the control unit 70, which will be described later.

[0043] One end of the second capacitor 62 is connected between the second electrode 122 and the second input terminal 242. The other end of the second capacitor 62 is connected to the control unit 70, which will be described later.

[0044] Here, let the capacitance of the first capacitor 61 be the first capacitor capacitance Ct1. Let the capacitance of the second capacitor 62 be the second capacitor capacitance Ct2.

[0045] Furthermore, the capacitance of the first capacitor Ct1 is considered to be the same as the capacitance of the second capacitor Ct2, and is therefore referred to as Ct0. Thus, Ct1 = Ct2 = Ct0.

[0046] As shown in Figure 5, the control unit 70 includes an adder 75, a synchronous detection unit 80, a controller 85, a first adjustment switch 91, and a second adjustment switch 92.

[0047] As shown in Figure 6, the summing unit 75 includes, for example, a first voltage follower circuit 751, a first power supply 761, a first constant current power supply 771, a second voltage follower circuit 752, a second power supply 762, and a second constant current power supply 772. Furthermore, the summing unit 75 includes a first filter capacitor 781, a second filter capacitor 782, a merging unit 785, a filter resistor 787, a high-pass filter 790, and a reference power supply 795.

[0048] The first voltage follower circuit 751 acquires a first input signal Vin1 and outputs a signal corresponding to the acquired first input signal Vin1. Specifically, the first voltage follower circuit 751 includes at least one transistor. Here, the number of transistors in the first voltage follower circuit 751 is one. The transistor in the first voltage follower circuit 751 is, for example, a MOSFET. The drain electrode of the MOSFET in the first voltage follower circuit 751 is connected to the first power supply 761. The gate electrode of the MOSFET in the first voltage follower circuit 751 corresponds to the input terminal of the first voltage follower circuit 751 and is connected between the first electrode 121 and the first input terminal 241. The source electrode of the MOSFET in the first voltage follower circuit 751 corresponds to the output terminal of the first voltage follower circuit 751 and is connected to ground via the first constant current power supply 771. Therefore, the first voltage follower circuit 751 acquires the first input signal Vin1 and outputs a signal of the voltage obtained by subtracting the first gate-source voltage Vgs1 from the voltage of the first input signal Vin1, i.e., the voltage Vin1-Vgs1. Note that MOSFET is an abbreviation for Metal-Oxide-Semiconductor Field-Effect Transistor. The first gate-source voltage Vgs1 is the voltage between the gate electrode and the source electrode of the MOSFET in the first voltage follower circuit 751.

[0049] The second voltage follower circuit 752 acquires the second input signal Vin2 and outputs a signal corresponding to the acquired second input signal Vin2. Specifically, the second voltage follower circuit 752 includes at least one transistor. Here, the number of transistors in the second voltage follower circuit 752 is one. Furthermore, the transistor in the second voltage follower circuit 752 is, for example, a MOSFET. The drain electrode of the MOSFET in the second voltage follower circuit 752 is connected to the second power supply 762. The gate electrode of the MOSFET in the second voltage follower circuit 752 corresponds to the input terminal of the second voltage follower circuit 752 and is connected between the second electrode 122 and the second input terminal 242. The source electrode of the MOSFET in the second voltage follower circuit 752 corresponds to the output terminal of the second voltage follower circuit 752 and is connected to ground via the second constant current power supply 772. Therefore, the second voltage follower circuit 752 acquires the second input signal Vin2 and outputs a signal of the voltage obtained by subtracting the second gate-source voltage Vgs2 from the voltage of the second input signal Vin2, i.e., the voltage Vin2-Vgs2. The second gate-source voltage Vgs2 is the voltage between the gate electrode and the source electrode of the MOSFET in the second voltage follower circuit 752.

[0050] One end of the first filter capacitor 781 is connected to the source electrode of the MOSFET of the first voltage follower circuit 751. Therefore, the first filter capacitor 781 outputs the signal output from the first voltage follower circuit 751.

[0051] One end of the second filter capacitor 782 is connected to the source electrode of the MOSFET of the second voltage follower circuit 752. Therefore, the second filter capacitor 782 outputs the signal output from the second voltage follower circuit 752.

[0052] The merging unit 785 is connected to the other end of the first filter capacitor 781 and the other end of the second filter capacitor 782. Therefore, the signal from the merging unit 785 is the sum of the signal output from the first filter capacitor 781 and the signal output from the second filter capacitor 782. The signal output from the first filter capacitor 781 is the signal relating to the first input signal Vin1, and the signal output from the second filter capacitor 782 is the signal relating to the second input signal Vin2. Thus, the summing unit 75 acquires a signal relating to the sum of the first input signal Vin1 and the second input signal Vin2.

[0053] One end of the filter resistor 787 is connected to the other end of the first filter capacitor 781 and the other end of the second filter capacitor 782 via the junction 785.

[0054] The high-pass filter 790 consists of a first filter capacitor 781, a second filter capacitor 782, and a filter resistor 787. The high-pass filter 790 also removes low-frequency components contained in the signal of the confluence unit 785. As a result, the high-pass filter 790 removes DC components contained in the signal of the confluence unit 785. Therefore, the high-pass filter 790 removes DC components contained in the signal relating to the sum of the first input signal Vin1 and the second input signal Vin2.

[0055] The positive terminal of the reference power supply 795 is connected to the confluence section 785 via the filter resistor 787. The negative terminal of the reference power supply 795 is connected to ground. The voltage of the reference power supply 795 is, for example, half the output voltage of the first power supply 761 or the second power supply 762.

[0056] The synchronous detection unit 80 demodulates the signal relating to the sum of the first input signal Vin1 and the second input signal Vin2, corresponding to the frequency and phase of the modulated signal S. For example, the synchronous detection unit 80 includes a first switch 801, a second switch 802, a third switch 803, and a fourth switch 804.

[0057] One end of the first switch 801 is connected to the merging unit 785. Furthermore, the first switch 801 is switched on and off in accordance with the modulation signal S. One end of the second switch 802 is connected to the merging unit 785. Furthermore, the second switch 802 is switched on and off in accordance with the inverse phase signal Sinv. One end of the third switch 803 is connected to the other end of the filter resistor 787 and the positive terminal of the reference power supply 795. Furthermore, the third switch 803 is switched on and off in accordance with the modulation signal S. One end of the fourth switch 804 is connected to the other end of the filter resistor 787 and the positive terminal of the reference power supply 795. Furthermore, the fourth switch 804 is switched on and off in accordance with the inverse phase signal Sinv.

[0058] Therefore, the first switch 801, the second switch 802, the third switch 803, and the fourth switch 804 are switched on and off by the modulated signal S and the inverse phase signal Sinv. As a result, demodulation corresponding to the frequency and phase of the modulated signal S is performed on the signal at the merging section 785. Consequently, demodulation corresponding to the frequency and phase of the modulated signal S is performed on the signal relating to the sum of the first input signal Vin1 and the second input signal Vin2.

[0059] The controller 85 includes a controller transconductance amplifier 850 and a controller capacitor 852.

[0060] The non-inverting input terminal of the controller transconductance amplifier 850 is connected to the other end of the second switch 802 and the other end of the third switch 803. Furthermore, the non-inverting input terminal of the controller transconductance amplifier 850 is connected to the positive terminal of the reference power supply 795 via the third switch 803. The inverting input terminal of the controller transconductance amplifier 850 is connected to the other end of the first switch 801 and the other end of the fourth switch 804. Also, the inverting input terminal of the controller transconductance amplifier 850 is connected to the positive terminal of the reference power supply 795 via the fourth switch 804. Therefore, the controller transconductance amplifier 850 compares the signal relating to the sum of the first input signal Vin1 and the second input signal Vin2, which have been demodulated by the synchronous detection unit 80, with the signal from the reference power supply 795.

[0061] One end of the controller capacitor 852 is connected to the output terminal of the controller transconductance amplifier 850. The other end of the controller capacitor 852 is connected to ground. Therefore, the controller 85 is configured as a gm-c integrator by the controller transconductance amplifier 850 and the controller capacitor 852.

[0062] Furthermore, the controller 85 uses the signal relating to the sum of the first input signal Vin1 and the second input signal Vin2, which have been demodulated by the synchronous detection unit 80, the signal from the reference power supply 795, the controller transconductance amplifier 850, and the controller capacitor 852. As a result, the controller 85 calculates a feedback amplitude Vcnt that makes the amplitude of the signal relating to the sum of the first input signal Vin1 and the second input signal Vin2, which have been demodulated by the synchronous detection unit 80, zero. The controller 85 also outputs a signal with this calculated feedback amplitude Vcnt to the first adjustment switch 91.

[0063] One end of the first adjustment switch 91 is connected to the output terminal of the controller transconductance amplifier 850 and one end of the controller capacitor 852. As a result, a signal with a feedback amplitude Vcnt is input to the first adjustment switch 91. Furthermore, the other end of the first adjustment switch 91 is connected to the other end of the first capacitor 61 and the other end of the second capacitor 62. The first adjustment switch 91 also switches on and off in response to an inverse phase signal Sinv.

[0064] One end of the second adjustment switch 92 is connected to ground. Furthermore, the other end of the second adjustment switch 92 is connected to the other end of the first capacitor 61, the other end of the second capacitor 62, and the other end of the first adjustment switch 91. The second adjustment switch 92 is also switched on and off in response to the modulation signal S.

[0065] Furthermore, the first adjustment switch 91 and the second adjustment switch 92 are switched on and off by the modulated signal S and the inverse phase signal Sinv. As a result, as shown in Figure 7, the frequency of the signal with feedback amplitude Vcnt input to the first adjustment switch 91 is adjusted to match the frequency of the modulated signal S. Also, the phase of the signal with feedback amplitude Vcnt input to the first adjustment switch 91 is adjusted to be the opposite phase to the phase of the modulated signal S, i.e., the phase of the inverse phase signal Sinv. The signal with feedback amplitude Vcnt, whose frequency and phase have been adjusted, is output to the first capacitor 61 and the second capacitor 62, as shown in Figure 2.

[0066] As described above, the capacitive sensor detection circuit 20 of the first embodiment is configured as described. Next, the operation of the capacitive sensor detection circuit 20 will be explained.

[0067] The signal generation unit 22 outputs a modulated signal S having input amplitude Vm, frequency, and phase to the movable electrode 100 and the control unit 70. Furthermore, the signal generation unit 22 outputs an inverse phase signal Sinv to the control unit 70. At the same time, the movable electrode 100 is displaced toward the first electrode 121. At this time, the first capacitance Cs1 increases. Furthermore, the second capacitance Cs2 decreases. Let ΔCs be the amount of change between the first capacitance Cs1 and the second capacitance Cs2. At this time, the first capacitance Cs1 is expressed as shown in the following relation (1-1). The second capacitance Cs2 is expressed as shown in the following relation (1-2). Note that Cs0 is the first capacitance Cs1 and the second capacitance Cs2 when the movable electrode 100 is not displaced, as described above.

[0068] Cs1 = Cs0 + ΔCs ... (1-1) Cs² = Cs₀ - ΔCs ···(1-2)

[0069] Furthermore, the first electrode 121 outputs a signal corresponding to ΔCs to the first input terminal 241. As a result, the signal from the first electrode 121 is input to the first input terminal 241. Also, the second electrode 122 outputs a signal corresponding to ΔCs to the second input terminal 242. As a result, the signal from the second electrode 122 is input to the second input terminal 242. At this time, the first output terminal 251 outputs a first output signal Vout1 corresponding to the first input signal Vin1 and the second input signal Vin2 to the calculation unit 50. The second output terminal 252 outputs a second output signal Vout2 corresponding to the first input signal Vin1 and the second input signal Vin2 to the calculation unit 50.

[0070] At this time, the amplitude of the difference between the first output signal Vout1 and the second output signal Vout2 is expressed using the input amplitude Vm, ΔCs, and Cf as shown in the following relation (1-3). Note that Cf is the capacitance of the first feedback capacitor 31 and the second feedback capacitor 32, as described above. Note that Vout1 in the following relation (1-3) is the amplitude of the first output signal Vout1. Note that Vout2 in the following relation (1-3) is the amplitude of the second output signal Vout2.

[0071] Vout1-Vout2=2×Vm×ΔCs / Cf (1-3)

[0072] Therefore, the calculation unit 50 acquires the first output signal Vout1 from the first output terminal 251. Furthermore, the calculation unit 50 acquires the second output signal Vout2 from the second output terminal 252. The calculation unit 50 also calculates ΔCs using the acquired first output signal Vout1 and second output signal Vout2, the preset input amplitudes Vm and Cf, and the above relational equation (1-3). Furthermore, the calculation unit 50 calculates the displacement of the movable electrode 100 from this calculated ΔCs. The calculation unit 50 also calculates the acceleration and pressure of the movable electrode 100 from this calculated displacement of the movable electrode 100. In this way, the calculation unit 50 calculates the acceleration and pressure of a detection target (not shown) that displaces together with the movable electrode 100.

[0073] Here, ΔCe is defined as the absolute value of the difference between Cs0 and the capacitances of the first capacitor Ct1 and the second capacitor Ct2. Also, the amplitude of the signals output from the control unit 70 to the first capacitor 61 and the second capacitor 62 is assumed to be the same as the input amplitude Vm.

[0074] In this case, the amplitude of the first input signal Vin1, whose frequency and phase correspond to the frequency and phase of the modulated signal S, is expressed using the input amplitude Vm, ΔCe, and Cf as shown in the following relation (1-4). The amplitude of the second input signal Vin2, whose frequency and phase correspond to the frequency and phase of the modulated signal S, is expressed using the input amplitude Vm, ΔCe, and Cf as shown in the following relation (1-5). Note that in relation (1-4), Vin1 is the amplitude of the first input signal Vin1. In relation (1-5), Vin2 is the amplitude of the second input signal Vin2.

[0075] Vin1 = Vm × ΔCe × Cf ... (1-4) Vin² = Vm × ΔCe × Cf ... (1-5)

[0076] Furthermore, suppose that the first input signal Vin1, represented by the above relation (1-4), is input to the first input terminal 241. Suppose that the second input signal Vin2, represented by the above relation (1-5), is input to the second input terminal 242. In this case, because the fully differential amplifier 24 includes the output common-mode feedback circuit 260, the first input signal Vin1 and the second input signal Vin2 are in phase. Therefore, the influence that the first input signal Vin1, represented by the above relation (1-4), and the second input signal Vin2, represented by the above relation (1-5), have on the difference between the first output signal Vout1 and the second output signal Vout2, i.e., Vout1-Vout2, is small.

[0077] However, as described above, the capacitive sensor detection circuit 20 includes a first parasitic capacitor 51 and a second parasitic capacitor 52. The capacitance of the first parasitic capacitor 51 is denoted as the first parasitic capacitance Cp1. The capacitance of the second parasitic capacitor 52 is denoted as the second parasitic capacitance Cp2. The absolute value of the difference between the first parasitic capacitance Cp1 and the second parasitic capacitance Cp2 is denoted as ΔCp.

[0078] The amplitude of the common-mode signals of the first input signal Vin1 and the second input signal Vin2 is a value related to Vm × ΔCe / Cf. Furthermore, the amplitude of the difference between the first output signal Vout1 and the second output signal Vout2 is expressed using the input amplitude Vm, ΔCe, Cf, and ΔCp as shown in the following relation (1-6). Note that Vout1 in the following relation (1-6) is the amplitude of the first output signal Vout1. Vout2 in the following relation (1-6) is the amplitude of the second output signal Vout2.

[0079] Vout1-Vout2=Vm×ΔCe / Cf×ΔCp / Cf (1-6)

[0080] Therefore, the amplitude of the difference between the first output signal Vout1 and the second output signal Vout2 includes the value expressed on the right side of the above relation (1-6). Thus, the amplitude of the difference between the first output signal Vout1 and the second output signal Vout2, as expressed by the above relation (1-6), becomes the offset component of the detected values ​​such as acceleration and pressure calculated from the above relation (1-3).

[0081] Furthermore, the amplitude of the first input signal Vin1, whose frequency and phase correspond to the frequency and phase of the modulated signal S, is expressed as shown in the following relation (1-7) using the input amplitude Vm, the feedback amplitude Vcnt, Cs0, Ct0, and Cf. The amplitude of the second input signal Vin2, whose frequency and phase correspond to the frequency and phase of the modulated signal S, is expressed as shown in the following relation (1-8) using the input amplitude Vm, the feedback amplitude Vcnt, Cs0, Ct0, and Cf. Note that Ct0 is the capacitance of the first capacitor 61 and the second capacitor 62, as described above. Note that Vin1 in the following relation (1-7) is the amplitude of the first input signal Vin1. Vin2 in the following relation (1-8) is the amplitude of the second input signal Vin2.

[0082] Vin1=(Vm×Cs0-Vcnt×Ct0) / Cf (1-7) Vin2=(Vm×Cs0-Vcnt×Ct0) / Cf (1-8)

[0083] Therefore, when Vm × Cs0 - Vcnt × Ct0 is zero, the amplitudes of the first input signal Vin1 and the second input signal Vin2, whose frequencies and phases correspond to the frequency and phase of the modulated signal S, become zero. For this reason, even if there is a difference between Cs0 and Ct0, the offset component becomes zero. Thus, even if there is ΔCe, which is the absolute value of the difference between Cs0 and the first capacitor capacitance Ct1 and the second capacitor capacitance Ct2, the offset component becomes zero.

[0084] Therefore, the control unit 70 calculates the feedback amplitude Vcnt that makes Vm × Cs0 - Vcnt × Ct0 zero. For this purpose, the control unit 70 includes, for example, an adder 75, a synchronous detection unit 80, a controller 85, a first adjustment switch 91, and a second adjustment switch 92.

[0085] As described above, the first input terminal 241 is connected to the first electrode 121 and the first capacitor 61. The second input terminal 242 is connected to the second electrode 122 and the second capacitor 62. Therefore, the first input signal Vin1 and the second input signal Vin2 are signals relating to the input amplitude Vm, the feedback amplitude Vcnt, Cs0, and Ct0.

[0086] Therefore, the adder 75 acquires the first input signal Vin1 and the second input signal Vin2. The adder 75 also includes a first voltage follower circuit 751, a second voltage follower circuit 752, and a merging unit 785. As a result, the adder 75 acquires a signal relating to the sum of the first input signal Vin1 and the second input signal Vin2 from the acquired first input signal Vin1 and second input signal Vin2.

[0087] Furthermore, the high-pass filter 790 of the adder 75 removes low-frequency components contained in the signal relating to the sum of the first input signal Vin1 and the second input signal Vin2 acquired by the adder 75. In this way, the high-pass filter 790 removes DC components contained in the signal relating to the sum of the first input signal Vin1 and the second input signal Vin2 acquired by the adder 75.

[0088] The synchronous detection unit 80 demodulates the signal, which is the sum of the first input signal Vin1 and the second input signal Vin2 from which the DC component has been removed by the high-pass filter 790, in accordance with the frequency and phase of the modulated signal S.

[0089] The controller 85 uses the signal relating to the sum of the first input signal Vin1 and the second input signal Vin2, which have been demodulated by the synchronous detection unit 80, and the signal from the reference power supply 795. Based on this, the controller 85 calculates a feedback amplitude Vcnt that makes the amplitude of the signal relating to the sum of the first input signal Vin1 and the second input signal Vin2, which has been demodulated by the synchronous detection unit 80, zero. This calculates a feedback amplitude Vcnt that makes Vm × Cs0 - Vcnt × Ct0 zero. The controller 85 then outputs a signal with this calculated feedback amplitude Vcnt to the first adjustment switch 91.

[0090] Furthermore, the first adjustment switch 91 and the second adjustment switch 92 are switched on and off by the modulated signal S and the inverse phase signal Sinv. As a result, the frequency of the signal with feedback amplitude Vcnt input to the first adjustment switch 91 becomes the frequency of the modulated signal S. Also, the phase of the signal with feedback amplitude Vcnt input to the first adjustment switch 91 becomes the opposite phase to the phase of the modulated signal S, i.e., the phase of the inverse phase signal Sinv. Then, the signal whose amplitude is the feedback amplitude Vcnt, whose frequency is the same as the frequency of the modulated signal S, and whose phase is the opposite phase to the phase of the modulated signal S is output to the first capacitor 61 and the second capacitor 62. As a result, the amplitude of the first input signal Vin1 and the amplitude of the second input signal Vin2, whose frequency and phase correspond to the frequency and phase of the modulated signal S, approach zero. Therefore, the offset component becomes zero.

[0091] As described above, the capacitive sensor detection circuit 20 operates. Next, we will explain how the output signal in the capacitive sensor detection circuit 20, in response to changes in capacitance, becomes a continuous signal with respect to time.

[0092] Here, as described in Non-Patent Document 1, a detection circuit for a capacitive sensor that detects acceleration from a change in capacitance that changes due to electrode displacement is known. Also, as described in U.S. Patent No. 1,0591,318, a detection circuit for a capacitive sensor that detects a change in capacitance that changes due to electrode displacement is known. In detection circuits such as those described in Non-Patent Document 1 and U.S. Patent No. 1,0591,318, the input voltage of the full differential amplifier is reset. However, while the input voltage of the full differential amplifier is reset, the signal output from the full differential amplifier does not include a signal corresponding to acceleration, and therefore becomes a time-discontinuous signal.

[0093] In contrast, the capacitive sensor detection circuit 20 of this embodiment includes a control unit 70. The control unit 70 acquires a first input signal Vin1 and a second input signal Vin2, which are signals relating to the input amplitude Vm, Cs0, and Ct0. Furthermore, the control unit 70 outputs a signal having a feedback amplitude Vcnt to the first capacitor 61 and the second capacitor 62. The feedback amplitude Vcnt brings the amplitudes of the first input signal Vin1 and the second input signal Vin2, whose frequency and phase correspond to the frequency and phase of the modulated signal S, closer to zero. In addition, the frequency of the signal having the feedback amplitude Vcnt is the same as or corresponding to the frequency of the modulated signal S. Furthermore, the phase of the signal having the feedback amplitude Vcnt is the opposite phase to the phase of the modulated signal S.

[0094] As a result, the amplitudes of the first input signal Vin1 and the second input signal Vin2, whose frequencies and phases correspond to the frequency and phase of the modulated signal S, continuously approach zero. Therefore, there is no need to provide a reset period for the first input signal Vin1 and the second input signal Vin2. Consequently, the output signal from the fully differential amplifier 24, which corresponds to the changes in the first capacitance Cs1 and the second capacitance Cs2, becomes a continuous signal with respect to time.

[0095] Furthermore, in detection circuits such as those described in Non-Patent Document 1 and U.S. Patent No. 10591318, noise is retained in each capacitor when it is reset. As a result, the detection accuracy of capacitance changes is reduced in detection circuits such as those described in Non-Patent Document 1 and U.S. Patent No. 10591318.

[0096] In contrast, in the capacitive sensor detection circuit 20 of this embodiment, the output signals corresponding to changes in the first capacitance Cs1 and the second capacitance Cs2 become continuous signals with respect to time, thus suppressing noise held in each capacitor. Therefore, the decrease in detection accuracy of changes in capacitance is suppressed.

[0097] Furthermore, the capacitive sensor detection circuit 20 of the first embodiment also provides the following effects.

[0098] [1-1] The control unit 70 includes an adder 75, a synchronous detection unit 80, and a controller 85. This makes it easier for the control unit 70 to calculate the feedback amplitude Vcnt.

[0099] [1-2] The control unit 70 has a high-pass filter 790. The high-pass filter 790 removes the DC component contained in the signal relating to the sum of the first input signal Vin1 and the second input signal Vin2.

[0100] The high-pass filter 790 makes it easier to adjust the gain of the controller 85. As a result, oscillation of the feedback amplitude Vcnt in the controller 85 is suppressed.

[0101] [1-3] The summing unit 75 includes a first voltage follower circuit 751, a first filter capacitor 781, a second voltage follower circuit 752, a second filter capacitor 782, and a merging unit 785.

[0102] The first voltage follower circuit 751 prevents the current that should flow from the first electrode 121 to the first input terminal 241 from flowing to the control unit 70. Furthermore, the second voltage follower circuit 752 prevents the current that should flow from the second electrode 122 to the second input terminal 242 from flowing to the control unit 70. Therefore, interference between the control unit 70 and the operation of the fully differential amplifier 24 is prevented.

[0103] [1-4] The synchronous detection unit 80 includes a first switch 801, a second switch 802, a third switch 803, and a fourth switch 804. The controller 85 includes a controller transconductance amplifier 850 and a controller capacitor 852.

[0104] This makes it easier to demodulate the signal, which is the sum of the first input signal Vin1 and the second input signal Vin2, in accordance with the frequency and phase of the modulated signal S. It also makes it easier to calculate the feedback amplitude Vcnt.

[0105] (Second Embodiment) In the second embodiment, the configuration of the synchronous detection unit 80 and the controller 85 differs from that of the first embodiment. Otherwise, it is the same as the first embodiment.

[0106] Specifically, as shown in Figure 8, the synchronous detection unit 80 includes the first switch 801 and the second switch 802, but does not include the third switch 803 and the fourth switch 804.

[0107] Furthermore, one end of the first switch 801 is connected to the merging section 785. In addition, the first switch 801 is switched on and off in response to the inverse phase signal Sinv. Furthermore, one end of the second switch 802 is connected to the other end of the filter resistor 787 and the positive terminal of the reference power supply 795. Furthermore, the second switch 802 is switched on and off in response to the modulation signal S.

[0108] Therefore, the first switch 801 and the second switch 802 are switched on and off by the modulated signal S and the inverse phase signal Sinv. As a result, demodulation corresponding to the frequency and phase of the modulated signal S is performed on the signal at the merging section 785. Consequently, demodulation corresponding to the frequency and phase of the modulated signal S is performed on the signal relating to the sum of the first input signal Vin1 and the second input signal Vin2.

[0109] The controller 85 includes a controller operational amplifier 854 instead of a controller transconductance amplifier 850. In addition, the controller 85 includes a controller resistor 856 in addition to a controller capacitor 852. The non-inverting input terminal of the controller operational amplifier 854 is connected to one end of the second switch 802, the other end of the filter resistor 787, and the positive terminal of the reference power supply 795. The inverting input terminal of the controller operational amplifier 854 is connected via the controller resistor 856 to the other end of the first switch 801 and the other end of the second switch 802. Therefore, the controller operational amplifier 854 compares the signal relating to the sum of the first input signal Vin1 and the second input signal Vin2, which have been demodulated by the synchronous detection unit 80, with the signal from the reference power supply 795.

[0110] Furthermore, one end of the controller capacitor 852 is connected to the inverting input terminal of the controller operational amplifier 854. The other end of the controller capacitor 852 is connected to the output terminal of the controller operational amplifier 854. Therefore, the controller 85 is an integrator with capacitor feedback applied by the controller operational amplifier 854 and the controller capacitor 852.

[0111] Furthermore, the controller 85 uses the signal relating to the sum of the first input signal Vin1 and the second input signal Vin2, which have been demodulated by the synchronous detection unit 80, the signal from the reference power supply 795, the controller operational amplifier 854, the controller capacitor 852, and the controller resistor 856. Using these, the controller 85 calculates a feedback amplitude Vcnt that makes the amplitude of the signal relating to the sum of the first input signal Vin1 and the second input signal Vin2, which have been demodulated by the synchronous detection unit 80, zero. The controller 85 then outputs this calculated feedback amplitude Vcnt to the first adjustment switch 91.

[0112] Furthermore, the first adjustment switch 91 and the second adjustment switch 92 are turned on and off by the modulated signal S and the inverse phase signal Sinv. The frequency of the signal with feedback amplitude Vcnt input to the first adjustment switch 91 is the frequency of the modulated signal S. In addition, the phase of the signal with feedback amplitude Vcnt input to the first adjustment switch 91 is the opposite phase to the phase of the modulated signal S, i.e., the phase of the inverse phase signal Sinv. Then, a signal whose amplitude is the feedback amplitude Vcnt, whose frequency is the same as the frequency of the modulated signal S, and whose phase is the opposite phase to the phase of the modulated signal S is output to the first capacitor 61 and the second capacitor 62. As a result, the amplitude of the first input signal Vin1 and the amplitude of the second input signal Vin2, whose frequency and phase correspond to the frequency and phase of the modulated signal S, approach zero. Therefore, the offset component becomes zero.

[0113] As described above, the capacitive sensor detection circuit 20 of the second embodiment is configured as described above. This second embodiment also provides the same effects as the first embodiment.

[0114] (Third embodiment) In the third embodiment, as shown in Figure 9, the capacitive sensor detection circuit 20 further includes a first adjustment capacitor 611 and a second adjustment capacitor 622. Otherwise, it is the same as in the first embodiment.

[0115] One end of the first adjustment capacitor 611 is connected between the first electrode 121 and the first input terminal 241. The other end of the first adjustment capacitor 611 is connected to the signal generation unit 22.

[0116] One end of the second adjustment capacitor 622 is connected between the second electrode 122 and the second input terminal 242. The other end of the second adjustment capacitor 622 is connected to the signal generation unit 22.

[0117] Furthermore, the signal generation unit 22 outputs an inverted phase signal Sinv to the first adjustment capacitor 611 and the second adjustment capacitor 622.

[0118] As described above, the capacitive sensor detection circuit 20 of the third embodiment is configured. This third embodiment also provides the same effects as the first embodiment. Furthermore, the third embodiment also provides the effects described below.

[0119] [2] The capacitive sensor detection circuit 20 further comprises a first adjustment capacitor 611 and a second adjustment capacitor 622. The signal generation unit 22 outputs an inverse phase signal Sinv to the first adjustment capacitor 611 and the second adjustment capacitor 622.

[0120] The first adjustment capacitor 611 adjusts the current between the first electrode 121 and the first input terminal 241. This suppresses the increase in current flowing from the control unit 70 to the first capacitor 61 when a signal with feedback amplitude Vcnt is output from the control unit 70 to the first capacitor 61. Similarly, the second adjustment capacitor 622 adjusts the current between the second electrode 122 and the second input terminal 242. Therefore, when a signal with feedback amplitude Vcnt is output from the control unit 70 to the first capacitor 61, the increase in current flowing from the control unit 70 to the first capacitor 61 is suppressed. Consequently, the current consumption of the control unit 70 is suppressed.

[0121] (Fourth Embodiment) In the fourth embodiment, the configuration of the fully differential amplifier 24 and the processing of the control unit 70 differ from those of the first embodiment. Otherwise, it is the same as the first embodiment.

[0122] The fully differential amplifier 24 includes an input common-mode feedback circuit 270, as shown in Figure 10, instead of the output common-mode feedback circuit 260. Therefore, the voltage is controlled to be half of the voltage related to the sum of the first input signal Vin1 and the second input signal Vin2, i.e., (Vin1 + Vin2) / 2, which is a predetermined voltage. This predetermined voltage is determined through experiments, simulations, etc.

[0123] Since the fully differential amplifier 24 includes an input common-mode feedback circuit 270, in the fourth embodiment, unlike the first embodiment, the first input signal Vin1, whose frequency and phase correspond to the frequency and phase of the modulated signal S, is not expressed as shown in relation (1-7) above. Also, the second input signal Vin2, whose frequency and phase correspond to the frequency and phase of the modulated signal S, is not expressed as shown in relation (1-8) above.

[0124] In contrast, the first output signal Vout1, whose frequency and phase correspond to the frequency and phase of the modulated signal S, is expressed using the input amplitude Vm, the feedback amplitude Vcnt, Cs0, Ct0, and Cf as shown in the following relational equation (2-1). Furthermore, the second output signal Vout2, whose frequency and phase correspond to the frequency and phase of the modulated signal S, is expressed using the input amplitude Vm, the feedback amplitude Vcnt, Cs0, Ct0, and Cf as shown in the following relational equation (2-2).

[0125] Vout1=(Vm×Cs0-Vcnt×Ct0) / Cf...(2-1) Vout2=(Vm×Cs0-Vcnt×Ct0) / Cf (2-2)

[0126] Therefore, when Vm × Cs0 - Vcnt × Ct0 is zero, the first output signal Vout1 and the second output signal Vout2, whose frequencies and phases correspond to the frequency and phase of the modulated signal S, become zero, and thus the offset component becomes zero.

[0127] Therefore, the control unit 70 calculates Vcnt so that Vm × Cs0 - Vcnt × Ct0 becomes zero. For this purpose, the control unit 70 includes, for example, an adder 75, a synchronous detection unit 80, a controller 85, a first adjustment switch 91, and a second adjustment switch 92, as shown in Figures 11 and 12.

[0128] As described above, the first input terminal 241 is connected to the first electrode 121 and the first capacitor 61. The second input terminal 242 is connected to the second electrode 122 and the second capacitor 62. Therefore, the first input signal Vin1 and the second input signal Vin2 are signals relating to the input amplitude Vm, the feedback amplitude Vcnt, Cs0, and Ct0. The first output terminal 251 outputs a signal corresponding to the first input signal Vin1 and the second input signal Vin2. The second output terminal 252 outputs a signal corresponding to the first input signal Vin1 and the second input signal Vin2. Therefore, the first output signal Vout1 and the second output signal Vout2 are signals relating to the input amplitude Vm, the feedback amplitude Vcnt, Cs0, and Ct0.

[0129] Therefore, the summer 75 acquires the first output signal Vout1 and the second output signal Vout2. Furthermore, the summer 75 includes a first voltage follower circuit 751, a second voltage follower circuit 752, and a merging unit 785. As a result, the summer 75 acquires a signal relating to the sum of the first output signal Vout1 and the second output signal Vout2 from the acquired first output signal Vout1 and second output signal Vout2.

[0130] Furthermore, the high-pass filter 790 of the summer 75 removes low-frequency components contained in the signal relating to the sum of the first output signal Vout1 and the second output signal Vout2 acquired by the summer 75. In this way, the high-pass filter 790 removes DC components contained in the signal relating to the sum of the first output signal Vout1 and the second output signal Vout2 acquired by the summer 75.

[0131] The synchronous detection unit 80 demodulates the signal, which is the sum of the first output signal Vout1 and the second output signal Vout2 from which the DC component has been removed by the high-pass filter 790, in accordance with the frequency and phase of the modulated signal S.

[0132] The controller 85 uses the signal relating to the sum of the first output signal Vout1 and the second output signal Vout2 demodulated by the synchronous detection unit 80, and the signal from the reference power supply 795. Based on this, the controller 85 calculates a feedback amplitude Vcnt that makes the amplitude of the signal relating to the sum of the first output signal Vout1 and the second output signal Vout2 demodulated by the synchronous detection unit 80 zero. This calculates the feedback amplitude Vcnt that makes Vm × Cs0 - Vcnt × Ct0 zero. The controller 85 then outputs the signal with this calculated feedback amplitude Vcnt to the first adjustment switch 91.

[0133] Furthermore, the first adjustment switch 91 and the second adjustment switch 92 are switched on and off by the modulated signal S and the inverse phase signal Sinv. As a result, the frequency of the signal with feedback amplitude Vcnt input to the first adjustment switch 91 becomes the frequency of the modulated signal S. Also, the phase of the signal with feedback amplitude Vcnt input to the first adjustment switch 91 becomes the opposite phase to the phase of the modulated signal S, i.e., the phase of the inverse phase signal Sinv. Then, the signal whose amplitude is the feedback amplitude Vcnt, whose frequency is the same as the frequency of the modulated signal S, and whose phase is the opposite phase to the phase of the modulated signal S is output to the first capacitor 61 and the second capacitor 62. As a result, the amplitude of the first output signal Vout1 and the amplitude of the second output signal Vout2, whose frequency and phase correspond to the frequency and phase of the modulated signal S, approach zero. Therefore, the offset component becomes zero.

[0134] As described above, the capacitive sensor detection circuit 20 of the fourth embodiment is configured, and the control unit 70 performs the processing. This fourth embodiment also provides the same effects as the first embodiment.

[0135] (Fifth embodiment) In the fifth embodiment, the configuration of the synchronous detection unit 80 and the controller 85 differs from that of the fourth embodiment. Otherwise, it is the same as the fourth embodiment.

[0136] The fifth embodiment is a combination of the second and fourth embodiments. Specifically, as shown in Figure 13, the synchronous detection unit 80 includes the first switch 801 and the second switch 802, but does not include the third switch 803 and the fourth switch 804.

[0137] Furthermore, one end of the first switch 801 is connected to the merging section 785. In addition, the first switch 801 is switched on and off in response to the inverse phase signal Sinv. Furthermore, one end of the second switch 802 is connected to the other end of the filter resistor 787 and the positive terminal of the reference power supply 795. Furthermore, the second switch 802 is switched on and off in response to the modulation signal S.

[0138] Therefore, the first switch 801 and the second switch 802 are switched on and off by the modulated signal S and the inverse phase signal Sinv. As a result, demodulation corresponding to the frequency and phase of the modulated signal S is performed on the signal at the merging section 785. Consequently, demodulation corresponding to the frequency and phase of the modulated signal S is performed on the signal relating to the sum of the first output signal Vout1 and the second output signal Vout2.

[0139] The controller 85 includes a controller operational amplifier 854 instead of a controller transconductance amplifier 850. In addition, the controller 85 includes a controller resistor 856 in addition to a controller capacitor 852. The non-inverting input terminal of the controller operational amplifier 854 is connected to one end of the second switch 802, the other end of the filter resistor 787, and the positive terminal of the reference power supply 795. The inverting input terminal of the controller operational amplifier 854 is connected via the controller resistor 856 to the other end of the first switch 801 and the other end of the second switch 802. Therefore, the controller operational amplifier 854 compares the signal relating to the sum of the first output signal Vout1 and the second output signal Vout2, which have been demodulated by the synchronous detection unit 80, with the signal from the reference power supply 795.

[0140] Furthermore, one end of the controller capacitor 852 is connected to the inverting input terminal of the controller operational amplifier 854. The other end of the controller capacitor 852 is connected to the output terminal of the controller operational amplifier 854. Therefore, the controller 85 is an integrator with capacitor feedback applied by the controller operational amplifier 854 and the controller capacitor 852.

[0141] Furthermore, the controller 85 uses the signal relating to the sum of the first output signal Vout1 and the second output signal Vout2, which have been demodulated by the synchronous detection unit 80, the signal from the reference power supply 795, the controller operational amplifier 854, the controller capacitor 852, and the controller resistor 856. Using these, the controller 85 calculates a feedback amplitude Vcnt that makes the amplitude of the signal relating to the sum of the first output signal Vout1 and the second output signal Vout2, which have been demodulated by the synchronous detection unit 80, zero. The controller 85 then outputs this calculated feedback amplitude Vcnt to the first adjustment switch 91.

[0142] Furthermore, the first adjustment switch 91 and the second adjustment switch 92 are turned on and off by the modulated signal S and the inverse phase signal Sinv. The frequency of the signal with feedback amplitude Vcnt input to the first adjustment switch 91 is the frequency of the modulated signal S. In addition, the phase of the signal with feedback amplitude Vcnt input to the first adjustment switch 91 is the opposite phase to the phase of the modulated signal S, i.e., the phase of the inverse phase signal Sinv. Then, a signal whose amplitude is the feedback amplitude Vcnt, whose frequency is the same as the frequency of the modulated signal S, and whose phase is the opposite phase to the phase of the modulated signal S is output to the first capacitor 61 and the second capacitor 62. As a result, the amplitude of the first output signal Vout1 and the amplitude of the second output signal Vout2, whose frequency and phase correspond to the frequency and phase of the modulated signal S, approach zero. Therefore, the offset component becomes zero.

[0143] As described above, the capacitive sensor detection circuit 20 of the fifth embodiment is configured as described above. This fifth embodiment also provides the same effects as the fourth embodiment.

[0144] (Sixth Embodiment) In the sixth embodiment, as shown in Figure 14, the capacitive sensor detection circuit 20 further includes a first adjustment capacitor 611 and a second adjustment capacitor 622. Otherwise, it is the same as in the fourth embodiment.

[0145] The sixth embodiment is a combination of the third and fourth embodiments. Specifically, one end of the first adjustment capacitor 611 is connected between the first electrode 121 and the first input terminal 241. The other end of the first adjustment capacitor 611 is connected to the signal generation unit 22.

[0146] One end of the second adjustment capacitor 622 is connected between the second electrode 122 and the second input terminal 242. The other end of the second adjustment capacitor 622 is connected to the signal generation unit 22. The signal generation unit 22 also outputs an inverted phase signal Sinv to the first adjustment capacitor 611 and the second adjustment capacitor 622.

[0147] As described above, the capacitive sensor detection circuit 20 of the sixth embodiment is configured. This sixth embodiment also provides the same effects as the fourth embodiment. Furthermore, the sixth embodiment provides the same effects as those described in [2] above for the third embodiment.

[0148] (Other embodiments) This disclosure is not limited to the embodiments described above, and modifications can be made to these embodiments as appropriate. Furthermore, it goes without saying that, in each of the embodiments described above, the elements constituting the embodiment are not necessarily essential, except in cases where they are explicitly stated to be particularly essential or where they are clearly considered essential in principle.

[0149] The control unit and method described herein may be implemented by a dedicated computer provided by configuring a processor and memory programmed to perform one or more functions embodied by a computer program. Alternatively, the control unit and method described herein may be implemented by a dedicated computer provided by configuring a processor by one or more dedicated hardware logic circuits. Alternatively, the control unit and method described herein may be implemented by one or more dedicated computers configured by a combination of a processor and memory programmed to perform one or more functions and a processor configured by one or more hardware logic circuits. Furthermore, the computer program may be stored as instructions executed by the computer on a computer-readable non-transitional tangible recording medium.

[0150] In each of the above embodiments, the number of transistors in the first voltage follower circuit 751 is one. However, the number of transistors in the first voltage follower circuit 751 is not limited to one, and may be two or more. Similarly, the number of transistors in the second voltage follower circuit 752 is one. However, the number of transistors in the second voltage follower circuit 752 is not limited to one, and may be two or more.

[0151] In each of the above embodiments, the transistors of the first voltage follower circuit 751 and the second voltage follower circuit 752 are MOSFETs. However, the transistors of the first voltage follower circuit 751 and the second voltage follower circuit 752 are not limited to MOSFETs, and may be, for example, bipolar transistors.

[0152] In each of the above embodiments, the first capacitance Cs1 when the movable electrode 100 is not displaced is set to be the same as the second capacitance Cs2 when the movable electrode 100 is not displaced, and is set to Cs0. However, the first capacitance Cs1 when the movable electrode 100 is not displaced is not limited to being the same as the second capacitance Cs2 when the movable electrode 100 is not displaced. The first capacitance Cs1 when the movable electrode 100 is not displaced may be different from the second capacitance Cs2 when the movable electrode 100 is not displaced.

[0153] In each of the embodiments described above, the first feedback capacitance Cf1 is the same as the second feedback capacitance Cf2 and is denoted as Cf. However, the first feedback capacitance Cf1 is not limited to being the same as the second feedback capacitance Cf2. The first feedback capacitance Cf1 may be different from the second feedback capacitance Cf2.

[0154] In each of the embodiments described above, the first resistor Rf1 is the same as the second resistor Rf2 and is denoted as Rf. However, the first resistor Rf1 is not limited to being the same as the second resistor Rf2. The first resistor Rf1 may be different from the second resistor Rf2.

[0155] In each of the above embodiments, the high-pass filter 790 includes a filter resistor 787. In contrast, the high-pass filter 790 may include a switched capacitor instead of the filter resistor 787.

[0156] In each of the above embodiments, the first adjustment switch 91 is turned on and off in accordance with the inverse phase signal Sinv. The second adjustment switch 92 is turned on and off in accordance with the modulation signal S. For these, the signal that turns the first adjustment switch 91 on and off is a signal whose frequency is the same as the frequency of the modulation signal S and the inverse phase signal Sinv, and whose phase is the same as the phase of the inverse phase signal Sinv. The signal that turns the second adjustment switch 92 on and off is a signal whose frequency is the same as the frequency of the modulation signal S and the inverse phase signal Sinv, and whose phase is the same as the phase of the modulation signal S.

[0157] In the first, third, fourth, and sixth embodiments described above, the first switch 801 is switched on and off in accordance with the modulated signal S. The second switch 802 is switched on and off in accordance with the inverse phase signal Sinv. The third switch 803 is switched on and off in accordance with the modulated signal S. The fourth switch 804 is switched on and off in accordance with the inverse phase signal Sinv. For these, the signal that switches the first switch 801 on and off is a signal whose frequency is the same as the frequency of the modulated signal S and the inverse phase signal Sinv, and whose phase is the same as the phase of the modulated signal S. The signal that switches the second switch 802 on and off is a signal whose frequency is the same as the frequency of the modulated signal S and the inverse phase signal Sinv, and whose phase is the same as the phase of the inverse phase signal Sinv. The signal that switches the third switch 803 on and off is a signal whose frequency is the same as the frequency of the modulated signal S and the inverse phase signal Sinv, and whose phase is the same as the phase of the modulated signal S and the inverse phase signal Sinv. The signal that turns the fourth switch 804 on or off is a signal whose frequency is the same as the frequency of the modulated signal S and the inverse signal Sinv, and whose phase is the same as the phase of the inverse signal Sinv.

[0158] In the second and fifth embodiments described above, the first switch 801 is switched on and off in response to the inverse phase signal Sinv. The second switch 802 is switched on and off in response to the modulated signal S. For these, the signal that switches the first switch 801 on and off is a signal whose frequency is the same as the frequency of the modulated signal S and the inverse phase signal Sinv, and whose phase is the same as the phase of the inverse phase signal Sinv. The signal that switches the second switch 802 on and off is a signal whose frequency is the same as the frequency of the modulated signal S and the inverse phase signal Sinv, and whose phase is the same as the phase of the modulated signal S.

[0159] In the second and fifth embodiments described above, the controller 85 includes a controller resistor 856. In contrast, the controller 85 may include a switched capacitor instead of the controller resistor 856.

[0160] The above embodiments may be combined as appropriate.

[0161] (Perspective of this disclosure) [Perspective 1] A capacitive sensor detection circuit used in a sensor element (10) comprising a displaceable movable electrode (100), a first electrode (121) that outputs a signal corresponding to the change in a first capacitance (Cs1) between the movable electrode which changes due to the displacement of the movable electrode, and a second electrode (122) that outputs a signal corresponding to the change in a second capacitance (Cs2) between the movable electrode which changes due to the displacement of the movable electrode, wherein A signal generation unit (22) outputs a modulated signal (S), which is a signal having input amplitude (Vm), frequency, and phase, to the movable electrode. A fully differential amplifier (24) having a first input terminal (241) connected to the first electrode, a second input terminal (242) connected to the second electrode, a first output terminal (251) that outputs a signal corresponding to a first input signal (Vin1) input to the first input terminal and a second input signal (Vin2) input to the second input terminal, and a second output terminal (252) that outputs a signal corresponding to the first input signal and the second input signal, A first feedback capacitor (31) connected to the first input terminal and the first output terminal, A second feedback capacitor (32) connected to the second input terminal and the second output terminal, A calculation unit (50) calculates a value relating to the displacement of the movable electrode based on a first output signal (Vout1), which is a signal output from the first output terminal, and a second output signal (Vout2), which is a signal output from the second output terminal. A first capacitor (61) is connected between the first electrode and the first input terminal, A second capacitor (62) is connected between the second electrode and the second input terminal, A control unit (70) acquires the first input signal and the second input signal and outputs a signal to the first capacitor and the second capacitor that has a feedback amplitude (Vcnt) that brings the amplitudes of the first input signal and the second input signal closer to zero, wherein the frequency and phase of the signal correspond to the frequency and phase of the modulated signal, and the signal has a frequency that corresponds to the frequency of the modulated signal and a phase that is opposite to the phase of the modulated signal. A capacitive sensor detection circuit equipped with the following features. [Perspective 2] The control unit, An adder (75) that acquires a signal relating to the sum of the first input signal and the second input signal, A synchronous detection unit (80) performs demodulation of a signal relating to the sum of the first input signal and the second input signal, corresponding to the frequency and phase of the modulated signal. A controller (85) calculates the feedback amplitude based on a signal relating to the sum of the first input signal and the second input signal demodulated by the synchronous detection unit and a signal from the reference power supply (795), A capacitive sensor detection circuit according to viewpoint 1, having the following characteristics. [Perspective 3] The control unit has a high-pass filter (790) that removes the DC component included in the signal relating to the sum of the first input signal and the second input signal. The capacitive sensor detection circuit according to viewpoint 2, wherein the synchronous detection unit demodulates a signal relating to the sum of the first input signal and the second input signal from which the DC component has been removed by the high-pass filter. [Perspective 4] The aforementioned addition unit is A first voltage follower circuit (751) acquires the first input signal and outputs a signal corresponding to the first input signal, The first filter capacitor (781) is connected to the output terminal of the first voltage follower circuit, A second voltage follower circuit (752) acquires the second input signal and outputs a signal corresponding to the second input signal, The second filter capacitor (782) is connected to the output terminal of the second voltage follower circuit, A merging section (785) is connected to the first filter capacitor and the second filter capacitor, so that the signal is the sum of the first input signal and the second input signal, A capacitive sensor detection circuit according to perspective 2 or 3, including the aspect of a capacitive sensor detection circuit. [Perspective 5] The aforementioned synchronous detection unit, A first switch (801) that turns on or off in response to a signal whose frequency is the same as the frequency of the modulated signal and whose phase is the same as the phase of the modulated signal, A second switch (802) turns on and off in response to a signal whose frequency is the same as the frequency of the modulated signal, and whose phase is opposite to the phase of the modulated signal, A third switch (803) that turns on or off in response to a signal whose frequency is the same as the frequency of the modulated signal and whose phase is the same as the phase of the modulated signal, A fourth switch (804) that turns on or off in response to a signal whose frequency is the same as the frequency of the modulated signal and whose phase is opposite to the phase of the modulated signal, Includes, The controller is, A transconductance amplifier (850) is provided, in which the non-inverting input terminal is connected to the second switch and the third switch, and the inverting input terminal is connected to the first switch, the fourth switch and the reference power supply, The capacitor (852) connected to the output terminal and ground of the transconductance amplifier, A capacitive sensor detection circuit as described in any one of perspectives 2 to 4, including the following: [Perspective 6] The aforementioned synchronous detection unit, A first switch (801) that turns on or off in response to a signal whose frequency is the same as the frequency of the modulated signal and whose phase is opposite to the phase of the modulated signal, A second switch (802) that turns on or off in response to a signal whose frequency is the same as the frequency of the modulated signal and whose phase is the same as the phase of the modulated signal, Includes, The controller is, The resistor (856) connected to the first switch and the second switch, An operational amplifier (854) whose inverting input terminal is connected to the resistor and whose non-inverting input terminal is connected to the reference power supply, The capacitor (852) connected to the inverting input terminal and output terminal of the aforementioned operational amplifier, A capacitive sensor detection circuit as described in any one of perspectives 2 to 4, including the following: [perspective 7] The aforementioned capacitive sensor detection circuit is A first adjustment capacitor (611) is connected between the first electrode and the first input terminal, A second adjustment capacitor (622) is connected between the second electrode and the second input terminal, Equipped with, The capacitive sensor detection circuit according to any one of views 1 to 6, wherein the signal generation unit outputs a signal to the first adjustment capacitor and the second adjustment capacitor, the signal having an amplitude equal to the input amplitude, a frequency equal to the frequency of the modulated signal, and a phase opposite to the phase of the modulated signal. [Perspective 8] The fully differential amplifier is a capacitive sensor detection circuit according to any one of views 1 to 7, which includes an output common-mode feedback circuit (260) that brings half of the voltage relating to the sum of the first output signal and the second output signal closer to a predetermined voltage. [Perspective 9] A capacitive sensor detection circuit used in a sensor element (10) comprising a displaceable movable electrode (100), a first electrode (121) that outputs a signal corresponding to the change in a first capacitance (Cs1) between the movable electrode which changes due to the displacement of the movable electrode, and a second electrode (122) that outputs a signal corresponding to the change in a second capacitance (Cs2) between the movable electrode which changes due to the displacement of the movable electrode, wherein A signal generation unit (22) outputs a modulated signal (S), which is a signal having input amplitude (Vm), frequency, and phase, to the movable electrode. A fully differential amplifier (24) having a first input terminal (241) connected to the first electrode, a second input terminal (242) connected to the second electrode, a first output terminal (251) that outputs a signal corresponding to a first input signal (Vin1) input to the first input terminal and a second input signal (Vin2) input to the second input terminal, and a second output terminal (252) that outputs a signal corresponding to the first input signal and the second input signal, A first feedback capacitor (31) connected to the first input terminal and the first output terminal, A second feedback capacitor (32) connected to the second input terminal and the second output terminal, A calculation unit (50) calculates a value relating to the displacement of the movable electrode based on a first output signal (Vout1), which is a signal output from the first output terminal, and a second output signal (Vout2), which is a signal output from the second output terminal. A first capacitor (61) is connected between the first electrode and the first input terminal, A second capacitor (62) is connected between the second electrode and the second input terminal, A control unit (70) acquires the first output signal and the second output signal and outputs a signal to the first capacitor and the second capacitor, which has a feedback amplitude (Vcnt) that brings the amplitudes of the first output signal and the second output signal, whose frequency and phase correspond to the frequency and phase of the modulated signal, close to zero, wherein the frequency of the signal corresponds to the frequency of the modulated signal and the phase is opposite to the phase of the modulated signal. A capacitive sensor detection circuit equipped with the following features. [Perspective 10] The control unit, An adder (75) that acquires a signal relating to the sum of the first output signal and the second output signal, A synchronous detection unit (80) performs demodulation of a signal relating to the sum of the first output signal and the second output signal, corresponding to the frequency and phase of the modulated signal. A controller (85) calculates the feedback amplitude based on a signal relating to the sum of the first output signal and the second output signal demodulated by the synchronous detection unit, and a signal from the reference power supply (795). A capacitive sensor detection circuit according to viewpoint 9, having the characteristics described therein. [Perspective 11] The control unit has a high-pass filter (790) that removes the DC component included in the signal relating to the sum of the first output signal and the second output signal. The capacitive sensor detection circuit according to viewpoint 10, wherein the synchronous detection unit demodulates a signal relating to the sum of the first output signal and the second output signal from which the DC component has been removed by the high-pass filter. [Perspective 12] The aforementioned addition unit is A first voltage follower circuit (751) acquires the first output signal and outputs a signal corresponding to the first output signal, The first filter capacitor (781) is connected to the output terminal of the first voltage follower circuit, A second voltage follower circuit (752) acquires the second output signal and outputs a signal corresponding to the second output signal, The second filter capacitor (782) is connected to the output terminal of the second voltage follower circuit, A merging section (785) is connected to the first filter capacitor and the second filter capacitor, so that the signal is the sum of the first output signal and the second output signal, A capacitive sensor detection circuit as described in view 10 or 11, including the aspect. [Perspective 13] The aforementioned synchronous detection unit, A first switch (801) that turns on or off in response to a signal whose frequency is the same as the frequency of the modulated signal and whose phase is the same as the phase of the modulated signal, A second switch (802) turns on and off in response to a signal whose frequency is the same as the frequency of the modulated signal, and whose phase is opposite to the phase of the modulated signal, A third switch (803) that turns on or off in response to a signal whose frequency is the same as the frequency of the modulated signal and whose phase is the same as the phase of the modulated signal, A fourth switch (804) that turns on or off in response to a signal whose frequency is the same as the frequency of the modulated signal and whose phase is opposite to the phase of the modulated signal, Includes, The controller is, A transconductance amplifier (850) is provided, in which the non-inverting input terminal is connected to the second switch and the third switch, and the inverting input terminal is connected to the first switch, the fourth switch and the reference power supply, The capacitor (852) connected to the output terminal and ground of the transconductance amplifier, A capacitive sensor detection circuit as described in any one of views 10 to 12, including the following: [Perspective 14] The aforementioned synchronous detection unit, A first switch (801) turns on and off in response to a signal whose frequency is the same as the frequency of the modulated signal and whose phase is opposite to the phase of the modulated signal, A second switch (802) that turns on or off in response to a signal whose frequency is the same as the frequency of the modulated signal and whose phase is the same as the phase of the modulated signal, Includes, The controller is, The resistor (856) connected to the first switch and the second switch, An operational amplifier (854) whose inverting input terminal is connected to the resistor and whose non-inverting input terminal is connected to the reference power supply, The capacitor (852) connected to the inverting input terminal and output terminal of the aforementioned operational amplifier, A capacitive sensor detection circuit as described in any one of views 10 to 12, including the following: [Perspective 15] The aforementioned capacitive sensor detection circuit is A first adjustment capacitor (611) is connected between the first electrode and the first input terminal, A second adjustment capacitor (622) is connected between the second electrode and the second input terminal, Equipped with, The capacitive sensor detection circuit according to any one of viewpoints 9 to 14, wherein the signal generation unit outputs a signal to the first adjustment capacitor and the second adjustment capacitor, the signal having an amplitude equal to the input amplitude, a frequency equal to the frequency of the modulated signal, and a phase opposite to the phase of the modulated signal. [Perspective 16] The fully differential amplifier is a capacitive sensor detection circuit according to any one of views 9 to 15, which includes an input common-mode feedback circuit (270) that brings half of the voltage relating to the sum of the first input signal and the second input signal closer to a predetermined voltage. [Explanation of symbols]

[0162] 10 Sensor elements 22 Signal generation unit 24. All-differential amplifiers 241 First Input Terminal 242 Second Input Terminal 251 First Output Terminal 252 Second Output Terminal 50 Calculation Section 70 Control Unit

Claims

1. A capacitive sensor detection circuit used in a sensor element (10) comprising a displaceable movable electrode (100), a first electrode (121) that outputs a signal corresponding to the change in a first capacitance (Cs1) between the movable electrode which changes due to the displacement of the movable electrode, and a second electrode (122) that outputs a signal corresponding to the change in a second capacitance (Cs2) between the movable electrode which changes due to the displacement of the movable electrode, wherein A signal generation unit (22) outputs a modulated signal (S), which is a signal having input amplitude (Vm), frequency, and phase, to the movable electrode. A fully differential amplifier (24) having a first input terminal (241) connected to the first electrode, a second input terminal (242) connected to the second electrode, a first output terminal (251) that outputs a signal corresponding to a first input signal (Vin1) which is input to the first input terminal and a second input signal (Vin2) which is input to the second input terminal, and a second output terminal (252) that outputs a signal corresponding to the first input signal and the second input signal, A first feedback capacitor (31) connected to the first input terminal and the first output terminal, A second feedback capacitor (32) connected to the second input terminal and the second output terminal, A calculation unit (50) calculates a value relating to the displacement of the movable electrode based on a first output signal (Vout1), which is a signal output from the first output terminal, and a second output signal (Vout2), which is a signal output from the second output terminal. A first capacitor (61) is connected between the first electrode and the first input terminal, A second capacitor (62) is connected between the second electrode and the second input terminal, A control unit (70) acquires the first input signal and the second input signal and outputs a signal to the first capacitor and the second capacitor, which has a feedback amplitude (Vcnt) that brings the amplitudes of the first input signal and the second input signal closer to zero, wherein the frequency of the signal corresponds to the frequency of the modulation signal and the phase is opposite to the phase of the modulation signal. A capacitive sensor detection circuit equipped with the following features.

2. The control unit, An adder (75) that acquires a signal relating to the sum of the first input signal and the second input signal, A synchronous detection unit (80) performs demodulation of a signal relating to the sum of the first input signal and the second input signal, corresponding to the frequency and phase of the modulated signal. A controller (85) calculates the feedback amplitude based on a signal relating to the sum of the first input signal and the second input signal demodulated by the synchronous detection unit and a signal from the reference power supply (795), A capacitive sensor detection circuit according to claim 1, having the following features.

3. The control unit has a high-pass filter (790) that removes the DC component included in the signal relating to the sum of the first input signal and the second input signal. The capacitive sensor detection circuit according to claim 2, wherein the synchronous detection unit demodulates a signal relating to the sum of the first input signal and the second input signal from which the DC component has been removed by the high-pass filter.

4. The aforementioned addition unit is A first voltage follower circuit (751) acquires the first input signal and outputs a signal corresponding to the first input signal, The first filter capacitor (781) is connected to the output terminal of the first voltage follower circuit, A second voltage follower circuit (752) acquires the second input signal and outputs a signal corresponding to the second input signal, The second filter capacitor (782) is connected to the output terminal of the second voltage follower circuit, A merging section (785) is connected to the first filter capacitor and the second filter capacitor, so that the signal is the sum of the first input signal and the second input signal, A capacitive sensor detection circuit according to claim 2, including the following:

5. The aforementioned synchronous detection unit, A first switch (801) that turns on or off in response to a signal whose frequency is the same as the frequency of the modulated signal and whose phase is the same as the phase of the modulated signal, A second switch (802) turns on and off in response to a signal whose frequency is the same as the frequency of the modulated signal, and whose phase is opposite to the phase of the modulated signal, A third switch (803) that turns on or off in response to a signal whose frequency is the same as the frequency of the modulated signal and whose phase is the same as the phase of the modulated signal, A fourth switch (804) that turns on or off in response to a signal whose frequency is the same as the frequency of the modulated signal and whose phase is opposite to the phase of the modulated signal, Includes, The controller is, A transconductance amplifier (850) in which the non-inverting input terminal is connected to the second switch and the third switch, and the inverting input terminal is connected to the first switch, the fourth switch and the reference power supply, A capacitor (852) connected to the output terminal and ground of the transconductance amplifier, A capacitive sensor detection circuit according to claim 2, including the following:

6. The aforementioned synchronous detection unit, A first switch (801) that turns on or off in response to a signal whose frequency is the same as the frequency of the modulated signal and whose phase is opposite to the phase of the modulated signal, A second switch (802) that turns on or off in response to a signal whose frequency is the same as the frequency of the modulated signal and whose phase is the same as the phase of the modulated signal, Includes, The controller is, The resistor (856) connected to the first switch and the second switch, An operational amplifier (854) whose inverting input terminal is connected to the resistor and whose non-inverting input terminal is connected to the reference power supply, A capacitor (852) connected to the inverting input terminal and output terminal of the operational amplifier, A capacitive sensor detection circuit according to claim 2, including the following:

7. The aforementioned capacitive sensor detection circuit is A first adjustment capacitor (611) is connected between the first electrode and the first input terminal, A second adjustment capacitor (622) is connected between the second electrode and the second input terminal, Equipped with, The capacitive sensor detection circuit according to claim 1, wherein the signal generation unit outputs a signal to the first adjustment capacitor and the second adjustment capacitor, the signal having an amplitude equal to the input amplitude, a frequency equal to the frequency of the modulated signal, and a phase opposite to the phase of the modulated signal.

8. The capacitive sensor detection circuit according to any one of claims 1 to 7, further comprising an output common-mode feedback circuit (260) that brings half of the voltage relating to the sum of the first output signal and the second output signal closer to a predetermined voltage, wherein the fully differential amplifier is further comprising an output common-mode feedback circuit (260).

9. A capacitive sensor detection circuit used in a sensor element (10) comprising a displaceable movable electrode (100), a first electrode (121) that outputs a signal corresponding to the change in a first capacitance (Cs1) between the movable electrode which changes due to the displacement of the movable electrode, and a second electrode (122) that outputs a signal corresponding to the change in a second capacitance (Cs2) between the movable electrode which changes due to the displacement of the movable electrode, wherein A signal generation unit (22) outputs a modulated signal (S), which is a signal having input amplitude (Vm), frequency, and phase, to the movable electrode. A fully differential amplifier (24) having a first input terminal (241) connected to the first electrode, a second input terminal (242) connected to the second electrode, a first output terminal (251) that outputs a signal corresponding to a first input signal (Vin1) which is input to the first input terminal and a second input signal (Vin2) which is input to the second input terminal, and a second output terminal (252) that outputs a signal corresponding to the first input signal and the second input signal, A first feedback capacitor (31) connected to the first input terminal and the first output terminal, A second feedback capacitor (32) connected to the second input terminal and the second output terminal, A calculation unit (50) calculates a value relating to the displacement of the movable electrode based on a first output signal (Vout1), which is a signal output from the first output terminal, and a second output signal (Vout2), which is a signal output from the second output terminal. A first capacitor (61) is connected between the first electrode and the first input terminal, A second capacitor (62) is connected between the second electrode and the second input terminal, A control unit (70) acquires the first output signal and the second output signal and outputs a signal to the first capacitor and the second capacitor, which has a feedback amplitude (Vcnt) that brings the amplitudes of the first output signal and the second output signal closer to zero, and whose frequency and phase correspond to the frequency and phase of the modulated signal, wherein the frequency of the signal corresponds to the frequency of the modulated signal and the phase is opposite to the phase of the modulated signal. A capacitive sensor detection circuit equipped with the following features.

10. The control unit, An adder (75) that acquires a signal relating to the sum of the first output signal and the second output signal, A synchronous detection unit (80) performs demodulation of the signal relating to the sum of the first output signal and the second output signal, corresponding to the frequency and phase of the modulated signal. A controller (85) calculates the feedback amplitude based on a signal relating to the sum of the first output signal and the second output signal demodulated by the synchronous detection unit and a signal from the reference power supply (795), A capacitive sensor detection circuit according to claim 9, having the following features.

11. The control unit includes a high-pass filter (790) that removes the DC component included in the signal relating to the sum of the first output signal and the second output signal. The capacitive sensor detection circuit according to claim 10, wherein the synchronous detection unit demodulates a signal relating to the sum of the first output signal and the second output signal from which the DC component has been removed by the high-pass filter.

12. The aforementioned addition unit is A first voltage follower circuit (751) acquires the first output signal and outputs a signal corresponding to the first output signal, The first filter capacitor (781) is connected to the output terminal of the first voltage follower circuit, A second voltage follower circuit (752) acquires the second output signal and outputs a signal corresponding to the second output signal, The second filter capacitor (782) is connected to the output terminal of the second voltage follower circuit, A merging section (785) is connected to the first filter capacitor and the second filter capacitor, so that the signal is the sum of the first output signal and the second output signal, A capacitive sensor detection circuit according to claim 10, including the following:

13. The aforementioned synchronous detection unit, A first switch (801) that turns on or off in response to a signal whose frequency is the same as the frequency of the modulated signal and whose phase is the same as the phase of the modulated signal, A second switch (802) turns on and off in response to a signal whose frequency is the same as the frequency of the modulated signal, and whose phase is opposite to the phase of the modulated signal, A third switch (803) that turns on or off in response to a signal whose frequency is the same as the frequency of the modulated signal and whose phase is the same as the phase of the modulated signal, A fourth switch (804) that turns on or off in response to a signal whose frequency is the same as the frequency of the modulated signal and whose phase is opposite to the phase of the modulated signal, Includes, The controller is, A transconductance amplifier (850) in which the non-inverting input terminal is connected to the second switch and the third switch, and the inverting input terminal is connected to the first switch, the fourth switch and the reference power supply, A capacitor (852) connected to the output terminal and ground of the transconductance amplifier, A capacitive sensor detection circuit according to claim 10, including the following:

14. The aforementioned synchronous detection unit, A first switch (801) turns on and off in response to a signal whose frequency is the same as the frequency of the modulated signal and whose phase is opposite to the phase of the modulated signal, A second switch (802) that turns on or off in response to a signal whose frequency is the same as the frequency of the modulated signal and whose phase is the same as the phase of the modulated signal, Includes, The controller is, The resistor (856) connected to the first switch and the second switch, An operational amplifier (854) whose inverting input terminal is connected to the resistor and whose non-inverting input terminal is connected to the reference power supply, A capacitor (852) connected to the inverting input terminal and output terminal of the operational amplifier, A capacitive sensor detection circuit according to claim 10, including the following:

15. The aforementioned capacitive sensor detection circuit is A first adjustment capacitor (611) is connected between the first electrode and the first input terminal, A second adjustment capacitor (622) is connected between the second electrode and the second input terminal, Equipped with, The capacitive sensor detection circuit according to claim 9, wherein the signal generation unit outputs a signal to the first adjustment capacitor and the second adjustment capacitor, the signal having an amplitude equal to the input amplitude, a frequency equal to the frequency of the modulated signal, and a phase opposite to the phase of the modulated signal.

16. The capacitive sensor detection circuit according to any one of claims 9 to 15, further comprising an input common-mode feedback circuit (270) that brings half of the voltage relating to the sum of the first input signal and the second input signal closer to a predetermined voltage, wherein the fully differential amplifier is the capacitive sensor detection circuit according to any one of claims 9 to 15.

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