Semiconductor equipment

Abstract

We provide highly reliable semiconductor devices. [Solution] The semiconductor device has first to third transistors and capacitances. The zista has a first signal applied to one of its source and drain, and a second transistor applied to the other. The gate of the capacitor and one of its electrodes are connected, and a second pulse signal is applied to the gate. The second transistor receives the first pulse signal at one of its sources and drains, and the other... This is connected to the other electrode of the capacitance and to one of the source and drain of the third transistor. The third transistor has a first potential applied to the source and the other drain, and a third potential applied to the gate. A second signal is given, which is the inverted version of the first signal. The first pulse signal is a clock signal. The second pulse signal is a signal with a duty cycle of 55% or less.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device. Another aspect of the present invention relates to a display device. One aspect of the present invention relates to a drive circuit for a display device. Another aspect of the present invention relates to an electronic device.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the technical field is semiconductor devices, display devices, light-emitting devices, energy storage devices, and memory devices. Electronic equipment, lighting equipment, input devices, input / output devices, methods for driving them, or methods for manufacturing them. Laws can be cited as one example. Semiconductor devices function by utilizing semiconductor properties. This refers to all devices that can do so. [Background technology]

[0003] Display devices include a variety of devices such as smartphones and other mobile information terminals, and television equipment. It is applied to various devices. In recent years, there has been a demand for improved screen-to-body ratio in devices to which display devices are applied. Therefore, the display device narrows the area other than the display area (narrows the bezel). Furthermore, it is required that part or all of the driving circuit be fabricated on the same substrate as the pixel section. System-on-panel is effective in meeting the above requirements. The transistors provided in the drive circuit and the transistors provided in the pixel section are manufactured using the same process. Manufacturing by this method is desirable because it reduces the cost required for panel production. (Patent document) Reference 1 and Patent Document 2 describe inverters and shift registers used in the drive circuits of display devices. The document discloses techniques for constructing various circuits, such as staves, using unipolar transistors. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-325798 [Patent Document 2] Japanese Patent Application Laid-Open No. 2010-277652 [Summary of the Invention] [Problems to be Solved by the Invention]

[0005] A sequential circuit that outputs a pulse signal and is used in a drive circuit of a display device may experience fluctuations in the electrical characteristics of the transistors that make up the sequential circuit, particularly fluctuations in the threshold voltage, resulting in problems such as the inability to output the desired signal. As a result, there is a risk that the image cannot be displayed.

[0006] One aspect of the present invention is to provide a highly reliable semiconductor device, display device, or electronic device. One aspect of the present invention is to provide a semiconductor device, display device, or electronic device that can achieve a narrow border of the display device. One aspect of the present invention is to provide a semiconductor device, display device, or electronic device that is highly reliable and can be manufactured at a low cost. One aspect of the present invention is to provide a semiconductor device, display device, or electronic device having a novel configuration. One aspect of the present invention is to reduce at least one of the problems of the prior art.

[0007] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems can be extracted from the descriptions in the specification, drawings, claims, etc. ​​​​​​​

Means for Solving the Problem

[0008] One aspect of the present invention is a semiconductor device having first to third transistors, a first capacitor, and first to fifth wirings. One of the source and drain of the first transistor is electrically connected to the first wiring, and the other of the source and drain is electrically connected to the gate of the second transistor and one electrode of the first capacitor, and the gate is electrically connected to the third wiring. One of the source and drain of the second transistor is electrically connected to the fourth wiring, and the other of the source and drain is electrically connected to the other electrode of the first capacitor and one of the source and drain of the third transistor. One of the source and drain of the third transistor is electrically connected to the fifth wiring, and the gate is electrically connected to the second wiring. A first signal is applied to the first wiring, and a second signal obtained by inverting the first signal is applied to the second wiring. A first pulse signal is applied to the fourth wiring. A first potential is applied to the fifth wiring. A second pulse signal is applied to the third wiring. The first pulse signal is a clock signal, and the second pulse signal is a signal with a duty ratio of 55% or less.

[0009] Another aspect of the present invention is a semiconductor device having a control circuit, first to third transistors, a first capacitor, and first to fifth wirings. One of the source and drain of the first transistor is electrically connected to the first wiring, and the other of the source and drain is electrically connected to the gate of the second transistor and one electrode of the first capacitor, and the gate is electrically connected to the third wiring. One of the source and drain of the second transistor is electrically connected to the first wiring, and the other of the source and drain is electrically connected to the gate of the second transistor​​​​ The fourth wiring is electrically connected, with the source and the other drain being the other electrode of the first capacitance. and is electrically connected to one of the source and drain of the third transistor. The inverter has its source and drain electrically connected to the fifth wiring, and its gate is the second It is electrically connected to the wiring. The control circuit outputs a first signal to the first wiring, and also the first The second signal, which is the inverted version of the first signal, is output to wire 2. The first pulse is output to wire 4. A signal is applied. The fifth wire is given the first potential. The third wire is given the second potential. A pulse signal is given. The first pulse signal is a clock signal, and the second pulse signal This refers to a signal with a duty cycle of 55% or less.

[0010] Furthermore, it is preferable to have a signal generation circuit that outputs a second pulse signal. In this case, it is preferable that a third pulse signal be supplied to the signal generation circuit and the control circuit. Furthermore, the third pulse signal is preferably a signal with a duty cycle of 1% or less. It's nice.

[0011] Furthermore, in the above, the second pulse signal is a signal with a duty cycle of 1% or less. It is preferable.

[0012] Furthermore, in the above, the signal generation circuit includes a fourth transistor and a fifth transistor. Preferably, the fourth transistor has a second capacitance and A second potential higher than the first potential is applied to one of the source and drain, and the source and drain The other side consists of the third wiring, one of the source and drain of the fifth transistor, and the second capacitance. It is electrically connected to one of the electrodes. The fifth transistor has a source and a drain. A first potential is applied to the other electrode. Furthermore, the second capacitance is applied when the first potential is applied to the other electrode. Furthermore, the gate of the fourth transistor is supplied with the third pulse signal, and the fifth A fourth pulse signal is applied to the gate of the transistor. The signal is preferably one with a duty cycle of 1% or less.

[0013] Furthermore, in the above, the second pulse signal is supplied to the third wiring and the control circuit. It is preferable.

[0014] Furthermore, in the above, the first transistor is connected to the first semiconductor layer and through the first semiconductor layer It is preferable to have a first gate and a second gate that overlap each other. It is preferable that gate 1 and gate 2 are electrically connected.

[0015] Furthermore, in the above, the third transistor is connected to the second semiconductor layer and via the second semiconductor layer It is preferable to have a third gate and a fourth gate that overlap each other. One of the gates 3 and 4 is electrically connected to the second wiring, and the third gate and Preferably, the other end of the fourth gate is electrically connected to the fifth wiring.

[0016] Furthermore, in the above, it is preferable that the fourth gate be located below the second semiconductor layer. It seems so. At this time, the third gate is electrically connected to the second wiring, and the fourth gate is, It is preferable to electrically connect to the fifth wiring.

[0017] Furthermore, one aspect of the present invention relates to a display device having any of the above-mentioned semiconductor devices and pixels. Yes. The pixel has a display element and a sixth transistor. The sixth transistor is the A transistor 1, a second transistor, and a third transistor are provided on the same plane. It is preferable that this be done.

[0018] Furthermore, in the above, the display element is preferably a liquid crystal element or a light-emitting element.

[0019] Furthermore, one aspect of the present invention includes any of the above-mentioned display devices, an antenna, a battery, a housing, At least one of the following: camera, speaker, microphone, touch sensor, and operation button, It is an electronic device. [Effects of the Invention]

[0020] According to one aspect of the present invention, a highly reliable semiconductor device, display device, or electronic device is provided. Yes, it is possible. Alternatively, a semiconductor device, display device, or electronic device that can achieve a narrow bezel for a display device. We can provide devices, or highly reliable and low-cost-to-manufacture semiconductor devices, display devices, Or we can provide electronic equipment. Or semiconductor devices, display devices, and novel configurations. It can provide electronic devices, or at least mitigate one of the problems of the prior art. can.

[0021] Furthermore, the description of these effects does not preclude the existence of other effects. One embodiment does not necessarily have to possess all of these effects. Furthermore, other effects may be considered. This information can be extracted from descriptions such as specifications, drawings, and claims. [Brief explanation of the drawing]

[0022] [Figure 1] Figure 1 shows an example of a sequential circuit configuration. [Figure 2] Figure 2A shows an example of a sequential circuit configuration. Figure 2B is a timing chart. [Figure 3] Figures 3A to 3C show examples of sequential circuit configurations. [Figure 4] Figures 4A and 4B show examples of sequential circuit configurations. [Figure 5] Figures 5A and 5B show examples of sequential circuit configurations. [Figure 6] Figure 6 shows an example of a sequential circuit configuration. [Figure 7] Figure 7 is a timing chart. [Figure 8] Figure 8A shows an example of a sequential circuit configuration. Figure 8B is a circuit diagram of a shift register. Figure 8C is a timing chart. [Figure 9] Figure 9 shows an example of the configuration of a signal generation circuit. [Figure 10] Figure 10 shows an example of a sequential circuit configuration. [Figure 11] Figure 11 is a timing chart. [Figure 12] Figure 12A shows an example of a sequential circuit configuration. Figure 12B is a circuit diagram of a shift register. Figure 12C is a timing chart. [Figure 13] Figures 13A to 13C show examples of transistor configurations. [Figure 14] Figures 14A to 14C show examples of transistor configurations. [Figure 15] Figures 15A to 15C show examples of transistor and capacitor configurations. [Figure 16] Figure 16 shows an example of a transistor and capacitor configuration. [Figure 17] Figures 17A to 17F illustrate the method for fabricating a transistor. [Figure 18] Figures 18A to 18D illustrate the method for fabricating a transistor. [Figure 19] Figures 19A to 19C show examples of transistor configurations. [Figure 20]Figure 20A is a block diagram of the display device. Figures 20B and 20C are circuit diagrams of the pixel circuit. [Figure 21] Figures 21A, 21C, and 21D are circuit diagrams of the pixel circuit. Figure 21B is a timing chart. [Figure 22] Figures 22A and 22B show examples of the configuration of a display module. [Figure 23] Figures 23A and 23B show examples of electronic device configurations. [Figure 24] Figures 24A to 24E show examples of the configuration of electronic equipment. [Figure 25] Figures 25A to 25G show examples of electronic device configurations. [Figure 26] Figures 26A to 26D show examples of electronic device configurations. [Modes for carrying out the invention]

[0023] The embodiments will be described below with reference to the drawings. However, many embodiments are described. It can be implemented in different ways, without deviating from its purpose and scope. Those skilled in the art will readily understand that the form and details can be modified in various ways. Therefore, the present invention This shall not be interpreted as being limited to the contents described in the following embodiments.

[0024] In the configuration of the invention described below, the same part or part having a similar function is The same reference numerals are used consistently across different drawings, and explanations of their repetition are omitted. When referring to the function of [this], the hatch pattern is the same, and sometimes no specific symbol is assigned.

[0025] In each figure described herein, the size, layer thickness, or area of ​​each component is not specified. This may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. I can't.

[0026] In this specification, ordinal numbers such as "the first," "the second," etc., are used to avoid confusion of constituent elements. This is added for the purpose of providing a numerical limit, and is not intended to limit the number of items.

[0027] A transistor is a type of semiconductor device that has the function of amplifying current or voltage, and conducting electricity. Alternatively, switching operations that control non-conductivity can be implemented. The transistor is an IGFET (Insulated Gate Field Efficient). (ct Transistor), and Thin Film Transistor (TFT: Thin Film Includes Transistor.

[0028] Furthermore, the "source" and "drain" functions are used when transistors with different polarities are employed. Alternatively, their positions may be reversed if the direction of the current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" are used interchangeably. It shall be possible.

[0029] Furthermore, in this specification, etc., "electrically connected" means "having some kind of electrical effect." This includes cases where the connection is made via ". Here, "has some electrical effect The term "of" is not particularly limited as long as it enables the exchange of electrical signals between connected objects. For example, "things that have some kind of electrical effect" include electrodes and wiring, as well as transistors. Switching elements such as switches, resistive elements, coils, capacitive elements, and other various functional elements. This includes elements and other components.

[0030] In this specification, a display panel, which is one form of a display device, displays an image or the like on its display surface. It has the function of (powering). Therefore, the display panel is one form of an output device.

[0031] Furthermore, in this specification, the substrate of the display panel may be, for example, FPC (Flexible Printed Circuit). (inted Circuit) or TCP (Tape Carrier Packa A connector such as a ge is attached, or the circuit board has a COG (Chip On A display panel module or display module is a device on which an IC is mounted using a glass or similar method. It may be called a display panel, or simply a display board.

[0032] (Embodiment 1) This embodiment describes an example of the configuration of a semiconductor device according to one aspect of the present invention.

[0033] [Configuration Example 1] [Configuration Example 1-1] Figure 1 shows an example of the configuration of a sequential circuit 10 according to one aspect of the present invention. The sequential circuit 10 is connected to circuit 11 and Circuit 11 and Circuit 12 are connected by wiring 15a and wiring 15b. They are electrically connected. Circuit 12 can also be called a control circuit.

[0034] In the following, unless otherwise specified, among the signals and potentials applied to the sequential circuit 10, high Potential is sometimes described as potential VDD, and low potential as potential VSS.

[0035] Circuit 12, according to the potential of signal LIN and the potential of signal RIN, first The signal has the function of outputting a second signal to wiring 15b. Here, the second signal The signal is the inverted version of the first signal. That is, the first signal and the second signal are... If the signals have two types of potentials, high potential and low potential, then the circuit 12 to wiring 15a When a high potential is output, a low potential is output to wiring 15b, and a low potential is output to wiring 15a. When this occurs, a high potential is output to wiring 15b.

[0036] Circuit 11 includes transistors 21, 22, 23, and capacitor C1 It has. Transistors 21, 22, and 23 are each n It is a channel-type transistor. Transistor 21, transistor 22, and transistor As for STA23, a metal oxide exhibiting semiconductor properties is used as a semiconductor in which a channel is formed. Hereinafter, oxide semiconductors (also referred to as oxide semiconductors) can be preferably used. However, the invention is not limited to oxide semiconductors. Furthermore, silicon (single-crystal silicon, polycrystalline silicon, or amorphous silicon), germanium Semiconductors such as um may be used, or compound semiconductors may be used.

[0037] Transistor 23 has its gate electrically connected to the wiring to which the signal BDG is given, One of the source and drain is electrically connected to wiring 15a, and the other of the source and drain is connected to The gate of the transistor 22 and one electrode of the capacitor C1 are electrically connected. The TA22 is electrically connected to a wiring to which the signal CLK is applied, with one of its sources and drains being connected. The source and the other of the drains are the other electrode of capacitance C1, the source and the drain of transistor 21 It is electrically connected to one side of the rain. Transistor 21 has its gate electrically connected to wiring 15b. It is connected, and the source and the other drain are given a potential VSS (also called the first potential). It is electrically connected to the wiring. Also, one of the source and drain of transistor 21 The source and drain electrodes of the transistor 22, and the other electrode of the capacitor C1, are connected to the output terminal O It is electrically connected to UT. Note that the output terminal OUT is supplied with the output potential from circuit 11. This is a part that may be part of the wiring or part of the electrode.

[0038] One of the source and drain of transistor 22 is connected to the signal CLK, which is a clock signal. The following is input. The clock signal has a duty cycle (the period of one cycle of the signal). A signal in which the level potential (percentage of time at high potential) is 45% or more and 55% or less is preferably selected. It can be used. More preferably, as a clock signal, with a duty cycle of 50%. A signal can be used. Note that the duty cycle of the clock signal is not limited to the above, It can be modified as appropriate depending on the method of operation.

[0039] In this specification, a clock signal is defined as a signal in which high potential and low potential are alternated, , the interval between the rise of one potential and the rise of the next potential, or the interval between the fall of one potential and the next potential This refers to a signal in which the falling edge interval is constant. Also, in this specification, etc., a pulse signal and A pulse signal is a signal whose electric potential changes over time. This includes changing signals. For example, pulse signals include square waves, triangle waves, sawtooth waves, and sine waves. It includes signals whose electrical potential changes periodically, such as waves. Therefore, a clock signal is a pulse signal. It could also be said to be one form of the number.

[0040] The signal CLK is a signal in which high and low potentials are alternately applied. In this case, the signal CL It is preferable that the low potential of K be the same potential as the potential VSS. Note that instead of the signal CLK, A high potential (e.g., potential VDD) is applied to one of the source and drain of transistor 22. This configuration is also acceptable.

[0041] Furthermore, the signal BDG applied to the gate of transistor 23 is a periodic pulse signal. This is the case. In this instance, a lower duty cycle for signal BDG is preferable. For example, signal BD G has a duty cycle of 60% or less, preferably 55% or less, more preferably 50% or less. More preferably 10% or less, even more preferably 5% or less, and even more preferably 1% or less. A certain pulse signal can be used. The lower limit of the duty cycle of the signal BDG is small. The smaller the value, the better; it's fine as long as it's greater than 0%.

[0042] When a pulse signal with a short duty cycle is applied to the gate of transistor 23, This makes it possible to suppress fluctuations in the threshold voltage of transistor 23. Here, for example The gate of transistor 23 is always at a constant high potential (i.e., a duty cycle of 10 Assuming a configuration where a signal (which can also be called a 0% signal) is applied, the configuration of transistor 23 Because the voltage value tends to shift positively, the expected signal is output from the sequential circuit 10. There is a risk that it will become impossible. On the other hand, in one embodiment of the present invention, the gate of transistor 23 Because a signal BDG with a small duty cycle is applied, the electrical characteristics of transistor 23 fluctuate. This suppresses the noise, and as a result, a highly reliable sequential circuit 10 can be realized.

[0043] Here, signal BDG is a signal generated using the signal for driving circuit 12. It is preferable that the signal BDG also serves as a signal for driving circuit 12. This is preferable. This allows for the provision of a circuit to generate a new signal BDG outside of the sequential circuit 10. Since it is not necessary, the configuration of the equipment to which the sequential circuit 10 is applied can be simplified.

[0044] The operation of the sequential circuit 10 will be explained. A high potential is applied to wire 15a, and wire 15b When a low potential is applied and the signal BDG becomes high potential, transistors 23 and 2 2 becomes conductive (on), and transistor 21 becomes non-conductive (off). At this time, the output terminal OUT and the wiring to which the signal CLK is supplied become electrically connected.

[0045] In circuit 11, the output terminal OUT and the gate of transistor 22 are connected via capacitance C1. Because they are electrically connected, the bootstrap effect causes the potential of the output terminal OUT to rise. As the voltage rises, the gate potential of transistor 22 increases. Here, capacitance C1 is present. If not, the signal CLK will have a potential lower than the high potential by the threshold voltage of transistor 22. However, it is output to the output terminal OUT. However, because it has capacitance C1, The gate potential of transistor 22 is close to twice the potential VDD (for example, potential VDD and electric potential). Because it rises to a potential close to twice the difference in VSS, the threshold voltage of transistor 22 Without being affected, the output terminal OUT receives the high potential of the signal CLK (e.g., potential VDD). This allows for the output of ) without increasing the number of power supply potentials. A highly sequential circuit 10 can be realized.

[0046] Furthermore, since a high potential is applied as the signal BDG and transistor 23 is in the ON state, When a high potential is applied to wiring 15a, the gate of transistor 22 is transmitted through transistor 23. A high potential is applied to the wire 15a. At this time, the high potential applied to the wire 15a and the high potential of the signal BDG When the potentials are equal (for example, both are at potential VDD), the gate of transistor 22 A potential lower than the potential VDD by the threshold voltage of transistor 23 is applied to the terminal. As the signal CLK changes from a low potential to a high potential, the bootstrap effect causes transistor 22 The gate potential (the potential of the other side of the source and drain of transistor 23) rises. Therefore, when the potential of the source and the other drain of transistor 23 exceeds the potential VDD, Because transistor 23 is in the off state, the gate of transistor 22 and the wiring 15a are powered The transistor becomes electrically disconnected, and the gate of transistor 22 becomes floating. Furthermore, the potential of wiring 15a will not rise above the output potential (VDD) of circuit 12. Therefore, a potential higher than the output potential is applied to the transistors, etc., in circuit 12 via wiring 15a. This prevents this from happening. This improves the reliability of the sequential circuit 10. ru.

[0047] On the other hand, when a low potential is applied to wiring 15a and a high potential is applied to wiring 15b, the transient A low potential is applied to the gate of transistor 22 via sta 23, and transistor 22 is O The state becomes "F". Also, transistor 21 turns ON. At this time, the output terminal OUT and When the wiring to which the potential VSS is applied becomes conductive, the potential VSS is output to the output terminal OUT. This is done. Subsequently, the signal BDG is changed from a high potential to a low potential, and transistor 23 is turned off. It is preferable to maintain this state.

[0048] Figure 2A shows a more detailed configuration example of the sequential circuit 10 illustrated in Figure 1. The circuit 12 includes transistors 31, 32, 33, and It has a transistor 34. Transistors 31 to 34 have the above-mentioned n-channel It is preferable to apply a transistor of this type. In particular, an oxide is used in the semiconductor where the channel is formed. It is preferable to use transistors that utilize solid semiconductors.

[0049] Transistors 31 and 34 conduct or do not conduct according to the potential of the signal LIN. This is selected. Transistors 33 and 32 conduct according to the potential of the signal RIN. Alternatively, non-conductivity is selected.

[0050] When signal LIN is at a high potential and signal RIN is at a low potential, transistor 31 is in the ON state. When transistor 33 is in the off state, the wire to which the potential VDD is applied and the wire 15a are electrically connected. They are electrically connected. Also, when transistor 34 is in the ON state and transistor 32 is in the OFF state As a result, the wiring to which the potential VSS is applied and wiring 15b are electrically connected. Meanwhile, the signal When LIN is at a low potential and the signal RIN is at a high potential, transistor 31 is in the off state. When the zista 33 is turned on, the wiring to which the potential VSS is applied and the wiring 15a are electrically connected. They are connected. Also, transistor 34 is in the off state and transistor 32 is in the on state. The wiring to which the potential VDD is supplied is electrically connected to wiring 15b.

[0051] In sequential circuit 10, when signal LIN is at a high potential and signal RIN is at a low potential, wiring 15a Wiring 15b is at a high potential, while wiring 15b is at a low potential, and the potential of the signal CLK is output to the output terminal OUT. On the other hand, when signal LIN is at a low potential and signal RIN is at a high potential, wiring 15a is at a low potential, Line 15b becomes high potential, and the output terminal OUT and the wiring to which the potential VSS is applied are electrically connected. It will continue.

[0052] The potentials of signals LIN and RIN input to the sequential circuit 10 are alternately switched between high and low potentials. By changing the signal CLK and signal LIN, the output terminal OUT of the sequential circuit 10 is synchronized. A pulsed output signal is output to the output terminal OUT of the sequential circuit 10. By supplying force signals to wiring (e.g., scan lines) connected to multiple pixels, sequential rotations are achieved. The path 10 can be used as part of the gate driver circuit.

[0053] Figure 2B is a timing chart showing an example of a driving method for the sequential circuit 10 shown in Figure 2A. Figure 2B shows signals LIN, RIN, BDG, CLK, node N, and output. This diagram schematically shows the time variation of the potential at the force terminal OUT. Here, node N is the The gates of transistor 22 correspond to the nodes to which they are connected (see Figure 2A).

[0054] At time T1, signals LIN and BDG are at high potential, and signals RIN and CLK are at high potential. The potential becomes low. During the period T1-T2, a high potential is output from circuit 12 to wiring 15a. Since transistor 23 is ON, the potential of node N is lower than the potential of wiring 15a. The potential rises to a level lowered by the threshold voltage of converter 23.

[0055] Next, at time T2, the signal LIN becomes low in potential, and the signal CLK becomes high in potential. At this time, transistors 31 through 34 of circuit 12 are all in the OFF state. Therefore, wiring 15a is electrically floating. As the signal CLK reaches a high potential, the potential of node N rises. The difference between the gate potential of transistor 23 and the potential of node N reaches the threshold voltage of transistor 23. As a result, transistor 23 turns off, and node N becomes floating. As the gate potential of transistor 23 rises, the signal CLK increases at the output terminal OUT. An electric potential is applied.

[0056] Next, at time T3, the signal RIN becomes high potential and the signal CLK becomes low potential. During period T3-T4, a high potential is output from circuit 12 to wiring 15b, and transistor 2 1 is turned ON. Meanwhile, a low potential is output to wiring 15a, and transistor 23 turns ON. Because of this state, transistor 22 is in the OFF state. As a result, the output terminal OUT is A potential VSS is applied.

[0057] Then, at time T4, the signal BDG becomes low potential and transistor 23 turns off. Yes.

[0058] The above is an explanation of one example of how the sequential circuit 10 operates.

[0059] Here, we will explain the voltage stress applied to transistor 23. For simplicity, Therefore, we will explain high potential as potential VDD and low potential as potential VSS.

[0060] At time T1, a potential VDD is applied to the gate of transistor 23, and the wiring 15a side When a potential VDD is applied to the electrode, transistor 23 has the electrode on the node N side as the source. Yes. Next, at time T2, the signal CLK changes from potential VSS to potential VDD, and no Suppose the potential of N rises to twice the potential of potential VDD minus potential VSS. At this time, Since line 15a is floating and remains at potential VDD, transistor 23 The source and drain are swapped, and the electrode connected to wiring 15a becomes the source. At time T3, when a potential VSS is applied to wiring 15a and the potential at node N decreases, In this way, the electrode on the wiring 15a side of transistor 23 functions as the source. A transistor in which the source and drain functions are reversed during operation is called a bidirectional transistor (b This can be called an i-direction transistor.

[0061] During the period T1-T2, the voltage (potential difference) across the gate-source of transistor 23 is The maximum is VDD-VSS. However, as the potential of node N rises, the transient Because the voltage across the source-drain of station 23 drops sharply, voltage stress occurs immediately. This will be relaxed. Also, during period T2-T3, the gate-saw of transistor 23 Almost no potential difference occurs between the transistors. Also, during the period T3-T4, the gate of transistor 23 The voltage between the source and the transistor is VDD-VSS. Also, from time T4 onwards, No voltage stress occurs in transistor 23. Therefore, the gate-source of transistor 23 Stress occurs when a low potential is applied to wiring 15a and the signal BDG is at a high potential. It can be seen that this is the case. Therefore, during the period when a low potential is applied to wiring 15a By minimizing the period during which the signal BDG is at a high potential, the voltage of transistor 23 is controlled. This can reduce stress and suppress fluctuations in threshold voltage.

[0062] Here, the sequential circuit 10 can be used as a drive circuit for the display device. In particular, scanning It can be suitably used as a line drive circuit. In this case, the output terminal OUT is connected to the display device. When connecting scan lines connected to multiple pixels, the sequential circuit 10 outputs to the output terminal OUT. The duty cycle of the output signal is significantly smaller than that of the signal CLK, etc. Also, wiring 1 The potential input to 5a is such that the period of low potential is significantly longer than the period of high potential. Therefore, if a constant high potential is applied to the gate of transistor 23, The period during which voltage stress is applied between the gate and source of transistor 23 becomes significantly longer, The threshold voltage of the transistor 23 is prone to fluctuations. However, one aspect of the present invention is The gate of transistor 23 is not at a constant potential, but rather a pulsed signal with a small duty cycle. Since the signal BDG is applied, fluctuations in the threshold voltage of transistor 23 are effectively suppressed. This is possible. In particular, the signal BDG is used when the sequential circuit 10 outputs a signal to the output terminal OUT. The high potential occurs only during the operating period (for example, period T1-T4 in Figure 2B), and during other periods... It is preferable to apply a pulse signal that is always at a low potential. This allows the duration of the signal BDG Reduce the t-to-t ratio to 1% or less, preferably 0.5% or less, and more preferably 0.1% or less. This enables the sequential circuit 10, and by extension the semiconductor device, display device, and electronic device using the sequential circuit 10. This can impart extremely high reliability to the container.

[0063] Furthermore, when the sequential circuit 10 is used as a drive circuit for the display device, the pixels of the display device have Transistors and transistors that constitute the sequential circuit 10 (transistor 21, transistors It is preferable to provide the transistor 22 and transistor 23, etc., on the same substrate. The transistors provided in the base and the transistors that constitute the sequential circuit 10 are processed in the same step. It is preferable to produce it in a more conventional way.

[0064] [Configuration Example 1-2] Figure 3A shows an example of the configuration of a sequential circuit 10a having a circuit 11 that differs in some aspects from that in Figure 2A. This indicates.

[0065] The transistor 21 in circuit 11 has a pair of gates (hereinafter referred to as the first gate, the second gate) It has a gate. Transistor 21 has a first gate that is electrically connected to wiring 15b. The process continues, and the second gate is given its own source and drain, and the potential VSS is applied. The wiring is electrically connected, and one of the source and drain of transistor 22 is connected to the source and drain of transistor 22. It is electrically connected to the other electrode of the drain and the other electrode of the capacitance C1.

[0066] Here, if the sequential circuit 10a is used as the drive circuit for the display device, as described above, the sequential circuit The duty cycle of the output signal output from path 10a to output terminal OUT is determined by the signal CLK, etc. It becomes significantly smaller in comparison. At this time, transistor 21 is in an off state for a longer period than it is in the off state. The period during which it remains in the ON state becomes significantly longer. That is, transistor 21 is in the first gate The period during which a high potential is applied becomes significantly longer than the period during which a low potential is applied. Therefore, Transistor 21 is more prone to threshold voltage fluctuations than transistor 22. Specifically, transistor 21 has a more positive threshold voltage than transistor 22. It's easy to shift to that.

[0067] Therefore, in one aspect of the present invention, the transistor 21 is superimposed with a semiconductor layer in between. The configuration has a pair of gates. Then, one of the gates is connected to a wire to which a low potential is applied (electrical). The configuration will be such that the wiring to which the position VSS is given is electrically connected. In other words, the transistor The TA21 can also be described as a configuration in which one gate and one source are electrically connected to each other. By using such a configuration, the threshold voltage of transistor 21 is shifted in the positive direction. This can be effectively suppressed. Therefore, the sequential circuit 10a, and by extension the sequential circuit 10 The reliability of semiconductor devices, display devices, and electronic devices using a can be improved.

[0068] Furthermore, the transistor 21 is configured such that one of its gates and source are electrically connected. This effectively prevents the threshold voltage from becoming a negative value. It becomes easy to make transistor 21 have normally-off characteristics. - If it has the characteristics of a 1 / 4 transistor, the voltage between the other gate and source of transistor 21 is 0 When the voltage is V, a leakage current occurs between the source and drain, and the potential of the output terminal OUT cannot be maintained. Therefore, in order to turn off transistor 21, The other gate needs to be supplied with a potential lower than the potential VSS, requiring multiple power supplies. On the other hand, the transistor 21 in one aspect of the present invention can stably achieve normally-off characteristics. Therefore, a sequential circuit 10a with high output performance can be realized without increasing the number of power supply potential types. It is possible.

[0069] Furthermore, transistor 21 is configured such that one of its gates and source is electrically connected. This also has the effect of increasing saturation. As a result, the design of circuit 11 becomes easier, and the circuit This allows circuit 11 to be operated stably.

[0070] Thus, in the sequential circuit 10a, the period during which voltage stress is applied to the transistor is extremely long. A transistor with one gate and source connected is applied to TA21, and a bidirectional transistor is used. The gate of transistor 23, which functions as a zistor, receives a pulse signal with a short duty cycle. This configuration provides the following: This makes it possible to suppress fluctuations in the threshold voltage. As a result, high output performance and high This enables the realization of a sequential circuit 10a that achieves both reliability and performance.

[0071] [Configuration Examples 1-3] Figure 3B shows an example of the configuration of the sequential circuit 10b. In the sequential circuit 10b, circuit 12 is The transistor 33 has a pair of gates, and one gate and source are connected. Rangista is applied.

[0072] Transistor 33, like transistor 21 in circuit 11, operates during the operation of sequential circuit 10b. This transistor has an extremely long ON state. Therefore, transistor 33 By using the same configuration as transistor 21, fluctuations in the threshold voltage are suppressed, and sequential circuit 1 This can improve the reliability of 0b.

[0073] [Configuration Examples 1-4] Figure 3C shows an example of the configuration of the sequential circuit 10c.

[0074] The sequential circuit 10c has transistors 33 and 34 in circuit 12. Also, a transistor having a pair of gates, with one gate connected to the source, is applied. It is.

[0075] Compared to transistor 33, transistor 34 turns on when sequential circuit 10c is operating. Although the period during which this condition occurs is short, prolonged operation can cause fluctuations in the threshold voltage. Therefore, by making transistor 34 the same configuration as transistor 33, The fluctuations in the voltage are suppressed, and the reliability of the sequential circuit 10c can be improved.

[0076] In addition, in sequential circuit 10c, transistors 31, 32, and 22 A transistor having a pair of gates is applied to transistor 23.

[0077] In a transistor having a pair of gates separated by a semiconductor layer, the pair of gates are electrically By connecting to a transistor with one gate, or a pair of gates Compared to applying a constant potential to one side of the source, the region where the channel is formed increases, and the source- This allows for a larger current to flow between the drains (also called the on-current). Because the transistor size can be reduced while suppressing the decrease in current, the sequential circuit 10c, extension In this way, the area of ​​the drive circuit using the sequential circuit 10c can be reduced. In particular, the transient The st 22 and transistor 23 have a larger current than the transistor provided in circuit 12. Because current supply capability is required, transistors 22 and 23 are equipped with such a transistor. Applying a transistor is extremely effective in reducing the area.

[0078] Furthermore, by using a transistor with a pair of gates electrically connected, one gate can be used Compared to transistors, it is easier to achieve normally-off electrical characteristics and has improved saturation. This offers advantages such as improving performance. This enables the realization of a highly reliable sequential circuit 10c. It is possible.

[0079] Also, transistors 31, 32, 22, and 2 3. By applying a transistor with high current supply capability, the operating frequency of the sequential circuit 10c can be increased. It can also be improved.

[0080] Note that in Figure 3C, transistors 31, 32, 22, and An example of applying transistors with a pair of gates electrically connected to all of the Rangitor 23. As shown, this is not the only way; you can apply the above transistor to one or more transistors. In particular, transistors 22 and 23 included in circuit 11 have a pair of gates. It is preferable to use electrically connected transistors.

[0081] [Configuration Example 2] The following describes a sequential circuit with a configuration different from that of the above-mentioned Configuration Example 1.

[0082] [Configuration Example 2-1] Figure 4A shows an example of the configuration of the sequential circuit 20. The sequential circuit 20 has circuit 11 and circuit 13. Circuit 11 and circuit 13 are electrically connected by wiring 15a and wiring 15b. Yes. The configuration of circuit 11 can be adapted from configuration example 1.

[0083] The signals BDG and CLK1 are input to circuit 11. The output terminal is SROUT. The following are connected. Signal BDG is input to the gate of transistor 23. Signal CLK 1 is input to either the source or the drain of transistor 22.

[0084] Circuit 13 has transistors 41 to 47 and capacitance C2. The signals LIN, CLK2, CLK3, RIN, and RES are input to this device. Transistors 41 to 47 are n-channel type transistors as described above. It is preferable to apply a t-type semiconductor. In particular, it is preferable to apply an oxide semiconductor to the semiconductor in which the channel is formed. It is preferable to use a transistor.

[0085] Circuit 13 outputs a first signal to wiring 15a and a first signal to wiring 15b according to the various input signals. It has the function of outputting a second signal, which is the inverted version of the first signal.

[0086] Furthermore, circuits 11 and 13 have a high potential VDD and a low potential VS S is being supplied.

[0087] Specifically, transistor 41 has a gate that is connected to the wiring to which the signal LIN is applied, and a source that is connected to the wiring. One side of the drain is connected to wiring 15a, and one side of the source and drain of transistor 46. The other end is electrically connected to a wire to which a potential VDD is applied. 42 is a circuit where the gate is given the signal CLK3, and one of the source and drain is a transistor. One of the source and drain of the ZISTA 43 is connected to a wire to which the potential VDD is applied, and They are electrically connected. Transistor 43 is set to a gate when the signal CLK2 is applied. Wiring, source and drain, the other side of wiring 15b, one electrode of capacitance C2, and transient The gates of transistors 46 and 44 are electrically connected. Transistor 44 has a gate. A wire to which the signal RIN is applied has one source and one drain connected to wire 15b, and the other to the potential The wiring to which VDD is supplied is electrically connected to each other. Transistor 45 is The wire to which the signal RES is supplied, and one of the source and drain is wire 15b, and the other These are electrically connected to the wiring to which the potential VDD is applied. Transistor 46 The source and the other drain are electrically connected to wiring to which the potential VSS is applied. Transistor 47 has a gate that is connected to the wiring to which the signal LIN is applied, and a source and drain. One side is electrically connected to wiring 15b, and the other side is electrically connected to wiring to which potential VSS is applied. Capacitor C2 is such that the other electrode is electrically connected to the wiring to which the potential VSS is applied. Yes, they are.

[0088] In the circuit 13 shown in Figure 4A, transistor 46 has a pair of gates An example of applying the transistor is shown. Transistor 46 has one of its pair of gates at potential VS S is electrically connected to the given wiring.

[0089] Note that transistors 41, 45, 47, and 22 and at least one of the transistors 23 has a pair of electrically connected gates. A transistor having a pair may be applied. Figure 4B shows that all of the transistors have a pair This shows an example of applying a transistor with an electrically connected gate.

[0090] [Configuration Example 2-2] Figure 5A shows an example configuration of a sequential circuit 30 having two output terminals. Sequential circuit 30 This configuration has circuit 11a instead of circuit 11 in the sequence circuit 20 described above.

[0091] The signals BDG, CLK1, and PWC are input to circuit 11a. The output terminals SROUT and GOUT are connected to the circuit 11a.

[0092] Circuit 11a has a configuration in which two circuits 11 are connected in parallel. Transistor 2 1. Transistors 22 and 23, and capacitor C1 constitute a single circuit 11. Furthermore, transistors 24, 25, 26, and capacitor C3 also This constitutes one circuit 11. Transistors 24 to 26, capacitor C3 The connection configuration is the same as that of circuit 11 described above.

[0093] One of the sources and drains of transistor 25 is connected to the wiring to which the signal PWC is supplied and electrical They are connected precisely. Also, one of the source and drain of transistor 24, the transistor The source and drain electrodes of TA25, and the other electrode of capacitance C3, are connected to the output terminal GOUT. Electrically connected. The gate of transistor 26 is connected to the wiring to which the signal BDG is given. They are directly connected.

[0094] In circuit 11a, when a high potential is applied to wire 15a and a low potential to wire 15b, the output The potential of signal CLK1 is at terminal SROUT, and the potential of signal PWC is at output terminal GOUT. Each outputs a signal. On the other hand, when a low potential is applied to wiring 15a and a high potential is applied to wiring 15b, Both output terminals SROUT and GOUT are connected to wiring to which the potential VSS is applied. They are connected electrically.

[0095] Here, when the sequential circuit 30 is used as part of the gate driver circuit of the display device, The power terminal GOUT is used as the terminal to which the scan line is connected, and the output terminal SROUT is in the following order. The wiring input to the circuit 30 can be used as a terminal to which it is connected. Transistor 24 and transistor 25 are more efficient than transistors 21 and 22. It is preferable to use transistors with high current supply capability. For example, large channel width Larger transistors can be applied to transistors 24 and 25.

[0096] Here, the signal CLK1 and the signal PWC can be synchronized signals. In this case, a signal can be used in which the period of high potential coincides with the period of low potential. At this time, the high potential of signal CLK1 and signal PWC is potential VDD, and the low potential is potential Using a VSS signal eliminates the need to increase the number of power supply potentials required to drive the sequential circuit 30. It is preferable because it is unnecessary.

[0097] Furthermore, signals with different amplitudes may be used for signal CLK1 and signal PWC. For example, A signal with a larger amplitude than signal CLK1 can be used for signal PWC. In this case, In the signal PWC, the low potential is the potential VSS, and the high potential is a potential higher than the potential VDD. It is preferable to use a specific number. This allows a high potential to be output to the output terminal GOUT. Yes, it is possible. Also, by reducing the amplitude of signal CLK1, and the potential difference between potential VDD and potential VSS... By reducing this, the voltage stress on the transistors constituting the sequential circuit 30 is reduced. This suppresses fluctuations in electrical characteristics, including the threshold voltage of the transistor. This can be done, and the reliability of the sequential circuit 30 can be improved. The potential applied to the gate of transistor 25 is due to the bootstrap effect of capacitance C3. This allows the potential to be set to a sufficiently higher potential than VDD, so the transistor 25 Without being affected by the threshold voltage, the high potential of the signal PWC is output to the output terminal GOUT. It is possible to exert power.

[0098] Note that transistors 41, 45, 47, and 22 , at least one of transistors 23, 25, and 26 A transistor having a pair of electrically connected gates may be applied. Figure 5B shows This is a transistor having a pair of electrically connected gates in all of the above transistors. An example of its application is shown. In particular, transistors 22 and 25 have a pair It is preferable to use a transistor with an electrically connected gate and high current drive capability. It seems so.

[0099] [Example of drive circuit configuration] The following describes a configuration consisting of multiple sequential circuits connected in stages, which functions as a shift register. Let's explain an example of a drive circuit.

[0100] [Example of drive circuit configuration 1] First, we will explain an example of a sequential circuit configuration that can be used in a drive circuit. Figure 6 shows a sequential circuit. The circuit diagram of the sequential circuit 30a is shown. The sequential circuit 30a consists of circuit 13, circuit 11a, and signal generation. It has a circuit 14a. The signal generation circuit 14a is a circuit that generates the signal BDG.

[0101] Circuits 13 and 11a can be constructed using the above configuration example 2. Note that in Figure 6, The signal RIN exemplified in Configuration Example 2 is referred to as signal RIN1. Also, in circuit 11a The node to which the gate of transistor 22 is connected is node N1, and the gate of transistor 25 is connected Let node N2 be the node to which it is connected.

[0102] The signal generation circuit 14a has transistor 51, transistor 52, and capacitor C4. Furthermore, the signal generation circuit 14a receives signals LIN and RIN2 as inputs.

[0103] Transistor 51 has a gate that is connected to the wiring into which the signal LIN is input, and a source and drain. One side is the wiring to which the potential VDD is applied, and the other side is the source and drain of transistor 52. On the other hand, it is electrically connected to one electrode of capacitor C4. Transistor 52 is The gate is connected to the wiring into which the signal RIN2 is input, and the other side of the source and drain is at potential VSS. The given wiring is electrically connected to each other. Capacitor C4 is connected when the other electrode is at potential VSS. It is electrically connected to the provided wiring.

[0104] In the signal generation circuit 14a, the source and the other drain of transistor 51 are connected. The signal BDG is output to the wiring. The signal BDG is the gateway of transistor 23 in circuit 11a. It is supplied to the gate of transistor 26, respectively.

[0105] When signal LIN is at a high potential and signal RIN2 is at a low potential, transistor 51 is in the ON state. When the transistor 52 is turned off, the signal BDG output from the signal generation circuit 14a is high-voltage. This is the position. On the other hand, when signal LIN is at a low potential and signal RIN2 is at a high potential, transistor 51 With the switch in the off state and transistor 52 in the on state, the signal BDG becomes low potential.

[0106] Furthermore, capacitor C4 is connected to the wiring where signal BDG is output. Both LIN and signal RIN2 become low potential, and transistor 51 and transistor 52 When both are turned off, the wiring to which the BDG signal is output is electrically floating. Even when the state is disrupted, the potential of the wiring can be maintained. Therefore, the signal is maintained. It is not necessary to continuously output a high or low potential as the signal BDG from circuit 14a. Even when signals with a low duty cycle are used for signal LIN and signal RIN2, the potential of the wiring remains the same. This can be maintained over a long period of time. Specifically, the state in which the signal BDG is at a low potential can be maintained. Because it can be maintained over a long period of time, the signal BDG is a signal with an extremely low duty cycle. It can be designated as number. Also, by providing capacitance C4, the wiring on which the signal BDG is output This prevents the potential from fluctuating due to electrical noise. Also, the signal BDG is low. Since it is not necessary to keep transistor 52 in the ON state during the period when it is at potential, transistor 5 The voltage stress on point 2 is alleviated, and fluctuations in the threshold voltage can be suppressed.

[0107] Having such a signal generation circuit 14a, the signal BDG is generated with a duty cycle of 5% or less. Preferably 3% or less, more preferably 1% or less, even more preferably 0.5% or less. More preferably, the pulse signal can be 0.1% or less. In semiconductor devices, display devices, and electronic devices using the circuit 30a, and by extension the sequential circuit 30a, It can provide extremely high reliability.

[0108] In Figure 6, transistors 51 and 52 of the signal generation circuit 14a are paired This shows an example of applying a transistor whose gate is electrically connected. However, this is not limited to this example. Therefore, transistors 51 and 52 are given transistors with one gate each. It may also be applied. Furthermore, in transistor 52, one of the pair of gates is at potential VSS. A transistor that is electrically connected to the given wiring may be used.

[0109] Fig. 7 shows a timing chart of an example of a driving method for the sequential circuit 30a. Fig. 7 shows the potential's time variation of signal CLK1 (signal PWC), signal CLK2, signal CLK3, signal RES, signal L IN, signal RIN1, signal RIN2, signal BDG, node N1 (node N2), and output terminal SROUT (output terminal GOUT) schematically. Note that since signals CLK1 and PWC use signals with the same waveform, they are shown together for clarity. Also, since nodes N1 and N2 have generally the same potential time variation pattern, they are shown together for clarity. Also, signals CLK1, CLK2, and CLK3 use clock signals that are shifted by 1 / 4 cycle each in this order.

[0110] At time T11, when signal LIN is at high potential and signal RIN2 is at low potential, signal BDG becomes high potential. Subsequently, at time T12, when signals CLK1 and PWC become high potential, the potentials of nodes N1 and N2 rise. Also, during the period T12 - T 14, high potential is output to output terminal SROUT and output terminal GOUT. During period T14 when signal LIN is at low potential and signal RIN1 is at high potential, low potential is output to output terminal S ROUT and output terminal GOUT. Then, at time T15, when signal RIN2 becomes high potential, signal BDG becomes low potential. Also, at time T17 even after signal RIN2 becomes low potential, signal BDG remains at low potential.

[0111] Subsequently, a driving circuit configured by connecting a plurality of stages of the sequential circuit 30a will be described.

[0112] ​FIG. 8A is a diagram for explaining the input / output terminals of the sequential circuit 30a. The sequential circuit 30a has, as input terminals, a terminal to which a signal LIN, a signal RIN1, a signal RIN2, a signal CLK1, a signal CLK2, a signal CLK3, a signal PWC, and a signal RES are respectively input, and, as output terminals, has an output terminal SROUT and an output terminal GOUT.

[0113] FIG. 8B shows a configuration example of the drive circuit 40a. The drive circuit 40a has a plurality of sequential circuits . In FIG. 8B, sequential circuits 30a_1 to sequential circuit 30a_6 are shown, and the rest are omitted. The sequential circuits 30a_1 etc. have the same configuration as the sequential circuit 30a exemplified in FIG. 6. Hereinafter, the n-th sequential circuit located closer to the input of the drive circuit 40a will be denoted as the sequential circuit 30a_n (n is an integer of 1 or more).

[0114] Any three of signals CK1 to signal CK4 are used as the signals CLK1, signal CLK2, and signal CLK3 for the sequential circuit 30a_n. Also, any one of signals PWC1 to signal PWC4 is used as the signal PWC for the sequential circuit 30a_n. The combinations of signals CK1 to signal CK4 and signals PWC1 to signal PWC4 are the same combinations every four stages. That is, the same signals are input as the signals CLK1, signal CLK2, signal CLK3, and signal PWC to the sequential circuit 30a_n and the sequential circuit 30a_n + 4.

[0115] Also, a wiring OUTn which is an output wiring (in FIG. 8B, wirings OUT1 to wirings OUT6 are shown.) is connected to the output terminal GOUT of the sequential circuit 30a_n.

[0116] The sequential circuit 30a_1 receives the signal SP as the signal LIN. Also, n is 2 or greater. The sequential circuit 30a_n has a signal LIN at the output terminal of sequential circuit 30a_n-1. The SROUT signal is input. Also, the sequential circuit 30a_n receives the signal RIN1, The signal from the output terminal SROUT of the sequential circuit 30a_n+2 is input. Also, the sequential circuit 30 a_n is the signal RIN2, which is the signal from the output terminal SROUT of the sequential circuit 30a_n+3. The following is entered.

[0117] Specifically, the sequential circuit 30a_1 consists of signals CK1, CK2, CK3, and PW. C1, signal RES, signal SP, output signal of sequential circuit 30a_3, and sequential circuit 30a_4 The output signals are each input, and the output signals are output to wiring OUT1. Sequential circuit 30a _2 consists of signals CK2, CK3, CK4, PWC2, RES, and sequential circuit 3. The output signal of 0a_1, the output signal of sequential circuit 30a_4, and the output signal of sequential circuit 30a_5 The signal CK3 is input and outputs to wiring OUT2. Sequential circuit 30a_3 is for signal CK3 Signals CK4, CK1, PWC3, RES, and the output signal of sequential circuit 30a_2 The output signals of sequential circuit 30a_5 and sequential circuit 30a_6 are input and wired together. The output signal is output to OUT3. The sequential circuit 30a_4 is signal CK4, signal CK1, signal CK2, signal PWC4, signal RES, output signal of sequential circuit 30a_3, sequential circuit 30a_ The output signal of 6 and the output signal of sequential circuit 30a_7 (not shown) are input, wiring OU The output signal is output to T4. The sequential circuit 30a_5 outputs signals CK1, CK2, and CK 3. Signal PWC1, signal RES, output signal of sequential circuit 30a_4, sequential circuit 30a_7( The output signal of (not shown) and the output signal of sequential circuit 30a_8 (not shown) are input , and outputs the output signal to wiring OUT5. The sequential circuit 30a_6 receives the signal CK2, signal CK3 , signal CK4, signal PWC2, signal RES, the output signal of sequential circuit 30a_5, sequential circuit 3 0a_8 (not shown), and the output signal of sequential circuit 30a_9 (not shown) are input, and outputs the output signal to wiring OUT6.

[0118] Fig. 8C shows a timing chart related to the driving method of the driving circuit 40a. In Fig. 8 C, the transition of the potential change is shown for each of the signal RES, signal SP, signals CK1 to CK4, and wirings OUT1 to OUT6 from top to bottom. For signals PWC1 to signal PWC4, since clock signals having the same phase and period as signals CK1 to CK4 are used respectively, they are shown together .

[0119] Before time T0 shown in Fig. 8C, the signal SP is at a high potential and the signal CK1 is at a low potential . At this time, a low potential is output to wirings OUT1 to OUT6.

[0120] At time T0, when the signal CK1 (signal PWC1) changes from a low potential to a high potential, a high potential is output from the sequential circuit 30a_1 to the wiring OUT1. Thereafter, due to signals CK1 to signal C K4 and signals PWC1 to PWC4, high potentials are sequentially output to the wirings after wiring OUT2 . Signals CK1 to CK4 are signals that are shifted by one-quarter cycle in order. Similarly

[0121] , signals PWC1 to PWC4 are also signals that are shifted by one-quarter cycle in order . Therefore, as shown in Figure 8C, the wiring OUT1 to OUT6 etc. are connected to signals such as CK1 etc. The signals are output in that order, each shifted by one-quarter of a period.

[0122] Furthermore, during the period when a high potential is output to wiring OUT1 through OUT6, etc., signals such as CK1, etc. This corresponds to a period of half a cycle. That is, the period during which the wiring OUTn is at a high potential, and the wiring The period when OUTn+1 is at a high potential is superimposed. This leads to the selection of wiring OUTn. Because it allows for a longer period of operation, this type of drive is suitable when the wiring load is heavy. It is preferable to use this method. That is, the drive circuit 40a is used for display devices with a large number of pixels, and When using a scanning line drive circuit for a large-screen display device, such a drive method may be used. Using this method is preferable because it allows for a longer charging and discharging period for the scan lines. Note that the signal CK is used here. As signals 1 through CL4, use a 4-phase clock signal shifted by 1 / 4 period, and wire OUT. By setting the period during which n is at a high potential (selected) to the period of half a period of the signal CK1, etc. The configuration includes a period during which two adjacent wires are selected simultaneously, but is not limited to this. For example, by changing the period of the clock signal or the duty cycle, three adjacent lines The above wiring configuration may be selected simultaneously.

[0123] [Example of drive circuit configuration 2] The following describes a signal generation circuit that differs in some configurations from the signal generation circuit 14a exemplified in Figure 6 above. Let's explain some examples of road configurations.

[0124] Figure 9 shows the circuit diagram of the signal generation circuit 14b. The signal generation circuit 14b generates the signal BDG. This is a circuit that performs the following. Compared with the above signal generation circuit 14a, the signal R Since this configuration does not use IN2, the number of wires can be reduced.

[0125] The signal generation circuit 14b includes transistors 60 through 69, transistor 71, It also has a transistor 72.

[0126] Transistor 60 receives a signal LIN at its gate, and an electric current is supplied to either its source or drain. A terminal VDD is given, and the other is electrically connected to the gate of transistor 71. In sta 61, a signal CLK3 is applied to the gate, and a potential VDD is applied to either the source or the drain. One is given, and the other is electrically connected to the gate of transistor 71. Transistor 62 The signal RIN1 is applied to the gate, and the potential VDD is applied to either the source or the drain. The other end is electrically connected to the gate of transistor 71. Transistor 63 is connected to the gate A signal CLK1 is applied to the gate, and one of the source and drain is connected to the gate of transistor 71. One end is electrically connected to the other, and the other end is electrically connected to either the source or drain of transistor 64. Transistor 64 is subjected to the signal CLK2 at its gate, and its source and drain are... A potential VSS is applied to the other side. The signal CLK2 is applied to the gate of transistor 65. A potential VDD is applied to one of the source and drain, and the other is the source of transistor 66. And it is electrically connected to one of the drains. Transistor 66 receives the signal CLK1 at its gate. Given, the source and the other drain are electrically connected to the gate of transistor 72. Transistor 67 is subjected to the signal LIN at its gate, and either its source or drain is It is electrically connected to the gate of transistor 72, and a potential VSS is applied to the other side. The zista 68 is subjected to the signal CLK3 at its gate, and either the source or drain is transient. It is electrically connected to the gate of transistor 72, and potential VSS is applied to the other side. Transistor 6 9 is a transistor 72 to which the signal RIN1 is applied to the gate, and one of the source and drain is connected. It is electrically connected to the gate of and a potential VSS is applied to the other side. Transistor 71 is a so A potential VDD is applied to one of the source and drain of transistor 72, and the other is the source and drain of transistor 72. One of the drains and the wiring to which the signal BDG is output are electrically connected. Transistor In circuit 72, a potential VSS is applied to the source and the other drain.

[0127] The signal generation circuit 14b has a duty cycle of 45% or more and 55% or less, preferably a duty cycle of Generate a signal BDG with a ratio of 45% to 51%, typically between 50% and 51%. Therefore, compared to using the potential VDD instead of the signal BDG, high High reliability can be achieved.

[0128] By configuring the signal generation circuit 14b in this way, it supplies signals to circuits 13 and 11a. The signal BDG can be generated using only the signal.

[0129] [Example of drive circuit configuration 3] The following describes an example of a drive circuit configuration that does not use a signal generation circuit.

[0130] Figure 10 shows the circuit diagram of the sequential circuit 30b. The sequential circuit 30b uses the signal generation circuit 14a It differs primarily from the above sequential circuit 30a in that it does not have [a certain feature].

[0131] The sequential circuit 30b is configured to use the signal CLK3 as the signal BDG. Compared to the above sequential circuit 30a, the signal RIN2 and the signal generation circuit 14a can be used. Therefore, the configuration can be simplified.

[0132] Figure 11 shows a timing chart for an example of a driving method for the sequential circuit 30b. In 11, the signals are CLK1 (PWC), CLK2, CLK3, RES, and Node LIN, signal RIN1, signal BDG, node N1 (node ​​N2), and output terminal SRO This diagram schematically shows the time variation of the potential at UT (output terminal GOUT).

[0133] As shown in Figure 11, signals BDG and CLK3 are the same signal.

[0134] At time T21, when signal BDG is at a high potential and signal LIN is at a high potential, Nodes N1 and N2 become high potential. Subsequently, at time T22, signal CLK1 Furthermore, as the signal PWC becomes high potential, the potentials of nodes N1 and N2 rise. Furthermore, during the period T22-T24, a high potential is output to the output terminals SROUT and GOUT. At this time, the signal BDG becomes low potential, and transistor 23 and transistor Since 26 is in the off state, nodes N1 and N2 are electrically floating. Yes. Next, at time T24, signal LIN is at a low potential and signal RIN1 is at a high potential. As the signal BDG becomes high potential, transistors 23 and 26 turn on again. Therefore, the potentials of nodes N1 and N2 drop to a low potential. As a result, the output terminal S A low potential is output to ROUT and the output terminal GOUT. Then, at time T26, the signal BD G becomes low potential. From here on, high and low potentials are repeatedly input as the signal BDG. Since both signal LIN and signal RIN1 are at a low potential, the output terminal SROUT and the output terminal GOUT maintains a low potential.

[0135] Since the sequential circuit 30b uses the clock signal as the signal BDG, the signal BD As G, the duty cycle is 45% or more and 55% or less, preferably 45% or more. A pulse signal with a pulse strength of 51% or less, typically 50%, can be used. Compared to using potential VDD instead of BDG, higher reliability can be achieved. .

[0136] Figure 12A shows a diagram illustrating the input and output terminals of the sequential circuit 30b. The sequential circuit 30b is as follows: Compared to the sequence circuit 30a, it differs in that it does not have a terminal to which the signal RIN2 is input. ru.

[0137] Furthermore, Figure 12B shows an example configuration of the drive circuit 40b using the sequential circuit 30b. The drive circuit 40b receives the signal RIN2 from the sequential circuit 30a_n in the drive circuit 40a. The configuration is the same except that it does not have terminals to be powered or wiring to connect them.

[0138] Furthermore, Figure 12C shows a timing chart relating to the driving method of the drive circuit 40b. As shown in Figure 12C, the same output signal is obtained using the same driving method as the driving circuit 40a. It is possible.

[0139] The drive circuit illustrated here is a shift register that sequentially applies pulse signals to multiple wires. Because it functions in this way, it is suitable for use in the gate driver circuit (scan line driving circuit) of a display device. This is possible. Furthermore, the shift register circuit is not limited to display devices; it can also be applied to memory devices and other applications. It can be suitably used in a variety of devices.

[0140] The above is a description of an example of a drive circuit configuration.

[0141] [Example of transistor configuration] Below are some examples of transistor configurations that can be used in the sequential circuits exemplified above. I will explain.

[0142] The transistor illustrated below has a pair of gates sandwiching a semiconductor layer, and one of the gates The circuit has a configuration in which the source and one of the drains are electrically connected. An example is given below. The transistor is applied to transistor 21, etc., in the sequential circuit exemplified above. It is possible.

[0143] Note that the gate, source, and drain connections of the transistor exemplified below will be changed. Therefore, in the sequential circuit exemplified above, transistors 22 and 23, etc. A transistor applicable to the transistor can be fabricated. For example, a pair of gates A transistor with two gates electrically connected, or a transistor with only one gate, By changing the connection points of the conductive layer or the shape (pattern) of the conductive layer, the following transformers can be created, as illustrated below. It can be manufactured in the same way as ZISTA.

[0144] [Configuration Example 1] Figure 13A shows a schematic top view of transistor 100. Figure 13B shows the same top view as in Figure 13A. Figure 13C corresponds to a cross-sectional view of the cross-section along the dashed line A1-A2 in Figure 13A, and one point in Figure 13A This corresponds to the cross-sectional view of the section along the dashed line A3-A2. Note that in Figure 13A, the transition Some components of STA100 (such as the gate insulating layer) are omitted in the illustration. The direction of line A1-A2 includes the channel length direction of transistor 100, and the dashed line A3-A2 The direction includes the channel width direction of transistor 100. Also, the top view of the transistor is shown. Therefore, in subsequent drawings, as with Figure 13A, some of the components will be omitted from the illustration. Let's assume that.

[0145] The transistor 100 is provided on the substrate 102 and has a conductive layer 106a, an insulating layer 103, and a semiconductor It has a conductive layer 108, an insulating layer 110, a conductive layer 112a, etc. The conductive layer 106a is on the substrate 10 2 is provided on top. The insulating layer 103 is provided covering the substrate 102 and the conductive layer 106a, etc. The island-shaped semiconductor layer 108 is provided on the insulating layer 103 and overlaps with the conductive layer 106a. It has the following characteristics. The insulating layer 110 is provided covering the semiconductor layer 108 and the insulating layer 103. Conductive Layer 112a is provided on the insulating layer 110 and superimposed on the semiconductor layer 108 and the conductive layer 106a. It has a region.

[0146] Furthermore, an insulating layer 118 is provided covering the conductive layer 112a and the insulating layer 110.

[0147] In transistor 100, a portion of the conductive layer 112a is the first gate electrode (top gate It functions as a gate electrode, and a part of the conductive layer 106a is a second gate electrode ( It functions as a bottom gate electrode. In addition, a part of the insulating layer 110 is the first It functions as the gate insulating layer, and a portion of the insulating layer 103 functions as the second gate insulating layer. ru.

[0148] The semiconductor layer 108 preferably contains a metal oxide. For example, indium and M(M These are gallium, aluminum, silicon, boron, yttrium, tin, copper, and vanadium. Beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, rancid Tan, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium Preferably, M is a selected one or more, and zinc. It must be one or more species selected from tin, gallium, yttrium, and tin. In particular, the semiconductor layer 108 contains an oxide containing indium, gallium, and zinc. It is preferable to use IGZO (also written as IGZO). Alternatively, indium, tin, and zinc may be used. It is preferable to use oxides containing the following: or indium, gallium, tin, and zinc. It is preferable to use an oxide containing [the specified compound].

[0149] The semiconductor layer 108 has a region 108i that functions as a channel formation region, and region 108i It has a pair of low-resistance regions 108n provided on either side. One side functions as the source region of transistor 100, and the other side functions as the drain region. Region 108i overlaps with at least one of the conductive layer 112a and the conductive layer 106a. In Figure 13B, the portion of the semiconductor layer 108 that overlaps with the conductive layer 112a is defined as a channel formation region. Although shown as a functional region 108i, it does not actually overlap with the conductive layer 112a, and the conductive layer If a channel is also formed in the portion overlapping with 106a (the portion including the low-resistance region 108n) There are also others.

[0150] Furthermore, the low-resistance region 108n is a region with lower resistance and carrier concentration than the channel-forming region. This region is also known as a high-density region, a region with high oxygen defect density, a region with high impurity concentration, or an n-type region. It can be said that.

[0151] The low-resistance region 108n of the semiconductor layer 108 may be a region containing an impurity element. The Examples of the impurity element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, or noble gas. Representative examples of noble gas include helium, neon, argon, krypton, and xenon. In particular, it is preferable to contain boron or phosphorus. These elements may also be contained in two or more.

[0152] The process of adding an impurity to the low-resistance region 108n can be performed through the insulating layer 110 using the conductive layer 112a as a mask.

[0153] The low-resistance region 108n has an impurity concentration of 1×10 19 atoms / cm 3 or more and 1×1 0 23 atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or more and 5× 10 22 atoms / cm 3 or less, more preferably 1×10 20 atoms / cm 3 or more and 1×10 22 atoms / cm 3 or less, and preferably includes a region having such an impurity concentration.

[0154] The concentration of the impurity contained in the low-resistance region 108n can be analyzed by, for example, secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry), or X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy). When using XPS analysis, on the surface side Alternatively, ion sputtering from the back side and analysis such as SIMS analysis or XPS analysis. By combining this method with other techniques, it is possible to determine the concentration distribution in the depth direction.

[0155] In particular, when hydrogen is used as an impurity element, a neutron beam analysis method is used. That's good.

[0156] Furthermore, in the low-resistance region 10⁸n, impurity elements exist in an oxidized state. Preferred. For example, boron, phosphorus, magnesium, aluminum, and cinnabar are used as impurity elements. It is preferable to use easily oxidizable elements such as lycon. Therefore, in a later process, it can exist stably in an oxidized state by bonding with oxygen in the semiconductor layer 108. When exposed to high temperatures (for example, 400°C or higher, 600°C or higher, or 800°C or higher) Even if present, their detachment is suppressed. Furthermore, impurity elements can remove oxygen from the semiconductor layer 108. As a result, many oxygen vacancies are generated in the low-resistance region 10⁸n. These oxygen vacancies and the membrane Because it becomes a carrier source by bonding with hydrogen, the low resistance region 108n is extremely low resistance It becomes a resistive state.

[0157] For example, when boron is used as an impurity element, the boron contained in the low resistance region 10⁸n It can exist in a state bound to oxygen. This means that in XPS analysis, the B2O3 bond... This can be confirmed by observing the resulting spectral peak. Furthermore, in XPS analysis, The spectral peaks caused by the element boron existing in its elemental form are not observed, or are not measured. The peak intensity is so low that it is buried in the background noise observed near the lower limit. It becomes smaller.

[0158] The region of the insulating layer 110 that overlaps with the low-resistance region 108n contains the aforementioned impurity elements. In this case, the impurity elements in the insulating layer 110 may be similar to those in the low-resistance region 108n. It is preferable that it exists in a state of being bonded with oxygen. Such easily oxidized elements are insulating. Because it can exist stably in an oxidized state by bonding with oxygen in layer 110, it can be subjected to high temperatures in subsequent processes. Even if heat is applied, detachment is suppressed. In particular, detachment in the insulating layer 110 due to heating If the mixture contains oxygen that can be released (also called excess oxygen), the excess oxygen and the impurity elements will In order to bond and stabilize, oxygen is supplied from the insulating layer 110 to the low-resistance region 108n. This can suppress the oxidized state of impurity elements in the insulating layer 110. Because the part is in a state where oxygen does not easily diffuse, the insulating layer 110 is above the insulating layer 11 The supply of oxygen to the low-resistance region 108n via 0 is suppressed, and the low-resistance region 108n This also prevents the resistance from increasing.

[0159] The insulating layer 103 is formed by laminating insulating film 103a and insulating film 103b from the substrate 102 side. It has a laminated structure. In this case, the insulating film 103a located on the conductive layer 106a side has a conductive layer It is preferable to use an insulating film that does not easily diffuse the metal elements contained in 106a. For example, nitride Inorganic insulating films such as silicon films, silicon nitride films, aluminum oxide films, and hafnium oxide films. It is preferable to use a border film. In addition, the insulating film 103b in contact with the semiconductor layer 108 contains oxygen It is preferable to use an insulating film containing a silicon oxide film or silicon oxide nitride. It is preferable to use a membrane or the like.

[0160] The insulating layer 103 may be a single layer or a laminated structure consisting of three or more layers. It may have. Also, in Figures 13B and 13C, the insulating layer 110 is shown as a single-layer structure. However, it may also have a laminated structure in which two or more layers are stacked.

[0161] In Figures 13B and 13C, the insulating layer 110 is provided so as to cover the edge of the semiconductor layer 108. The example shown is that the configuration is not limited to this. For example, the insulating layer 110 may be the conductive layer 112 a may be processed so as to roughly match the top surface shape. In this case, the semiconductor layer 108 The upper surface of the low-resistance region 108n is in contact with the insulating layer 118.

[0162] In this specification, "approximately identical top surface shape" means that there is a small difference between the two stacked layers. This refers to the overlap of at least part of the outline. For example, the upper and lower layers using the same mask pattern. This includes cases where the mask pattern is the same for all or part of the product. However, strictly speaking, The outlines do not overlap, and the upper layer is located inside the lower layer, or the upper layer is located outside the lower layer. In some cases, this is described as "the top surface shape being roughly the same."

[0163] Furthermore, even if a layer that functions as a barrier film is provided between the conductive layer 112a and the insulating layer 110, Good. For example, a metal film, alloy film, or metal oxide film can be used with a conductive layer 112a and an insulating layer 110 It can also be provided between them. The layer that functions as a barrier film is at least an insulating layer 1 Using a material that is less permeable to oxygen and hydrogen, preferably both, than 10. This is preferable. This allows oxygen to diffuse from the semiconductor layer 108 to the conductive layer 112a, and This prevents hydrogen from diffusing from the conductive layer 112a to the semiconductor layer 108. Therefore, the carrier density of region 108i, which functions as a channel formation region of semiconductor layer 108, It can be made extremely low. It can be used in the layer that functions as the barrier film. Examples of metal oxide films include aluminum oxide films, hafnium oxide films, and hafnium aluminum films. Oxide insulating films such as tarnish films, or indium oxide, indium tin oxide, silicon A conductive oxide film such as indium tin oxide containing can be used.

[0164] Alternatively, as a metal oxide film that functions as a barrier film, the same elements as the semiconductor layer 108 may be used. Oxide material containing one or more of these, preferably using the same sputtering target as the semiconductor layer 108. It is preferable to apply a metal oxide film formed by sputtering. When forming a metal oxide film, forming it in an atmosphere containing oxygen gas ensures that the insulating layer 110 is formed in an atmosphere containing oxygen gas. Alternatively, oxygen can be suitably added to the semiconductor layer 108, etc. Furthermore, the metal oxide film can be... When formed for the purpose of supplying oxygen to the insulating layer 110 or the semiconductor layer 108, gold The oxide film may be removed after it has been formed.

[0165] Furthermore, as shown in Figures 13A and 13B, the transistor 100 is on the insulating layer 118. It has conductive layers 120a and conductive layers 120b. Conductive layer 120a is the source electrode and drain One electrode functions as one of the electrodes, and the conductive layer 120b functions as the other of the source electrode and drain electrode. The conductive layer 120a and the conductive layer 120b are the insulating layer 118 and the insulating layer 110, respectively. In the opening 141a or opening 141b provided therein, the low-resistance region of the semiconductor layer 108 It is electrically connected to region 108n.

[0166] The insulating layer 118 functions as a protective layer to protect the transistor 100. For example, inorganic insulating materials such as oxides or nitrides can be used. Specific examples include silicon oxide, silicon oxide nitride, silicon nitride, and silicon oxide nitride. Aluminum oxide, aluminum nitride oxide, aluminum nitride, hafnium oxide, haf Inorganic insulating materials such as nium aluminate can be used.

[0167] Furthermore, as shown in Figures 13A and 13C, in the channel width direction, the conductive layer 112a Furthermore, it is preferable that the conductive layer 106a extends outward beyond the edge of the semiconductor layer 108. At this time, as shown in Figure 13C, the entire channel width direction of the semiconductor layer 108 is the insulating layer. The structure is such that 110 is covered by conductive layers 112a and 106a via an insulating layer 103. .

[0168] The transistor 100 has a conductive layer 106a that functions as a back gate, and a source electrode and The conductive layer 120b, which functions as the other side of the drain electrode, is electrically connected to it. Specifically, conductive layer 106a and conductive layer 120b conduct electricity through conductive layer 112b. They are directly connected.

[0169] The conductive layer 112b is located on the same plane as the conductive layer 112a of the transistor 100, and is the same This is a layer formed by processing a conductive film. Conductive layer 112b and conductive layer 106a are insulated from insulating layer 1 The opening 143 provided in the 10 and the insulating layer 103 is electrically connected. Furthermore, the conductive layer 120b and the conductive layer 112b are separated by an opening 144 provided in the insulating layer 118. They are electrically connected. This connects the source and drain of transistor 100. One of these is electrically connected to the back gate. In this way, Openings are formed in the insulating layer 118, insulating layer 110, and insulating layer 103, and the conductive layer 120b and the conductive layer Instead of directly connecting to the conductive layer 106a, the electrical connection is made via the conductive layer 112b. This is preferable. This allows the depth of the opening to be shallower, resulting in a lower step at the opening. As a result, the stepped coverage of the conductive film covering the opening is improved, and the stepped area cannot be completely covered, resulting in the conductive film This prevents problems such as the system becoming fragmented.

[0170] Furthermore, in Figures 13A and 13C, the conductive layer 112a, which functions as the top gate, is used for wiring. It is electrically connected to conductive layer 106b, which functions as conductive layer 112a and conductive layer 10 6b refers to the opening 142 provided in the insulating layer 110 and the insulating layer 103, which electrically They are connected. The conductive layer 106b is located on the same plane as the conductive layer 106a, and is the same It is preferable that the layer is formed by processing a conductive film.

[0171] For example, transistor 100 is connected to transistor 21 in the sequential circuit 30 illustrated in Figure 5A. Alternatively, when applied to transistor 24, the conductive layer 106b is electrically connected to the wiring 15b. In response to the wiring, the conductive layer 120a electrically connects to output terminal GOUT or output terminal SROUT. Corresponding to the wiring to which it is connected, the conductive layer 120b corresponds to the wiring to which the potential VSS is applied.

[0172] Here, an oxide film is used for the insulating film 103b that is in contact with the semiconductor layer 108 of the insulating layer 103. Preferably, a silicon oxide film or silicon oxidnitridation film that can release oxygen upon heating is preferred. It is preferable to apply a recon film. This allows the transistor 100 to be manufactured during the manufacturing process. Oxygen released from the insulating layer 103 due to slight heat is supplied to the semiconductor layer 108, and the semiconductor Because oxygen deficiency in body layer 108 can be reduced, a highly reliable transistor 100 This can be achieved.

[0173] At this time, after the insulating film 103b has been formed and before the semiconductor layer 108 has been formed, It is preferable to perform a process to supply oxygen to 103b. Treatment options include plasma treatment or heat treatment in an oxygen-containing atmosphere. Alternatively, insulating film 1 can be formed by ion doping or ion implantation. Oxygen may be supplied to 03b. Alternatively, as described above, oxygen may be included on the insulating film 103b. By forming a metal oxide film by sputtering in a certain atmosphere, the insulating film 103b Oxygen may be supplied to the metal oxide film, and then the metal oxide film may be removed. Alternatively, the semiconductor layer 108 may be The semiconductor layer 108 is formed by sputtering in an oxygen-containing atmosphere. The process can also be combined with the process of supplying oxygen to the insulating film 103b.

[0174] Furthermore, if the insulating film 103b contains excess oxygen, the semiconductor layer 108 and the insulating film 103b Defect levels are likely to be generated at or near the interface with the second G When a high potential is applied to the conductive layer 106a, which functions as a lead electrode, a carrier is generated at the defect level. A certain electron gets trapped, and the threshold voltage of transistor 100 shifts to positive. However, in transistor 100, it is provided via an insulating layer 103. The conductive layer 106a, which functions as a second gate electrode, is subjected to a source potential (e.g., potential VSS). Because of this, carriers are present at or near the interface between the semiconductor layer 108 and the insulating film 103b. This is hardly induced. As a result, even if the above defect levels exist, electrons are trapped. Because this creates a state where the voltage is less likely to shift, the positive shift in the threshold voltage can be effectively suppressed. Therefore, transistor 100 can be considered an extremely reliable transistor.

[0175] [Configuration Example 2] Figure 14A shows transistor 100A, which has a slightly different configuration from transistor 100. A schematic top view is shown. Figure 14B shows the cross section along the dashed line B1-B2 in Figure 14A. This corresponds to a cross-sectional view, and Figure 14C is a cross-sectional view of the section along the dashed line B3-B2 in Figure 14A. It corresponds to this.

[0176] Transistor 100A has a conductive layer 112a that functions as the top gate and a conductive layer 12 It has a configuration in which 0b and are electrically connected. In the following, it is common with the above transistor 100. I will omit explanations for parts that are similar and mainly explain the parts that differ.

[0177] The conductive layer 120b and the conductive layer 112a are separated by an opening 144 provided in the insulating layer 118. They are electrically connected.

[0178] Furthermore, a portion of the conductive layer 106a functions as wiring.

[0179] For example, transistor 100A is transistor 21 in the sequential circuit 30 illustrated in Figure 5A. Alternatively, when applied to transistor 24, the conductive layer 106a is electrically connected to the wiring 15b. In accordance with the wiring, the conductive layer 120a provides electrical connections to the output terminal GOUT or output terminal SROUT. Corresponding to the wiring that is directly connected, the conductive layer 120b corresponds to the wiring to which the potential VSS is applied. .

[0180] In transistor 100A, the insulating layer 110 contains an oxide that can release oxygen upon heating. It is preferable to apply a film. This reduces the time required during the manufacturing process of transistor 100A. Oxygen released from the insulating layer 110 due to heat, etc., is supplied to the semiconductor layer 108, Because it can reduce oxygen deficiency in 10⁸, a highly reliable transistor 100A can be created. It can be achieved.

[0181] At this time, after the insulating layer 110 has been formed and before the conductive layer 112a etc. is formed, the insulating layer It is preferable to perform a process to supply oxygen to the insulating layer 110. Theoretically, this could involve plasma treatment or heat treatment in an oxygen-containing atmosphere. Alternatively, The insulating layer 110 is subjected to acid doping or ion implantation. A component may be supplied. Alternatively, as described above, under an oxygen-containing atmosphere on the insulating layer 110. By forming a metal oxide film using the sputtering method, oxygen is supplied into the insulating layer 110. The metal oxide film may be removed after film formation, and the conductive layer 112a and insulating layer 1 It may be left in place between 10 and 10.

[0182] Furthermore, if the insulating layer 110 contains excess oxygen, the relationship between the semiconductor layer 108 and the insulating layer 110 will be affected. Defect levels are prone to forming at or near the interface. Therefore, conductive layer 112a When a high potential is applied, the threshold voltage of transistor 100A shifts to positive. There is a risk of this happening. However, in transistor 100A, as the first gate electrode Because a source potential (e.g., potential VSS) is applied to the functional conductive layer 112a, the semiconductor layer Even if a defect level exists at or near the interface between 108 and the insulating layer 110, the transient The positive shift in the threshold voltage of the 100A transistor can be suppressed. The ZISTA 100A is an extremely reliable transistor.

[0183] [Configuration Example 3] The following describes an example of a configuration having two transistors and a capacitor.

[0184] Figure 15A shows transistor 100, transistor 150, and capacitor 160 connected. A schematic top view of the configuration is shown. Also, Figure 15B shows the area C1-C2 in Figure 15A. This corresponds to a cross-sectional view of the cut surface, and Figure 15C shows the cut surface along the dashed line C3-C4 in Figure 15A. This corresponds to a cross-sectional view. Figure 15B shows a cross-section of transistor 150 in the channel length direction and capacitance. Figure 15C includes a cross-section of transistor 150 in the channel width direction.

[0185] Furthermore, Figure 16 shows the upper surface of Figure 15A excluding conductive layers 120a to 120c. A schematic diagram is shown. In Figure 16, only the outlines of conductive layers 120a to 120c are shown as dashed lines. This is shown.

[0186] Transistor 100 has a second gate electrode (bottom gate electrode) located on the substrate 102 side. ) is a transistor in which one of the source and drain is electrically connected, as shown in Figure 1 above. The configuration exemplified in 3A, etc., can be used as a basis.

[0187] Transistor 150 is located on the same plane as transistor 100 and is manufactured through the same process. This is a transistor that is manufactured. Transistor 150 has a pair of gates that are electrically connected. It has the following configuration.

[0188] Capacitor 160 is manufactured using the same process as transistors 100 and 150. It is possible.

[0189] The transistor 150 has a conductive layer 106c, part of which functions as a second gate electrode, and The insulating layer 103, which functions as a second gate insulating layer, and the semiconductor layer 108a, and a part of the An insulating layer 110 that functions as a gate insulating layer, and a portion of which functions as a first gate electrode. It has a conductive layer 112c and a semiconductor layer 108a which functions as a channel formation region. Region 108ai and a pair of low-resistance regions 108an that function as source and drain To possess.

[0190] Furthermore, transistor 150 is electrically connected to one of the pair of low-resistance regions 108an. It has a conductive layer 120c and a conductive layer 120a that is electrically connected to the other. Point a is electrically connected to the low-resistance region 108n (not shown) of transistor 100. The conductive layer 120a and the conductive layer 120c are provided on the insulating layer 118 and the insulating layer 110, respectively. In the opening 141d or opening 141c, the low-resistance region 108an is electrically connected. It is being done.

[0191] Furthermore, as shown in Figures 15A and 15C, the conductive layer 112c and the conductive layer 106c are, In the openings 145 provided in the insulating layer 110 and the insulating layer 103, electrically connected In other words, the transistor 150 is provided with a pair of gates on either side of the semiconductor layer 108a. The electrodes have an electrically connected configuration.

[0192] With this configuration, the semiconductor layer 108a is connected by a pair of gate electrodes to generate electricity It can be electrically surrounded in the boundary. In particular, conductive layer 106c and conductive layer 112c The same potential is applied to this. This induces a channel in the semiconductor layer 108a. Because an electric field can be applied effectively, the on-current of transistor 150 can be increased. Therefore, it becomes possible to miniaturize transistor 150.

[0193] Furthermore, the conductive layer 112c and the conductive layer 106c may not be connected. In this case, A constant potential is applied to one of the pair of gate electrodes, and a signal is used to drive the transistor 150 on the other. A voltage may be given. At this time, the potential applied to one of the gate electrodes determines the transistor 15 It is also possible to control the threshold voltage when driving 0 with the other gate electrode.

[0194] Capacitance 160 is due to a portion of the semiconductor layer 108a (part of the low-resistance region 108an) and the insulating layer 1 It is composed of a part of 03 and a part of the conductive layer 106c. Capacitance 160 is the insulating layer 103 functions as a dielectric layer, and the conductive layer 106c and the semiconductor layer 108a each form a pair. It functions as an electrode.

[0195] Furthermore, in the region where the low-resistance region 108an and the conductive layer 106c overlap, the insulating layer 118 Furthermore, a plurality of openings 141e are provided in the insulating layer 110, and in the openings 141e, The conductive layer 120a and the low-resistance region 108an are electrically connected. 20a is added to function as either the source or drain electrode of transistor 150. It functions as an auxiliary wiring (auxiliary electrode) with a capacity of 160. Furthermore, the conductive layer 120a has low resistance By making contact with the anti-region 108an at multiple points, these contact resistances can be reduced. This is preferable because it reduces the parasitic resistance of a capacitance of 160. Also, as a pair of electrodes with a capacitance of 160 A configuration using conductive layer 106c and conductive layer 112c, or conductive layer 106c and conductive layer Compared to the configuration using 120a, the configuration using conductive layer 106c and low-resistance region 108an This allows for a reduction in the thickness of the insulating layer, which functions as a dielectric layer, thereby increasing capacitance. It is possible.

[0196] As shown in Figures 15A and 16, the conductive layer 120a is the source of transistor 100. One of the electrodes and the drain electrode, and one of the source electrode and the drain electrode of transistor 150. Furthermore, it can also serve as one of the electrodes with a capacitance of 160. Also, the island-shaped semiconductor layer 108a This can serve as part of transistor 150 and part of capacitor 160. This configuration allows for a reduction in the area occupied by the circuits shown in Figures 15A and 16. .

[0197] The configuration shown in Figure 15A, etc., can be applied to a part of the above sequential circuit. For example, Figure 5 When applied to the sequential circuit 30 illustrated in B, either transistor 21 or transistor 24 Transistor 100 is replaced by transistor 150 with transistor 22 or transistor 25. A capacity of 160 can be applied to either capacity C1 or capacity C3, respectively. The conductive layer 106b corresponds to the wiring that is electrically connected to the wiring 15b, and the conductive layer 120a is Corresponds to wiring electrically connected to the power terminal GOUT or output terminal SROUT, conductive layer 1 20b corresponds to the wiring to which potential VSS is applied, and the conductive layer 106c is transistor 23 This corresponds to the wiring that is electrically connected to the wiring 15a via the transistor 26, and the conductive layer 12 0c corresponds to a wire to which the signal CLK1 or signal PWC is applied.

[0198] The above is an explanation of an example of transistor configuration.

[0199] [Example of manufacturing method] The following describes an example of a method for manufacturing a transistor according to one aspect of the present invention. , the transistor configuration example 1 in the above transistor configuration example and the transistors illustrated in Figures 13A to 13C Let's explain using the 'Njista 100' as an example.

[0200] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices are produced by sputtering. Chemical vapor deposition (CVD) method Vacuum deposition, pulsed laser deposition (PLD) tion) method, Atomic Layer Deposition (ALD) method It can be formed using methods such as the CVD method. CVD methods include plasma chemical vapor deposition (PE This includes methods such as CVD (Plasma-Enhanced CVD) or thermal CVD. Furthermore, one of the thermal CVD methods is metal-organic chemical vapor deposition (MOCVD). There is also the anic CVD method.

[0201] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices are spin-coated. Dip, spray coating, inkjet, dispensing, screen printing, offset Printing, doctor's knife, slit coat, roll coat, curtain coat, knife coat It can be formed by methods such as those listed above.

[0202] Furthermore, when processing the thin films that make up semiconductor devices, photolithography and other methods are used. It can be processed using nanoimprint lithography, sandblasting, and lift-off. Thin films may be processed using methods such as the F method. Alternatively, a shielding mask such as a metal mask may be used. Island-like thin films may be directly formed by a film-forming method.

[0203] There are two main methods of photolithography. One is to process the image... A resist mask is formed on a thin film, and the thin film is processed by etching or the like, and the resist This is a method for removing the mask. Another method is to deposit a photosensitive thin film and then expose it to light. This method involves developing the film and then processing it into a desired shape.

[0204] In photolithography, the light used for exposure is, for example, the i-line (wavelength 365 nm). Using g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof This can be done by using ultraviolet light, KrF laser light, or ArF laser light, etc. It is also possible to perform exposure using immersion lithography. Furthermore, the light used for exposure and Extreme ultraviolet (EUV) light or X-rays Any of these may be used. Furthermore, an electron beam can be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or electron beams are preferred because they enable extremely fine processing. It is important to note that when exposure is performed by scanning a beam such as an electron beam, photo Masks are not necessary.

[0205] Thin film etching methods include dry etching, wet etching, and sandblasting. Laws and other regulations can be used.

[0206] Figures 17A to 18D show cross-sectional views of each stage in the manufacturing process of transistor 100. This is shown. In Figures 17A to 18D, to the left of the dashed line, the transistor 100 is shown. The cross-section in the channel length direction is shown on the right, and the cross-section in the channel width direction is shown side by side.

[0207] [Formation of conductive layer 106a] A conductive film is formed on the substrate 102, and this is processed by etching to form a second gate electrode. A conductive layer 106a is formed that functions as such (Figure 17A).

[0208] At this time, as shown in Figure 17A, the end of the conductive layer 106a is tapered. It is preferable to carry out the process. This improves the step coverage of the insulating layer 103 to be formed next. It is possible.

[0209] Furthermore, by using a conductive film containing copper as the conductive film that forms the conductive layer 106a, the wiring resistance This can reduce the size of displays, for example, large displays or high-resolution displays. When applying transistor 100, a conductive film containing copper is used for the conductive layer 106a. Preferably. Also, even if a conductive film containing copper is used for the conductive layer 106a, the insulating layer 1 Because 03 suppresses the diffusion of copper elements towards the semiconductor layer 108, a highly reliable It is possible to implement Rangista.

[0210] [Formation of insulating layer 103] Next, an insulating layer 103 is formed by covering the substrate 102 and the conductive layer 106a (Figure 17B). The insulating layer 103 is formed using methods such as PECVD, ALD, and sputtering. It is possible.

[0211] Here, the insulating layer 103 is formed by laminating insulating film 103a and insulating film 103b. In particular, each insulating film constituting the insulating layer 103 is preferably formed by the PECVD method. It's nice.

[0212] Examples of insulating film 103a include silicon nitride film, silicon nitride oxide film, and aluminum nitride film. Insulating films containing nitrogen, such as um film and hafnium nitride film, can be used. As 103a, a dense silicon nitride film deposited using a PECVD apparatus is used. This is preferable. By using such a nitrogen-containing insulating film, even when the thickness is thin, This effectively suppresses the diffusion of impurities from the surface being formed.

[0213] Furthermore, by using a nitrogen-containing insulating film as insulating film 103a, the insulating film 103b Oxygen diffuses into the conductive layer 106a, etc., and the amount of oxygen contained in the insulating film 103b decreases, and Furthermore, it is possible to suppress oxidation of the conductive layer 106a, etc.

[0214] In this specification, an oxidized nitride is defined as a compound whose composition contains more oxygen than nitrogen. This refers to materials with a high nitrogen content, and nitride oxides are materials whose composition contains more nitrogen than oxygen. This refers to a composition that contains more oxygen than nitrogen. For example, if silicon oxidiznitride is mentioned, it means that the composition contains more oxygen than nitrogen. When referring to a material with a high content, and it is written as silicon nitride oxide, its composition is such that oxygen This indicates a material with a high nitrogen content.

[0215] Furthermore, in this specification, oxidized nitrides and nitride oxides containing the same elements are described respectively. In that case, the oxidized nitride has a higher oxygen content than the nitride oxide, and nitriding It contains ingredients that satisfy one or both of the following conditions: low content of the element. Furthermore, nitride oxides have a lower oxygen content than oxidized nitrides, and the nitrogen content is also lower. Among the many materials, some satisfy one or both of the following conditions. For example, oxidative nitridation. When silicon and silicon nitride are mentioned, silicon oxide nitride is a type of silicon nitride. It contains materials with a higher oxygen content and a lower nitrogen content than Ricon. Silicon nitride has a lower oxygen content than silicon oxide nitride, and also contains less nitrogen. It contains ingredients in high quantities.

[0216] The insulating film 103b in contact with the semiconductor layer 108 is formed from an insulating film containing an oxide. It is preferable that this is the case. In particular, it is preferable to use an oxide film for the insulating film 103b. Furthermore, the insulating film 103b is a dense insulating film that does not easily adsorb impurities such as water onto its surface. It is preferable to use [this]. Also, it should have as few defects as possible, and contain impurities such as water or hydrogen. It is preferable to use a reduced insulating film.

[0217] Examples of insulating film 103b include silicon oxide film, silicon oxide nitride film, silicon oxide nitride film. Recon film, aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide um film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, oxide An insulating film containing one or more cerium films and neodymium oxide films can be used. In particular, an insulating film can be used. It is preferable to use a silicon oxide film or a silicon oxide-nitride film as the border film 103b. .

[0218] The insulating film 103b may have regions containing an excess of oxygen compared to its stoichiometric composition. It is preferable. In other words, the insulating film 103b is an insulating film that can release oxygen by heating. It is preferable to form a border film. For example, forming the insulating film 103b under an oxygen atmosphere. The insulating film 103b is subjected to heat treatment in an oxygen atmosphere after film formation, and the insulating film 103b Plasma treatment or the like is performed in an oxygen atmosphere after film formation, or an oxygen atmosphere is applied to the insulating film 103b. By forming an oxide film under ambient air conditions, oxygen can also be supplied into the insulating film 103b. Yes, it is possible. Furthermore, in each of the above oxygen supply processes, it is possible to use a substitute for oxygen, or in addition to oxygen. Alternatively, an oxidizing gas (such as nitrous oxide or ozone) may be used. After forming an insulating film on the edge film 103b that can release oxygen by heating, heat treatment is performed. By doing so, oxygen may be supplied from the insulating film to the insulating film 103b. Alternatively, plastic Oxygen is supplied to the insulating film 103b by methods such as sumay ion doping or ion implantation. That's fine.

[0219] Here, it is preferable that the insulating film 103b is formed to be thicker than the insulating film 103a. As a result, the amount of oxygen that can be released from insulating film 103b by heating increases, and insulating film 103a The amount of hydrogen released is reduced. Therefore, hydrogen is supplied to the subsequent semiconductor layer 108. It can supply a large amount of oxygen while suppressing the process, resulting in a highly reliable transistor. This can be achieved. The thickness of the insulating film 103b is preferably 2 times or more and 50 times or less than the thickness of the insulating film 103a. 3 times or more and 30 times or less, more preferably 5 times or more and 20 times or less, even more preferably 7 times or more It is preferable to have a thickness of 5 times or less, and typically around 10 times.

[0220] Furthermore, the metal oxide film that will become the semiconductor layer 108 is formed by sputtering in an oxygen-containing atmosphere. During the formation process, oxygen can be supplied into the insulating film 103b. After forming the metal oxide film layer, heat treatment may be performed. Heat treatment can further enhance the properties of the film. This effectively supplies oxygen from the insulating film 103b to the metal oxide film, and oxygen in the metal oxide film This can reduce data loss.

[0221] [Formation of semiconductor layer 108] Next, a metal oxide film 108f is formed on the insulating layer 103 (Figure 17C).

[0222] The metal oxide film 108f is formed by a sputtering method using a metal oxide target. It is preferable to do so.

[0223] The metal oxide film 108f is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film 108f has been made as pure as possible, with impurities such as hydrogen or water reduced as much as possible. It is preferable that the film is crystalline. In particular, the metal oxide film 108f is crystalline metal acid It is preferable to use a chemical film.

[0224] Furthermore, when forming the metal oxide film 108f, oxygen gas and an inert gas (for example, helical gas) are used. It may be mixed with (such as um gas, argon gas, or xenon gas). The proportion of oxygen gas in the total deposition gas when forming a film (hereinafter also called the oxygen flow rate ratio) The higher the value, the greater the crystallinity of the metal oxide film, resulting in a more reliable transistor. Yes, it is possible. On the other hand, the lower the oxygen flow rate ratio, the lower the crystallinity of the metal oxide film, and the higher the on-current. It can be made into a transistor.

[0225] When depositing the metal oxide film 108f, the higher the substrate temperature, the higher the crystallinity and density of the metal. It can be formed as an oxide film. On the other hand, the lower the substrate temperature, the lower the crystallinity and electrical conductivity. A high-quality metal oxide film can be formed.

[0226] The conditions for depositing the metal oxide film 108f are preferably such that the substrate temperature is between room temperature and 250°C. The temperature should be between room temperature and 200°C, more preferably between room temperature and 140°C. For example, setting the substrate temperature above room temperature but below 140°C is preferable as it increases productivity. Furthermore, the metal oxide film is deposited with the substrate temperature at room temperature or without intentional heating. This allows for a reduction in crystallinity.

[0227] Here, the metal oxide film 108f is formed in an oxygen-containing atmosphere, Oxygen can be supplied to the insulating layer 103 during the deposition of the film 108f. In particular, metal oxide film It is preferable to deposit 108f by sputtering in an oxygen-containing atmosphere.

[0228] When depositing the metal oxide film 108f, the total flow rate of the deposition gas introduced into the deposition chamber of the deposition apparatus is The higher the ratio of oxygen flow rate (oxygen flow rate ratio), or the higher the oxygen partial pressure in the deposition chamber, the more insulating layer 1 The amount of oxygen supplied to 03 can be increased. The oxygen flow rate ratio or oxygen partial pressure depends on the crystallinity of the metal oxide film 108f, or the electrical conductivity of the transistor. Since this also affects the thermal characteristics, it should be determined based on the required electrical characteristics of the transistor. This is possible. For example, the oxygen flow rate ratio or oxygen partial pressure during the deposition of the metal oxide film 108f is The amount is determined appropriately within the range of 10% to 100%, preferably 20% to 100%. That's all you need to do.

[0229] Furthermore, a metal oxide film 108f is formed by sputtering in an oxygen-containing atmosphere. At this point, the surface of the insulating layer 103 is covered with the metal oxide film 108f that is in the process of being formed. As a result, when the metal oxide film 108f is formed, some of the oxygen supplied to the insulating layer 103 is converted This prevents the film from detaching to the outside. As a result, the insulating layer 103 contains a very large amount of It can contain oxygen.

[0230] Furthermore, before forming the metal oxide film 108f, water and hydrogen adsorbed on the surface of the insulating layer 103 Alternatively, a treatment to remove organic matter, etc., and a treatment to supply oxygen into the insulating layer 103. It is preferable to perform at least one of the following: For example, under a reduced pressure atmosphere at 70°C or higher and 200°C Heat treatment can be performed at temperatures below °C. This heat treatment is performed on the metal oxide film 108f. This can also be done in a film deposition apparatus. Alternatively, plasma treatment can be performed in an oxygen-containing atmosphere. It is also acceptable to do so in an atmosphere containing an oxidizing gas such as nitrous oxide (N2O). Oxygen may be supplied to the insulating layer 103 by plasma treatment. The rasma treatment effectively removes organic matter from the surface of the insulating layer 103 while supplying oxygen. This can be done. After such processing, the surface of the insulating layer 103 is not exposed to the atmosphere. It is preferable to subsequently form a metal oxide film 108f.

[0231] Furthermore, if the semiconductor layer 108 is a stacked structure in which multiple metal oxide films are stacked, After forming the metal oxide film, the surface is continuously exposed to the atmosphere. It is preferable to form the following metal oxide film.

[0232] When stacking multiple metal oxide films, use sputtering targets with different compositions. Alternatively, a laminated film can be formed by stacking metal oxide films with different compositions. By using a deposition target and varying the deposition conditions, metal oxide films can also be layered. The film deposition conditions include the type of deposition gas, the flow rate of the deposition gas, the flow rate ratio of the deposition gas, and the size of the deposition chamber. These include pressure, substrate temperature (stage temperature), and power.

[0233] Here, when depositing a metal oxide film by sputtering, the higher the power, the faster the film deposition rate. This can increase the film deposition rate. Also, the lower the power, the slower the film deposition rate can be, and the film thickness and film This reduces variations in quality and other in-plane characteristics. Using a tweezers, a metal oxide film was deposited under high power conditions, and under lower power conditions... By stacking the deposited metal oxide films, in-plane variations are reduced while increasing the film deposition rate. It is possible.

[0234] For example, a metal oxide film is first deposited on the insulating layer 103 at low power, and then at a higher power. Metal oxide films can be deposited using electricity. Alternatively, a metal oxide film can be deposited first using high power. Furthermore, metal oxide films can be deposited with even lower power. Alternatively, with low power The process of forming the film and then forming it again at high power may be repeated.

[0235] The higher the power used during film deposition, the denser (more compact) the metal oxide film formed. The lower the power used, the lower the density of the metal oxide film that can be deposited. The oxide film can supply more oxygen to the layer below it during deposition. These are some of its characteristics.

[0236] For example, as the semiconductor layer 108, a metal oxide film deposited with low power from the insulating layer 103 side and This allows for a laminated structure of metal oxide films deposited with high power. It can supply a lot of oxygen to 03. Also, the semiconductor layer 108 can be made denser on the upper side. Therefore, when the openings 141a and 141b are formed later, the semiconductor layer 108 is... Because chipping becomes less likely, the manufacturing yield can be increased.

[0237] Furthermore, the semiconductor layer 108 is a metal oxide film deposited from the insulating layer 103 side using high power, It is also possible to create a layered structure of metal oxide films deposited with low power. This can suppress the incorporation of impurities remaining in the deposition chamber into the metal oxide film. In particular, by using high power in the initial stages of the film deposition process, impurities in the film can be more effectively reduced. A reduced metal oxide film can be formed. Therefore, the metal that was deposited on the insulating layer 103 side with high power It is preferable to use an oxide film. Alternatively, a low-power coating can be applied to a dense metal oxide film deposited at high power. When metal oxide films are deposited using electricity, the second layer of metal oxide film also tends to become denser. When a dense, highly crystalline film is formed in the first layer, the crystallinity of the second layer reflects that crystallinity. This can improve performance. Also, by depositing a metal oxide film in the second layer with low power, the first layer Because oxygen can be directly supplied to the metal oxide film, during the deposition of the semiconductor layer 108, the film This can reduce oxygen deficiency inside.

[0238] Next, by etching a portion of the metal oxide film 108f, an island-shaped semiconductor layer 1 Forms O8 (Figure 17D).

[0239] The metal oxide film 108f can be processed using either a wet etching method or a dry etching method. Either one or both may be used. In this case, insulation that does not overlap with the semiconductor layer 108 is required. In some cases, a portion of layer 103 may be etched and become thinner. For example, of the insulating layer 103, In some cases, the insulating film 103b may disappear due to etching, exposing the surface of the insulating film 103a. .

[0240] Here, after the metal oxide film 108f is formed, or the metal oxide film 108f is placed on the semiconductor layer 10 It is preferable to perform a heat treatment after processing to 8. The heat treatment creates a metal oxide film 10 Removes hydrogen or water contained in or adsorbed on the surface of 8f or the semiconductor layer 108. This can be done. In addition, the metal oxide film 108f or semiconductor layer 108 can be heated. Quality may improve (for example, by reducing defects or improving crystallinity).

[0241] Furthermore, the heat treatment reduces the acid supplied to the insulating layer 103 during the formation of the metal oxide film 108f. The element can be diffused throughout the insulating layer 103. For example, the metal oxide film 108f Immediately after film formation, the supplied oxygen is mostly located on the upper part of the insulating layer 103, and the oxygen is easily desorbed. In some cases, the state may be saturated. At this time, in the process of forming the insulating layer 110, which will be described later, There is a risk that a large amount of oxygen will be leached from the exposed surface of the insulating layer 103. By diffusing oxygen throughout the insulating layer 103 through heat treatment, after the insulating layer 110 is formed... Even in this case, a state in which a large amount of oxygen is trapped in the insulating layer 103 can be maintained.

[0242] Furthermore, heat treatment removes the metal oxide film 108f or semiconductor layer 10 from the insulating layer 103. Oxygen can also be supplied to 8. At this time, heat treatment is performed before processing the semiconductor layer 108. By doing so, oxygen detached from the insulating layer 103 can be efficiently supplied to the metal oxide film 108f. Therefore, it is preferable.

[0243] Furthermore, heat treatment can be used to remove water or hydrogen from the insulating layer 103. At this time, when the semiconductor layer 108 is processed and then heat-treated, the insulating layer 103 is exposed. Water or hydrogen becomes more easily detached from the part, and water or hydrogen detached from the insulating layer 103 This prevents the supply of such substances into the semiconductor layer 108. If the content of water or hydrogen is high, heat treatment is performed after processing the semiconductor layer 108. It is preferable to do so.

[0244] The heat treatment temperature is typically 150°C or higher but below the strain point of the substrate, or 200°C or higher but below 5°C. The temperature must be below 00°C, or between 250°C and 450°C, or between 300°C and 450°C. It is possible.

[0245] The heat treatment can be carried out in an atmosphere containing a noble gas or nitrogen. After heating with gas, it may be heated in an oxygen-containing atmosphere. Alternatively, it may be heated in a dry air atmosphere. It is also preferable that the atmosphere during the above heat treatment contains as little hydrogen, water, etc. as possible. The heat treatment is carried out in an electric furnace or RTA (Rapid Thermal Annealing). al) Equipment can be used. By using an RTA device, the heat treatment time can be shortened. It is possible.

[0246] Note that this heat treatment may be omitted if it is not necessary. Also, heat treatment is not performed here. Furthermore, it may be combined with the heat treatment performed in a later step. Also, high-temperature treatment in a later step (e.g.) In some cases, such as in the film deposition process, this heat treatment can be carried out in conjunction with other processes.

[0247] [Formation of insulating layer 110] Next, the insulating layer 110 is formed by covering the insulating layer 103 and the semiconductor layer 108 (Figure 17). E).

[0248] The insulating film constituting the insulating layer 110 is preferably formed by the PECVD method.

[0249] For example, the insulating layer 110 may be a silicon oxide film, a silicon oxide nitride film, or a silicon oxide nitride film. Cone film, aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide Calcium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, cereal oxide film An insulating layer containing one or more of a lium film and a neodymium oxide film can be used.

[0250] The insulating layer 110 in contact with the semiconductor layer 108 preferably has a laminated structure of oxide insulating films. Furthermore, the insulating layer 110 has regions that contain an excess of oxygen compared to the stoichiometric composition. This is more preferable. In other words, the insulating layer 110 is an insulating film that can release oxygen. It is preferable to have it.

[0251] Here, as the insulating layer 110, a laminated film is obtained by stacking three insulating films with different deposition conditions. It is preferable to use a silicon oxide film or It is preferable to use a silicon oxide nitride film.

[0252] Since the first insulating film layer is deposited on the semiconductor layer 108, it is important to keep it as close to the semiconductor layer 108 as possible. It is preferable that the film is deposited under conditions that do not cause damage. For example, compared to other films It is possible to deposit films under conditions where the deposition rate (also called the deposition rate) is sufficiently low. For example, 1 When forming a silicon oxidizride film as the insulating layer using plasma CVD, low voltage Formation under specific force conditions, deposition gas containing silicon such as silane and disilane in the deposition gas By reducing the flow rate of the solvent, etc., the deposition rate is lowered, and the amount of solvent applied to the semiconductor layer 108 is reduced. The image can be made extremely small.

[0253] The second insulating layer is a film deposited under conditions with a higher deposition rate than the first insulating layer. This is preferable. This can improve productivity.

[0254] The third insulating layer has reduced surface defects and absorbs impurities from the atmosphere, such as water. It is preferable that the film is extremely dense and difficult to adhere to. For example, similar to the first insulating layer, The film can be deposited under conditions where the deposition rate is sufficiently low.

[0255] Furthermore, before forming the insulating layer 110, the surface of the semiconductor layer 108 is subjected to plasma treatment. This is preferable. The plasma treatment removes water and other impurities adsorbed on the surface of the semiconductor layer 108. Pure matter can be reduced. Therefore, at the interface between the semiconductor layer 108 and the insulating layer 110 Because impurities can be reduced, highly reliable transistors can be realized. In particular, semiconductor layer 1 Between the formation of 08 and the deposition of the insulating layer 110, the surface of the semiconductor layer 108 is exposed to the atmosphere. In some cases, this is preferable. Examples of plasma treatments include oxygen, ozone, nitrogen, and nitrous oxide. It can be carried out in an atmosphere containing one or more of the following: argon, etc. Also, plasma treatment. Preferably, the deposition of the insulating layer 110 is carried out continuously without exposure to the atmosphere.

[0256] Here, it is preferable to perform a heat treatment after forming the insulating layer 110. This allows for the removal of hydrogen or water contained in or adsorbed on the insulating layer 110. This also reduces defects in the insulating layer 110.

[0257] Furthermore, the heat treatment removes oxygen contained in the insulating layer 103, and in the semiconductor layer 108 It can be supplied to. For example, when the insulating layer 110 is formed, damage to the semiconductor layer 108 As a result, defects such as oxygen vacancies may be generated in the semiconductor layer 108. Therefore, by performing a heat treatment after the formation of the insulating layer 110, oxygen supplied from the insulating layer 103 is released. This reduces oxygen vacancies in the semiconductor layer 108, enabling the realization of highly reliable transistors. ru.

[0258] The conditions for heat treatment can be applied as described above.

[0259] Note that this heat treatment may be omitted if it is not necessary. Also, heat treatment is not performed here. Furthermore, it may be combined with the heat treatment performed in a later step. Also, high-temperature treatment in a later step (e.g.) In some cases, such as in the film deposition process, this heat treatment can be carried out in conjunction with other processes.

[0260] [Formation of opening 143] Next, by etching a portion of the insulating layer 110 and the insulating layer 103, the conductive layer 106 It forms an opening 143 that reaches a.

[0261] [Formation of conductive layer 112a and conductive layer 112b] Next, a conductive film is formed on the insulating layer 110 so as to cover the opening 143, and the conductive film is By processing to the desired shape, conductive layers 112a and 112b are formed (Figure 17F). ).

[0262] As conductive layers 112a and 112b, low-resistance metal or alloy materials are used. This is preferable. Also, the conductive layer 112a and conductive layer 112b may be made of a material that does not easily release hydrogen. It is preferable to use a material that is also resistant to hydrogen diffusion. Also, conductive layer 112a Furthermore, it is preferable to use a material that is resistant to oxidation as the conductive layer 112b.

[0263] For example, conductive layers 112a and 112b are sputtering layers containing metal or alloy. It is preferable to deposit the film using a sputtering method with a GET.

[0264] For example, conductive layers 112a and 112b are made to be resistant to oxidation and resistant to hydrogen diffusion. It is preferable to use a laminated film in which a conductive film with low resistance and a conductive film with low resistance are laminated together.

[0265] In this way, without etching the insulating layer 110, the top and side surfaces of the semiconductor layer 108, and By creating a structure in which an insulating layer 103 is covered by an insulating layer 110, conductive layers such as conductive layer 112a are formed. During the etching of the film, a portion of the semiconductor layer 108 or the insulating layer 103 is etched. This prevents the film from becoming thin.

[0266] Furthermore, during the processing of conductive layers 112a and 112b, a portion of the insulating layer 110 may be etched. This can lead to thinning of the film.

[0267] Furthermore, when forming the opening 143 shown in Figures 13A to 13C, first the conductive layer 112a And before forming the conductive film that will become the conductive layer 112b, a part of the insulating layer 110 and insulating layer 103 Etching is performed to form an opening 143 that reaches the conductive layer 106a. Then, the opening 14 A conductive film, which will become the conductive layer 112a and the conductive layer 112b, is formed on the insulating layer 110 so as to cover 3. Then, by processing the conductive film, a conductive layer 112a and a conductive layer 112b are formed. As a result, the conductive layer 112b is electrically connected to the conductive layer 106a at the opening 143. It is possible to form this.

[0268] [Processing of supplying impurity elements] Next, using the conductive layer 112a as a mask, impurities are introduced into the semiconductor layer 108 via the insulating layer 110. The process involves supplying (also called adding or injecting) physical elements (Figure 18A). This allows, By forming a low-resistance region 108n in the region of the semiconductor layer 108 that is not covered by the conductive layer 112a, This can be done. At this time, in the region of the semiconductor layer 108 that overlaps with the conductive layer 112a, impurity elements To minimize supply, the material or thickness of the conductive layer 112a, etc., which will serve as a mask, etc. It is preferable to consider this when determining the conditions for supplying impurity elements. In the region of layer 108 that overlaps with the conductive layer 112a, a channel is formed with a sufficiently reduced impurity concentration. It can form a region.

[0269] The impurity element supply process involves plasma in an atmosphere containing the impurity element to be supplied. Examples of processing include plastics in an atmosphere containing hydrogen gas or ammonia gas. By performing the Zuma treatment, hydrogen is supplied to the semiconductor layer 108 via the insulating layer 110. This is possible. In particular, plasma processing in an atmosphere containing hydrogen gas is preferred.

[0270] In Figure 18A, exposure to plasma 140 causes the semiconductor layer 10 to be transmitted through the insulating layer 110. This diagram schematically illustrates how impurities are supplied to 8.

[0271] Examples of devices capable of generating plasma 140 include dry etching equipment and apron. A single-phase device, a plasma CVD device, a high-density plasma CVD device, etc., can be used.

[0272] Here, after plasma treatment, an insulating layer 118 is continuously deposited without exposure to the atmosphere. It is preferable to do so. At this time, in the same deposition chamber of the deposition apparatus for forming the insulating layer 118 Therefore, it is preferable to perform the plasma treatment and the film deposition treatment in succession. For example, water in the film deposition chamber. Plasma treatment is performed by supplying a processing gas containing elementary gases, and then the deposition gas is supplied to the deposition chamber. By supplying the necessary materials, the insulating layer 118 can be formed. At this time, the plasma treatment and the film formation process are performed. It is preferable to perform this process under the same conditions regarding substrate temperature (temperature of the stage that holds the substrate).

[0273] In one aspect of the present invention, impurity elements are supplied to the semiconductor layer 108 via the insulating layer 110. Therefore, even if the semiconductor layer 108 has crystalline properties, the impurity elements The damage to the semiconductor layer 108 during supply is reduced, and its crystallinity is compromised. This can suppress the decrease in crystallinity, which can lead to an increase in electrical resistance. It is suitable.

[0274] Alternatively, plasma ion doping or ion injection may be used as a treatment method for supplying impurity elements. The input method can be suitably used. These methods allow for the concentration profile in the depth direction to be obtained. High precision control is possible through ON acceleration voltage and dose amount, etc. Plasma ions Doping methods can increase productivity. Also, io By using the injection method, the purity of the supplied impurity elements can be increased.

[0275] In the supply process of impurity elements, at the interface between the semiconductor layer 108 and the insulating layer 110, or the semiconductor The portion of the body layer 108 near the interface, or the portion of the insulating layer 110 near the interface, It is preferable to control the processing conditions so that the concentration is high. This allows for a single processing. This allows for the supply of an optimal concentration of impurity elements to both the semiconductor layer 108 and the insulating layer 110. Cut.

[0276] The impurity elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, and aluminum. Examples include nium, magnesium, silicon, or noble gases. (Note: Representative noble gases...) Examples include helium, neon, argon, krypton, and xenon. In particular, Boron, phosphorus, aluminum, magnesium, or silicon are preferred.

[0277] As the raw material gas for impurity elements, a gas containing the above-mentioned impurity elements can be used. When supplying porcini, typical gases such as B2H6 or BF3 can be used. Furthermore, when supplying phosphorus, pH3 gas can typically be used. A mixed gas obtained by diluting these source gases with a noble gas may also be used.

[0278] Other raw material gases include CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and noble gases can be used. Furthermore, the ion source is not limited to gases; solids or liquids that have been heated and vaporized can also be used. That's fine.

[0279] The addition of impurity elements takes into consideration the composition, density, and thickness of the insulating layer 110 and the semiconductor layer 108. This can then be controlled by setting conditions such as acceleration voltage or dose amount.

[0280] [Formation of insulating layer 118] Next, the insulating layer 110, conductive layer 112a, and conductive layer 112b are covered with the insulating layer 11 Forms 8 (Figure 18B).

[0281] When forming the insulating layer 118 by plasma CVD, if the deposition temperature is too high, low resistance occurs. Impurities contained in region 108n, etc., in the peripheral region including the channel formation region of the semiconductor layer 108 There are concerns that the signal may diffuse, or that the electrical resistance in the low-resistance region of 10⁸n may increase. Therefore, the film deposition temperature for the insulating layer 118 should be determined by taking these factors into consideration. .

[0282] For example, the film deposition temperature for the insulating layer 118 is preferably between 150°C and 550°C. More preferably 160°C to 500°C, more preferably 180°C to 450°C, even more preferably Alternatively, a temperature of 250°C to 400°C is preferable. The insulating layer 118 is formed at a low temperature. This allows even transistors with short channel lengths to be given good electrical characteristics. It is possible.

[0283] Furthermore, a heat treatment may be performed after the formation of the insulating layer 118. This heat treatment reduces resistance. In some cases, region 108n can be made more stable and have lower resistance. For example, Through heat treatment, impurity elements are moderately diffused and locally homogenized, resulting in an ideal impurity A low-resistance region 108n with a concentration gradient of pure elements can be formed. Note that the temperature of the heat treatment If the temperature is too high (for example, above 500°C), impurity elements will diffuse into the channel-forming region. This could lead to a deterioration in the electrical characteristics or reliability of the transistor.

[0284] The conditions for heat treatment can be applied as described above.

[0285] Note that this heat treatment may be omitted if it is not necessary. Also, heat treatment is not performed here. Furthermore, it may be combined with the heat treatment performed in a later step. Also, high-temperature treatment in a later step (e.g.) For example, if there is a film formation process, it may be possible to combine it with the heat treatment.

[0286] [Formation of openings 141a, 141b, and 144] Next, by etching a portion of the insulating layer 118, an opening is formed that reaches the conductive layer 112b. A mouth portion 144 is formed. In addition, a portion of the insulating layer 118 and insulating layer 110 is etched. This forms openings 141a and 141b that reach the low-resistance region 108n. Figure 18C).

[0287] The formation of opening 144 and the formation of openings 141a and 141b can be performed simultaneously. Yes, or they can be done separately. If done simultaneously, position at the bottom of opening 144. Under conditions that the conductive layer 112b is less likely to be etched, the opening 141a and the opening 141b It is preferable to etch the insulating layer 110 located at [location].

[0288] Next, an insulating layer 1 is applied to cover openings 141a, 141b, and 144. A conductive film is formed on 18, and the conductive film is processed into a desired shape, thereby forming a conductive layer 120a and Then a conductive layer 120b is formed (Figure 18D).

[0289] By following the above steps, transistor 100 can be manufactured. For example, When applying Ta 100 to the pixels or drive circuits of a display device, a protective insulating layer is applied afterward. The process may be further modified by adding a step of forming one or more of the following: a planarization layer, pixel electrodes, or wiring.

[0290] The above is an explanation of an example of the manufacturing method.

[0291] Note that when fabricating the transistor 100A as exemplified in Configuration Example 2, the conductive layer 112a Furthermore, it can be manufactured by varying the pattern of the conductive layer 106a.

[0292] Furthermore, when manufacturing the configuration shown in Figure 15A, etc., conductive layer 106b and conductive layer 106c The semiconductor layer 108a is formed by processing the same conductive film as the conductive layer 106a, and the semiconductor layer 108a is formed by the semiconductor layer 1 A conductive layer 112c is formed by processing the same metal oxide film as 08, and conductive layer 112a and conductive The conductive layer 120c is formed by processing the same conductive film as the conductive layer 112b, and the conductive layer 120a and The conductive film can be formed by processing the same conductive film as the conductive layer 120b. Also, the opening 142 and the opening Part 145 is formed in the same way as opening 143, and openings 141c, 141d, and opening The part 141e can be formed in the same way as the opening 141a. This allows the process to be completed in the same manner. On the same substrate, without increasing the number of processes, transistor 100, transistor 150, and A quantity of 160 can be formed.

[0293] [Example of manufacturing method] [Variation 1] In the above example of manufacturing method, when processing conductive layer 112a and conductive layer 112b, conductive layer 1 The insulating layer 110 in the region that does not overlap with 12a and the conductive layer 112b is removed by etching. It is also possible to use a configuration that eliminates this. A schematic cross-sectional view of the transistor fabricated in this way is shown in Figure. This is shown in 19A.

[0294] The transistor shown in Figure 19A consists of a low-resistance region 108n of the semiconductor layer 108 and an insulating layer 11 It has a configuration in which it is in contact with 8. In this case, the insulating layer 118 is made which releases hydrogen when heated. By using an insulating film, hydrogen can be suitably introduced into the low-resistance region 108n during the formation process of the insulating layer 118. It can be supplied. Alternatively, heat treatment can be performed after the formation of the insulating layer 118, The heat generated in a later process supplies hydrogen from the insulating layer 118 to the low-resistance region 108n. This can be done. In this case, the insulating layer 118 may be a silicon nitride film or silicon nitride oxide film. A nitrogen-containing insulating film, such as a nitrate film, can be suitably used. As a result, the insulating layer 118 This achieves both the function of releasing hydrogen and the function of acting as a barrier film against water or hydrogen. It is possible.

[0295] Furthermore, the insulating layer 118 is formed in contact with a portion of the semiconductor layer 108 that forms a low-resistance region 108n. If this makes it possible to sufficiently reduce the resistance of a portion of the semiconductor layer 108, then the insulating layer 118 It is not necessary to use an insulating film that can release hydrogen when heated. In this case, the insulating layer 118 is, for example, an oxygen-containing insulating film such as a silicon oxide film or a silicon oxide-nitride film. A border film can be used.

[0296] Alternatively, after the formation of the insulating layer 118, the above-mentioned impurity element supply treatment is performed to the insulating layer 118. Impurity elements may be supplied to the low-resistance region 108n via this. In this case, the insulating layer 118 is The insulating film does not necessarily have to be capable of releasing hydrogen when heated.

[0297] [Variation 2] Using the above example of fabrication method, a transistor having only one gate can be fabricated simultaneously. This is possible. A schematic cross-sectional view of the transistor fabricated in this way is shown in Figure 19B.

[0298] The transistor shown in Figure 19B has a conductive layer 106a that functions as the bottom gate. The fact that it does not have openings 143 and 144, and the conductive layer 112b It differs primarily from the transistor 100 described above in that it does not have [a certain feature].

[0299] Furthermore, Figure 19C shows that, similar to the modification 1 described above, the insulating layer 110 is connected to the conductive layer 112a on the top surface. This shows a schematic cross-sectional view of a transistor that has been processed to roughly match its shape.

[0300] The above is an explanation of the variations.

[0301] The transistors exemplified above are used not only in sequential circuits but also in the pixels of display devices. It can also be applied to transistors. In this case, the transistors provided in the sequential circuit and The transistors provided in the pixels of the display device are manufactured on the same substrate using the same process. This makes it possible to manufacture highly reliable display devices at a low cost. This becomes possible.

[0302] [Components of semiconductor devices] The following describes the components included in the semiconductor device of this embodiment.

[0303] 〔substrate〕 There are no major restrictions on the material of the substrate 102, but it should at least be able to withstand subsequent heat treatment. It must have heat resistance. For example, silicon or silicon carbide may be used as the material. Single-crystal semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, glass substrates, ceramic substrates, quartz substrates, sapphire substrates, etc., are used for substrate 102 It may also be used as such. Furthermore, a substrate on which semiconductor elements are provided may be called substrate 10 It may also be used as 2.

[0304] Furthermore, a flexible substrate is used as the substrate 102, and a semiconductor device is formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate 102 and the semiconductor device. The release layer is After partially or completely completing the semiconductor device on top of it, it is separated from the substrate 102 and placed on another substrate It can be used for reproduction. In that case, the semiconductor device is a substrate with poor heat resistance, or It can also be mounted on flexible substrates.

[0305] [Conductive film] In addition to the gate, source, and drain of transistors, various wiring components make up semiconductor devices. Materials that can be used for conductive layers such as electrodes include aluminum, titanium, and crystalline aluminum. Chromium, nickel, copper, yttrium, zirconium, molybdenum, gold, silver, zinc, tantalum Metals such as iron, manganese, iron, niobium, cobalt, or tungsten, or primarily composed of these metals. Examples of alloys used as components include these materials. Furthermore, films containing these materials can be made as a single layer or in a multilayer structure. It can be used as such.

[0306] For example, a single-layer structure of an aluminum film containing silicon, or an aluminum film deposited on a titanium film. Layered two-layer structure, two-layer structure with aluminum film laminated on tungsten film, copper-magnesium A two-layer structure in which a copper film is laminated on an aluminum-aluminum alloy film, and a two-layer structure in which a copper film is laminated on a titanium film. Layered structure, two-layer structure with a copper film laminated on a tungsten film, titanium film or titanium nitride film, An aluminum film or copper film is then layered on top of that, and a titanium film or nitride film is placed on top of that. A three-layer structure forming a titanium film, a molybdenum film or a molybdenum nitride film, and layered on top of it An aluminum film or copper film is laminated, and then a molybdenum film or molybdenum nitride film is placed on top of it. There are structures such as a three-layer structure that forms a film. Furthermore, oxidation of indium oxide, tin oxide, or zinc oxide is also possible. Materials may be used. Also, if copper containing manganese is used, the shape can be controlled by etching. This is preferable because it increases the risk.

[0307] Furthermore, the conductive layer constituting the semiconductor device includes In-Sn oxide, In-W oxide, and In- W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In -Oxide conductors such as Sn-Si oxide and In-Ga-Zn oxide, or metal oxides are applied. It is also possible.

[0308] Here, we will explain oxide conductors (OC). For example, an oxygen vacancy is formed in a metal oxide having semiconductor properties, and hydrogen is added to the oxygen vacancy. Then, a donor level is formed near the conduction band. As a result, the metal oxide has high conductivity. It becomes conductive. A metal oxide that has become conductive can be called an oxide conductor.

[0309] Furthermore, the conductive layer constituting the semiconductor device includes the above-mentioned oxide conductor (metal oxide). A laminated structure of an electrical film and a conductive film containing a metal or alloy may also be used. By using an insulating film, the wiring resistance can be reduced. In this case, the gate insulating film is used. It is preferable to apply a conductive film containing an oxide conductor to the side that is in contact with the insulating layer that functions as an insulating layer.

[0310] [Semiconductor layer] If the semiconductor layer 108 is In-M-Zn oxide, then to deposit the In-M-Zn oxide film... The atomic ratio of metal elements in the sputtering target used is In:M:Zn=1: 1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Z n=1:3:4, In:M:Zn=1:3:6, In:M:Zn=2:2:1, In:M :Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In :M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=10:1 :3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5 Examples include :1:8, In:M:Zn=6:1:6, and In:M:Zn=5:2:5. Furthermore, in the above, if element M includes two or more elements, the atomic ratio is as follows: The proportion of M shall correspond to the sum of the number of atoms of the two or more metal elements in question.

[0311] Furthermore, a target containing a polycrystalline oxide is used as the sputtering target. This is preferable because it facilitates the formation of a crystalline semiconductor layer 108. The atomic ratio of semiconductor layer 108 is the original number of metal elements contained in the sputtering target mentioned above. This includes variations of plus or minus 40% in the number of particles. For example, sputtering used for semiconductor layer 108. When the composition of the ring target is In:Ga:Zn=4:2:4.1 [atomic ratio], The composition of the semiconductor layer 108 is in the vicinity of In:Ga:Zn=4:2:3 [atomic ratio]. There are cases where this occurs.

[0312] Note that when the atomic ratio is stated as In:Ga:Zn=4:2:3 or close to it, In When we set the ratio to 4, this includes the case where Ga is between 1 and 3, and Zn is between 2 and 4. Furthermore, when stating that the atomic ratio is In:Ga:Zn = 5:1:6 or close to it, When n is set to 5, Ga is greater than 0.1 and less than or equal to 2, and Zn is between 5 and 7. This includes cases where the atomic ratio is In:Ga:Zn = 1:1:1 or close to it. When listing, if In is set to 1, Ga must be greater than 0.1 and less than or equal to 2, and Zn must be 0. This includes cases where the value is greater than 1 and less than or equal to 2.

[0313] Furthermore, the semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or less. As shown above, by using metal oxides with a wider energy gap than silicon... This allows for a reduction in the transistor's off-current.

[0314] Furthermore, it is preferable that the semiconductor layer 108 has a non-single-crystal structure. A non-single-crystal structure is, for example, This includes the CAAC structure, polycrystalline structure, microcrystalline structure, or amorphous structure described later. Non-single crystal structure In construction, amorphous structures have the highest defect level density, while CAAC structures have the highest defect level density. low.

[0315] The following explains CAAC (c-axis aligned crystal). CAAC represents an example of a crystal structure.

[0316] A CAAC structure is a structure that has multiple nanocrystals (crystalline regions with a maximum diameter of less than 10 nm). It is one of the crystalline structures of thin films, in which each nanocrystal has its c-axis oriented in a specific direction, and its a-axis and The b-axis does not have orientation, and the nanocrystals are continuously connected without forming grain boundaries. This crystal structure has the following characteristics. In particular, thin films with a CAAC structure have each nanocrystal The c-axis is oriented in the thickness direction of the thin film, the normal direction of the surface to be formed, or the normal direction of the surface of the thin film. It has the characteristic of being inexpensive.

[0317] CAAC-OS (Oxide Semiconductor) is a highly crystalline oxide semiconductor. It is a conductor. On the other hand, CAAC-OS does not allow for the identification of clear grain boundaries, It can be said that a decrease in electron mobility caused by grain boundaries is less likely to occur in oxide semiconductors. Crystalline properties may decrease due to the inclusion of impurities or the formation of defects, therefore CAAC -OS can be described as an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, C Oxide semiconductors containing AAC-OS exhibit stable physical properties. Therefore, CAAC-O Oxide semiconductors containing sulfur are highly heat-resistant and reliable.

[0318] In crystallography, the three axes that constitute the unit cell are the a-axis, b-axis, and c-axis (crystal). Regarding the axis, it is common to take a unit cell with a specific axis as the c-axis. Especially in layered structures In crystals with a structure, the two axes parallel to the plane direction of the layer are defined as the a-axis and the b-axis, and the axis intersecting the layer is defined as the axis intersecting the layer. It is common to use the c-axis. A typical example of a crystal having such a layered structure is... There is graphite, which is classified as a hexagonal crystal system, and the a-axis and b-axis of its unit cell are parallel to the cleavage plane. The row is oriented, and the c-axis is perpendicular to the cleavage plane. For example, the layered structure of YbFe2O4 type crystal structure. InGaZnO4 crystals can be classified as hexagonal, and their unit cell a-axis and The b-axis is parallel to the plane direction of the layer, and the c-axis is perpendicular to the layer (i.e., the a-axis and b-axis).

[0319] Oxide semiconductor films having a microcrystalline structure (microcrystalline oxide semiconductor films) can be examined using a transmission electron microscope ( TEM (Transmission Electron Microscope) In some cases, the crystalline portion may not be clearly visible in the observed image. (Microcrystalline oxide semiconductor film) The crystalline portion contained therein is between 1 nm and 100 nm in size, or between 1 nm and 10 nm in size. This is often the case. In particular, the minute particles are between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor film having nanocrystals (nc) which are crystalline, -OS(nanocrystalline oxide semiconductor) It is called a film. Furthermore, nc-OS films, for example, clearly show grain boundaries in TEM observation images. It may not be possible to confirm this.

[0320] nc-OS films are used in minute regions (for example, regions between 1 nm and 10 nm, especially regions between 1 nm and 10 nm). The atomic arrangement has periodicity in the region of 3 nm or less. In addition, the nc-OS film is different There is no regularity in the crystal orientation between the crystalline regions. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS films may be indistinguishable from amorphous oxide semiconductor films. There are cases where X-rays with a diameter larger than that of the crystalline region are used on an nc-OS film. When structural analysis is performed using an X-ray Diffraction (XRD) device, Analysis using the ut-of-plane method does not detect peaks indicating crystal planes. For nc-OS films, an electron beam with a probe diameter larger than the crystalline region (e.g., 50 nm or larger) is applied. When electron diffraction (also called limited-field electron diffraction) is performed, a halo pattern is observed. A diffraction pattern is observed. On the other hand, for the nc-OS film, the size of the crystalline region is close to that of the crystalline region. Electron diffraction using electron beams with smaller probe diameters (e.g., 1 nm to 30 nm) Also known as nanobeam electron diffraction, when this is performed, a ring-shaped region of high brightness is observed, tracing a circular pattern. This may be observed, and multiple spots may be observed within the ring-shaped region.

[0321] nc-OS films have a lower defect level density than amorphous oxide semiconductor films. However, nc-O The S film shows no regularity in crystal orientation between different crystalline regions. Therefore, the nc-OS film is Compared to CAAC-OS films, nc-OS films have a higher defect level density. Therefore, nc-OS films are CAAC- Compared to OS films, it may have a higher carrier density and higher electron mobility. Therefore, nc Transistors using OS films may exhibit high field-effect mobility.

[0322] Compared to CAAC-OS films, nc-OS films require a lower oxygen flow rate ratio during deposition. It can be formed by [method]. In addition, compared to CAAC-OS films, nc-OS films have [processing time] It can also be formed by lowering the substrate temperature. For example, the nc-OS film can be formed by lowering the substrate temperature. A state where the temperature is set to a relatively low temperature (for example, below 130°C), or a state where the substrate is not heated. However, because it can form thin films, it is suitable for use with large glass substrates or resin substrates. This allows for increased productivity.

[0323] An example of a metal oxide crystal structure is described. In-Ga-Zn oxide target ( Using In:Ga:Zn=4:2:4.1 (atomic ratio), the substrate temperature was set to 100°C or higher. At temperatures below 30°C, metal oxides formed by sputtering are nc(nano C Either a crystalline structure (rystal) or a CAAC structure, or a mixture of both. It is easy to form such a structure. On the other hand, metal oxides formed with the substrate temperature at room temperature (RT) It readily adopts an nc crystal structure. Note that room temperature (RT) here refers to the substrate being intentionally cooled. This includes the temperature when not heated.

[0324] [Composition of metal oxides] Hereinafter, CAC(C) that can be used in the transistor disclosed in one aspect of the present invention will be described. This document describes the configuration of a loud-Aligned Composite (Loud) OS.

[0325] Note that CAAC (c-axis aligned crystal) is an example of a crystal structure. This represents CAC (Cloud-Aligned Composite), which is a function or material. This shows an example of the composition of the ingredients.

[0326] CAC-OS or CAC-metal oxide is a material in which some parts are conductive. It has both electrical and insulating properties in some parts of the material, and the material as a whole has semiconductor properties. Furthermore, CAC-OS or CAC-metal oxide is used to activate the transistor. When used in layers, the conductive function is the function of allowing electrons (or holes) that act as carriers to flow. In other words, the insulating function is the function of preventing the flow of electrons, which act as carriers. Conductive function and insulating function By making the functions of sex and other functions work complementaryly, a switching function (On / O) is created. The function of ff (fastening) can be imparted to CAC-OS or CAC-metal oxide. In CAC-OS or CAC-metal oxide, the respective functions are separated. By doing so, the functions of both can be maximized.

[0327] Furthermore, CAC-OS or CAC-metal oxide provides conductive and insulating properties. It has conductive regions. The conductive regions have the conductive function described above, and the insulating regions have the insulating function described above. It has the function of being conductive. Furthermore, within the material, the conductive region and the insulating region are separated by nanoparticles. In some cases, they are separated by a bell. Also, conductive regions and insulating regions are located within the material. It may be unevenly distributed. Also, the conductive region appears blurred around the edges and connected in a cloud-like manner when observed. There are cases where this can happen.

[0328] Furthermore, in CAC-OS or CAC-metal oxide, the conductive region and The insulating region is defined as 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. They may be dispersed in the material in sizes smaller than m.

[0329] Furthermore, CAC-OS or CAC-metal oxide have different band gaps. It is composed of components having [a certain characteristic]. For example, CAC-OS or CAC-metal ox The ide consists of a component with a wide gap due to the insulating region and a component with a wide gap due to the conductive region. It consists of a component having a narrow gap. In this configuration, when the carrier is flowing... In components with a narrow gap, the carrier mainly flows. The component with a gap acts complementaryly with the component with a wide gap, and the component with a narrow gap In conjunction with the components that perform this action, carriers also flow to components with a wide gap. Therefore, the above CAC-OS or CAC-metal oxide in the channel formation region of the transistor When used in this way, a high current driving force, i.e., a large on-current, is required in the transistor's on state. Furthermore, high field-effect mobility can be obtained.

[0330] In other words, CAC-OS or CAC-metal oxide is a matrix composite Material (matrix composite), or metal matrix composite material (metal It can also be called a matrix composite.

[0331] The above is an explanation of the composition of metal oxides.

[0332] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., are at least a part of them. This can be combined with other configuration examples or drawings as appropriate.

[0333] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0334] (Embodiment 2) In this embodiment, a display device having a semiconductor device according to one aspect of the present invention is shown in Figure 20A. Further explanation will be provided using Figure 20C.

[0335] The display device shown in Figure 20A comprises a pixel unit 502, a drive circuit unit 504, and a protection circuit 506. It has a terminal section 507 and a protective circuit 506.

[0336] A transistor in the pixel unit 502 or the drive circuit unit 504, etc., according to one aspect of the present invention A transistor can be applied to the protection circuit 506 as well. You may apply a generator.

[0337] The pixel section 502 consists of pixels arranged in X rows and Y columns (where X and Y are independent natural numbers greater than or equal to 2). It has a basic circuit 501. Each pixel circuit 501 has a circuit that drives a display element. .

[0338] The drive circuit section 504 outputs a scanning signal to gate lines GL_1 to GL_X. The driver 504a supplies data signals to data lines DL_1 through DL_Y. It has a drive circuit such as a source driver 504b. The gate driver 504a is at least It is also possible to have a configuration that includes a shift register. In addition, the source driver 504b can be, for example, multiple It is constructed using a number of analog switches, etc. It also uses shift registers, etc. Driver 504b may be configured.

[0339] A sequential circuit according to one aspect of the present invention can be applied to the gate driver 504a. A sequential circuit according to one aspect of the present invention may also be applied to the source driver 504b.

[0340] The terminal section 507 inputs power, control signals, and image signals, etc., from an external circuit to the display device. This refers to the part that is equipped with terminals for that purpose.

[0341] The protection circuit 506, when a potential outside a certain range is applied to the wiring to which it is connected, This is a circuit that creates a conductive state between two wires. The protection circuit 506 shown in Figure 20A is, for example, For example, the gate line GL, which is the wiring between the gate driver 504a and the pixel circuit 501, or - Various wirings such as data lines DL, which are the wiring between driver 504b and pixel circuit 501. It continues. Note that in Figure 20A, in order to distinguish between the protection circuit 506 and the pixel circuit 501, protection Circuit 506 is hatched.

[0342] Furthermore, the gate driver 504a and the source driver 504b are connected to the pixel section 502 and They may be provided on the same board, or the gate driver circuit or source driver circuit may be A separately formed substrate (for example, a drive circuit base formed from a single-crystal semiconductor or polycrystalline semiconductor) The board is bonded using COG or TAB (Tape Automated Bonding), etc. Alternatively, it may be configured to be mounted on a substrate on which the pixel unit 502 is provided.

[0343] Figures 20B and 20C show one of the pixel circuit configurations that can be applied to the pixel circuit 501. An example is shown. Figures 20B and 20C show the mth row and nth column (where m is a natural number between 1 and X, and n is 1). The following shows a pixel circuit for natural numbers (Y or less).

[0344] The pixel circuit 501 shown in Figure 20B consists of a liquid crystal element 570, a transistor 550, and a capacitive element. It has a sub-unit 560 and a gate line GL_m. The pixel circuit 501 also has a data line DL_n and a gate line GL_m The potential supply line VL and other connections are connected.

[0345] The potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set according to the data being written to it. A common potential is set on one of the pairs of electrodes of the liquid crystal element 570 that each of the pixel circuits 501 possesses. (Common potential) may be applied. Also, a pair of liquid crystal elements 570 of the pixel circuit 501 in each row One of the electrodes may be given a different potential.

[0346] Furthermore, the pixel circuit 501 shown in Figure 20C includes transistor 552 and transistor 554 It also has a capacitive element 562 and a light-emitting element 572. The pixel circuit 501 also has data Line DL_n, gate line GL_m, potential supply line VL_a, and potential supply line VL_b are connected. It is being done.

[0347] Furthermore, one of the potential supply lines VL_a and VL_b has a potential that is the high power supply potential. A potential VSS, which is the low power supply potential, is applied to one side of the transistor. The current flowing through the light-emitting element 572 is controlled according to the potential applied to the gate of 554. This controls the luminescence brightness from the light-emitting element 572.

[0348] Transistor 550 shown in Figure 20B, or transistor 552 shown in Figure 20C. And transistor 554 is on the same board as the transistor in gate driver 504a. It is preferable that it be provided on top.

[0349] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., are at least a part of them. This can be implemented by combining it with other configuration examples or drawings as appropriate.

[0350] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0351] (Embodiment 3) Below, we have a pixel circuit equipped with memory for correcting the gradation displayed in the pixel, and this The display device will be described below. The transistor exemplified in Embodiment 1 is exemplified below. This can be applied to transistors used in pixel circuits.

[0352] [Circuit Configuration] Figure 21A shows the circuit diagram of the pixel circuit 400. The pixel circuit 400 consists of transistor M1, It has a transistor M2, a capacitor C1, and a circuit 401. The pixel circuit 400 also has wiring S1, wiring S2, wiring G1, and wiring G2 are connected.

[0353] Transistor M1 has its gate connected to wiring G1, and one of its sources or drains connected to wiring S1. The other end is connected to one electrode of capacitance C1. Transistor M2 has a gate that is wired G2, one of the source and drain is connected to wiring S2, the other electrode is connected to capacitance C1, and rotation It connects to Route 401, respectively.

[0354] Circuit 401 is a circuit that includes at least one display element. Various elements can be used as the display element. While sub-elements can be used, typical examples include light-emitting elements such as organic EL elements and LED elements, and liquid crystals. Device, or MEMS (Micro Electro Mechanical System) EMS elements and the like can be applied.

[0355] The node connecting transistor M1 and capacitor C1 is node N1, and the node connecting transistor M2 and... Let node N2 be the node connecting to path 401.

[0356] The pixel circuit 400 maintains the potential of node N1 by turning off transistor M1. It can be maintained. Also, by turning off transistor M2, the power of node N2 can be controlled. It can maintain its position. Also, with transistor M2 in the OFF state, By writing a predetermined potential to node N1 via station M1, capacitive coupling via capacitor C1 is achieved. This allows the potential of node N2 to be changed in accordance with the change in the potential of node N1. .

[0357] Here, in the embodiment, one or both of transistors M1 and M2 are The transistor using oxide semiconductors, as exemplified in 1, can be applied. Therefore, the extremely low off-current maintains the potential of node N1 or node N2 for an extended period. This is possible. However, if the period for which the potential of each node is maintained is short (specifically, if the freight Transistors using semiconductors such as silicon are used when the frequency is 30Hz or higher. You may use "sta".

[0358] [Example of driving method] Next, an example of how the pixel circuit 400 operates will be explained using Figure 21B. This is a timing chart related to the operation of the pixel circuit 400. For simplicity of explanation, this chart is presented here. Therefore, various resistors such as wiring resistance, parasitic capacitance of transistors or wiring, and transistors The effects of the threshold voltage of the zista are not considered.

[0359] In the operation shown in Figure 21B, one frame period is divided into period T1 and period T2. Period T1 Period T2 is the period during which the potential is written to node N2, and period N1 is the period during which the potential is written to node N1. That is the case.

[0360] [Period T1] During period T1, a potential is applied to both wire G1 and wire G2 that turns the transistor ON. Also, the wiring S1 has a fixed potential V ref It supplies the first day to wiring S2. Potential V w To supply.

[0361] Node N1 receives a potential V from wiring S1 via transistor M1. ref It is given. Furthermore, node N2 receives the first data potential V from wiring S2 via transistor M2. w is given Therefore, a potential difference V can be obtained across capacitance C1. w -V ref This state is maintained.

[0362] [Period T2] Next, during period T2, a potential is applied to wiring G1 to turn on transistor M1, and The wire G2 is given a potential that turns off transistor M2. Also, the wiring S1 is supplied with the second diode DATA potential V data It supplies a predetermined constant potential to the wiring S2, or a floating It may also be in a ling state.

[0363] Node N1 receives a second data potential V from wiring S1 via transistor M1. data but Given. At this time, the second data potential V is generated by capacitive coupling with capacitance C1. data in response Then the potential of node N2 changes by a potential of dV. That is, circuit 401 receives the first data Potential V w The input will be the sum of the potential dV and the potential dV. Note that in Figure 21B, the potential dV Although it is shown to be a positive value, it may also be a negative value. That is, the second data potential. V data The potential is V ref It can be even lower.

[0364] Here, the potential dV is roughly determined by the capacitance value of capacitor C1 and the capacitance value of circuit 401. If the capacitance value of capacitor C1 is sufficiently larger than the capacitance value of circuit 401, the potential dV is the second dV. DATA potential V data The potential will be close to that.

[0365] Thus, the pixel circuit 400 combines two types of data signals to form a display element. Since it is possible to generate the potential supplied to path 401, grayscale correction can be performed within the pixel circuit 400. It becomes possible to do so.

[0366] Furthermore, the pixel circuit 400 can supply source drivers connected to wiring S1 and wiring S2. It also becomes possible to generate potentials exceeding the maximum potential. For example, when using a light-emitting element, It can also perform high dynamic range (HDR) display, etc. Furthermore, it uses liquid crystal elements. In this case, overdrive operation and other similar features can be achieved.

[0367] [Examples of application] [Examples using liquid crystal elements] The pixel circuit 400LC shown in Figure 21C has circuit 401LC. Circuit 401LC is It has a liquid crystal element LC and a capacitance C2.

[0368] In a liquid crystal element (LC), one electrode is the electrode of node N2 and capacitance C2, and the other electrode is Potential V com2 Connect to the wiring provided. Capacitor C2 is connected when the other electrode is at potential V com1 Connect to the provided wiring.

[0369] Capacity C2 functions as the retention capacity. Note that capacity C2 can be omitted if it is not needed. Cut.

[0370] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, for example High-speed display is achieved through overdrive operation, and high-voltage liquid crystal materials are applied. It is possible to do things like this. Also, by supplying a correction signal to wiring S1 or wiring S2, The gradation can also be corrected according to the operating temperature or the degradation state of the liquid crystal element (LC).

[0371] [Examples using light-emitting elements] The pixel circuit 400EL shown in Figure 21D has circuit 401EL. Circuit 401EL is It has a light-emitting element EL, a transistor M3, and a capacitor C2.

[0372] Transistor M3 has a gate that connects to one electrode of node N2 and capacitance C2, and a source and a dot. One side of Rain has a potential of V H One is a wire that is given, and the other is one electrode of the light-emitting element EL, and They are connected. Capacitor C2 is connected when the other electrode is at potential V com Connect to the provided wiring. In the light-emitting element (EL), the other electrode is at potential V L Connect to the provided wiring.

[0373] Transistor M3 has the function of controlling the current supplied to the light-emitting element EL. Capacitor C2 This functions as a holding capacity. Capacity C2 can be omitted if it is not needed.

[0374] Note that this configuration shows the anode side of the light-emitting element EL connected to transistor M3. However, transistor M3 may be connected to the cathode side. In that case, the potential V H and potential V L The value can be changed as needed.

[0375] The pixel circuit 400EL generates light by applying a high potential to the gate of transistor M3. Because it can supply a large current to the sub-EL, it can enable features such as HDR display. It can also be done by supplying a correction signal to wiring S1 or wiring S2, to transistor M3. Alternatively, it can also compensate for variations in the electrical characteristics of light-emitting elements (ELs).

[0376] Note that the circuits are not limited to those illustrated in Figures 21C and 21D, and may also include transistors or capacitors. A configuration that includes these additions is also acceptable.

[0377] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0378] (Embodiment 4) In this embodiment, a display module that can be manufactured using one aspect of the present invention is provided. I will explain.

[0379] The display module 6000 shown in Figure 22A consists of an upper cover 6001 and a lower cover 6002 Between them are the display device 6006, frame 6009, and print, with the FPC6005 connected. It has a circuit board 6010 and a battery 6011.

[0380] For example, a display device manufactured using one aspect of the present invention may be used in the display device 6006. This is possible. The display device 6006 enables the realization of an extremely low-power display module. It is possible.

[0381] The upper cover 6001 and the lower cover 6002 are sized to fit the display device 6006. The shape or dimensions can be changed as appropriate.

[0382] The display device 6006 may also have the functionality of a touch panel.

[0383] Frame 6009 is determined by the protection function of the display device 6006 and the operation of the printed circuit board 6010. It may also have functions such as blocking electromagnetic waves generated, or functioning as a heat sink.

[0384] Printed circuit board 6010 is a power supply circuit and a signal for outputting video signals and clock signals. It includes a processing circuit, a battery control circuit, and the like.

[0385] Figure 22B shows a cross-sectional view of the display module 6000 when equipped with an optical touch sensor. This is a schematic diagram.

[0386] The display module 6000 includes a light-emitting section 6015 and a receiver provided on the printed circuit board 6010. It has a light-emitting section 6016. It is also surrounded by an upper cover 6001 and a lower cover 6002. The region has a pair of light guides (light guide 6017a, light guide 6017b).

[0387] The display device 6006 connects to the printed circuit board 6010 or a battery via the frame 6009. It is installed on top of Terry 6011, etc. Display device 6006 and frame 6009 are It is fixed to the light guide section 6017a and the light guide section 6017b.

[0388] Light 6018 emitted from the light-emitting unit 6015 is directed by the light guide unit 6017a to the display device 600. It passes through the upper part of 6, through the light guide part 6017b, and reaches the light receiving part 6016. For example, a finger or Touch operation is detected when light 6018 is blocked by an object being detected, such as a stylus. It is possible.

[0389] Multiple light-emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. Multiple light-receiving units 6016 are provided at positions opposite to the light-emitting unit 6015. This allows for... Information about the location where the operation was performed can be obtained.

[0390] The light-emitting section 6015 can use a light source such as an LED element, and in particular, infrared light It is preferable to use a light source that emits light. The light receiving unit 6016 receives the light emitted by the light emitting unit 6015. A photoelectric element that converts light into an electrical signal can be used. Preferably, one that can receive infrared light. A photodiode can be used.

[0391] The light-emitting unit 60 is controlled by the light guide units 6017a and 6017b, which control the path of the light 6018. 15 and the light receiving unit 6016 can be placed below the display device 6006, and ambient light can reach the light receiving unit Reaching 6016 can suppress touch sensor malfunctions. In particular, it absorbs visible light. By using a resin that transmits infrared rays, malfunctions of touch sensors can be suppressed more effectively.

[0392] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0393] (Embodiment 5) This embodiment describes an example of an electronic device to which a display device according to one aspect of the present invention can be applied. I will reveal it.

[0394] The electronic device 6500 shown in Figure 23A is a portable device that can be used as a smartphone. It is a news terminal device.

[0395] The electronic device 6500 consists of a housing 6501, a display unit 6502, a power button 6503, and a button 6 It includes 504, speaker 6505, microphone 6506, camera 6507, and light source 6508, etc. The display unit 6502 is equipped with a touch panel function.

[0396] A display device according to one aspect of the present invention can be applied to the display unit 6502.

[0397] Figure 23B is a schematic cross-sectional view of the housing 6501, including the end on the microphone 6506 side.

[0398] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and the housing 650 Within the space surrounded by 1 and protective member 6510, display panel 6511, optical member 6512, The touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged. Yes, they are.

[0399] The protective member 6510 includes a display panel 6511, an optical member 6512, and a touch sensor panel. Nel 6513 is fixed by an adhesive layer (not shown).

[0400] Furthermore, in the area outside the display unit 6502, a portion of the display panel 6511 is folded back. It is done. Furthermore, the FPC6515 is connected to the folded portion. IC6516 is mounted on the 6515. Also, the FPC6515 is printed circuit board 6 It is connected to the terminal provided at 517.

[0401] A flexible display panel according to one aspect of the present invention is applied to the display panel 6511. This makes it possible to create extremely lightweight electronic devices. Also, the display panel 651 Because it is extremely thin, it allows for a reduction in the thickness of electronic devices while incorporating a large-capacity 6518 battery. It is also possible to fold back a portion of the display panel 6511 and place an FPC on the back of the pixel area. By positioning the connection point with 6515, it is possible to realize electronic devices with narrow bezels.

[0402] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0403] (Embodiment 6) In this embodiment, an electronic device equipped with a display device manufactured using one aspect of the present invention is provided. I will explain.

[0404] The electronic device described below is equipped with a display device according to one embodiment of the present invention in its display unit. Therefore, it is an electronic device that achieves high resolution. Also, high resolution and a large screen It can be made into an electronic device that is compatible with both systems.

[0405] The display unit of an electronic device according to one aspect of the present invention may display, for example, Full HD, 4K2K, 8K4 It can display video with resolutions of K, 16K, 8K, or higher.

[0406] Examples of electronic devices include television equipment, notebook personal computers, Equipped with relatively large screens such as monitors, digital signage, pachinko machines, and game machines. In addition to electronic devices, digital cameras, digital video cameras, digital photo frames, and portable devices are also available. Examples include mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0407] Electronic devices to which one aspect of the present invention is applied include interior or exterior walls of houses, buildings, automobiles, etc. It can be incorporated along the flat or curved surfaces of the interior or exterior of the vehicle.

[0408] Figure 24A shows the external appearance of the camera 8000 with the viewfinder 8100 attached. That is the case.

[0409] The camera 8000 consists of a housing 8001, a display unit 8002, operation buttons 8003, and a shutter. It has buttons 8004, etc. The camera 8000 also has a detachable lens 8006. It is attached.

[0410] The camera 8000 may have the lens 8006 and the housing integrated into a single unit.

[0411] Camera 8000 can be operated by pressing the shutter button 8004, or by using the touch panel function. Image capture can be performed by touching the display unit 8002.

[0412] The housing 8001 has a mount with electrodes, and in addition to the viewfinder 8100, it also has a strobe It can be connected to devices such as power supply units.

[0413] The viewfinder 8100 has a housing 8101, a display unit 8102, buttons 8103, etc. .

[0414] The housing 8101 engages with the mount of the camera 8000 via a mount, and the camera 800 It is attached to the 0. The viewfinder 8100 receives images and other data from the camera 8000. This can be displayed on the display unit 8102.

[0415] Button 8103 functions as a power button, etc.

[0416] The display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100 are equipped with this A display device according to one embodiment of the invention can be applied. Note that a camera with a built-in viewfinder can also be used. It could also be 8000.

[0417] Figure 24B shows the external appearance of the head-mounted display 8200.

[0418] The head-mounted display 8200 consists of a mounting part 8201, lenses 8202, and a main body 82 03, it has a display unit 8204, a cable 8205, etc. Also, the mounting part 8201 has It has a built-in 8206 battery.

[0419] Cable 8205 supplies power from battery 8206 to main unit 8203. Unit 203 is equipped with a wireless receiver and can display the received video information on the display unit 8204. It can. In addition, the main unit 8203 is equipped with a camera to input information about the user's eyeball or eyelid movements. It can be used as a means of force.

[0420] Furthermore, the attachment part 8201 is positioned in a location that touches the user, and the flow follows the movement of the user's eyeballs. Multiple electrodes capable of detecting currents may be provided, and the device may also have a function to recognize line of sight. Furthermore, the device may have a function to monitor the user's pulse rate based on the current flowing through the electrode. Furthermore, the mounting section 8201 is equipped with various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. It is also possible to have a function that displays the user's biometric information on the display unit 8204, or the user's head Even if it has a function to change the image displayed on the display unit 8204 in accordance with the movement of the unit, good.

[0421] A display device according to one aspect of the present invention can be applied to the display unit 8204.

[0422] Figures 24C, 24D, and 24E show the appearance of the head-mounted display 8300. The diagram shows the head-mounted display 8300, which consists of a housing 8301 and a display unit 830 It comprises 2, a band-shaped fixing device 8304, and a pair of lenses 8305.

[0423] The user can view the display on the display unit 8302 through the lens 8305. Furthermore, by arranging the display unit 8302 in a curved shape, the user can experience a high level of realism. This is preferable. Also, another image displayed in a different area of ​​the display unit 8302 is displayed by the lens 8 By viewing through the 305, it is also possible to perform 3D displays using parallax. The configuration is not limited to having one display unit 8302, but can also have two display units 8302, allowing one of the users to... One display unit may be placed for each eye.

[0424] Furthermore, a display device according to one embodiment of the present invention can be applied to the display unit 8302. A display device having a semiconductor device according to one embodiment has extremely high resolution, as shown in Figure 24E. Even when magnified using lens 8305, the user cannot see the individual pixels, resulting in a more detailed view. It can display highly realistic images.

[0425] The electronic equipment shown in Figures 25A to 25G consists of a housing 9000, a display unit 9001, and a speaker 9 003, Operation key 9005 (including power switch or operation switch), Connection terminal 900 6. Sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, Magnetism, temperature, chemicals, sound, time, hardness, electric field, electric current, voltage, power, radiation, flow rate, humidity (Including functions for measuring degrees, inclines, vibrations, odors, or infrared radiation), Microphone 900 8, etc.

[0426] The electronic devices shown in Figures 25A to 25G have various functions. For example, they can provide various information ( Functions to display still images, videos, text images, etc. on the display unit, touch panel function, calendar A function that displays the date or time, etc., through various software (programs) Functions that control processing, wireless communication functions, programs or data recorded on recording media It can have functions such as reading and processing data. Furthermore, the functions of electronic devices are related to these. It is not limited and can have a variety of functions. Even if an electronic device has multiple display units Good. Also, an electronic device may be equipped with a camera, etc., to take still images or videos and record them on a recording medium (external... It has functions such as saving to the camera (built into the camera), and displaying the captured image on the display unit. It's okay to be there.

[0427] Details of the electronic equipment shown in Figures 25A to 25G will be explained below.

[0428] Figure 25A is a perspective view showing the television equipment 9100. 0 is a display unit 9001 with a large screen, for example, 50 inches or larger, or 100 inches or larger. It is possible to insert it.

[0429] Figure 25B is a perspective view showing the personal digital assistant 9101. The personal digital assistant 9101 is, for example, For example, it can be used as a smartphone. Note that the mobile information terminal 9101 is a speed A connector (9003), connection terminal (9006), sensor (9007), etc. may be provided. Also, a portable information terminal may be provided. The 9101 can display text or image information on its multiple surfaces. (Figure 25B) The following shows an example displaying three icons 9050. Also, information 9 is shown by a dashed rectangle. 051 can also be displayed on other sides of the display unit 9001. An example of information 9051 is as follows: Notifications of incoming emails, social media messages, and phone calls, the subject of emails or social media messages, and sending... This includes the believer's name, date, time, battery level, and antenna signal strength. You may also display an icon such as 9050 in the location where 9051 is displayed.

[0430] Figure 25C is a perspective view showing the personal digital assistant 9102. The personal digital assistant 9102 is a table The display unit 9001 has the function of displaying information on three or more sides. Here, information 9052, information This shows an example where information 9053 and information 9054 are displayed on different sides. For example, the user With the mobile information terminal 9102 stored in the breast pocket of his clothing, the mobile information terminal 9102 Information 9053, displayed in a position visible from above, can also be viewed. The user can, You can check the display without taking the 9102 personal digital assistant out of your pocket, for example, to answer a phone call. It is possible to determine whether or not to do so.

[0431] Figure 25D is a perspective view showing a wristwatch-type portable information terminal 9200. Also, the display unit 90 01 has a curved display surface, and can display information along the curved surface. Furthermore, the portable information terminal 9200 can communicate with, for example, a wireless headset. This also allows for hands-free calling. Furthermore, the 9200 mobile information terminal is connected The connection terminal 9006 is used for mutual data transmission with other information terminals, or for charging. It is also possible to perform the charging operation via wireless power supply.

[0432] Figures 25E, 25F, and 25G show a foldable portable information terminal 9201 from an oblique angle. This is a visual view. Figure 25E shows the mobile information terminal 9201 in its unfolded state, and Figure 25G shows it folded. Figure 25F is a perspective view of the state in which Figure 25E and Figure 25G are transitioning from one to the other. The portable information terminal 9201 is highly portable when folded, and when unfolded... The seamless, wide display area provides excellent readability. (Features of the 9201 mobile information terminal) The display unit 9001 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a radius of curvature of 1 mm or more and 150 mm or less. Cut.

[0433] Figure 26A shows an example of a television system. The television system 7100 has a housing 710 The display unit 7500 is incorporated into 1. Here, the stand 7103 connects to the housing 710. This shows the configuration that supports option 1.

[0434] The television device 7100 shown in Figure 26A is operated by the operation switches provided on the housing 7101. This can be done by the 75 or a separate remote control unit 7111. Alternatively, the display unit 75 A touch panel is applied to 00, and the television device 7100 is operated by touching it. Alternatively, the remote control unit 7111 may have a display in addition to the operation buttons.

[0435] The television equipment 7100 is a television broadcast receiver or a network-connected device. They may have a communication device for that purpose.

[0436] Figure 26B shows the 7200 notebook personal computer. The Computer 7200 consists of a casing 7211, a keyboard 7212, and a pointing device 7 It has external connection ports 7214, etc. The display unit 7500 is incorporated into the housing 7211. It is being made.

[0437] Figures 26C and 26D show digital signage. An example of an electronic sign is shown.

[0438] The digital signage 7300 shown in Figure 26C consists of a housing 7301, a display unit 7500, and It has a speaker 7303, etc. Furthermore, it has an LED lamp, operation keys (power switch, or It may include an operating switch, connection terminals, various sensors, a microphone, etc. .

[0439] Figure 26D shows a digital signage 7400 mounted on a cylindrical column 7401. Yes. The digital signage 7400 has a display unit 75 that is installed along the curved surface of the column 7401. It has 00.

[0440] The larger the display unit 7500, the more information can be provided at once, and the more human eyes... Because it is easily absorbed, it can, for example, enhance the effectiveness of advertising.

[0441] It is preferable to apply a touch panel to the display unit 7500 so that the user can operate it. This allows for applications beyond advertising, such as route information, traffic information, or commercial facility guidance information. It can also be used to provide users with the information they are looking for.

[0442] Furthermore, as shown in Figures 26C and 26D, the digital signage 7300 or digital The Tal Signage 7400 is an information terminal 7311 such as a smartphone owned by the user. It is preferable that communication is possible via wireless communication. For example, the wide display shown on the display unit 7500 To display the information on the screen of the information terminal 7311, or to operate the information terminal 7311 By doing so, the display on the 7500 display unit can be switched.

[0443] Additionally, information terminals can be connected to the Digital Signage 7300 or Digital Signage 7400. It is also possible to run games using the 7311 as the control device (controller). This allows a large number of users to participate in and enjoy the game simultaneously.

[0444] A display device according to one embodiment of the present invention is applied to the display unit 7500 in Figures 26A to 26D. It is possible.

[0445] Although the electronic device in this embodiment has a display unit, electronic devices that do not have a display unit can also be used. An embodiment of the present invention can also be applied.

[0446] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination. [Explanation of Symbols]

[0447] LIN: Signal: RIN: Signal: BDG: Signal: CLK: Signal: OUT: Output terminal: GOU T: Output terminal: SROUT: Output terminal: PWC: Signal: RES: Signal: SP: Signal: C1 C4 to C4: Capacity: CK1 to CK4: Signal: CLK1 to CLK3: Signal: N, N1, N 2: Node: OUT to OUT6: Wiring: PWC1 to PWC4: Signal: RIN1, RI N2: Signal: 10, 10a, 10b, 10c: Sequential circuit: 11, 11a, 12, 13: times Route: 14a, 14b: Signal generation circuit: 15a, 15b: Wiring: 20: Sequential circuit: 21 to 26: Transistor: 30, 30a, 30a_n: Sequential circuit: 30b: Sequential circuit: 31 Transistors up to 34: 40a, 40b: Drive circuits: 41 to 47, 51, 52, 60 Pages 69, 71, 72: Transistors

Claims

[Claim 1] It comprises an oxide semiconductor layer, a first conductive layer, and a second conductive layer. The oxide semiconductor layer has a channel formation region for the transistor, The first conductive layer functions as the gate electrode of the transistor. The second conductive layer functions as the source electrode or drain electrode of the transistor. In a plan view, the channel length direction of the transistor is aligned with the first direction. In a plan view, the oxide semiconductor layer has a first region that extends in a second direction intersecting the first direction, The first region is a region with lower resistance than the channel formation region. In a plan view, the first conductive layer has a second region extending in the second direction, In a plan view, the second conductive layer has a third region extending in the second direction. The third region has a region that is in contact with the first region in each of the plurality of contact holes, In a plan view, the plurality of contact holes are arranged in line in the second direction, A semiconductor device in which the plurality of contact holes overlap with the first conductive layer.

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