Indication device

Abstract

To provide a display device that can improve yield. [Solution] According to the embodiment, the display device comprises a display area including a plurality of subpixels, a rib layer having a plurality of pixel apertures, a partition wall surrounding each of the plurality of pixel apertures, a plurality of display elements each arranged in the plurality of subpixels and including an organic layer that emits light in response to the application of a voltage, a plurality of sealing layers formed of an inorganic insulating material and covering each of the plurality of display elements, and a light-shielding touch detection electrode positioned above the partition wall for detecting operations on the display area. The partition wall includes a first segment and a second segment separated by a first slit, and a connecting portion that crosses the first slit and connects the first segment and the second segment. Furthermore, the touch detection electrode overlaps the connecting portion in a plan view.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device.

Background Art

[0002] In recent years, display devices applying organic light emitting diodes (OLEDs) as display elements have been put into practical use. In this type of display device, technologies for improving the yield are required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0004] One object of the present invention is to provide a display device capable of improving the yield.

Means for Solving the Problems

[0005] Generally, according to the embodiment, the display device comprises a display area including a plurality of subpixels; a rib layer having a plurality of pixel apertures located in each of the plurality of subpixels; a partition wall surrounding each of the plurality of pixel apertures, including a conductive lower part disposed above the rib layer and an upper part having an end protruding from the side surface of the lower part; a plurality of display elements disposed in each of the plurality of subpixels, each including an organic layer that emits light in response to the application of a voltage; a plurality of sealing layers formed of an inorganic insulating material that cover each of the plurality of display elements; and a light-shielding touch detection electrode disposed above the partition wall for detecting operations on the display area. The partition wall includes a first segment and a second segment separated by a first slit, and a connecting portion that crosses the first slit and connects the first segment and the second segment. Furthermore, the touch detection electrode overlaps the connecting portion in a plan view.

[0006] In another aspect of the embodiment, the display device comprises a display area including a plurality of subpixels; a rib layer having a plurality of pixel apertures located in each of the plurality of subpixels; a partition wall surrounding each of the plurality of pixel apertures, including a conductive lower part disposed above the rib layer and an upper part having an end protruding from the side surface of the lower part; a plurality of display elements disposed in each of the plurality of subpixels, each including an organic layer that emits light in response to the application of a voltage; a plurality of sealing layers made of an inorganic insulating material that cover each of the plurality of display elements; and a light-shielding touch detection electrode disposed above the partition wall for detecting operations on the display area. Furthermore, the touch detection electrode has a shape that overlaps the partition wall overall in a plan view. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 shows an example of the configuration of a display device according to the first embodiment. [Figure 2] Figure 2 is a schematic plan view showing an example of a sub-pixel layout. [Figure 3] Figure 3 is a schematic cross-sectional view of the display device along the line III-III in Figure 2. [Figure 4] Figure 4 is a schematic plan view showing some elements of the display device according to the first embodiment. [Figure 5] Figure 5 is a schematic plan view showing an example of a configuration applicable to the partition wall, sealing layer, and touch detection electrode according to the first embodiment. [Figure 6] Figure 6 is a schematic cross-sectional view of the display device along the line VI-VI in Figure 5. [Figure 7] Figure 7 is a schematic cross-sectional view of the display device along the line VII-VII in Figure 5. [Figure 8] Figure 8 is a schematic plan view showing an example of a configuration applicable to the partition wall, sealing layer, and touch detection electrode according to the second embodiment. [Figure 9] Figure 9 is a schematic plan view showing an example of a configuration applicable to the partition wall, sealing layer, and touch detection electrode according to the third embodiment. [Figure 10] Figure 10 is a schematic plan view showing an example of a configuration applicable to the partition wall, sealing layer, and touch detection electrode according to the fourth embodiment. [Figure 11A] Figure 11A is a schematic cross-sectional view showing a structure applicable to the display device according to the fourth embodiment. [Figure 11B] Figure 11B is a schematic cross-sectional view showing another structure applicable to the display device according to the fourth embodiment. [Figure 11C] Figure 11C is a schematic cross-sectional view showing yet another structure applicable to the display device according to the fourth embodiment. [Figure 12] Figure 12 is a schematic plan view showing an example of a configuration applicable to the partition wall, sealing layer, and touch detection electrode according to the fifth embodiment. [Figure 13A] Figure 13A is a schematic cross-sectional view showing a structure applicable to the display device according to the fifth embodiment. [Figure 13B] Figure 13B is a schematic cross-sectional view showing another structure applicable to the display device according to the fifth embodiment. [Figure 13C] Figure 13C is a schematic cross-sectional view showing yet another structure applicable to the display device according to the fifth embodiment.

Best Mode for Carrying Out the Invention

[0008] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and for those skilled in the art, modifications that can be easily conceived while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, for the purpose of making the description clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment, but this is merely an example and does not limit the interpretation of the present invention. Also, in this specification and each drawing, components that exhibit the same or similar functions as those described above for the previously presented drawings may be given the same reference numerals, and detailed descriptions that are repeated may be omitted as appropriate.

[0009] In the drawings, for the sake of easy understanding as necessary, the X-axis, Y-axis, and Z-axis that are orthogonal to each other are described. The direction along the X-axis is referred to as the X direction, the direction along the Y-axis is referred to as the Y direction, and the direction along the Z-axis is referred to as the Z direction. The Z direction is the normal direction of the plane including the X direction and the Y direction. Also, viewing various elements parallel to the Z direction is referred to as a plan view.

[0010] The display device according to each embodiment is an organic electroluminescence display device including an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as a television, a personal computer, an in-vehicle device, a tablet terminal, a smartphone, a mobile phone terminal, a wearable terminal, etc.

[0011] [First Embodiment] FIG. 1 is a diagram showing a configuration example of a display device DSP according to the first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be glass or a resin film having flexibility.

[0012] In this embodiment, the shapes of the substrate 10 and the display area DA in plan view are circular. However, the shapes of the substrate 10 and the display area DA in plan view are not limited to circular, and may be other shapes such as rectangles, squares, or ellipses.

[0013] The display area DA comprises a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of sub-pixels SP that display different colors. In this embodiment, it is assumed that each pixel PX includes a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. Each pixel PX may include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of sub-pixels SP1, SP2, and SP3.

[0014] The display device DSP further includes a terminal section T located in the peripheral region SA. A flexible circuit board, for example, that supplies voltage and signals for driving the display device DSP, is connected to the terminal section T.

[0015] The sub-pixel SP comprises a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0016] The display area DA is arranged with multiple scan lines G that supply scan signals to the pixel circuits 1 of each sub-pixel SP, multiple signal lines S that supply video signals to the pixel circuits 1 of each sub-pixel SP, and multiple power lines PL. In Figure 1, the scan lines G and power lines PL extend in the X direction, and the signal lines S extend in the Y direction, but this is not the only example.

[0017] The gate electrode of pixel switch 2 is connected to scan line G. One of the source and drain electrodes of pixel switch 2 is connected to signal line S, and the other is connected to the gate electrode of drive transistor 3 and capacitor 4. In drive transistor 3, one of the source and drain electrodes is connected to power line PL and capacitor 4, and the other is connected to display element DE.

[0018] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0019] Figure 2 is a schematic plan view showing an example of the layout of sub-pixels SP1, SP2, and SP3 that constitute a single pixel PX. In the example in Figure 2, sub-pixels SP1 and SP3 are aligned in the Y direction. Also, sub-pixels SP1 and SP3 are aligned with sub-pixel SP2 in the X direction.

[0020] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP1 and SP3 are alternately arranged in the Y direction, and columns in which multiple sub-pixels SP2 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2.

[0021] A rib layer 5 is arranged in the display area DA. The rib layer 5 has pixel apertures AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. In the example in Figure 2, pixel apertures AP1, AP2, and AP3 are all rectangular. The area of ​​pixel aperture AP1 is larger than the area of ​​pixel aperture AP3. Also, the area of ​​pixel aperture AP2 is larger than the area of ​​pixel aperture AP1. However, the shapes of pixel apertures AP1, AP2, and AP3 are not limited to this example.

[0022] Sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the pixel aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the pixel aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the pixel aperture AP3.

[0023] The lower electrode LE1, upper electrode UE1, and organic layer OR1 constitute the display element DE1 of the sub-pixel SP1. The lower electrode LE2, upper electrode UE2, and organic layer OR2 constitute the display element DE2 of the sub-pixel SP2. The lower electrode LE3, upper electrode UE3, and organic layer OR3 constitute the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0024] A conductive partition wall 6 is positioned above the rib layer 5. The partition wall 6 serves as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3. The partition wall 6 overlaps the rib layer 5 overall and has a similar planar shape to the rib layer 5. The partition wall 6 surrounds the sub-pixels SP1, SP2, and SP3.

[0025] The partition wall 6 has multiple slits SL extending in the Y direction. In the example in Figure 2, subpixels SP1, SP2, and SP3 that constitute one pixel PX are arranged between two slits SL in the X direction.

[0026] Furthermore, the partition wall 6 has a connecting section CT that connects the parts separated by the slit SL (segments described later). Note that the arrangement of the slit SL and the connecting section CT is not limited to the example in Figure 2. For example, there may be slit SL without a connecting section CT.

[0027] Sub-pixels SP1, SP2, and SP3 are each provided with sealing layers SE11, SE12, and SE13, respectively. Sealing layer SE11 continuously covers the display element DE1 and the surrounding partition wall 6. Sealing layer SE12 continuously covers the display element DE2 and the surrounding partition wall 6. Sealing layer SE13 continuously covers the display element DE3 and the surrounding partition wall 6. For example, sealing layer SE12 is formed continuously across multiple sub-pixels SP2 aligned in the Y direction. As another example, each sub-pixel SP2 may be provided with a sealing layer SE12 that is separated from the others.

[0028] In the example shown in Figure 2, a portion of the edge of sealing layer SE11 overlaps with slit SL. On the other hand, the edges of sealing layers SE12 and SE13 overlap with partition wall 6 all around. However, as will be described later in Figure 5, there may be sealing layers SE11 whose edges do not overlap with slit SL all around, and sealing layers SE13 whose edges overlap with slit SL in part. Also, a portion of the edge of sealing layer SE12 may overlap with slit SL.

[0029] Furthermore, in the example shown in Figure 2, the ends of sealing layers SE11 and SE12 overlap, the ends of sealing layers SE11 and SE13 overlap, and the ends of sealing layers SE12 and SE13 overlap. In another example, the ends of sealing layers SE11, SE12, and SE13 may be spaced apart.

[0030] Figure 3 is a schematic cross-sectional view of the display device DSP along the line III-III in Figure 2. A circuit layer 11 is arranged on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring such as the pixel circuit 1, scan line G, signal line S, and power line PL shown in Figure 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11.

[0031] The lower electrodes LE1, LE2, and LE3 are each placed on top of the organic insulating layer 12. The rib layer 5 is placed on top of the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are all covered by the rib layer 5.

[0032] The partition wall 6 includes a conductive lower portion 61 positioned on the rib layer 5 and an upper portion 62 positioned on the lower portion 61. The upper portion 62 has a greater width than the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the sides of the lower portion 61. In other words, the partition wall 6 is overhanging in that both ends of the upper portion 62 protrude beyond the sides of the lower portion 61.

[0033] In the example shown in Figure 3, the lower part 61 has a bottom layer 63 and an axial layer 64. The bottom layer 63 is formed thinner than the axial layer 64 and is located between the axial layer 64 and the rib layer 5. Both ends of the bottom layer 63 protrude from both sides of the axial layer 64.

[0034] The organic layer OR1 covers the lower electrode LE1 through the pixel aperture AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel aperture AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel aperture AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of the partition wall 6.

[0035] Display element DE1 includes a cap layer CP1 covering the upper electrode UE1. Display element DE2 includes a cap layer CP2 covering the upper electrode UE2. Display element DE3 includes a cap layer CP3 covering the upper electrode UE3. The cap layers CP1, CP2, and CP3 each serve as optical adjustment layers that improve the efficiency of light extraction from the organic layers OR1, OR2, and OR3, respectively.

[0036] In the following explanation, a multilayer containing an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as multilayer film FL1, a multilayer containing an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as multilayer film FL2, and a multilayer containing an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as multilayer film FL3.

[0037] The sub-pixels SP1, SP2, and SP3 are each covered by the aforementioned sealing layers SE11, SE12, and SE13, respectively, which cover the stacked films FL1, FL2, and FL3. Specifically, sealing layer SE11 continuously covers the cap layer CP1 and the partition wall 6 surrounding sub-pixel SP1. Sealing layer SE12 continuously covers the cap layer CP2 and the partition wall 6 surrounding sub-pixel SP2. Sealing layer SE13 continuously covers the cap layer CP3 and the partition wall 6 surrounding sub-pixel SP3.

[0038] In the example shown in Figure 3, the ends of the sealing layers SE11 and SE12 overlap in the Z direction above the partition 6 between sub-pixels SP1 and SP2. Also, the ends of the sealing layers SE11 and SE13 overlap in the Z direction above the partition 6 between sub-pixels SP1 and SP3. This example is not limited to this one; the ends of the sealing layers SE11, SE12, and SE13 may be spaced apart above the partition 6.

[0039] For example, gaps are formed between the sealing layers SE11, SE12, SE13 and the upper part 62 of the partition wall 6. The laminated films FL1, FL2, FL3 may be placed in at least a portion of these gaps.

[0040] The sealing layers SE11, SE12, and SE13 are covered by the resin layer RS1. The resin layer RS1 is covered by the sealing layer SE2. The sealing layer SE2 is covered by the resin layer RS2. The resin layers RS1, RS2, and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0041] In this embodiment, a touch detection electrode 7 for detecting user touch operations is placed on the sealing layer SE2. The touch detection electrode 7 has the same shape as the partition wall 6 in a plan view.

[0042] A cover member, such as a polarizing plate, protective film, or cover glass, may be further placed above the resin layer RS2. Such a cover member may be bonded to the resin layer RS2 via an adhesive layer, such as OCA (Optical Clear Adhesive).

[0043] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, SE2 are formed of silicon nitride. The resin layers RS1, RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0044] The lower electrodes LE1, LE2, and LE3 each have a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of this reflective layer, respectively. Each conductive oxide layer can be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0045] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0046] The organic layers OR1, OR2, and OR3 are composed of multiple thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked sequentially in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including multiple emissive layers.

[0047] The cap layers CP1, CP2, and CP3 have a laminated structure in which multiple transparent layers are stacked, for example. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from those of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. Note that at least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0048] The bottom layer 63 and axial layer 64 of the partition wall 6 are formed of a metallic material. For example, the metallic material for the bottom layer 63 can be molybdenum, titanium, titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb). For example, the metallic material for the axial layer 64 can be aluminum, aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi). The axial layer 64 may also be formed of an insulating material.

[0049] The upper part 62 of the partition wall 6 includes, for example, a lower layer formed of a metallic material and an upper layer formed of a conductive oxide. In this case, the metallic material of the lower layer can be titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy. The conductive oxide of the upper layer can be ITO or IZO. The upper part 62 may consist of three or more layers, or it may be formed of a single layer. Furthermore, the upper part 62 may include a layer formed of an insulating material.

[0050] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the lower part 61. The lower electrodes LE1, LE2, and LE3 are supplied with pixel voltages corresponding to the video signal on the signal line S through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0051] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of organic layer OR1 emits light in the blue wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of organic layer OR2 emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of organic layer OR3 emits light in the red wavelength range.

[0052] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layers into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3.

[0053] The touch detection electrode 7 is made of, for example, a metallic material and has light-shielding properties. The touch detection electrode 7 may have a single-layer structure or a multi-layer structure. Various configurations can be applied to the multi-layer structure, but one example is a three-layer structure of titanium, aluminum, and titanium (so-called TAT).

[0054] Figure 4 is a schematic plan view showing some elements of the display device DSP. The partition wall 6 is divided into multiple segments SG by multiple slits SL, as also shown in Figure 2. Note that in Figure 4, the slits SL and segments SG are schematically shown. For example, if slits SL are located on both sides of the pixel PX in the X direction, as shown in Figure 2, more slits SL are formed in the display area DA.

[0055] At least some of the multiple segments SG are connected by connecting sections CT that cross the slits SL, as shown in Figure 2. On the other hand, some of the multiple slits SL may not have connecting sections CT.

[0056] Each slit SL contributes to improving the transmittance of the display device DSP. This allows for an improvement in the detection capability of an optical sensor, for example, when the optical sensor is located on the back side of the display device DSP.

[0057] Furthermore, one possible usage configuration for the display device DSP is to place an antenna on its back side, enabling short-range wireless communication through this antenna. In this usage configuration, eddy currents may be generated in the partition wall 6 due to the magnetic field during communication, potentially reducing signal strength. In this case, if there is a slit SL where no connection CT is located, the generation of large eddy currents throughout the entire display area DA can be suppressed, thereby preventing a decrease in signal strength.

[0058] Each segment SG is connected to a power supply line PW located in the surrounding area SA. The power supply line PW is connected to a terminal section T. A common voltage is applied to each segment SG from the terminal section T via the power supply line PW.

[0059] Multiple touch detection electrodes 7 are arranged in the display area DA. These touch detection electrodes 7 are connected to the terminal section T via wiring. When an object such as a user's finger touches or comes into close proximity to the display area DA, the capacitance between the object and the touch detection electrode 7 changes, and a corresponding signal is output from the touch detection electrode 7 to the terminal section T. However, the detection method using the touch detection electrodes 7 is not limited to this example.

[0060] Figure 5 is a schematic plan view showing an example of a configuration applicable to the partition wall 6, sealing layers SE11, SE12, SE13, and touch detection electrode 7 according to this embodiment. In this figure, the partition wall 6 is given a dot pattern and the touch detection electrode 7 is given a diagonal line pattern.

[0061] In Figure 5, the partition wall 6 shows a portion of the four segments SG1, SG2, SG3, and SG4 (the first to fourth segments) arranged in the X direction. These segments SG1, SG2, SG3, and SG4 are separated by three slits SL.

[0062] Segments SG1 and SG2 are connected by multiple connecting sections CT (only one is shown in Figure 5). Segments SG3 and SG4 are also connected by multiple connecting sections CT. On the other hand, segments SG2 and SG3 are not connected by connecting sections CT. In the following explanation, slits SL that have connecting sections CT, such as the slit SL between segments SG1 and SG2, or between segments SG3 and SG4, will be called slit SLa (first slit). Also, slits SL that do not have connecting sections CT, such as the slit SL between segments SG2 and SG3, will be called slit SLb (second slit).

[0063] In the example shown in Figure 5, a connection section CT is provided at a position aligned with the subpixel SP3 in the X direction. The connection section CT may be provided to the sides of all subpixel SP3 in segments SG2 and SG4, or it may be provided only to the sides of some of the subpixel SP3.

[0064] In the example shown in Figure 5, the shapes of the sealing layers SE11, SE12, and SE13 located in segment SG2 are the same as those shown in Figure 2. That is, the ends of sealing layers SE12 and SE13 overlap with the partition wall 6 overall, and a portion of the end of sealing layer SE11 is located in the slit SLa.

[0065] On the other hand, in segment SG3, the end of the sealing layer SE11 overlaps with the partition wall 6 all around, and a portion of the end of the sealing layer SE13 is located in the slit SLb. The end of the sealing layer SE12 overlaps with the partition wall 6 overall, similar to segment SG2.

[0066] Here, pixels having sealing layers SE11, SE12, and SE13 of segment SG2 as shown in Figure 5 are defined as pixels PX1, and pixels having sealing layers SE11, SE12, and SE13 of segment SG3 are defined as pixels PX2. For example, in the display area DA, pixels PX1 and pixels PX2 may be arranged alternately in the X direction. Also, pixels PX1 and pixels PX2 may be arranged alternately in the Y direction as well.

[0067] The touch detection electrode 7 is mostly composed of linear sections that are thinner than the partition wall 6. For example, the touch detection electrode 7 has a linear section La that extends in the X direction between two adjacent subpixels SP2 in the Y direction, and linear sections Lb and Lc that extend in the X direction between adjacent subpixels SP1 and SP3 in the Y direction. Linear section Lb is spaced apart from linear section La and aligned in the X direction. Linear section Lc has a larger width than linear sections La and Lb.

[0068] Furthermore, the touch detection electrode 7 has a first portion P1, a second portion P2, and a third portion P3 located near the slit SLa. The first portion P1 overlaps with segment SG1. The second portion P2 overlaps with segment SG2.

[0069] The first section P1 is connected to the straight section La that overlaps with segment SG1 and extends in the Y direction (the direction in which slit SLa extends) along slit SLa. The second section P2 is connected to the straight section Lc that overlaps with segment SG2 and extends in the Y direction along slit SLa. The third section P3 connects the first section P1 and the second section P2. The third section P3 has a larger width than the first section P1 and the second section P2 and overlaps with the entire connecting section CT that crosses slit SLa. A portion of the connecting section CT may be exposed from the third section P3.

[0070] Furthermore, the touch detection electrode 7 has a fourth portion P4, a fifth portion P5, and a sixth portion P6 located near the slit SLb. The fourth portion P4 overlaps with segment SG2. The fifth portion P5 overlaps with segment SG3.

[0071] The fourth section P4 is connected to the straight section La that overlaps with segment SG2 and extends in the Y direction (the direction in which slit SLb extends) along slit SLb. The fifth section P5 is connected to the straight section Lc that overlaps with segment SG3 and extends in the Y direction along slit SLb. The sixth section P6 connects the fourth section P4 and the fifth section P5. The sixth section P6 is wider than the fourth section P4 and the fifth section P5 and overlaps with slit SLb.

[0072] For example, the fourth part P4, the fifth part P5, and the sixth part P6 have the same shape as the first part P1, the second part P2, and the third part P3. However, at least one of these may have a different shape.

[0073] The first part P1, the second part P2, and the third part P3 are provided for all connection parts CT, for example. The fourth part P4, the fifth part P5, and the sixth part P6 do not overlap with the connection parts CT, but are provided in positions aligned with the first part P1, the second part P2, and the third part P3 in the X direction. This increases the regularity of the pattern of the touch detection electrode 7, regardless of the presence or absence of connection parts CT.

[0074] Figure 6 is a schematic cross-sectional view of the display device DSP along the line VI-VI in Figure 5. Figure 7 is a schematic cross-sectional view of the display device DSP along the line VII-VII in Figure 5. In these figures, elements below the organic insulating layer 12 and elements above the sealing layer SE2 and touch detection electrode 7 are omitted.

[0075] As shown in Figure 6, the connecting portion CT, like the rest of the partition wall 6, has a lower portion 61 (bottom layer 63 and axial layer 64) and an upper portion 62. The end E2 of the sealing layer SE12 and the end E3 of the sealing layer SE13 are located above the partition wall 6. The third portion P3 of the touch detection electrode 7 faces the partition wall 6 (connecting portion CT) via the resin layer RS1 and the sealing layer SE2.

[0076] As shown in Figure 7, the side portion of the partition wall 6 along the slit SL (SLb) is an overhang shape, with the upper part 62 protruding from the side surface of the axial layer 64. For example, the rib layer 5 is not open in the slit SLb. In the example in Figure 7, the end E3 of the sealing layer SE13 is located in the slit SLb. The sixth portion P6 of the touch detection electrode 7 faces the partition wall 6 via the resin layer RS1 and the sealing layer SE2, and overlaps with the slit SLb in the Z direction.

[0077] In Figures 6 and 7, a gap GP is formed beneath the edges E2 and E3. Although not shown in Figures 6 and 7, a gap GP is also formed beneath the edges of the sealing layer SE11. At least a portion of the gap GP is filled with the resin layer RS1. As described above in the explanation of Figure 2, the laminated films FL1, FL2, and FL3 may be placed in at least a portion of the gap GP.

[0078] The gap GP is formed during the manufacturing process of the DSP display device when the originally formed multilayer films FL1, FL2, and FL3 disappear. Specifically, the multilayer films FL2 and FL3 beneath the edges of the sealing layers SE11, SE12, and SE13 are eroded by various etching solutions, creating voids. In one example, the multilayer film FL1 and sealing layer SE11 are formed first, the multilayer film FL2 and sealing layer SE12 are formed second, and the multilayer film FL3 and sealing layer SE13 are formed last. In this case, among the multilayer films FL1, FL2, and FL3, the first-formed film FL1 is the most likely to disappear, while the last-formed film FL3 is the least likely to disappear. Therefore, in the areas indicated as gap GP, it is possible that the multilayer films FL1 and FL2 have disappeared, but the multilayer film FL3 remains.

[0079] Furthermore, if the connection portion CT is located in the configuration shown in Figure 5, and is positioned to align with the sub-pixel SP1 in the X direction, the sealing layer SE11 of segment SG2 will partially cover the connection portion CT. In this case, the laminated film FL located above the connection portion CT will also be more susceptible to erosion by etching solutions, etc., through the laminated film FL located above the sub-pixel SP1 and onto the partition wall 6 surrounding it. Therefore, from the viewpoint of stably controlling the degree of disappearance of the initially formed laminated film FL, it is preferable to provide the connection portion CT near the last-to-form sub-pixel SP3, as shown in Figure 5.

[0080] Next, an example of the effects of this embodiment will be described. In this embodiment, when the partition wall 6 is composed of multiple segments SG, if slits SLa with connecting CTs and slits SLb without connecting CTs are mixed, there is a possibility that differences in appearance will occur between these slits SLa and SLb. That is, when ambient light is incident on the display area DA with all pixels PX turned off, reflection due to the connecting CT occurs in slit SLa but not in slit SLb, so streaky unevenness extending in the Y direction may be visible to the user.

[0081] In contrast, in this embodiment, the touch detection electrode 7 (third portion P3) overlaps with the connection portion CT. This makes it possible to suppress unevenness in reflected light caused by the connection portion CT. Furthermore, if the slit SLb also has a sixth portion P6 similar to the third portion P3, the reflected light from the touch detection electrode 7 in both slits SLa and SLb will have a similar pattern. Therefore, it is possible to suppress unevenness in reflected light caused by the touch detection electrode 7. In addition to the above, various other desirable effects can be obtained from this embodiment.

[0082] [Second Embodiment] A second embodiment will now be described. The configuration of the display device DSP, unless otherwise specified, can be the same as that of the first embodiment.

[0083] Figure 8 is a schematic plan view showing an example of a configuration applicable to the partition wall 6, sealing layers SE11, SE12, SE13, and touch detection electrode 7 according to the second embodiment. Similar to Figure 5, the partition wall 6 is given a dot pattern and the touch detection electrode 7 is given a diagonal line pattern.

[0084] In this embodiment, the first portion P1, the second portion P2, the fourth portion P4, and the fifth portion P5 extend in directions that intersect the X and Y directions (the extension direction of the slit). In the example in Figure 8, the extension directions of the first portion P1, the second portion P2, the fourth portion P4, and the fifth portion P5 are the same. However, at least one extension direction of these portions may differ from the extension direction of the other portions.

[0085] If the position of the touch detection electrode 7 relative to the partition wall 6 is slightly shifted in the X direction, in a configuration where the first part P1, second part P2, fourth part P4, and fifth part P5 extend in the Y direction on both sides of the slit SL as in Figure 5, these parts may block light over a wide area of ​​the slit SL. In this case, the transmittance of the display device DSP will decrease.

[0086] In contrast, in this embodiment, the first portion P1, the second portion P2, the fourth portion P4, and the fifth portion P5 are inclined with respect to the extension direction of the slit SL. Therefore, even if the formation position of the touch detection electrode 7 on the partition wall 6 is slightly shifted in the X direction, the area in which these portions overlap with the slit SL can be reduced.

[0087] [Third Embodiment] A third embodiment will now be described. Unless otherwise specified, the configuration of the display device DSP can be the same as that of the first embodiment.

[0088] Figure 9 is a schematic plan view showing an example of a configuration applicable to the partition wall 6, sealing layers SE11, SE12, SE13, and touch detection electrode 7 according to the third embodiment. Similar to Figure 5, the partition wall 6 is given a dot pattern and the touch detection electrode 7 is given a diagonal line pattern.

[0089] In this embodiment, as in the second embodiment, the first portion P1, the second portion P2, the fourth portion P4, and the fifth portion P5 are inclined with respect to the Y direction (the extension direction of the slit SL). However, the inclination angles of the first portion P1 and the second portion P2 are different. Also, the inclination angles of the fourth portion P4 and the fifth portion P5 are different.

[0090] Specifically, the first part P1 and the second part P2 have shapes symmetrical with respect to the axis (center line in the X direction) of slit SLa. Similarly, the fourth part P4 and the fifth part P5 have shapes symmetrical with respect to the axis (center line in the X direction) of slit SLb.

[0091] In this embodiment, the second section P2 and the fifth section P5 are connected to the straight section Lb. As a result, the first section P1, the second section P2, and the third section P3 form a V shape. Similarly, the fourth section P4, the fifth section P5, and the sixth section P6 form a V shape.

[0092] Even with the configuration of this embodiment, as in the second embodiment, if the formation position of the touch detection electrode 7 on the partition wall 6 is slightly shifted in the X direction, the area in which these parts overlap with the slit SL can be reduced.

[0093] [Fourth Embodiment] A fourth embodiment will now be described. The configuration of the display device DSP, unless otherwise specified, can be the same as that of the embodiments described above.

[0094] Figure 10 is a schematic plan view showing an example of a configuration applicable to the partition wall 6, sealing layers SE11, SE12, SE13, and touch detection electrode 7 according to the fourth embodiment. Similar to Figure 5, the partition wall 6 is given a dot pattern and the touch detection electrode 7 is given a diagonal line pattern.

[0095] In this embodiment, the touch detection electrode 7 has a shape that overlaps the partition wall 6 overall. Here, "overall overlapping shape" includes not only a shape in which the touch detection electrode 7 completely overlaps the entire partition wall 6 in a plan view, but also a shape in which a small part of the partition wall 6 (for example, in a range of 3.0 μm or less) is exposed from the touch detection electrode 7, but the majority of the rest overlaps.

[0096] The touch detection electrode 7 has an electrode aperture AP71 that overlaps with the sub-pixel SP1, an electrode aperture AP72 that overlaps with the sub-pixel SP2, and an electrode aperture AP73 that overlaps with the sub-pixel SP3. Furthermore, the touch detection electrode 7 has a connection portion CTa that overlaps with the connection portion CT of the partition wall 6. In the example in Figure 10, a connection portion CTa is also provided in the slit SLb where the connection portion CT is not located.

[0097] As described above, the laminated films FL1, FL2, and FL3 on the partition wall 6 may disappear during the manufacturing process of the display device DSP. Since the laminated films FL1, FL2, and FL3 include upper electrodes UE1, UE2, and UE3 formed from metallic materials such as magnesium-silver alloy (MgAg), if the degree of disappearance of the laminated films FL1, FL2, and FL3 differs in various places, the appearance of the reflected light may deteriorate.

[0098] In contrast, if the touch detection electrode 7 is shaped to overlap the partition wall 6 as in this embodiment, it is possible to suppress the deterioration of appearance caused by differences in the degree of disappearance of the laminated films FL1, FL2, and FL3.

[0099] Figures 11A to 11C are schematic cross-sectional views showing structures applicable to the DSP display device according to this embodiment. These cross-sectional views correspond to those along the line XI-XI in Figure 10.

[0100] In Figure 11A, as in the example shown in Figure 3, the touch detection electrode 7 is positioned on top of the sealing layer SE2. The touch detection electrode 7 has the same width as, for example, the upper part 62 of the partition wall 6.

[0101] In Figure 11B, the touch detection electrode 7 has a first layer 71 and a second layer 72. The second layer 72 is located on top of the sealing layer SE2. The first layer 71 is located on top of the second layer 72. In other words, the first layer 71 is in contact with the upper surface of the second layer 72. The first layer 71 and the second layer 72 are covered by a resin layer RS2.

[0102] The second layer 72 has a smaller thickness than the first layer 71. The second layer 72 also has a larger width than the first layer 71. The first layer 71 and the second layer 72 are positioned so that their centers coincide in the width direction. The outline of the touch detection electrode 7 shown in Figure 10 corresponds to the outline of the second layer 72.

[0103] The first layer 71 is conductive and is formed of, for example, a metallic material. The first layer 71 may be a single layer or a multilayer structure. The second layer 72 has at least light-shielding properties. The second layer 72 may be formed of a metallic material and may further have conductivity.

[0104] In one example, the first layer 71 has a three-layer structure of titanium, aluminum, and titanium. The second layer 72 is made of titanium. The thickness of the first layer 71 is, for example, 300 nm or more, and the thickness of the second layer 72 is, for example, 200 nm or less. However, the composition and thickness of the first layer 71 and the second layer 72 are not limited to those exemplified here.

[0105] In Figure 11C, the touch detection electrode 7 also has a first layer 71 and a second layer 72. Furthermore, an insulating layer IL is placed between the first layer 71 and the second layer 72. The insulating layer IL is formed of an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0106] In the configuration shown in Figure 11C, it is preferable that the first layer 71 and the second layer 72 are at the same potential. Therefore, the first layer 71 and the second layer 72 may be connected, for example, through a contact hole provided in the insulating layer IL. Such a contact hole may be provided in the display area DA or in the peripheral area SA.

[0107] In this embodiment, the width of the touch detection electrode 7 is approximately the same as that of the partition wall 6. Therefore, if the touch detection electrode 7 is formed thickly in the configuration shown in Figure 11A, the light emitted from the display elements DE1, DE2, and DE3 that is tilted with respect to the Z direction may be blocked by the touch detection electrode 7, potentially reducing the viewing angle characteristics. On the other hand, if the touch detection electrode 7 is made thinner, a decrease in detection performance may occur.

[0108] In contrast, in the configurations shown in Figures 11B and 11C, the thick, narrow first layer 71 maintains detection performance while the thin, wide second layer 72 improves the appearance of the reflected light. Furthermore, because the second layer 72 is thin, the light emitted from the display elements DE1, DE2, and DE3, which is tilted in the Z direction, is less likely to be blocked. This suppresses a decrease in viewing angle characteristics.

[0109] [Fifth Embodiment] A fifth embodiment will now be described. The configuration of the display device DSP, unless otherwise specified, can be the same as that of the embodiments described above.

[0110] Figure 12 is a schematic plan view showing an example of a configuration applicable to the partition wall 6, sealing layers SE11, SE12, SE13, and touch detection electrode 7 according to the fifth embodiment. Similar to Figure 5, the partition wall 6 is given a dot pattern and the touch detection electrode 7 is given a diagonal line pattern.

[0111] In this embodiment, as in the fourth embodiment, the touch detection electrode 7 has a shape that overlaps the partition wall 6 overall. Furthermore, in this embodiment, the edges of the electrode apertures AP71, AP72, and AP73 substantially coincide with the edges of the pixel apertures AP1, AP2, and AP3, respectively. Here, "substantially coincide" includes not only cases where the edges of the electrode apertures AP71, AP72, and AP73 and the edges of the pixel apertures AP1, AP2, and AP3 perfectly coincide in a plan view, but also cases where they are slightly misaligned (for example, by a few percent of the aperture width).

[0112] Figures 13A to 13C are schematic cross-sectional views showing structures applicable to the DSP display device according to this embodiment. These cross-sectional views correspond to the line XIII-XIII in Figure 12.

[0113] In Figure 13A, as in the example in Figure 11A, the touch detection electrode 7 is positioned on top of the sealing layer SE2. The touch detection electrode 7 has the same width as the rib layer 5 below it.

[0114] In Figures 13B and 13C, the touch detection electrode 7 has a first layer 71 and a second layer 72, similar to the examples in Figures 11B and 11C. In Figure 13C, an insulating layer IL is placed between the first layer 71 and the second layer 72. In both of these figures, the second layer 72 has the same width as the rib layer 5 below it.

[0115] Although Figures 13A to 13C show a cross-section across the sub-pixel SP3, the structure of the partition wall 6 and touch detection electrode 7 surrounding the sub-pixels SP1 and SP2 is the same as that shown in Figures 13A to 13C.

[0116] With the configuration of this embodiment, the touch detection electrode 7 shields a wider area than in the fourth embodiment, thus more effectively suppressing the deterioration of appearance caused by differences in the degree of disappearance of the laminated films FL1, FL2, and FL3.

[0117] All display devices that a person skilled in the art can implement by appropriately modifying the design based on the display devices described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0118] Within the scope of the concept of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, any modifications made by a person skilled in the art to add, delete, or change the design of any of the above-described embodiments, or to add, omit, or change the conditions of any process, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0119] Furthermore, any other effects and advantages brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0120] DSP...Display device, DA...Display area, SA...Peripheral area, PX...Pixel, SP1, SP2, SP3...Sub-pixel, LE1, LE2, LE3...Lower electrode, OR1, OR2, OR3...Organic layer, UE1, UE2, UE3...Upper electrode, SE11, SE12, SE13...Sealing layer, SL...Slit, SG...Segment, 5...Rib layer, 6...Partition, 61...Lower part, 62...Upper part, 7...Touch detection electrode.

Claims

1. A display area containing multiple subpixels, A rib layer having a plurality of pixel apertures located in each of the plurality of subpixels, It includes a conductive lower part positioned above the rib layer and an upper part having an end protruding from the side surface of the lower part, and a partition wall surrounding each of the plurality of pixel apertures, Each of the aforementioned sub-pixels is arranged and includes a plurality of display elements, each containing an organic layer that emits light in response to the application of a voltage, A plurality of sealing layers formed of an inorganic insulating material, each covering the plurality of display elements, A light-shielding touch detection electrode positioned above the partition wall for detecting operations on the display area, Equipped with, The aforementioned partition wall is The first segment and the second segment, separated by the first slit, A connecting portion that crosses the first slit and connects the first segment and the second segment, Includes, The touch detection electrode overlaps with the connection portion in a plan view. Display device.

2. The aforementioned touch detection electrode is A linear first portion that overlaps with the first segment in a plan view, A linear second portion that overlaps with the second segment in a plan view, In a plan view, the third part overlaps with the connecting part and connects the first part and the second part, It has, The display device according to claim 1.

3. The first and second portions extend in the direction of extension of the first slit. The display device according to claim 2.

4. At least one of the first portion and the second portion extends in a direction intersecting the extending direction of the first slit. The display device according to claim 2.

5. The first part, the second part, and the third part form a V shape. The display device according to claim 4.

6. The partition wall further includes a third segment separated from the second segment by a second slit, The aforementioned touch detection electrode is A linear fourth portion that overlaps with the second segment in a plan view, A linear fifth portion that overlaps with the third segment in a plan view, A sixth portion that overlaps with the second slit in a plan view and connects the fourth portion and the fifth portion, It has The display device according to any one of claims 1 to 5.

7. A display area containing multiple subpixels, A rib layer having a plurality of pixel apertures located in each of the plurality of subpixels, It includes a conductive lower part positioned above the rib layer and an upper part having an end protruding from the side surface of the lower part, and a partition wall surrounding each of the plurality of pixel apertures, Each of the aforementioned sub-pixels is arranged and includes a plurality of display elements, each containing an organic layer that emits light in response to the application of a voltage, A plurality of sealing layers formed of an inorganic insulating material, each covering the plurality of display elements, A light-shielding touch detection electrode positioned above the partition wall for detecting operations on the display area, Equipped with, The touch detection electrode has a shape that, in a plan view, completely overlaps with the partition wall. Display device.

8. The touch detection electrode has an electrode aperture that overlaps with the pixel aperture, The edge of the electrode aperture and the edge of the pixel aperture substantially coincide in a plan view. The display device according to claim 7.

9. The aforementioned touch detection electrode is A conductive first layer, A light-shielding second layer having a thinner thickness and a wider width than the first layer, It is equipped with The display device according to claim 7 or 8.

10. The first layer is in contact with the upper surface of the second layer. The display device according to claim 9.

11. The system further comprises an insulating layer disposed between the first layer and the second layer. The display device according to claim 9.

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