Semiconductor equipment

Abstract

To provide a semiconductor device capable of reducing power consumption. [Solution] The nMOS transistor MNo receives an external power supply voltage Vcc as input to its drain and outputs an internal power supply voltage Vdd from its source. The charge pump circuit CP receives the external power supply voltage Vcc as input and generates a boosted power supply voltage Vcp that is higher than Vcc. The reference voltage generation circuit VREFG1 generates a first reference voltage Vref1 that reflects the characteristic variations of the nMOS transistor MNo, using a replica nMOS transistor MNr formed using the same manufacturing process as the nMOS transistor MNo. The voltage regulator circuit VREGb applies a gate voltage VGn determined based on the first reference voltage Vref1 to the gate of the nMOS transistor MNo.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, for example, a semiconductor device including a power supply circuit.

Background Art

[0002] Patent Document 1 shows a semiconductor device including a switching regulator and a linear regulator. When an input voltage is applied, the switching regulator is put into a stopped state and the linear regulator is put into an operating state. After the input voltage is applied, the switching regulator is controlled from the stopped state to the operating state.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In recent years, especially for ICs (integrated circuits), in other words, semiconductor devices for small devices typified by smartphones and tablets, reduction in the number of terminals and miniaturization of packages have been required. However, reduction in the number of terminals and miniaturization of packages lead to a decrease in heat dissipation. Therefore, it is desirable to suppress heat generation by reducing the power consumption of the semiconductor device.

[0005] On the other hand, a semiconductor device usually generates an internal power supply voltage lower than an external power supply voltage using a linear regulator, in other words, a LDO (Low Drop Out) regulator as shown in Patent Document 1. Logic circuits and the like in the semiconductor device operate at the internal power supply voltage. However, in order to operate the LDO regulator normally, a relatively high external power supply voltage is required. This high external power supply voltage can become a bottleneck in reducing power consumption.

[0006] The embodiments described later were made in view of these considerations, and other issues and novel features will become clear from the description and accompanying drawings of this specification. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment includes a power supply circuit that receives an external power supply voltage and generates an internal power supply voltage having a voltage value less than or equal to the external power supply voltage, and a load circuit to which the internal power supply voltage is supplied. The power supply circuit includes an n-channel output transistor, a charge pump circuit, a reference voltage generation circuit, and a voltage regulator circuit. The output transistor receives the external power supply voltage as input to its drain and outputs the internal power supply voltage from its source. The charge pump circuit receives the external power supply voltage as input and generates a boosted power supply voltage higher than the external power supply voltage. The reference voltage generation circuit is supplied with the boosted power supply voltage and generates a first reference voltage that reflects the characteristic variations of the output transistor using a replica transistor formed using the same manufacturing process as the output transistor. The voltage regulator circuit is supplied with the boosted power supply voltage and applies a gate voltage determined based on the first reference voltage to the gate of the output transistor. [Effects of the Invention]

[0008] According to the above embodiment, power consumption in a semiconductor device can be reduced. [Brief explanation of the drawing]

[0009] [Figure 1A] Figure 1A is a block diagram showing an example of the configuration of a semiconductor device according to one embodiment. [Figure 1B] Figure 1B is a schematic diagram showing an example of the external shape of a semiconductor device according to one embodiment. [Figure 2] Figure 2 is a circuit diagram showing an example of a power supply circuit configuration according to a comparative example in Figure 1A. [Figure 3] Figure 3 is a schematic diagram showing an example of the voltage values ​​of each node in Figure 2, corresponding to the external power supply voltage. [Figure 4] Figure 4 is a schematic diagram illustrating an example of the problems shown in Figure 2. [Figure 5] Figure 5 is a circuit diagram showing an example of the configuration of a power supply circuit according to one embodiment in Figure 1A. [Figure 6A] Figure 6A is a schematic diagram showing an example of the voltage relationships at each node in Figure 5. [Figure 6B] Figure 6B is a schematic diagram showing an example of the voltage values ​​of each node in Figure 5, corresponding to the external power supply voltage. [Figure 7] Figure 7 is a timing chart showing an example of the voltage or current generated at each node in Figure 5. [Figure 8] Figure 8 is a circuit diagram showing a modified configuration of the charge pump circuit shown in Figure 5. [Figure 9A] Figure 9A is a circuit diagram showing an example of a typical power supply circuit configuration in Figure 1A. [Figure 9B] Figure 9B is a circuit diagram showing an example of the amplifier circuit configuration in Figure 9A. [Figure 10] Figure 10 is a schematic diagram illustrating an example of the problems shown in Figures 9A and 9B. [Figure 11] Figure 11 is a timing chart illustrating an example of a problem different from that shown in Figure 10. [Modes for carrying out the invention]

[0010] In the following embodiments, the description will be divided into multiple sections or embodiments where necessary for convenience. Unless otherwise specified, these are not unrelated, and one may be a modification, detail, or supplementary explanation of part or all of the other. Furthermore, in the following embodiments, when referring to the number of elements (including number, numerical value, quantity, range, etc.), unless otherwise specified or clearly limited to a specific number in principle, it is not limited to that specific number, and may be greater than or less than that number.

[0011] Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential, except in cases where it is specifically stated or where it is considered clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it shall include those that are substantially approximated or similar to the shape, etc., except in cases where it is specifically stated and cases where it is clearly not so in principle. This also applies to the above numerical values and ranges.

[0012] Also, in the following embodiments, p-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and n-channel MOSFETs are referred to as pMOS transistors and nMOS transistors, respectively. Hereinafter, embodiments of the present invention will be described in detail based on the drawings. In all the drawings for explaining the embodiments, the same members are generally given the same reference numerals, and repeated explanations thereof are omitted.

[0013] <Configuration of Semiconductor Device> FIG. 1A is a block diagram showing a configuration example of a semiconductor device according to an embodiment. FIG. 1B is a schematic diagram showing an external shape example of a semiconductor device according to an embodiment. The semiconductor device DEV shown in FIG. 1A is, for example, a SoC (System on Chip) having a semiconductor chip CHP, or a microcontroller or the like. The semiconductor device DEV includes internal units connected to each other by a bus BS. Further, the semiconductor device DEV includes a power supply circuit PWG and a clock generation circuit CKG. Each of these components is formed on a single semiconductor chip CHP.

[0014] The internal unit includes, for example, a processor PRC, a volatile memory RAM, and a non-volatile memory NVM. Further, the internal unit includes an amplifier unit AMPU, an analog-to-digital converter ADC, a digital-to-analog converter DAC, a driver unit DRVU, a PWM (Pulse Width Modulation) unit PWMU, a serial-parallel interface SPI, and various peripheral circuits PERI, etc.

[0015] The volatile memory RAM is, for example, SRAM (Static Random Access Memory), etc. The non-volatile memory NVM is, for example, flash memory, etc. The processor PRC includes a CPU (Central Processing Unit), and in addition, may also include a DSP (digital signal processor), a GPU (Graphics Processing Unit), etc. The processor PRC executes a predetermined program copied from the non-volatile memory NVM to the volatile memory RAM, for example, a control program of an external system.

[0016] As an example, the semiconductor device DEV controls an external system including sensors and actuators, etc. In this case, the amplifier unit AMPU inputs a detection signal from the sensor, that is, an analog signal, and amplifies the input analog signal. The analog-to-digital converter ADC converts the signal amplified by the amplifier unit AMPU into a digital signal. The processor PRC inputs the digital signal via the bus BS, and thus the detection signal from the sensor, and generates an operation signal according to the detection signal.

[0017] The processor PRC then controls the actuator by outputting the generated control signal to the digital-to-analog converter DAC or the PWM unit PWMU via the bus BS. In this process, the digital-to-analog converter DAC converts the digital signal input as the control signal into an analog signal. The driver unit DRVU drives the actuator based on the analog signal from the digital-to-analog converter DAC. Alternatively, the PWM unit PWMU generates a PWM signal based on the duty cycle command value input as the control signal and drives the actuator using this PWM signal.

[0018] The serial-parallel interface (SPI) performs predetermined digital communication with an external system using serial-to-parallel conversion. Various peripheral circuits (PERI) provide other functions necessary for controlling the external system. The clock generation circuit (CKG) generates a reference clock signal based on an external crystal oscillator (not shown), and generates a clock signal (CK) based on this reference clock signal using a Phase Locked Loop (PLL) circuit, etc. The clock generation circuit (CKG) supplies the generated clock signal (CK) to logic circuits, such as the processor (PRC).

[0019] The power supply circuit PWG, as will be described in detail later, receives an external power supply voltage Vcc supplied from an external source and generates various power supply voltages with predetermined voltage values, including an internal power supply voltage Vdd for the load circuit. The internal power supply voltage Vdd has a voltage value less than or equal to the external power supply voltage Vcc. The load circuit is either a logic circuit or an analog circuit. In the example shown in Figure 1A, the logic circuit mainly corresponds to the processor PRC, and may also correspond to volatile memory RAM, serial-parallel interface SPI, or PWM unit PWMU, etc. The analog circuit may correspond to, for example, an amplifier unit AMPU, analog-to-digital converter ADC, and digital-to-analog converter DAC, etc.

[0020] The semiconductor device DEV shown in Figure 1A may be configured in a package such as the one shown in Figure 1B. Figure 1B shows an example of a planar configuration of the semiconductor device DEV and an example of a cross-sectional configuration between A and A'. In Figure 1B, solder balls BL, which serve as package terminals, are formed on the semiconductor chip CHP via a wiring layer WL. The wiring layer WL connects the electrode pads of the semiconductor chip CHP to the solder balls BL. Such packages are called CSP (Chip size package), WLP (Wafer Level Package), or WLCSP (Wafer Level CSP), etc.

[0021] In particular, for semiconductor device DEVs (developers) for small devices such as smartphones and tablets, packages with fewer terminals and smaller size, such as CSP (Compact Package), are often used instead of QFP (Quad Flat Package). As a specific example, the semiconductor device DEVs shown in Figures 1A and 1B are ICs for OIS (Optical Image Stabilizer). In this case, the semiconductor device DEV is mounted in a small space around a small module that includes a camera lens.

[0022] In particular, when using packages such as CSPs, heat dissipation may be reduced compared to packages that include heat dissipation components such as bonding wires and lead frames. Furthermore, the mounting space for the package is often located in areas where heat dissipation is difficult to achieve. Therefore, it is desirable to reduce the power consumption of the semiconductor device DEV in order to suppress heat generation. The external power supply voltage Vcc is supplied, for example, from a battery. In order to reduce the power consumption of the semiconductor device DEV while extending the battery operating time, it is desirable that the lower limit of the external power supply voltage Vcc be low. In the embodiment described later, a power supply circuit PWG is shown that satisfies these requirements.

[0023] <About power supply circuits (typical configurations)> Before describing the power supply circuit according to the embodiment, a general power supply circuit will be described first. Figure 9A is a circuit diagram showing an example configuration of a general power supply circuit PWG in Figure 1A. Figure 9B is a circuit diagram showing an example configuration of an amplifier circuit AMP in Figure 9A. The power supply circuit PWGx shown in Figure 9A comprises a reference voltage generation circuit VREFGx and a voltage regulator circuit VREGx. The reference voltage generation circuit VREFGx is composed of a bandgap reference circuit. The reference voltage generation circuit VREFGx generates a reference voltage Vref, for example, 1.2V.

[0024] The voltage regulator circuit VREGx is a linear regulator or an LDO regulator. The voltage regulator circuit VREGx comprises an amplifier circuit AMP and a pMOS transistor MPo, which is the output transistor. The pMOS transistor MPo takes an external power supply voltage Vcc as its source and outputs an internal power supply voltage Vdd from its drain. The amplifier circuit AMP compares the internal power supply voltage Vdd with a reference voltage Vref and controls the gate voltage VGp of the pMOS transistor MPo using negative feedback to bring the internal power supply voltage Vdd closer to the reference voltage Vref.

[0025] This generates an internal power supply voltage Vdd, such as 1.2V. The load circuit LDC is supplied with this internal power supply voltage Vdd. As shown in Figure 1A, the load circuit LDC is a logic circuit or analog circuit formed on the semiconductor chip CHP. A relatively large load current Iload flows through the load circuit LDC. For this reason, the pMOS transistor MPo has high current drive capability, i.e., a large gate width (W).

[0026] As shown in Figure 9B, the amplifier circuit AMP is supplied with an external power supply voltage Vcc referenced to the ground power supply voltage GND, and constitutes an nMOS input type differential amplifier circuit. The amplifier circuit AMP comprises pMOS transistors MP1 and MP2 and nMOS transistors MN1-MN3. The nMOS transistors MN1 and MN2 constitute the differential input pair of the differential amplifier circuit. The nMOS transistor MN1 receives the reference voltage Vref as its negative input. The nMOS transistor MN2 receives the internal power supply voltage Vdd as its positive input.

[0027] The pMOS transistors MP1 and MP2 form a current mirror circuit and serve as the load current source for the differential amplifier circuit. The pMOS transistor MP2 is configured in a diode connection. The common drain node of pMOS transistor MP1 and nMOS transistor MN1 becomes the positive output node of the differential amplifier circuit. A gate voltage VGp is ​​generated at this positive output node for the output transistor, the pMOS transistor MPo. The nMOS transistor MN3 is connected to the common source node of nMOS transistors MN1 and MN2 and serves as the tail current source for the differential amplifier circuit.

[0028] Here, the source-drain voltage VdsN of the nMOS transistors MN1-MN3 may need to be at least 0.5V for stable operation of the differential amplifier circuit. Furthermore, the gate-source voltage VgsP of the pMOS transistor MP2, and consequently the source-drain voltage VdsP, may need to be at least 0.7V based on threshold voltages, etc. In this case, the external power supply voltage Vcc may need to be at least 1.7V (=0.5*2+0.7V).

[0029] Figure 10 is a schematic diagram illustrating an example of the problems shown in Figures 9A and 9B. Figure 10 shows an example of the value of the internal power supply voltage Vdd corresponding to the external power supply voltage Vcc. As described in Figure 9B, in order for the amplifier circuit AMP to operate normally, a lower limit voltage Vmin1 of about 1.7V must be set relative to the external power supply voltage Vcc. Therefore, as shown in Figure 10, even if the target value of the internal power supply voltage Vdd is low, for example, 1.2V, an external power supply voltage Vcc of 1.7V or higher is required. This high external power supply voltage Vcc can become a bottleneck, making it difficult to reduce the power consumption of the semiconductor device DEV (A).

[0030] Figure 11 is a timing chart illustrating an example of a different problem than that shown in Figure 10. Figure 11 shows example waveforms of the load current Iload, internal power supply voltage Vdd, gate voltage VGp, and gate current IGp in Figure 9B. As shown in Figure 11, when the load current Iload increases or decreases rapidly, the internal power supply voltage Vdd decreases or increases instantaneously. The amplifier circuit AMP rapidly suppresses fluctuations in the internal power supply voltage Vdd by rapidly decreasing or increasing the gate voltage VGp in response to this instantaneous decrease or increase in the internal power supply voltage Vdd.

[0031] Here, the amplifier circuit AMP needs to pass a large discharge current Idg or charge current Icg as the gate current IGp in order to rapidly decrease or increase the gate voltage VGp, that is, to rapidly discharge or charge a large gate capacitance. For this reason, (B) the amplifier circuit AMP may consume a certain amount of power. Furthermore, the transistors constituting the amplifier circuit AMP require a certain level of current drive capability, that is, a certain level of large gate width (W). As a result, (C) the circuit area of ​​the amplifier circuit AMP may increase.

[0032] <Regarding the power supply circuit (comparative example)> Next, we will describe a power supply circuit according to a comparative example, which was considered prior to the power supply circuit according to the embodiment. Figure 2 is a circuit diagram showing an example configuration of the power supply circuit PWG according to the comparative example in Figure 1A. The power supply circuit PWGa shown in Figure 2 comprises an nMOS transistor MNo, which is an output transistor, and a drive circuit DVa that drives the nMOS transistor MNo.

[0033] Thus, in Figure 2, an nMOS transistor MNo is used as the output transistor instead of the pMOS transistor MPo shown in Figure 9A. The nMOS transistor MNo takes the external power supply voltage Vcc as input to its drain and outputs the internal power supply voltage Vdd from its source. In other words, the nMOS transistor MNo constitutes a source follower circuit. If the current driving capability is the same, using an nMOS transistor can reduce the circuit area compared to a pMOS transistor.

[0034] The drive circuit DVa comprises a charge pump circuit CP, a charge pump control circuit CPCTa, a current source CSa and a Zener diode Dz, and a resistive voltage divider circuit RDIV. The charge pump circuit CP receives an external power supply voltage Vcc as input and generates a boosted power supply voltage Vcp that is higher than the external power supply voltage Vcc. The resistive voltage divider circuit RDIV generates a sense voltage Vdet that reflects the boosted power supply voltage Vcp by resistively dividing the boosted power supply voltage Vcp.

[0035] The current source CSa and Zener diode Dz are connected in series between the external power supply voltage Vcc and the ground power supply voltage GND. This generates a Zener voltage Vz at one end of the Zener diode Dz. The Zener voltage Vz is the reference voltage for determining the value of the boosted power supply voltage Vcp. The charge pump control circuit CPCTa compares the magnitude of the detected voltage Vdet and the Zener voltage Vz. Based on this comparison, the charge pump control circuit CPCTa uses the enable signal ENcp to control the charge pump circuit CP to either an active or inactive state.

[0036] Specifically, when "Vdet < Vz", the charge pump control circuit CPCT activates the charge pump circuit CP, and when "Vdet > Vz", it deactivates the charge pump circuit CP. Thereby, the charge pump control circuit CPCTa maintains the boosted power supply voltage Vcp at a predetermined value determined by the resistance division ratio of the resistance division circuit RDIV and the Zener voltage Vz. The nMOS transistor MNo, which is the output transistor, inputs the boosted power supply voltage Vcp generated in this way as the gate voltage VGn. Then, the nMOS transistor MNo outputs the voltage that has dropped by the gate-source voltage VgsN from the gate voltage VGn as the internal power supply voltage Vdd.

[0037] Figure 3 is a schematic diagram showing an example of the voltage values of each node according to the external power supply voltage Vcc in Figure 2. In Figure 3, an example of the voltage values of the boosted power supply voltage Vcp, the internal power supply voltage Vdd, and the Zener voltage Vz is shown. As shown in Figure 3, by using the power supply circuit PWGa shown in Figure 2, the lower limit voltage Vmin2 of the external power supply voltage Vcc can be lowered to the voltage value of the required internal power supply voltage Vdd, for example, about 1.2V. In this example, the lower limit voltage Vmin2 is 1.3V, which is lower than the lower limit voltage Vmin1 shown in Figure 10, for example, 1.7V.

[0038] In the range above this lower limit voltage Vmin2, the boosted power supply voltage Vcp is maintained at, for example, 1.8V based on the Zener voltage Vz such as 0.9V and the resistance division ratio such as 1 / 2. The nMOS transistor MNo inputs this boosted power supply voltage Vcp such as 1.8V as the gate voltage VGn and outputs the voltage that has dropped by the gate-source voltage VgsN such as 0.6V as the internal power supply voltage Vdd.

[0039] Figure 4 is a schematic diagram illustrating an example of the problems in Figure 2. Figure 4 shows an example of the temporal changes in the boosted power supply voltage Vcp and the internal power supply voltage Vdd. The charge pump circuit CP typically generates the boosted power supply voltage Vcp by alternately repeating the charging operation of the capacitor and the boosting operation of the capacitor. Therefore, the boosted power supply voltage Vcp usually contains a ripple voltage ΔVrpl. In addition, the gate-source voltage VgsN of the nMOS transistor MNo may experience voltage fluctuations ΔVgs ranging from ±50mV to ±200mV depending on, for example, manufacturing variations or temperature changes.

[0040] As a result, the internal power supply voltage Vdd may experience a voltage fluctuation ΔVdd(ΔVrpl) corresponding to (D) the ripple voltage ΔVrpl. Furthermore, the internal power supply voltage Vdd may also experience a voltage fluctuation ΔVdd(ΔVgs) corresponding to (E) the voltage fluctuation ΔVgs of the gate-source voltage VgsN. Consequently, it may be difficult to determine the internal power supply voltage Vdd with high precision using the comparative example method shown in Figure 2.

[0041] <Regarding the power supply circuit (embodiment)> Figure 5 is a circuit diagram showing an example configuration of a power supply circuit PWG according to one embodiment in Figure 1A. The power supply circuit PWGb shown in Figure 5 receives an external power supply voltage Vcc as input and generates an internal power supply voltage Vdd having a voltage value less than or equal to the external power supply voltage Vcc. The power supply circuit PWGb comprises an nMOS transistor MNo, which is an output transistor, and a drive circuit DVb that controls the nMOS transistor MNo. The nMOS transistor MNo receives the external power supply voltage Vcc as input to its drain and outputs the internal power supply voltage Vdd from its source, similar to the case in Figure 2. On the other hand, the drive circuit DVb has a different configuration than the case in Figure 2.

[0042] The drive circuit DVb comprises a charge pump circuit CP, a charge pump control circuit CPCTb, two reference voltage generation circuits VREFG1 and VREFG2, and a voltage regulator circuit VREGb. The charge pump circuit CP receives an external power supply voltage Vcc as input and generates a boosted power supply voltage Vcp that is higher than the external power supply voltage Vcc. The charge pump control circuit CPCTb controls the charge pump circuit CP to an active or inactive state, for example, using an enable signal ENcp.

[0043] The reference voltage generation circuit VREFG2 is, for example, a bandgap reference circuit BGR, which generates a second reference voltage Vref2 that is independent of temperature. On the other hand, the reference voltage generation circuit VREFG1 is supplied with a boosted power supply voltage Vcp. The reference voltage generation circuit VREFG1 has a replica transistor, i.e., an nMOS transistor MNr, which is formed using the same manufacturing process as the output transistor, an nMOS transistor MNo. In general terms, the reference voltage generation circuit VREFG1 uses the replica transistor, an nMOS transistor MNr, to generate a first reference voltage Vref1 that reflects the characteristic variations of the output transistor.

[0044] In detail, the reference voltage generation circuit VREFG1 comprises an nMOS transistor MNr, a current source CS, and an amplifier circuit (first amplifier circuit) AMP1. The current source CS is supplied with a boosted power supply voltage Vcp at one end and generates a reference current Iref to flow through the nMOS transistor MNr. The current source CS is composed of, for example, a pMOS transistor type current mirror circuit including a pMOS transistor MPc, which is the mirrored transistor. The nMOS transistor MNr is configured in diode connection. When the reference current Iref flows between the drain and source of the nMOS transistor MNr, a gate-source voltage VgsR is generated between the commonly connected drain and gate and the source.

[0045] The amplifier circuit AMP1 is supplied with a boosted power supply voltage Vcp. The amplifier circuit AMP1 applies a second reference voltage Vref2 from the reference voltage generation circuit VREFG2 to the source of the nMOS transistor MNr. In detail, the amplifier circuit AMP1 is configured, for example, by a voltage follower circuit that uses the second reference voltage Vref2 as its positive input. This voltage follower circuit applies an output voltage of the same magnitude as the second reference voltage Vref2 to the source of the nMOS transistor MNr. The amplifier circuit AMP1 is configured, for example, using a differential amplifier circuit as shown in Figure 9B. Therefore, in order to operate the amplifier circuit AMP1 stably, a boosted power supply voltage Vcp of, for example, 1.7V or higher is required.

[0046] A first reference voltage Vref1 is generated at the gate and drain of the nMOS transistor MNr. Specifically, the reference voltage generation circuit VREFG1 generates the first reference voltage Vref1 by adding the gate-source voltage VgsR generated in the nMOS transistor MNr to the second reference voltage Vref2. The second reference voltage Vref2 is set to, for example, 1.2V based on the target value of the internal power supply voltage Vdd. The gate-source voltage VgsR is, for example, about 0.6V based on the threshold voltage value of the nMOS transistor MNr and the value of the reference current Iref. In this case, the first reference voltage Vref1 is about 1.8V.

[0047] The voltage regulator circuit VREGb is supplied with a boosted power supply voltage Vcp. The voltage regulator circuit VREGb, in general terms, applies a gate voltage VGn, determined based on a first reference voltage Vref1, to the gate of the output transistor, an nMOS transistor MNo. More specifically, the voltage regulator circuit VREGb comprises a drive transistor, a pMOS transistor MPd, an amplifier circuit AMP2, and a discharge transistor, an nMOS transistor MNdg.

[0048] The pMOS transistor MPd forms a source-drain path between the boosted power supply voltage Vcp and the gate of the output transistor, the nMOS transistor MNo. The amplifier circuit AMP2 negatively feedbacks the gate voltage VGp of the pMOS transistor MPd so that the error between the gate voltage VGn of the nMOS transistor MNo (which is also the drain voltage of the pMOS transistor MPd) and the first reference voltage Vref1 approaches zero.

[0049] The discharge transistor, nMOS transistor MNdg, discharges the gate voltage VGn of nMOS transistor MNo toward the ground power supply voltage GND in response to the discharge instruction signal DG. The amplifier circuit AMP2 is constructed using a differential amplifier circuit, for example, as shown in Figure 9B. Similar to the case of amplifier circuit AMP1, a boosted power supply voltage Vcp of, for example, 1.7V or higher is required for stable operation of amplifier circuit AMP2.

[0050] With this voltage regulator circuit VREGb, a gate voltage VGn of approximately 1.8V is applied to the gate of the output transistor, an nMOS transistor MNo, based on a first reference voltage Vref1. The value of the internal power supply voltage Vdd is the value obtained by dropping the gate voltage VGn by the gate-source voltage VgsN of the nMOS transistor MNo. For example, if the gate-source voltage VgsN is approximately 0.6V, the internal power supply voltage Vdd will be approximately 1.2V.

[0051] In detail, the nMOS transistor MNo has a sufficiently high current drive capability, i.e., a sufficiently large gate width (W), depending on the required load current Iload. In this case, the overdrive voltage Vov (=VgsN-Vth) generated in response to the load current Iload can be, for example, 0.1V or less. If the threshold voltage (Vth) of the nMOS transistor MNo is around 0.5V, the gate-source voltage VgsN can be around 0.6V.

[0052] The charge pump control circuit CPCTb controls the charge pump circuit CP so that the boosted power supply voltage Vcp is above the lower limit voltage and below the upper limit voltage. The lower limit voltage of the boosted power supply voltage Vcp is the higher of the following two voltages. The first voltage is the voltage required for the stable operation of the amplifier circuits AMP1 and AMP2, as mentioned above, for example, 1.7V. The second voltage is the required gate voltage VGn, which is the voltage obtained by adding the gate-source voltage VgsN, for example, 0.6V, to the target internal power supply voltage Vdd, for example, 1.2V. In other words, in order for the pMOS transistor MPd to operate normally, the relationship "Vcp > VGn" must be satisfied.

[0053] Furthermore, the gate-source voltage VgsN can be appropriately changed by setting the threshold voltage (Vth) and size of the nMOS transistor MNo. Accordingly, the lower limit voltage of the boost supply voltage Vcp may also change. On the other hand, the upper limit voltage of the boost supply voltage Vcp is determined by considering, for example, power consumption and transistor breakdown voltage. When the boost supply voltage Vcp reaches the upper limit voltage, the charge pump control circuit CPCTb deactivates the charge pump circuit CP using the enable signal ENcp.

[0054] Figure 6A is a schematic diagram showing an example of the voltage relationships at each node in Figure 5. In Figure 6A, the second reference voltage Vref2 is set to, for example, 1.2V. The first reference voltage Vref1 is set to, for example, 1.8V by adding the gate-source voltage VgsR of the replica transistor (MNr) to the second reference voltage Vref2. Accordingly, the gate voltage VGn to the output transistor (MNo) is also 1.8V. The internal power supply voltage Vdd becomes 1.2V due to a voltage drop of VgsN from the gate voltage VGn to the gate voltage VgsN of the output transistor (MNo).

[0055] In this example, the boosted power supply voltage Vcp is 2.4V. As shown in Figure 6A, a predetermined ripple voltage ΔVrpl is superimposed on the boosted power supply voltage Vcp, with 2.4V as the reference. However, even when the boosted power supply voltage Vcp contains the ripple voltage ΔVrpl, the reference voltage generation circuit VREFG1 can generate a stable first reference voltage Vref1 through the rectification action of the current source CS and the rectification action of the amplifier circuit AMP1 that constitutes the voltage follower circuit.

[0056] Similarly, the voltage regulator circuit VREGb can generate a stable gate voltage VGn through the rectification action of the amplifier circuit AMP2, which has a negative feedback configuration, even when the boosted power supply voltage Vcp contains a ripple voltage ΔVrpl. As a result, the output transistor (MNo) can generate a stable internal power supply voltage Vdd. That is, the voltage fluctuation ΔVdd(ΔVrpl) of the internal power supply voltage Vdd corresponding to the ripple voltage ΔVrpl, as described in Figure 4, can be suppressed.

[0057] Furthermore, the replica transistor, the nMOS transistor MNr, has a gate width (W) of 1 / K of the output transistor, the nMOS transistor MNo. Accordingly, the reference current Iref from the current source CS is also set to a value of 1 / K of the expected load current Iload for the load circuit LDC. The value of K is 10 or greater, and may be on the order of 100 or 1000. The expected load current Iload is, for example, the average current or rated current that is anticipated in the load circuit LDC.

[0058] With these parameter settings, if the gate-source voltage VgsN in the nMOS transistor MNo varies due to manufacturing variations or temperature changes, the gate-source voltage VgsR in the nMOS transistor MNr will also vary similarly. As a result, the state "VgsR = VgsN" can be maintained for various variation elements, allowing the value of the internal power supply voltage Vdd to be determined by the value of the second reference voltage Vref2. This suppresses the voltage fluctuation ΔVdd(ΔVgs) of the internal power supply voltage Vdd due to manufacturing variations or temperature changes in the nMOS transistor MNo, as described in Figure 4. Furthermore, the area overhead associated with the nMOS transistor MNr and the current source CS can also be reduced.

[0059] Figure 6B is a schematic diagram showing an example of the voltage values ​​of each node in Figure 5 according to the external power supply voltage Vcc. As shown in Figure 6B, by using the power supply circuit PWGb shown in Figure 5, the external power supply voltage Vcc required to generate the internal power supply voltage Vdd of 1.2V can be lowered to a lower limit voltage Vmin2 of approximately 1.3V, similar to the case in Figure 3. In other words, the external power supply voltage Vcc can be lowered from a lower limit voltage Vmin1 of approximately 1.7V shown in Figure 10 to a lower limit voltage Vmin2 of approximately 1.3V. Depending on the gate width (W) of the output transistor (MNo), it is also possible to set the lower limit voltage Vmin2 to a value closer to 1.2V.

[0060] Thus, by lowering the external power supply voltage Vcc, the power consumption of the semiconductor device DEV (A) can be reduced, unlike in the case of Figure 10. Furthermore, if the external power supply voltage Vcc is supplied from a battery, the battery operating time can be extended. In Figure 6B, the boosted power supply voltage Vcp increases in response to the increase in the external power supply voltage Vcc at a boost ratio corresponding to the configuration of the charge pump circuit CP. The gate voltage VGn is set to 1.8V, etc., when the boosted power supply voltage Vcp exceeds the lower limit voltage of the boosted power supply voltage Vcp mentioned above.

[0061] Figure 7 is a timing chart showing an example of the voltage or current generated at each node in Figure 5. Figure 7 shows example waveforms of the load current Iload, internal power supply voltage Vdd, gate voltages VGn, VGp, and gate currents IGn, IGp in Figure 5. As shown in Figure 7, when the load current Iload increases, the internal power supply voltage Vdd may decrease slightly depending on the current driving capability of the nMOS transistor MNo. On the other hand, the voltage regulator circuit VREGb generates the gate voltage VGn in an open loop. Therefore, unlike in Figure 11, the gate voltage VGn is constant. Consequently, the gate voltage VGp is ​​also constant.

[0062] When the gate voltages VGn and VGp are constant, the gate currents IGn and IGp are both approximately zero. That is, unlike in the case of Figure 11, the gate current IGp is ​​approximately zero, so high current driving capability is not required for the amplifier circuit AMP2. Furthermore, high-speed response is not required for the amplifier circuit AMP2. As a result, (B) the power consumption of the amplifier circuit AMP2 can be reduced. In addition, the amplifier circuit AMP2 can operate stably with a boosted power supply voltage Vcp with low current supply capability, without using an external power supply voltage Vcc. Furthermore, (C) the circuit area of ​​the amplifier circuit AMP2 can be reduced. Note that these effects are also true for the amplifier circuit AMP1.

[0063] <Modified example of charge pump circuit> Figure 8 is a circuit diagram showing a modified configuration of the charge pump circuit CP shown in Figure 5. Figure 8 shows the configuration around the charge pump circuit CP in detail. In Figure 8, in addition to the charge pump circuit CP and the charge pump control circuit CPCTc, a switch SW1 is provided. The charge pump control circuit CPCTc compares the external power supply voltage Vcc with a predetermined lower limit voltage VcpMIN of the boosted power supply voltage Vcp. Then, if the external power supply voltage Vcc exceeds the lower limit voltage VcpMIN, the charge pump control circuit CPCTc deactivates the charge pump circuit CP using the enable signal ENcp.

[0064] Switch SW1 connects node Nvcc of the external power supply voltage Vcc to node Nvcp of the boosted power supply voltage Vcp when the external power supply voltage Vcc exceeds the lower limit voltage VcpMIN. In this example, the charge pump control circuit CPCTc controls switch SW1 to ON when it deactivates the charge pump circuit CP. As a result, the boosted power supply voltage Vcp is replaced by the external power supply voltage Vcc. If the external power supply voltage Vcc does not exceed the lower limit voltage VcpMIN, the charge pump circuit CP is controlled to be active, and switch SW1 is controlled to be OFF.

[0065] By using this configuration, the charge pump circuit CP can be kept inactive when the external power supply voltage Vcc is sufficiently large, thereby further reducing the power consumption of the semiconductor device DEV. The switch SW1 can be composed of, for example, a pMOS transistor. The charge pump control circuit CPCTc can be composed of, for example, a comparator that compares the value obtained by dividing the external power supply voltage Vcc with a lower limit voltage VcpMIN corresponding to the resistance division ratio.

[0066] <Other variations> In Figure 5, a pMOS transistor MPd is used as the driving transistor in the voltage regulator circuit VREGb. However, it is also possible to use an nMOS transistor instead of a pMOS transistor. In this case, the amplifier circuit AMP2 is composed of a pMOS input type differential amplifier circuit instead of the nMOS input type differential amplifier circuit shown in Figure 9B, for example.

[0067] Furthermore, the power supply circuit PWGb shown in Figure 5 is configured to make the second reference voltage Vref2 equal to the internal power supply voltage Vdd. However, it is also possible to create a constant voltage difference between the second reference voltage Vref2 and the internal power supply voltage Vdd by, for example, feeding back the value obtained by resistively dividing the internal power supply voltage Vdd to the amplifier circuit AMP2.

[0068] <Main effects of the embodiment> As described above, the semiconductor device according to one embodiment generates an internal power supply voltage from an external power supply voltage using an n-channel output transistor that constitutes a source follower circuit. This reduces the external power supply voltage to the same level as the internal power supply voltage, thereby reducing the power consumption of the semiconductor device. In addition, a reference voltage generation circuit and a voltage regulator circuit are provided to generate the gate voltage of the output transistor. Since these circuits generate the gate voltage in an open loop, current drive capability is not required. As a result, the power consumption of the reference voltage generation circuit and the voltage regulator circuit can also be reduced.

[0069] The present invention has been described in detail above based on embodiments, but the present invention is not limited to the embodiments described above and can be modified in various ways without departing from its essence. For example, the embodiments described above are described in detail in order to explain the present invention in an easy-to-understand manner and are not necessarily limited to those having all the described configurations. Furthermore, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add a configuration from another embodiment to the configuration of one embodiment. In addition, it is possible to add, delete, or replace a part of the configuration of each embodiment with a configuration from another embodiment. [Explanation of symbols]

[0070] AMP, AMP1, AMP2 Amplifier Circuit CP Charge Pump Circuit CPCTb, CPCTc Charge Pump Control Circuit DEV semiconductor equipment LDC load circuit MNo nMOS transistor (output transistor) MNr nMOS transistor (replica transistor) MPd pMOS transistor (driver transistor) PWG power circuit SW1 Switch VREFG1 Reference Voltage Generation Circuit VREGb Voltage Regulator Circuit Vcc External power supply voltage Vcp Boost Power Supply Voltage Vdd Internal power supply voltage VgsN, VgsR Gate-source voltage Vref1 First reference voltage Vref2 Second reference voltage

Claims

1. A power supply circuit that takes an external power supply voltage as input and generates an internal power supply voltage having a voltage value less than or equal to the external power supply voltage, The load circuit to which the aforementioned internal power supply voltage is supplied, A semiconductor device having, The aforementioned power supply circuit is An n-channel output transistor that inputs the external power supply voltage to its drain and outputs the internal power supply voltage from its source, A charge pump circuit that receives the aforementioned external power supply voltage and generates a boosted power supply voltage higher than the aforementioned external power supply voltage, A reference voltage generation circuit is provided to which the boosted power supply voltage is supplied and which has a replica transistor formed by the same manufacturing process as the output transistor, and which uses the replica transistor to generate a first reference voltage that reflects the characteristic variations of the output transistor, A voltage regulator circuit is provided which the boosted power supply voltage is supplied and which applies a gate voltage determined based on the first reference voltage to the gate of the output transistor, Equipped with, Semiconductor equipment.

2. In the semiconductor device described in claim 1, The replica transistor has a gate width of 1 / K of the output transistor, The value of K is 10 or greater. Semiconductor equipment.

3. In the semiconductor device described in claim 2, The aforementioned replica transistor is configured in a diode connection. The reference voltage generation circuit further includes a current source that generates a reference current to flow through the replica transistor, and generates the first reference voltage by adding the gate-source voltage generated in the replica transistor to a second reference voltage that is not temperature-dependent. Semiconductor equipment.

4. In the semiconductor device described in claim 3, The reference current is set to a value of 1 / K of the load current expected for the load circuit. Semiconductor equipment.

5. In the semiconductor device described in claim 3, The reference voltage generation circuit has a first amplifier circuit to which the boosted power supply voltage is supplied, The first amplifier circuit receives the second reference voltage as input and applies a voltage of the same magnitude as the second reference voltage to the source of the replica transistor. Semiconductor equipment.

6. In the semiconductor device described in claim 1, The aforementioned voltage regulator circuit is A drive transistor that forms a source-drain path between the boosted power supply voltage and the gate of the output transistor, A second amplifier circuit that negatively feedbacks the gate voltage of the drive transistor so as to bring the error between the gate voltage of the output transistor and the first reference voltage closer to zero, Equipped with, Semiconductor equipment.

7. In the semiconductor device according to claim 1, further, A charge pump control circuit that deactivates the charge pump circuit when the external power supply voltage exceeds a predetermined lower limit voltage of the boosted power supply voltage, A switch that connects the node of the external power supply voltage to the node of the boost power supply voltage when the external power supply voltage exceeds the lower limit voltage of the boost power supply voltage, Equipped with, Semiconductor equipment.

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