Semiconductor device manufacturing method

Abstract

The present invention provides a method for manufacturing semiconductor devices that improves the integration density and reliability of semiconductor devices. [Solution] The method comprises the steps of: removing a portion of the interlayer insulating layer and the source / drain region to form a contact hole; forming a metal-semiconductor compound layer on the lower end of the contact hole; forming a liner conductive layer on the metal-semiconductor compound layer so as to cover the side surface of the contact hole; selectively oxidizing the liner conductive layer formed on the metal-semiconductor compound layer; selectively removing the oxidized liner conductive layer; forming a preliminary contact conductive layer on the liner conductive layer; forming a sacrificial metal layer on the preliminary contact conductive layer; removing a portion of the sacrificial metal layer and the preliminary contact conductive layer by a planarization process; and forming a contact conductive layer by heat treatment of the preliminary contact conductive layer using hydrogen plasma.

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for manufacturing semiconductor devices that provides improved integration density and reliability, and reduces process difficulty and cost. [Background technology]

[0002] As the demand for higher performance, faster speeds, and / or more functionality in semiconductor devices increases, the integration density of semiconductor devices is also increasing.

[0003] In manufacturing semiconductor devices with fine patterns to meet the trend of increasing integration in semiconductor devices, realizing patterns with minute widths or minute spacing distances is required and has become a daily challenge. Furthermore, in order to overcome the limitations in operating characteristics due to the reduction in size of planar MOSFETs (metal oxide semiconductor FETs), efforts are underway to develop semiconductor devices, including FinFETs, that have a three-dimensional channel structure. [Overview of the project] [Problems that the invention aims to solve]

[0004] The present invention has been made in view of the problems in the above-mentioned conventional semiconductor device manufacturing method, and the object of the present invention is to provide a semiconductor device with improved integration density and reliability, and a semiconductor device manufacturing method with reduced process difficulty and process cost. [Means for solving the problem]

[0005] To achieve the above objective, the method for manufacturing a semiconductor device according to the present invention comprises the steps of: alternately stacking a plurality of sacrificial layers and a plurality of channel layers on a substrate; partially removing the plurality of channel layers, the plurality of sacrificial layers, and the substrate to form a plurality of active structures extending in a first horizontal direction on the upper surface of the substrate; forming a sacrificial gate structure and a spacer layer on the plurality of active structures, extending in a second direction intersecting the first direction; forming source / drain regions on both sides of the sacrificial gate structure; forming an interlayer insulating layer on the source / drain region and removing the sacrificial gate structure and the plurality of sacrificial layers; forming a gate structure extending in the second direction in the region from which the sacrificial gate structure and the plurality of sacrificial layers were removed; and the interlayer insulating layer and the The method is characterized by comprising the steps of: removing a portion of each of the source / drain regions to form a contact hole; forming a metal-semiconductor compound layer on the lower end of the contact hole; forming a liner conductive layer on the metal-semiconductor compound layer so as to cover the side surface of the contact hole; selectively oxidizing the liner conductive layer formed on the metal-semiconductor compound layer; selectively removing the oxidized liner conductive layer; forming a preliminary contact conductive layer on the liner conductive layer; forming a sacrificial metal layer on the preliminary contact conductive layer; removing a portion of the sacrificial metal layer and the preliminary contact conductive layer by a planarization process; and forming a contact conductive layer by heat treatment of the preliminary contact conductive layer using hydrogen plasma.

[0006] Furthermore, a method for manufacturing a semiconductor element according to the present invention, which is made to achieve the above objective, comprises the steps of: forming a semiconductor region and an interlayer insulating layer on a substrate; forming a contact hole by removing a part of the interlayer insulating layer and the semiconductor region; forming a metal-semiconductor compound layer on the lower end of the contact hole; forming a liner conductive layer on the metal-semiconductor compound layer so as to cover the side surface of the contact hole; selectively oxidizing a part of the liner conductive layer and removing the oxidized part of the liner conductive layer; forming a preliminary contact conductive layer on the liner conductive layer; and forming a contact conductive layer by heat-treating the preliminary contact conductive layer using hydrogen plasma, wherein the crystal grain size of the contact conductive layer is larger than that of the preliminary contact conductive layer.

[0007] Furthermore, a method for manufacturing a semiconductor device according to the present invention, made to achieve the above objective, comprises the steps of: alternately stacking a plurality of sacrificial layers and a plurality of channel layers on a substrate; forming a sacrificial gate structure extending in one direction on the plurality of channel layers and the plurality of sacrificial layers; forming a source / drain region on at least one side of the sacrificial gate structure and forming an interlayer insulating layer on the source / drain region; removing the sacrificial gate structure and the plurality of sacrificial layers to form a gate structure; removing a part of the interlayer insulating layer and the source / drain region to form a contact hole; and forming a metal-semiconductor compound layer on the lower end of the contact hole. The method comprises the steps of: forming a liner conductive layer on the metal-semiconductor compound layer so as to cover the side surface of the contact hole; selectively removing a portion of the liner conductive layer; forming a preliminary contact conductive layer on the liner conductive layer; forming a sacrificial metal layer on the preliminary contact conductive layer; removing a portion of the sacrificial metal layer and the preliminary contact conductive layer by a planarization step; and forming a contact conductive layer by heat treatment of the preliminary contact conductive layer using hydrogen plasma, wherein the liner conductive layer has a first thickness on the side surface of the contact conductive layer and a second thickness greater than the first thickness on the bottom surface of the contact conductive layer. [Effects of the Invention]

[0008] According to the semiconductor device manufacturing method of the present invention, by optimizing, for example, the structure of the liner conductive layer and the particle size of the contact conductive layer of the contact plug connected to the source / drain region, a semiconductor device with improved electrical characteristics can be provided, and a semiconductor device manufacturing method with reduced process difficulty and cost can be provided. [Brief explanation of the drawing]

[0009] [Figure 1] This is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 2]This is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 3] This is a partially enlarged cross-sectional view showing area A in Figure 2. [Figure 4] This is a partially enlarged cross-sectional view showing area A in Figure 2, according to another embodiment of the present invention. [Figure 5] This is a partially enlarged cross-sectional view showing area A in Figure 2, according to another embodiment of the present invention. [Figure 6] This is a cross-sectional view showing a schematic configuration of a semiconductor device according to another embodiment of the present invention. [Figure 7a] This is a cross-sectional view illustrating a process for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7b] This is a cross-sectional view illustrating a process for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7c] This is a cross-sectional view illustrating a process for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7d] This is a cross-sectional view illustrating a process for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7e] This is a cross-sectional view illustrating a process for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7f] This is a cross-sectional view illustrating a process for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7g] This is a cross-sectional view illustrating a process for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7h] This is a cross-sectional view illustrating a process for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7i] This is a cross-sectional view illustrating a process for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7j] This is a cross-sectional view illustrating a process for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7k] This is a cross-sectional view illustrating a process for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7l]It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7m] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7n] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] It is a schematic flowchart for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0010] Next, a specific example of an embodiment for carrying out the method of manufacturing a semiconductor device according to the present invention will be described while referring to the drawings.

[0011] Unless otherwise specified, in this specification, terms such as "upper", "upper surface", "lower", "lower surface", "side surface", etc. are based on the drawings and may actually change according to the direction in which the components are arranged. Also, ordinal numbers such as "first", "second", "third", etc. can be used as labels for specific elements, steps, directions, etc. to distinguish various elements, steps, directions, etc. from each other. Terms not described using "first", "second", etc. in the specification can still be referred to as "first" or "second" in the claims. Also, a term referred to by a specific ordinal number (e.g., "the first" in a specific claim) can be described by another ordinal number (e.g., "the second" in the specification or another claim) elsewhere.

[0012] FIG. 1 is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. FIG. 2 shows a cross-section of the semiconductor device in FIG. 1 cut along the lines I-I' and II-II'. For convenience of explanation, only some of the components of the semiconductor device are shown in FIG. 1. Figure 3 is a partially enlarged view showing a semiconductor device according to an embodiment of the present invention. Figure 3 shows a magnified view of area "A" in Figure 2.

[0013] Referring to Figures 1 to 3, the semiconductor device 100 includes a substrate 101 including an active region 105, a channel structure 140 including first to fourth channel layers (141, 142, 143, 144) arranged perpendicularly apart on the active region 105, gate structures 160 extending across the active region 105 and each including a gate electrode 165, a source / drain region 150 in contact with the channel structure 140, and a contact plug 180 connected to the source / drain region 150. The semiconductor device 100 further includes an element isolation layer 110, a gate capping layer 170, an insulating layer liner layer 192, and an interlayer insulating layer 199.

[0014] The semiconductor device 100 has an active region 105 with a fin structure, and a gate electrode 165 is positioned between the active region 105 and the channel structure 140, between the first to fourth channel layers (141, 142, 143, 144) of the channel structure 140, and on the channel structure 140. As a result, the semiconductor device 100 includes a transistor with an MBCFET (registered trademark) (Multi Bridge Channel FET) structure, which is a gate-all-around type field-effect transistor.

[0015] The substrate 101 has an upper surface that extends in the x and y directions. The substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, Group IV semiconductors include silicon, germanium, or silicon-germanium. The substrate 101 may be provided as a bulk wafer, an epitaxial layer, an SOI (Silicon On Insulator) layer, or an SeOI (Semiconductor On Insulator) layer, etc.

[0016] The substrate 101 includes an active region 105 located at the top. The active region 105 is defined within the substrate 101 by the element isolation layer 110 and is positioned to extend in a first direction, for example, in the x-direction. However, depending on the explanation method, it is also possible to describe the active region 105 as having a configuration separate from the substrate 101. The active region 105 partially protrudes onto the element isolation layer 110, and the upper surface of the active region 105 is located at a higher level than the upper surface of the element isolation layer 110. The active region 105 consists of a part of the substrate 101 and includes an epitaxial layer grown from the substrate 101. However, on both sides of the gate structure 160, the active region 105 is partially recessed to form a recessed region, and the source / drain region 150 is located in the recessed region.

[0017] In one embodiment, the active region 105 may or may not include a well region containing impurities. For example, in the case of a p-type transistor (pFET), the well region contains n-type impurities such as phosphorus (P), arsenic (As), or antimony (Sb), while in the case of an n-type transistor (nFET), the well region contains p-type impurities such as boron (B), gallium (Ga), or indium (In). The well region is located, for example, at a predetermined depth from the upper surface of the active region 105.

[0018] The element isolation layer 110 defines an active region 105 within the substrate 101. The element isolation layer 110 is formed, for example, by a shallow trench isolation (STI) process. The element isolation layer 110 can also expose the upper surface of the active region 105 and partially expose the upper part. In one embodiment, the element isolation layer 110 has an upper surface that is bent such that it has a higher level adjacent to the active region 105. The element isolation layer 110 is made of an insulating material. The element isolation layer 110 may be, for example, an oxide, a nitride, or a combination thereof.

[0019] The gate structure 160 is positioned on the active region 105 and the channel structure 140 so as to extend in a second direction, for example, the y direction, intersecting the active region 105 and the channel structure 140. The active region 105 and / or channel structure 140 that intersect with the gate electrode 165 of the gate structure 160 form a functional channel region of the transistor. Each of the gate structures 160 includes a gate electrode 165, a gate dielectric layer 162 between the gate electrode 165 and the first to fourth channel layers (141, 142, 143, 144), and a gate spacer layer 164 on the side surface of the gate electrode 165.

[0020] The gate dielectric layer 162 is positioned between the active region 105 and the gate electrode 165, and between the channel structure 140 and the gate electrode 165, and is positioned to cover at least a portion of the surface of the gate electrode 165. For example, the gate dielectric layer 162 is arranged to surround all surfaces of the gate electrode 165 except for the top surface. The gate dielectric layer 162 extends between the gate electrode 165 and the gate spacer layer 164, but is not limited to this. The gate dielectric layer 162 may contain oxides, nitrides, or high-dielectric constant (high-k) materials.

[0021] High dielectric constant materials refer to dielectric materials that have a higher dielectric constant than silicon oxide (SiO2). High dielectric constant materials include, for example, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), and zirconium silicon oxide (ZrSi x O y ), hafnium oxide (HfO2), hafnium silicon oxide (HfSi x O y)、lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y ), and any one of praseodymium oxide (Pr2O3). According to an embodiment, the gate dielectric layer 162 may be composed of a multilayer film.

[0022] The gate electrode 165 fills the space between the first to fourth channel layers (141, 142, 143, 144) on the active region 105 and is extended and disposed on the channel structure 140. The gate electrode 165 is separated from the first to fourth channel layers (141, 142, 143, 144) by the gate dielectric layer 162. The gate electrode 165 contains a conductive material, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material such as doped polysilicon. According to an embodiment, the gate electrode 165 may be composed of two or more multilayers.

[0023] The gate spacer layer 164 is disposed on both side surfaces of the gate electrode 165 on the channel structure 140. The gate spacer layer 164 insulates the source / drain region 150 and the gate electrode 165. According to an embodiment, the gate spacer layer 164 may be composed of a multilayer structure. The gate spacer layer 164 may be composed of at least one of an oxide, a nitride, and an oxynitride, for example, a low dielectric constant film.

[0024] The channel structure 140 is disposed on the active region 105 in a region where the active region 105 intersects the gate structure 160. Each of the channel structures 140 includes first to fourth channel layers (141, 142, 143, 144), which are multiple channel layers spaced apart from each other in the z direction. The first to fourth channel layers (141, 142, 143, 144) are arranged sequentially from the top, with the first channel layer 141 being the uppermost channel layer. The channel structure 140 is connected to the source / drain region 150. The channel structure 140 has the same or similar width as the gate structure 160 in the x-direction, and the same or smaller width as the active region 105 in the y-direction. In a cross-section along the y-direction, the lower channel layer among the first to fourth channel layers (141, 142, 143, 144) has the same width as or greater than the upper channel layer. The number and shape of the channel layers forming a single channel structure 140 can be varied in various ways according to the embodiment. For example, a single channel structure 140 may include three channel layers, two channel layers, or five or more channel layers.

[0025] The channel structure 140 is made of a semiconductor material and may include, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). The channel structure 140 is made of the same material as the active region 105, for example. In one embodiment, the channel structure 140 also includes an impurity region located adjacent to the source / drain region 150.

[0026] The source / drain region 150 is located in recessed regions on both sides of the gate structure 160, where the upper part of the active region 105 is partially recessed. The recess region extends along the side of the channel structure 140 and the side of the gate dielectric layer 162. The source / drain region 150 is positioned to cover the sides of the first to fourth channel layers (141, 142, 143, 144) of the channel structure 140 along the x-direction. The upper surface of the source / drain region 150 is at the same level as, or higher than, the lower surface of the gate electrode 165 on the channel structure 140, and this level can be varied in various embodiments. The sides of the source / drain region 150 have bends due to the first to fourth channel layers (141, 142, 143, 144) and the gate structure 160. However, the specific shape of the side surface of the source / drain region 150 can be varied in various embodiments.

[0027] The source / drain region 150 comprises a semiconductor material, for example, at least one of silicon (Si) and germanium (Ge), and further comprises a dopant. For example, if the semiconductor device 100 is a pFET, the dopant may be at least one of boron (B), gallium (Ga), and indium (In). The source / drain region 150 consists of an epitaxial layer.

[0028] The gate capping layers 170 are each placed on top of the gate structures 160. The insulating liner layer 192 covers the sides of the gate capping layer 170 and the outer surface of the gate spacer layer 164, and is folded and extended onto the upper surface of the source / drain region 150. The gate capping layer 170, the insulating liner layer 192, and the interlayer insulating layer 199 may each contain at least one of oxides, nitrides, and oxynitrides. The interlayer insulating layer 199 is formed on the insulating liner layer 192 to fill the space between the sacrificial gate structures 200. The interlayer insulating layer 199 may contain at least one of oxides, nitrides, and oxynitrides, for example, a low dielectric constant material. In one embodiment, the insulating liner layer 192 may be omitted. In one embodiment, the interlayer insulating layer 199 may include a plurality of insulating layers.

[0029] The contact plug 180 penetrates the insulating liner layer 192 and connects to the source / drain region 150, applying an electrical signal to the source / drain region 150. The contact plug 180 recesses into the source / drain region 150 and extends into the source / drain region 150. The lower end of the contact plug 180 is located, for example, at the level between the lower surface of the first channel layer 141 and the upper surface of the third channel layer 143. The contact plug 180 includes a metal-semiconductor compound layer 182 located at the bottom, a liner conductive layer 184 placed on the metal-semiconductor compound layer 182, and a contact conductive layer 186 filling the inside of the contact plug 180.

[0030] The metal-semiconductor compound layer 182 is in contact with the source / drain region 150. The metal-semiconductor compound layer 182 is positioned along the recessed surface where the source / drain region 150 is located. The lower end of the metal-semiconductor compound layer 182 corresponds to the lower end of the contact plug 180. The metal-semiconductor compound layer 182 has a non-uniform thickness along the surface of the source / drain region 150. Here, "thickness" refers to the dimension of the recessed surface of the source / drain region 150 in a direction locally perpendicular to it. The metal-semiconductor compound layer 182 has a shape in which its thickness increases towards the lower end of the contact plug 180, for example. The metal-semiconductor compound layer 182 has a thickness in the range of approximately 1 nm to 4 nm. The metal-semiconductor compound layer 182 contains a metal element and a semiconductor element, for example, TiSi. Alternatively, the metal-semiconductor compound layer 182 may also contain germanium (Ge) in addition to silicon (Si) in the above-mentioned material, or instead of silicon (Si).

[0031] The contact conductive layer 186 is positioned on the liner conductive layer 184, filling the recessed area of ​​the source / drain region 150, and extends over the contact plug 180. The contact conductive layer 186 has a shape in which its width decreases non-linearly as it approaches the source / drain region 150. The contact conductive layer 186 contains a metallic substance such as tungsten (W) or molybdenum (Mo).

[0032] The liner conductive layer 184 is positioned between the metal-semiconductor compound layer 182 and the contact conductive layer 186. The liner conductive layer 184 is interposed between the metal-semiconductor compound layer 182 and the contact conductive layer 186 at its lower end, and surrounds the sides of the contact conductive layer 186 at its upper end. The liner conductive layer 184 contains, for example, no nitrogen (N) and only metallic elements, for example, no titanium (Ti), no tantalum (Ta), and contains at least one of tungsten (W) or molybdenum (Mo).

[0033] The resistivity of the contact conductive layer 186 is in the range of approximately 9 μΩcm to approximately 18 μΩcm, and the resistivity of the liner conductive layer 184 is in the range of approximately 10 μΩcm to approximately 20 μΩcm. As a result, the ratio of the resistivity of the liner conductive layer 184 to the resistivity of the contact conductive layer is in the range of approximately 0.45 to approximately 1.8.

[0034] Referring to Figure 3, the lateral region of the liner conductive layer 184, which extends along the side of the contact conductive layer 186, increases in thickness toward the source / drain region. The liner conductive layer 184 has a first thickness T1 and a third thickness T3 on the side surface of the contact conductive layer 186, and a second thickness T2 which is greater than the first thickness T1 and the third thickness T3 on the bottom surface of the contact conductive layer 186. The first thickness T1 is smaller than the third thickness T3, and the third thickness T3 is smaller than the second thickness T2. The first thickness T1 is approximately 1 nm to 2 nm, the second thickness T2 is approximately 2 nm to 7 nm, and the third thickness T3 is approximately 2 nm to 3 nm. The ratio of the second thickness T2 to the first thickness T1 is in the range of approximately 1 to approximately 7. The second thickness T2 is greater than the thickness of the metal-semiconductor compound layer.

[0035] According to one embodiment of the contact plug 180, by including a liner conductive layer 184 made of a material with relatively lower resistance than the above-mentioned materials, and without a diffusion prevention layer such as TiN, Ta, TaN, WC, TiSiN, etc., the electrical characteristics of the contact plug 180 connected to the source / drain region 150 can be improved. For example, the contact resistance of the contact plug 180 can be reduced. Further wiring structures, such as contact plugs, can be placed on the gate electrode 165, and further wiring structures, such as wiring lines connected to the contact plug 180, can be placed on the contact plug 180.

[0036] Figure 4 is a cross-sectional view showing the schematic configuration of a semiconductor device according to an embodiment of the present invention, and Figure 4 shows the region corresponding to Figure 3. In the following descriptions of embodiments, explanations that overlap with the above explanation will be omitted with reference to Figures 1 to 3. Referring to Figure 4, the structure of the liner conductive layer 184 of the contact plug 180a in the semiconductor element 100a is different from that of the embodiment shown in Figure 3.

[0037] Referring to Figure 4, the contact conductive layer 186 includes a lower region LC and an upper region UC on the lower region LC, where the side surface of the liner conductive layer 184 is formed, extending along the side surface of the contact conductive layer 186. In the upper region UC of the contact conductive layer 186, the liner conductive layer 184 is not present, while in the lower region LC of the contact conductive layer 186, the liner conductive layer 184 is formed.

[0038] The contact conductive layer 186 includes a bent portion BR whose width changes discontinuously between the lower region LC and the upper region UC. The bent portion BR is located at a height of approximately 1 / 3 or more and 1 / 2 or less of the overall height of the contact plug 180a, but is not limited to this. The position of the folded portion may change depending on the degree of oxidation of the liner conductive layer 184 (see Figures 7i and 7j). If the position of the bent portion BR is less than or equal to approximately 1 / 3 of the total height of the contact plug 180a, damage to the lower contact may occur during the selective removal of the oxidized liner conductive layer 184.

[0039] The lateral region of the liner conductive layer 184, which extends along the side surface of the contact conductive layer 186, increases in thickness toward the source / drain region. The liner conductive layer 184 has a first thickness T1 and a third thickness T3 on the side surface of the contact conductive layer 186, and a second thickness T2 which is greater than the first thickness T1 and the third thickness T3 on the bottom surface of the contact conductive layer 186. The first thickness T1 is smaller than the third thickness T3, and the third thickness T3 is smaller than the second thickness T2. The first thickness T1 is approximately 1 nm to 2 nm, the second thickness T2 is approximately 2 nm to 7 nm, and the third thickness T3 is approximately 2 nm to 3 nm. The ratio of the second thickness T2 to the first thickness T2 is in the range of approximately 1 to approximately 7. The second thickness T2 is greater than the thickness of the metal-semiconductor compound layer. Such semiconductor element 100a may be further arranged in a region of the semiconductor element of another embodiment.

[0040] Figure 5 is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention, and Figure 5 shows the region corresponding to Figure 3. Referring to Figure 5, in the semiconductor element 100b, the structure of the liner conductive layer 184 of the contact plug 180b is different from that of the embodiments in Figure 3 and Figure 4. Referring to Figure 5, the contact conductive layer 186 includes a lower region LC and an upper region UC on the lower region LC, where the side surface of the liner conductive layer 184 is formed, extending along the side surface of the contact conductive layer 186. The contact conductive layer 186 includes a bent portion BR whose width changes discontinuously between the lower region LC and the upper region UC.

[0041] The bent portion BR is located at a height of approximately 1 / 3 to 1 / 2 of the overall height of the contact plug 180b, but is not limited to this. The position of the folded portion may change depending on the degree of oxidation of the liner conductive layer 184 (see Figures 7i and 7j). If the position of the bent portion BR is less than or equal to approximately 1 / 3 of the total height of the contact plug 180b, damage to the lower contact may occur during the selective removal of the oxidized liner conductive layer 184.

[0042] Referring to Figure 5, in the semiconductor element 100b, the contact plug 180b further includes an upper liner conductive layer 185 formed on the side surface of the contact conductive layer 186 of the upper region UC. The position of the upper liner conductive layer 185 may change depending on the degree of oxidation of the liner conductive layer 184 (see Figures 7i and 7j). The upper liner conductive layer 185 is formed unevenly on the sides of the contact conductive layer 186 of the upper region UC, separated perpendicularly from each other, and there is no limit to the number of layers formed. Such semiconductor element 100b may be further arranged in a region of the semiconductor element of another embodiment. The same principles apply to the first to third thicknesses as described in Figure 4.

[0043] Figure 6 is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention, and Figure 6 shows the region corresponding to Figure 2. Referring to Figure 6, the semiconductor element 100c does not include a channel structure 140, unlike the embodiments in Figures 1 to 3, and as a result, the arrangement of the gate structure 160 is different from that of the above embodiments. The semiconductor device 100c may include a FinFET that does not have a separate channel layer.

[0044] In the semiconductor device 100c, the channel region of the transistor is limited to the active region 105 of the fin structure, which is an active structure. Furthermore, there is no separate channel layer interposed within the gate electrode 165. As a result, the source / drain region 150 does not have bends on its sides corresponding to the gate structure 160 and the channel layer. For further details regarding the structure of the contact plug 180c, the explanations in the embodiments shown in Figures 1 to 3 apply similarly. Such semiconductor element 100c may be further arranged in a region of the semiconductor element of other embodiments.

[0045] Figures 7a to 7n are cross-sectional view diagrams illustrating the process for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 7a to 7n illustrate one embodiment of a manufacturing method for producing the semiconductor device shown in Figure 2. Figure 8 is a schematic flowchart illustrating the method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0046] Referring to Figure 7a, a sacrificial layer 120 and the first to fourth channel layers (141, 142, 143, 144) are alternately stacked on the substrate 101. The sacrificial layer 120, the first to fourth channel layers (141, 142, 143, 144), and the substrate 101 are partially removed to form an active structure AS including an active region 105, thereby forming an element isolation layer 110.

[0047] The sacrificial layer 120 is a layer that, through subsequent processes, replaces the gate dielectric layer 162 and gate electrode 165 below the first channel layer 141, as shown in Figure 2. The sacrificial layer 120 is made of a material that has etching selectivity for each of the first to fourth channel layers (141, 142, 143, and 144). The first to fourth channel layers (141, 142, 143, 144) contain a different substance from the sacrificial layer 120. The sacrificial layer 120 and the first to fourth channel layers (141, 142, 143, 144) contain a semiconductor material that includes, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge), but may contain different materials from each other and may or may not contain impurities. For example, the sacrificial layer 120 contains silicon germanium (SiGe), and the first to fourth channel layers (141, 142, 143, 144) contain silicon (Si). The sacrificial layer 120 and the first to fourth channel layers (141, 142, 143, 144) are formed by performing an epitaxial growth process from the laminated structure. The number of channel layers stacked alternately with the sacrificial layer 120 can be varied in various ways according to the embodiment.

[0048] The active structure AS includes an active region 105, a sacrificial layer 120, and first to fourth channel layers (141, 142, 143, 144). The active structure AS is formed in a linear form extending in one direction, for example, in the x-direction, and is formed spaced apart from adjacent active structures in the y-direction. The sides of the active structure AS along the y-direction are coplane and located in a straight line. In the regions where parts of the active region 105, the sacrificial layer 120, and the first to fourth channel layers (141, 142, 143, 144) have been removed, an insulating material is embedded, and then a portion of the insulating material is removed so that the active region 105 protrudes, thereby forming the element isolation layer 110. The upper surface of the element isolation layer 110 is formed lower than the upper surface of the active region 105.

[0049] Referring to Figure 7b, a sacrificial gate structure 200 and a gate spacer layer 164 are formed on the active structure AS. Each of the sacrificial gate structures 200 is a sacrificial structure formed in the region on the channel structure 140 where the gate dielectric layer 162 and the gate electrode 165 are located, as shown in Figure 2, through a subsequent process. The sacrificial gate structure 200 has a linear shape that intersects with the active structure and extends in one direction. The sacrificial gate structure 200 is extended, for example, in the y-direction. Each of the sacrificial gate structures 200 includes sequentially stacked first and second sacrificial gate layers (202, 205) and a mask pattern layer 206. The first and second sacrificial gate layers (202, 205) are patterned using the mask pattern layer 206.

[0050] The first and second sacrificial gate layers (202, 205) are an insulating layer and a conductive layer, respectively, but are not limited to this, and the first and second sacrificial gate layers (202, 205) can also consist of a single layer. For example, the first sacrificial gate layer 202 contains silicon oxide, and the second sacrificial gate layer 205 contains polysilicon. The mask pattern layer 206 may contain silicon oxide and / or silicon nitride. The gate spacer layer 164 is formed on both side walls of the sacrificial gate structure 200. The gate spacer layer 164 is made of a low dielectric constant material and may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiCN.

[0051] Referring to Figure 7c, a portion of the active structure AS exposed from the sacrificial gate structure 200 is removed to form a recess region, and a source / drain region 150 is formed in the recess region. Using the sacrificial gate structure 200 and the gate spacer layer 164 as masks, a portion of the exposed sacrificial layer 120 and a portion of the first to fourth channel layers (141, 142, 143, 144) are removed to form a recess region RC. As a result, the first to fourth channel layers (141, 142, 143, 144) form a channel structure 140 having a limited length along the x-direction. The source / drain region 150 is formed within the recess region and is formed by growing it from the sides of the active region 105 and the channel structure 140, for example, by a selective epitaxial process. The source / drain region 150 may contain impurities through in-situ doping and may also include multiple layers having different doping elements and / or doping concentrations.

[0052] Referring to Figure 7d, an insulating liner layer 192 and an interlayer insulating layer 199 are formed, and the sacrificial gate structure 200 and sacrificial layer 120 are removed. The insulating liner layer 192 is formed to extend along the sides of the sacrificial gate structure 200 and the upper surface of the source / drain region 150. The insulating liner layer 192 contains a material that is relatively hard and has a low dielectric constant. For example, the insulating liner layer 192 contains a material that is harder than the interlayer insulating layer 199, such as SiCN. The interlayer insulating layer 199 is formed on the insulating liner layer 192 so as to fill the space between the sacrificial gate structures 200. The insulating liner layer 192 and the interlayer insulating layer 199 are formed so as to expose the mask pattern layer 206 through a planarization process.

[0053] The sacrificial gate structure 200 and the sacrificial layer 120 are selectively removed relative to the gate spacer layer 164, the insulating liner layer 192, and the channel structure 140. First, the sacrificial gate structure 200 is removed to form the upper gap region UR, and then the sacrificial layer 120 exposed through the upper gap region UR is removed to form the lower gap region LR. For example, if the sacrificial layer 120 contains silicon germanium (SiGe) and the channel structure 140 contains silicon (Si), the sacrificial layer 120 is selectively removed from the channel structure 140 by a wet etching process.

[0054] Referring to Figure 7e, the gate structure 160 and the gate capping layer 170 are formed. The gate structure 160 is formed to fill the upper gap region UR and the lower gap region LR. The gate dielectric layer 162 is formed to conformally cover the inner surfaces of the upper gap region UR and the lower gap region LR. The gate electrode 165 is formed to completely fill the upper gap region UR and the lower gap region LR, and then, together with the gate dielectric layer 162 and the gate spacer layer 164, is removed from the top of the upper gap region UR to a predetermined depth. This forms a gate structure 160 that includes a gate dielectric layer 162, a gate electrode 165, and a gate spacer layer 164, respectively. The gate capping layer 170 is formed by filling the region where the gate electrode 165, gate dielectric layer 162, and gate spacer layer 164 have been removed with insulating material and performing a planarization process. The relative thickness of the gate capping layer 170 and the shape of its lower surface can be varied in various ways depending on the embodiment.

[0055] Referring to Figure 7f together with Figure 8, a portion of the interlayer insulating layer 199, the insulating liner layer 192, and the source / drain region 150 are removed to form a contact hole CH (step S100). The contact hole CH is formed in the region where the contact plug 180 (see Figure 2) is formed by sequentially etching the interlayer insulating layer 199 and the insulating liner layer 192 from the top, and recessing the exposed source / drain region 150 from the top surface. The lower end of the contact hole is located, for example, at the level between the lower surface of the first channel layer 141 and the upper surface of the third channel layer 143.

[0056] Referring to Figure 7g together with Figure 8, a metal-semiconductor compound layer 182 is formed in the region including the lower end of the contact hole CH (step S200). The metal-semiconductor compound layer 182 is formed by depositing a metal layer at a relatively high temperature, for example, about 300°C to about 500°C, while allowing the metal layer to react with the source / drain region 150. The metal layer may contain, for example, Ti (titanium). The metal-semiconductor compound layer 182 contains a metal element and a semiconductor element, for example, TiSi. Unlike the one shown in Figure 7g, the metal-semiconductor compound layer 182 is formed in a form that protrudes from the inner surface of the contact hole CH. As a result, the metal-semiconductor compound layer 182 shown in Figures 2 to 6 is formed in a shape that protrudes inward toward the contact conductive layer 186, and the thickness of the liner conductive layer 184 in contact with the metal-semiconductor compound layer 182 is formed unevenly.

[0057] Referring to Figure 7h together with Figure 8, a liner conductive layer 184 is formed on the metal-semiconductor compound layer 182 so as to cover the side surface of the contact hole CH (step S300). The liner conductive layer 184 is formed to conformally cover the side surface of the contact hole CH and to extend onto the gate capping layer 170. The liner conductive layer 184 is formed by depositing a metallic substance. The liner conductive layer 184 contains, for example, W (tungsten) or Mo (molybdenum). The method for depositing the liner conductive layer 184 may vary depending on the type of metal used for the liner conductive layer 184. The method for depositing the liner conductive layer 184 may include, for example, physical vapor deposition (PVD) or atomic layer deposition (ALD). For example, when depositing a tungsten metal layer using atomic layer deposition, the tungsten layer is formed by reacting WCl5 (tungsten pentachloride) with hydrogen (H2). For example, when depositing a molybdenum metal layer using atomic layer deposition, the molybdenum layer is formed by reacting MoCl5 (molybdenum pentachloride) or MoO2Cl2 (molybdenum dioxydichloride) with hydrogen (H2).

[0058] Referring to Figure 7i together with Figure 8, the liner conductive layer 184 formed on the metal-semiconductor compound layer 182 is selectively oxidized (step S400). The surface of the liner conductive layer 184 formed on the metal-semiconductor compound layer 182 reacts with oxygen to form a liner oxide layer 184o. The liner oxide layer 184o is formed, for example, by the reaction of oxygen plasma with the metal on the surface of the liner conductive layer 184. The liner oxide layer 184o is formed on the gate capping layer 170.

[0059] In the deposition process of the liner conductive layer 184, the liner conductive layer 184 is formed to conformally cover the side surface of the contact hole CH, but a protruding overhang is formed on the upper part of the liner conductive layer 184. To remove the overhang, a step is required to selectively oxidize and remove the liner conductive layer 184. As a result, part of the liner conductive layer 184, including the upper region, is oxidized, while part of it, including the lower region, remains unoxidized. The liner oxide layer 184o is formed on the upper part of the liner conductive layer 184, but not on at least a portion of the lower part.

[0060] The extent of the formed liner oxide layer 184o can be varied in various embodiments, for example, it can be formed deeper than shown in Figure 7i in the direction of the source / drain region 150. The thickness of the formed liner oxide layer 184o can be varied in various embodiments. For example, the liner oxide layer 184o extending along the side surface of the contact hole CH may decrease in thickness abruptly or gradually toward the source-drain region 150. Depending on the extent of the formed liner oxide layer 184o, the bent portion BR shown in Figures 4 and 5 is formed, and the upper liner conductive layer 185 shown in Figure 5 is formed.

[0061] Referring to Figure 7j together with Figure 8, the oxidized liner conductive layer 184 is selectively removed (step S500). Here, the oxidized liner conductive layer 184 refers to the liner oxide layer 184o in Figure 7i. The liner oxide layer 184o is removed by dry etching using a chlorine (Cl)-based chemical. Specifically, the liner oxide layer 184o is selectively removed using a precursor containing WCl5 (tungsten pentachloride) and / or MoCl5 (molybdenum pentachloride). As a result, the oxidized liner conductive layer 184 forms the structure of the liner conductive layer 184.

[0062] The step of selectively removing the oxidized liner conductive layer 184 is adjusted according to the pressure inside the chamber and the dose of the precursor. For example, when using a relatively low chamber pressure, the area of ​​the liner conductive layer 184 that is removed is smaller than when using a relatively high chamber pressure. This forms the structure of the liner conductive layer 184 shown in Figure 3. When high chamber pressure is used, a wide area of ​​the liner conductive layer 184 is removed, which may result in the formation of the liner conductive layer 184 structure shown in Figure 4, or the liner conductive layer 184 and upper liner conductive layer 185 shown in Figure 5.

[0063] When the precursor dose is relatively low, the area of ​​the liner conductive layer 184 that is removed is smaller than when the precursor dose is relatively high. This forms the structure of the liner conductive layer 184 shown in Figure 3. When the precursor dose is high, a wide area of ​​the liner conductive layer 184 is removed, which may result in the formation of the liner conductive layer 184 structure shown in Figure 4, or the liner conductive layer 184 and upper liner conductive layer 185 shown in Figure 5. Depending on the extent of the liner conductive layer 184 to be removed, the bent portion BR shown in Figures 4 and 5 is formed, and the upper liner conductive layer 185 shown in Figure 5 is formed. This forms the structure of the liner conductive layer 184 of the semiconductor device according to the embodiment of the present invention shown in Figures 3, 4, and 5.

[0064] Referring to Figure 7k together with Figure 8, a preliminary contact conductive layer 186p is formed on the liner conductive layer 184 (step S600). The preliminary contact conductive layer 186p is formed on the liner conductive layer 184 so as to fill at least a portion of the contact hole CH. In one embodiment, the preliminary contact conductive layer 186p may be formed to extend onto the gate capping layer 170. The pre-contact conductive layer contains tungsten (W) or molybdenum (Mo). The preliminary contact conductive layer 186p may contain crystal grains internally. The crystal grains of the preliminary contact conductive layer 186p have a size of approximately 4 nm to 9 nm. The resistivity of the preliminary contact conductive layer 186p is, for example, in the range of approximately 10 μΩcm to approximately 20 μΩcm.

[0065] The preliminary contact conductive layer 186p is formed by depositing a metallic substance. The preliminary contact conductive layer 186p contains, for example, W (tungsten) or Mo (molybdenum). The method for depositing the preliminary contact conductive layer 186p may vary depending on the type of metal used for the preliminary contact conductive layer 186p. The method for depositing the preliminary contact conductive layer 186p may include, for example, atomic layer deposition or chemical vapor deposition (CVD). When depositing tungsten metal using atomic layer deposition, a tungsten layer is formed by reacting WCl5 (tungsten pentachloride) with hydrogen (H2). When depositing a molybdenum metal layer using atomic layer deposition, the molybdenum layer is formed by reacting MoCl5 (molybdenum pentachloride) or MoO2Cl2 (molybdenum dioxydichloride) with hydrogen (H2). When depositing tungsten metal using chemical vapor deposition, a tungsten layer is formed by reacting WF6 (tungsten hexafluoride) with hydrogen (H2).

[0066] Referring to Figure 7l together with Figure 8, a sacrificial metal layer 190 is formed on the preliminary contact conductive layer 186p (step S700). The sacrificial metal layer 190 is formed on the preliminary contact conductive layer 186p to fill the contact holes CH and to extend onto the gate capping layer 170. The sacrificial metal layer 190 may contain tungsten (W) or molybdenum (Mo), etc.

[0067] Referring to Figure 7m together with Figure 8, the planarization process removes a portion of the sacrificial metal layer 190 and the preliminary contact conductive layer 186p (step S800). The sacrificial metal layer 190 is removed using an etching process and / or a planarization process, and a portion of the preliminary contact conductive layer 186p is removed from the top surface to form separate preliminary contact conductive layers 186p. At this stage, the gate capping layer 170 is also partially removed, resulting in a form with a reduced height. During the process, a sacrificial metal layer 190 forms a preliminary contact conductive layer 186p of the desired height. The leveling process may result in uneven distribution. To prevent this, a sacrificial metal layer 190 can be formed to minimize any non-uniformity that may occur during the planarization process, and a preliminary contact conductive layer 186p of the desired height can be formed.

[0068] Referring to Figure 7n together with Figure 8, the contact conductive layer 186 is formed by heat-treating the preliminary contact conductive layer 186p using hydrogen plasma (step S900). Specifically, the contact conductive layer 186 is formed by heat treatment at a temperature of approximately 300°C to 500°C, which rearranges the atoms inside the metal. The contact conductive layer 186 contains crystal grains, the size of which is approximately 10 nm to 12 nm. As a result of heat treatment using hydrogen plasma, the crystal grain size of the contact conductive layer 186 is larger than that of the preliminary contact conductive layer 186p. As a result, the contact conductive layer 186 has a reduced number of crystal grain boundaries, which allows for smoother electron movement and thus lowers its resistivity. The resistivity of the contact conductive layer 186 is, for example, in the range of approximately 9 μΩcm to approximately 18 μΩcm.

[0069] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of Symbols]

[0070] 100, 100a~100c semiconductor devices 101 circuit board 105 Active region 110-element isolation layer 120 layers of victims 130 Internal spacer layer 140 Channel Structures 141, 142, 143, 144 Channel Layers 1-4 150 Source / Drain Area 160 Gate Structure 162 Gate Dielectric Layer 164 Gate Spacer Layer 165 Guard Station 170 Gate capping layer 180, 180a~180c Contact Plug 182 Metal-semiconductor compound layer 184 Liner conductive layer 185 Upper liner conductive layer 186 Contact conductive layer 192 Insulating liner layer 194 Contact Spacer Layer 199 Interlayer insulating layer BR folding section

Claims

1. The steps include alternately stacking multiple sacrificial layers and multiple channel layers on a substrate, The steps include partially removing the plurality of channel layers, the plurality of sacrificial layers, and the substrate to form a plurality of active structures extending horizontally in a first direction on the upper surface of the substrate, The steps include forming sacrificial gate structures and spacer layers on the plurality of active structures, extending in a second direction intersecting the first direction, The steps include forming source / drain regions on both sides of the sacrificial gate structure, The steps include forming an interlayer insulating layer on the source / drain region and removing the sacrificial gate structure and the plurality of sacrificial layers, The steps include forming a gate structure extending in the second direction in the region where the sacrificial gate structure and the plurality of sacrificial layers have been removed, The steps include: removing a portion of the interlayer insulating layer and a portion of the source / drain region to form a contact hole; The steps include forming a metal-semiconductor compound layer on the lower end of the contact hole, The steps include forming a liner conductive layer on the metal-semiconductor compound layer so as to cover the side surface of the contact hole, A step of selectively oxidizing the liner conductive layer formed on the metal-semiconductor compound layer, A step of selectively removing the oxidized liner conductive layer, The steps include forming a preliminary contact conductive layer on the liner conductive layer, The steps include forming a sacrificial metal layer on the aforementioned pre-contact conductive layer, A step of removing a portion of the sacrificial metal layer and the preliminary contact conductive layer by a planarization process, A method for manufacturing a semiconductor device, characterized by comprising the step of forming a contact conductive layer by heat-treating the aforementioned pre-contact conductive layer using hydrogen plasma.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that the ratio of the resistivity of the liner conductive layer to the resistivity of the contact conductive layer is in the range of 0.45 to 1.

8.

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that the side region of the liner conductive layer extending along the side of the contact conductive layer includes a region in which the thickness increases toward the source / drain region.

4. The contact conductive layer includes a lower region where the side surface of the liner conductive layer extending along the side surface of the contact conductive layer is formed, and an upper region on the lower region. The method for manufacturing a semiconductor element according to claim 1, characterized in that the contact conductive layer has a bent portion whose width is discontinuously changed between the lower region and the upper region.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that the contact conductive layer further includes an upper liner conductive layer formed on the side surface of the contact conductive layer in the upper region.

6. The method for manufacturing a semiconductor element according to claim 4, characterized in that the bent portion is located at a height of 1 / 3 or more and 1 / 2 or less of the overall height of the contact hole.

7. The steps include forming a semiconductor region on a substrate and an interlayer insulating layer on the semiconductor region, The steps include: removing a portion of the interlayer insulating layer and the semiconductor region to form a contact hole; The steps include forming a metal-semiconductor compound layer on the lower end of the contact hole, The steps include forming a liner conductive layer on the metal-semiconductor compound layer so as to cover the side surface of the contact hole, A step of selectively oxidizing a portion of the liner conductive layer and removing the oxidized portion of the liner conductive layer, The steps include forming a preliminary contact conductive layer on the liner conductive layer, The process includes the step of forming a contact conductive layer by heat-treating the aforementioned pre-contact conductive layer using hydrogen plasma, A method for manufacturing a semiconductor device, characterized in that the size of the crystal grains in the contact conductive layer is larger than the size of the crystal grains in the preliminary contact conductive layer.

8. The steps include alternately stacking multiple sacrificial layers and multiple channel layers on a substrate, The steps include forming a sacrificial gate structure extending in one direction on the plurality of channel layers and the plurality of sacrificial layers, The steps include forming a source / drain region on at least one side of the sacrificial gate structure and forming an interlayer insulating layer on the source / drain region, The steps include removing the sacrificial gate structure and the plurality of sacrificial layers to form a gate structure, The steps include: removing a portion of the interlayer insulating layer and a portion of the source / drain region to form a contact hole; The steps include forming a metal-semiconductor compound layer on the lower end of the contact hole, The steps include forming a liner conductive layer on the metal-semiconductor compound layer so as to cover the side surface of the contact hole, A step of selectively removing a portion of the liner conductive layer, The steps include forming a preliminary contact conductive layer on the liner conductive layer, The steps include forming a sacrificial metal layer on the aforementioned pre-contact conductive layer, A step of removing a portion of the sacrificial metal layer and the preliminary contact conductive layer by a planarization process, The process includes the step of forming a contact conductive layer by heat-treating the aforementioned pre-contact conductive layer using hydrogen plasma, A method for manufacturing a semiconductor device, characterized in that the liner conductive layer has a first thickness on the side surface of the contact conductive layer and a second thickness greater than the first thickness on the bottom surface of the contact conductive layer.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that the step of selectively removing a portion of the liner conductive layer includes a step of selectively oxidizing the liner conductive layer formed on the metal-semiconductor compound layer and removing the oxidized liner conductive layer.

10. The method for manufacturing a semiconductor device according to claim 8, characterized in that the ratio of the resistivity of the liner conductive layer to the resistivity of the contact conductive layer is in the range of 0.45 to 1.8.

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