Semiconductor equipment

Abstract

To provide a semiconductor device that can reduce turn-off losses while improving short-circuit withstand capability. [Solution] The semiconductor substrate 11 includes an FS layer 13 between the collector layer 12 and the drift layer 14. The total dose of the collector layer 12 is 1 × 10⁻⁶. 13 / cm 2 It is less than. The collector layer 12 has multiple carrier concentration peaks. At least a portion of the collector layer 12 is configured such that the dose amount contained within ±3σp of the deepest peak, which is the deepest peak relative to the back surface 11b of the semiconductor substrate 11, accounts for 13% or more of the total dose amount.

Description

[Technical Field]

[0001] The disclosures in this specification relate to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device in which IGBTs are formed as vertical elements. The contents of the prior art documents are incorporated by reference in this specification to explain the technical elements. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-43301 [Overview of the project] [Problems that the invention aims to solve]

[0004] In Patent Document 1, an n+ type field stop layer is placed between an n- type drift layer and a p+ type collector layer to improve the breakdown voltage. Furthermore, in order to improve the short-circuit withstand capability, the distance between the maximum peaks of carrier concentration in the field stop layer and the collector layer, and the ratio of the total dose amount in the collector layer to the total dose amount in the field stop layer are set to satisfy a predetermined relationship.

[0005] However, in applications requiring low turn-off losses, the total dose of the collector layer must be reduced, and the ratio of distance to total dose may not satisfy the predetermined relationship. In other words, there is a risk that short-circuit withstand capability cannot be ensured. Further improvements to semiconductor devices are needed in the above-mentioned respects, or in other respects not mentioned.

[0006] One of the objectives of the disclosure is to provide a semiconductor device that can reduce turn-off losses while improving short-circuit withstand capability. [Means for solving the problem]

[0007] The semiconductor device disclosed herein is A first conductive drift layer (14) and A second conductive base layer (15) is placed on the drift layer and provides one surface (11a) of the semiconductor substrate (11), A first-conductivity type emitter region (16) formed on the surface layer of one side of the base layer, A gate electrode (20) facing the base layer located between the drift layer and the emitter region is connected via a gate insulating film (19), A second conductive collector layer (12) is positioned on the opposite side of the drift layer from the base layer and provides the back surface (11b) of the semiconductor substrate, A first-conductivity type field stop layer (13) is placed between the collector layer and the drift layer and has a higher carrier concentration than the drift layer, An emitter electrode (21) is arranged on one surface and electrically connected to the base layer and the emitter region, A collector electrode (25) is positioned on the back surface and electrically connected to the collector layer, Equipped with, The collector layer has a total dose of 1 × 10⁻⁶ 13 / cm 2 It is less than, The collector layer has multiple peaks in carrier concentration. At least a portion of the collector layer is configured such that the dose contained within ±3σp of the deepest peak, which is the deepest peak relative to the back surface, accounts for 13% or more of the total dose.

[0008] According to the disclosed semiconductor device, the total dose amount of the collector layer is 1 × 10⁻⁶ 13 / cm 2Since it is less than that, the turn-off loss can be reduced. In addition, at least a part of the collector layer is provided such that the doping amount included within ±3σp with respect to the deepest peak among the plurality of peaks occupies 13% or more of the total doping amount. As a result, the short-circuit withstand voltage can be improved. As a result, it is possible to provide a semiconductor device capable of reducing the turn-off loss while improving the short-circuit withstand voltage.

[0009] The plurality of disclosed aspects in this specification adopt different technical means to achieve their respective purposes. The claims and the reference numerals in parentheses described in this section exemplarily show the correspondence with the parts of the embodiments described later, and are not intended to limit the technical scope. The objects, features, and effects disclosed in this specification will become clearer by referring to the subsequent detailed description and the accompanying drawings.

Brief Description of Drawings

[0010] [Figure 1] It is a diagram showing a semiconductor device according to the first embodiment. [Figure 2] It is a cross-sectional view taken along the line II-II of FIG. 1. [Figure 3] It is a timing chart showing the operation of the semiconductor device. [Figure 4] It is a diagram showing the electric field strength of the semiconductor device. [Figure 5] It is a diagram for explaining the electric field strength peak at the time of short circuit. [Figure 6] It is a diagram showing the peak of carrier concentration in the collector layer. [Figure 7] It is a diagram showing the relationship between the doping amount of the deepest peak and the improvement rate of the short-circuit withstand voltage. [Figure 8] It is a diagram showing the relationship between the on-voltage and the turn-off loss. [Figure 9] It is a diagram showing a semiconductor device according to the second embodiment. [Figure 10] It is a diagram showing the first element region. [Figure 11] It is a diagram showing the second element region. [Figure 12] This is a diagram showing a modified example. [Figure 13] This is a diagram showing a modified example. [Figure 14] This is a diagram showing a modified example. [Modes for carrying out the invention]

[0011] Several embodiments will be described below with reference to the drawings. In each embodiment, the same reference numerals are used for corresponding components, and redundant explanations may be omitted. If only a part of the configuration is described in each embodiment, the configuration of other embodiments described earlier can be applied to the other parts of that configuration. Furthermore, in addition to the combinations of configurations explicitly stated in the description of each embodiment, configurations from multiple embodiments can be partially combined even if not explicitly stated, as long as there are no particular problems with the combination.

[0012] The semiconductor device of this embodiment is applied, for example, to a power conversion device for a mobile body that uses a rotating electric machine as a drive source. The mobile body is, for example, an electric vehicle (BEV), a hybrid electric vehicle (HEV), a plug-in hybrid electric vehicle (PHEV), an aircraft such as an electric vertical take-off and landing aircraft or a drone, a ship, construction machinery, or agricultural machinery.

[0013] (First Embodiment) First, the schematic configuration of the semiconductor device will be described based on Figures 1 and 2. Figure 1 is a top view plan of the semiconductor device. Figure 2 is a cross-sectional view taken along line II-II in Figure 1. As an example, the semiconductor device of this embodiment is applied to a DC-DC converter.

[0014] <Semiconductor device> In the following, the thickness direction of the semiconductor substrate is defined as the Z direction. The direction perpendicular to the Z direction is defined as the X direction. The direction perpendicular to both the Z and X directions is defined as the Y direction. Unless otherwise specified, the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is defined as the planar shape. Furthermore, the view from the Z direction is sometimes simply referred to as the planar view.

[0015] As shown in Figures 1 and 2, the semiconductor device 10 includes a semiconductor substrate 11. The semiconductor substrate 11 is made of materials such as silicon (Si) or a wide-bandgap semiconductor with a wider bandgap than silicon. Examples of wide-bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond.

[0016] Vertical elements are formed on the semiconductor substrate 11. The vertical elements are configured to carry the main current in the thickness direction of the semiconductor substrate 11, i.e., in the Z direction. The vertical elements are IGBTs. IGBT is an abbreviation for Insulated Gate Bipolar Transistor. The semiconductor substrate 11 has one surface 11a and a back surface 11b as the surfaces on which electrodes are provided.

[0017] The semiconductor substrate 11 has a collector layer 12, a field stop layer 13 (hereinafter referred to as FS layer 13), a drift layer 14, a base layer 15, an emitter region 16, and a base contact region 17. The semiconductor substrate 11 is formed by creating each semiconductor region by impurity ion implantation or the like. The semiconductor regions of the semiconductor substrate 11 are sometimes referred to as semiconductor layers, diffusion layers, etc.

[0018] The collector layer 12 is located on the opposite side of the base layer 15 from the drift layer 14. The collector layer 12 is formed on the surface layer of the back surface 11b of the semiconductor substrate 11. The collector layer 12 provides the back surface 11b of the semiconductor substrate 11. The collector layer 12 is a p-conductivity type (p+) semiconductor region with a higher impurity concentration than the base layer 15.

[0019] The FS layer 13 is positioned between the collector layer 12 and the drift layer 14. The FS layer 13 is formed on the surface of the collector layer 12 opposite to the back surface 11b. The FS layer 13 is an n-conductivity (n+) semiconductor region with a higher carrier concentration (impurity concentration) than the drift layer 14. By including the FS layer 13, it is possible to suppress the depletion layer from spreading towards the collector layer 12. The FS layer 13 is sometimes referred to as a buffer layer.

[0020] The drift layer 14 is located between the FS layer 13 and the base layer 15. The drift layer 14 is formed on the surface of the FS layer 13 opposite to the surface facing the collector layer 12. The drift layer 14 is an n-conductivity semiconductor region with a lower impurity concentration than the FS layer 13.

[0021] The base layer 15 is located on the side of the drift layer 14 opposite to the side of the FS layer 13. The base layer 15 is formed on the surface layer of one side 11a of the semiconductor substrate 11. The base layer 15 provides one side 11a of the semiconductor substrate 11. The base layer 15 is a p-conductivity (p) semiconductor region with a lower impurity concentration than the collector layer 12. The base layer 15 is sometimes referred to as the channel region or body region.

[0022] The emitter region 16 is located on the surface layer on the side 11a within the base layer 15. The emitter region 16 is terminated within the base layer 15. The emitter region 16 is an n-conductivity (n+) semiconductor region with a higher carrier concentration than the drift layer 14. The emitter region 16 is formed to be in contact with the side surface of the trench 18, which will be described later. The emitter region 16 extends along the direction of extension of the trench 18.

[0023] The base contact region 17, like the emitter region 16, is located on the surface layer of the base layer 15, on the side 11a. The base contact region 17 terminates within the base layer 15. The base contact region 17 is a p-conductivity (p+) semiconductor region with a higher impurity concentration than the base layer 15. The base contact region 17 is located adjacent to the emitter region 16. The base contact region 17 also extends along the direction of extension of the trench 18. As an example, in this embodiment, the base contact region 17 is formed to a deeper position than the emitter region 16. The base contact region 17 is sometimes referred to as the body contact region or contact region.

[0024] Multiple trenches 18 are formed in the semiconductor substrate 11 having the above configuration. The trenches 18 are formed from one surface 11a to a predetermined depth. The trenches 18 penetrate the base layer 15. The leading edge of the trenches 18 reaches the drift layer 14. As an example, each of the multiple trenches 18 in this embodiment extends in the X direction. The multiple trenches 18 are arranged at approximately equal intervals in the Y direction, forming a stripe shape in a plan view. The trenches 18 define cells. Cells may be referred to as main cells, unit structures, unit circuits, elements, etc. Multiple cells are connected in parallel to each other to constitute a trench gate IGBT.

[0025] A gate insulating film 19 is formed on the wall surface of the trench 18. The gate insulating film 19 is made of an oxide film or the like and is formed to cover the wall surface of the trench 18. A gate electrode 20 is formed on the surface of the gate insulating film 19 so as to fill the trench 18. The gate electrode 20 is made of doped polysilicon or the like. The trench 18 is filled by the gate insulating film 19 and the gate electrode 20.

[0026] The gate electrode 20 penetrates the base layer 15 and reaches the drift layer 14. Multiple gate electrodes 20 are formed on the semiconductor substrate 11. Each of the multiple gate electrodes 20 extends in the X direction. The multiple gate electrodes 20 are arranged at approximately equal intervals in the Y direction, forming a stripe pattern in a plan view.

[0027] An emitter electrode 21 is arranged on one surface 11a of the semiconductor substrate 11. The emitter electrode 21 is electrically connected to the emitter region 16. The emitter electrode 21 is electrically connected to the base layer 15 via the base contact region 17. The emitter electrode 21 is electrically isolated from the gate electrode 20 by an interlayer insulating film 22 such as a BPSG. BPSG is an abbreviation for boro phosphosilite glass.

[0028] A signal electrode pad 23 is also arranged on one surface 11a of the semiconductor substrate 11. The pad 23 is formed in a position that does not overlap with the emitter electrode 21 in a plan view, specifically on the outer peripheral region surrounding the element formation area. The pad 23 includes at least a pad for the gate electrode 20. As an example, in this embodiment, five pads 23 are formed on the semiconductor substrate 11. The five pads 23 are formed together on one end in the Y direction and arranged in the X direction on the semiconductor substrate 11, which is substantially rectangular in plan.

[0029] A protective film 24 is placed on one surface 11a of the semiconductor substrate 11. The protective film 24 is an insulating film provided on one surface 11a of the semiconductor substrate 11 so as to cover the peripheral edge of the emitter electrode 21. The protective film 24 is made of, for example, polyimide or silicon nitride. The protective film 24 has an opening 241 that defines the bonding region of the emitter electrode 21 and an opening 242 that defines the bonding region of the pad 23.

[0030] A collector electrode 25 is positioned on the back surface 11b of the semiconductor substrate 11. The collector electrode 25 is formed over almost the entire surface of the back surface 11b. The collector electrode 25 is electrically connected to the collector layer 12.

[0031] In the semiconductor device 10 configured as described above, the n-conductivity type corresponds to the first conductivity type, and the p-conductivity type corresponds to the second conductivity type.

[0032] <Semiconductor device operation> Next, the operation of the semiconductor device 10 (IGBT) will be explained based on Figure 3. Figure 3 is a diagram showing the operation of the semiconductor device 10.

[0033] When a higher voltage is applied to the collector electrode 25 than to the emitter electrode 21, the pn junction formed between the base layer 15 and the drift layer 14 becomes reverse-conductive, and a depletion layer is formed. To turn on the IGBT, with a higher voltage applied to the collector electrode 25 than to the emitter electrode 21, a voltage equal to or greater than the threshold voltage Vth of the insulated gate structure is applied to the gate electrode 20. In Figure 3, at time t1, a voltage equal to or greater than the threshold voltage Vth is applied to the gate electrode 20.

[0034] As a result, the gate-emitter voltage Vge increases, and an inversion layer, or channel, is formed in the portion of the base layer 15 that is in contact with the trench 18. Then, electrons are supplied from the emitter region 16 to the drift layer 14 via the inversion layer, and electrons are also supplied from the collector layer 12 to the drift layer 14. Conductivity modulation reduces the resistance of the drift layer 14, causing the IGBT to turn on. In other words, the collector-emitter voltage Vce decreases, and current Ic flows.

[0035] Then, when the voltage application to the gate electrode 20 is stopped at time t2, the gate-emitter voltage Vge decreases, the inversion layer disappears, and the IGBT turns off. In other words, the current Ic decreases and the IGBT turns off. However, when a short circuit occurs, the current Ic increases sharply while the collector-emitter voltage Vce decreases sharply, as shown by the dashed line in Figure 3.

[0036] <Electric field strength during short circuit> Next, the electric field strength during a short circuit will be explained based on Figures 4 and 5. Figure 4 shows the simulation results of a reference example. Figure 5 is a diagram to explain the occurrence of an electric field strength peak within the FS in the reference example. In Figure 5, holes are indicated by + (plus) and electrons by - (minus).

[0037] In the reference example, the code of each element is obtained by adding 'r' to the end of the code of the related element of the semiconductor device 10. In the reference example, the total dose of the collector layer 12r is 3.56 × 10⁻⁶. 12 cm -2 Furthermore, the collector layer 12r was formed by a single ion implantation, and in order to improve the ohmic characteristics, it was configured to have a carrier concentration peak at a shallow position, that is, close to the back surface 11b, as shown in Figure 5.

[0038] As shown in Figure 4, in the reference example, the electric field strength when off peaks near the junction between the base layer 15r and the drift layer 14r, and gradually decreases toward the collector layer 12r. On the other hand, the electric field strength when short-circuited peaks within the FS layer 13r.

[0039] Thus, during a short circuit, the peak of the electric field strength occurs within the FS layer 13r because, as shown in Figure 5, there are fewer holes injected at the edges on the back side of the substrate in the electric field strength (E), and there is an excess of electrons at the edges enclosed by the dashed line. When the peak of the electric field strength occurs on the back side of the substrate in this way, there is a risk of avalanche breakdown occurring near the peak. In other words, in a configuration with the FS layer 13r, there is a risk of low short-circuit withstand capability.

[0040] By increasing the carrier concentration in the collector layer 12r, it is possible to increase the number of holes injected at locations that could become peaks in the electric field strength in the FS layer 13r, thereby mitigating the aforementioned transient states of electrons. In other words, it is possible to suppress the occurrence of electric field strength peaks in the FS layer 13r during a short circuit.

[0041] <Collector layer> Next, the configuration of the collector layer 12 of the semiconductor device 10 will be described based on Figure 6. Figure 6 shows the carrier concentration peaks of the collector layer 12 and the FS layer 13. Figure 6 shows the distance from the back surface 11b of the semiconductor substrate 11 to the carrier concentration peak position. When indicating the position of the peak, the peak apex is used as the reference point.

[0042] The semiconductor device 10 of this embodiment is applied to a DC-DC converter as described above. In order to meet the low turn-off loss required for the converter, the total dose amount of the collector layer 12 is 1 × 10⁻¹⁶. 13 / cm 2 It is less than this. By reducing the total dose in this way, hole injection during turn-off can be suppressed, and the turn-off loss can be reduced. Therefore, for applications that require low turn-off loss characteristics, it is difficult to improve short-circuit withstand capability by increasing the carrier concentration in the collector layer, as described above.

[0043] Therefore, in this embodiment, as shown in Figure 6, the carrier concentration of the collector layer 12 has multiple peaks. Some of the multiple peaks may not be perfect peaks but rather have gentle shoulders. As an example, the collector layer 12 has two peaks 12a and 12b. Peak 12a is the peak located furthest from the back surface 11b, i.e., the deepest peak. Peak 12a is the peak located closest to the FS layer 13, i.e., the shallowest peak. Peak 12b is the peak located furthest from the FS layer 13.

[0044] And at least a part of the collector layer 12 is configured to satisfy the condition that the dose amount included within ±3σp with respect to the deepest peak, which is the peak at the deepest position with reference to the back surface 11b, occupies 13% or more of the total dose amount. As an example in this embodiment, throughout the entire collector layer 12 in the element formation region, the dose amount included within ±3σp of the peak 12a, which is the deepest peak, occupies 13% or more of the total dose amount.

[0045] Furthermore, the collector layer 12 is formed such that the minimum concentration from the back surface 11b to the deepest peak is 1×10 16 / cm 3 or more. As an example in this embodiment, the carrier concentration is the lowest between the peaks 12a and 12b. And from the back surface 11b to the peak 12a, which is the deepest peak, the concentration at the lowest concentration position 12c where the carrier concentration is the lowest is 1×10 16 / cm 3 or more.

[0046] Also, the carrier concentration of the FS layer 13 also has at least one peak. In the example shown in FIG. 6, it has one peak. And when the distance from the back surface 11b to the maximum peak where the carrier concentration is the maximum in the FS layer 13 is L1, the distance L1 is 0.8 μm or more. The distance L1 is the distance to the apex position of the maximum peak.

[0047] <Summary of the First Embodiment> As described above, in this embodiment, the total dose amount of the collector layer 12 is less than 1×10 13 / cm 2 . Thus, by reducing the total dose amount in this way, the injection of holes can be suppressed at turn-off, and the turn-off loss can be reduced.

[0048] In addition, at least a portion of the collector layer 12 is configured such that the dose contained within ±3σp of the deepest peak (peak 12a) among the multiple peaks of carrier concentration accounts for 13% or more of the total dose. By securing the dose around the deepest peak in this way, the short-circuit withstand capability can be improved while reducing the total dose. Therefore, the semiconductor device 10 of this embodiment can reduce turn-off loss while improving short-circuit withstand capability. The semiconductor device 10 is suitable for applications that require low turn-off characteristics, such as converters. In this embodiment, the collector layer 12 satisfies the above conditions throughout the entire element formation region.

[0049] Figure 7 shows the relationship between the dose amount at the deepest peak and the improvement rate of short-circuit tolerance in a configuration with multiple peaks. Figure 7 shows the simulation results. The dose amount at the deepest peak is the percentage (%) of the total dose amount that is contained within ±3σp of the deepest peak. σp is the projected variance derived from the boron injection depth. In this simulation, the total dose amount is set to 5.4 × 10⁻⁶ 12 / cm 2 The distance from the back surface 11b to the deepest peak, i.e., the depth, was checked at three levels. The solid line shows the result for a depth of 0.55 μm, the dashed line for a depth of 0.44 μm, and the dotted line for a depth of 0.32 μm. The withstand capability improvement rate shows the rate of change in short-circuit withstand capability compared to a configuration with a single peak at a depth of 0.05 μm. The depth of the collector layer 12 was set to 1 μm.

[0050] As shown in Figure 7, if the dose amount contained in ±3σp of the deepest peak is 13% or more of the total dose amount, the short-circuit withstand capability can be improved regardless of the depth (position) of the deepest peak, specifically by 5% or more. In particular, if the dose amount contained in ±3σp of the deepest peak is 22% or more of the total dose amount, the short-circuit withstand capability can be further improved regardless of the depth (position) of the deepest peak, specifically by 10% or more. Furthermore, the deeper the position of the deepest peak, that is, the closer it is to the FS layer 13, the more the short-circuit withstand capability can be improved. For example, if the depth of the deepest peak is 0.55 μm, that is, if the peak position is offset towards the FS layer 13 side rather than the center in the depth direction of the collector layer 12, the short-circuit withstand capability can be improved by 10% or more by setting it to 13% or more of the total dose amount.

[0051] In the collector layer 12, the minimum concentration in the region from the back surface 11b of the semiconductor substrate 11 to the deepest peak is not particularly limited. For example, in this embodiment, the minimum concentration from the back surface 11b to the deepest peak is 1 × 10⁻⁶ 16 / cm 3 That concludes the explanation. According to this method, the on-voltage can be lowered while reducing the turn-off loss as described above.

[0052] Figure 8 shows the relationship between the on-voltage (Von) and the turn-off loss (Eoff). Figure 8 shows the simulation results. In this simulation, the depth of the collector layer 12 was set to 1 μm, and two levels of the minimum concentration were confirmed. The solid line represents 1 × 10⁻⁶ 16 / cm 3 The solid line is 1 x 10 15 / cm 3 This shows the results.

[0053] Minimum concentration 1 × 10 16 / cm 3 Then, the minimum concentration is 1 × 10 15 / cm 3 Compared to the configuration shown above, the resistance in the current path is reduced. Therefore, as shown in Figure 8, the on-voltage can be lowered while the turn-off loss can be reduced.

[0054] The distance L1 from the back surface 11b to the maximum peak of the FS layer 13 is not particularly limited. As an example, in this embodiment, the distance L1 is 0.8 μm or more. This makes it difficult for scratches to reach the FS layer 13 even if scratches occur on the back surface 11b side during the manufacturing process. This makes it possible to suppress fluctuations in withstand voltage, that is, fluctuations in the characteristics of the semiconductor device 10.

[0055] (Second Embodiment) This embodiment is a modification based on a prior embodiment, and the description of the prior embodiment can be referenced. In the prior embodiment, the above conditions were satisfied throughout the entire collector layer. Alternatively, the conditions may be satisfied only in a part of the collector layer.

[0056] Figure 9 shows the semiconductor device 10 according to this embodiment. Figure 9 corresponds to Figure 2. In Figure 9, the back surface 11b side of the semiconductor device 10 is shown. Figure 10 shows the first element region. Figure 11 shows the second element region. Figures 10 and 11 also show the carrier concentration of the collector layer.

[0057] As shown in Figures 9, 10, and 11, the semiconductor substrate 11 comprises a first element region 31 and a second element region 32. Some of the multiple cells are in the first element region 31, and other parts are in the second element region 32. Similar to the prior embodiment, the total dose of the collector layer 12 is 1 × 10⁻⁶ 13 / cm 2 It is less than.

[0058] The first element region 31 and the second element region 32 have different collector layer configurations 12. The collector layer 121 of the first element region 31 satisfies the above-mentioned conditions. That is, the collector layer 121 is configured such that the dose amount contained within ±3σp of the deepest peak accounts for 13% or more of the total dose amount. Furthermore, the maximum peak 12m, where the carrier concentration is highest in the collector layer 121, is located biased towards the drift layer 14 side from the center C1 in the depth direction of the collector layer 12. That is, the maximum peak 12m is located closer to the FS layer 13 than to the center C1.

[0059] The collector layer 122 of the second element region 32 does not satisfy the above conditions. That is, the dose amount included in ±3σp of the deepest peak of the collector layer 122 is less than 13% of the total dose amount. In addition, the maximum peak 12m of the collector layer 122 is located biased toward the collector electrode 25 side than the center C1 of the collector layer 12. That is, the maximum peak 12m is located closer to the back surface 11b than to the center C1.

[0060] As an example, in this embodiment, the first element region 31 and the second element region 32 are arranged alternately. Specifically, in the Y direction, which is the direction in which the multiple trenches 18 are arranged side by side, the first element region 31 and the second element region 32 are arranged alternately. The alternating arrangement of the first element region 31 and the second element region 32 forms a stripe pattern.

[0061] <Summary of the second embodiment> According to this embodiment, the semiconductor substrate 11 comprises a first element region 31 and a second element region 32. The total dose of the collector layer 12 is 1 × 10⁻⁶. 13 / cm 2 The collector layer 121 of the first element region 31 is configured such that the dose amount contained within ±3σp relative to the deepest peak accounts for 13% or more of the total dose amount. Therefore, similar to the configuration shown in the prior embodiment, it is possible to reduce turn-off losses while improving short-circuit withstand capability. In particular, since the maximum peak 12m is located deeper than the center C1, short-circuit withstand capability can be improved.

[0062] On the other hand, the collector layer 122 of the second element region 32 does not satisfy the conditions for the deepest peak. However, the maximum peak 12m of the collector layer 122 is located shallower than the center C1. This allows for improved ohmic characteristics.

[0063] Thus, the semiconductor device 10 includes a first element region 31 that can improve short-circuit withstand capability while reducing turn-off losses, and a second element region 32 that can improve ohmic characteristics. The first element region 31 and the second element region 32 are mixed together. Therefore, it is possible to improve short-circuit withstand capability while reducing turn-off losses and ensuring ohmic characteristics.

[0064] As an example, in this embodiment, the first element region 31 and the second element region 32 are arranged alternately. This makes it possible to suppress bias in characteristics within the plane. For example, it is possible to suppress bias at ohmic contact locations.

[0065] <Variation> The arrangement of the first element region 31 and the second element region 32 is not limited to the example described above. For example, the width of the second element region 32 may be set to be greater than or equal to the thickness of the drift layer 14. Specifically, the width of the second element region 32 may be set to 50 μm or more. This further stabilizes the operation of the second element region 32. Note that the width corresponds to the width of the collector layer. The width is the length of the corresponding collector layer and the length in the direction in which the first element region 31 and the second element region 32 are aligned.

[0066] The arrangement of the first element region 31 and the second element region 32 is not limited to an alternating arrangement. The semiconductor substrate 11 only needs to have at least one first element region 31 and at least one second element region 32. In the example shown in Figure 12, the semiconductor substrate 11 has at least one first element region 31 and at least one second element region 32.

[0067] The widths of the first element region 31 and the second element region 32 may be equal or different. For example, as shown in Figure 13, the width of the first element region 31 may be wider than the width of the second element region 32. This can improve the short-circuit withstand capability compared to a configuration where the widths are equal. As shown in Figure 14, the width of the second element region 32 may be wider than the width of the first element region 31. This can improve the ohmic characteristics compared to a configuration where the widths are equal.

[0068] The arrangement of the first element region 31 and the second element region 32 is not limited to a stripe pattern. For example, they may be arranged in a dot pattern.

[0069] (Other embodiments) The disclosures in this specification and drawings are not limited to the exemplary embodiments. The disclosures include the exemplary embodiments and variations thereof by those skilled in the art. For example, the disclosures are not limited to combinations of parts and / or elements shown in the embodiments. The disclosures are implementable in a variety of combinations. The disclosures may have additional parts that can be added to the embodiments. The disclosures include those in which parts and / or elements of the embodiments have been omitted. The disclosures include substitutions or combinations of parts and / or elements between one embodiment and another. The scope of the disclosed technical areas is not limited to the descriptions of the embodiments. Some of the scope of the disclosed technical areas are indicated by the claims and should be understood to include all modifications within the meaning and scope equivalent to the claims.

[0070] The disclosures in the specification and drawings are not limited by the claims. The disclosures in the specification and drawings encompass the technical ideas described in the claims and extend to a wider and more diverse range of technical ideas than those described in the claims. Therefore, a variety of technical ideas can be extracted from the disclosures in the specification and drawings without being bound by the claims.

[0071] When an element or layer is referred to as “on top of,” “connected to,” “connected to,” or “joined,” it may be directly on top of, connected to, connected to, or joined to another element or layer, and there may also be an intervening element or layer. In contrast, when an element is referred to as “directly on top of,” “directly connected to,” “directly connected to,” or “directly joined to” another element or layer, there is no intervening element or layer. Other words used to describe relationships between elements should be interpreted in a similar manner (e.g., “between” vs. “directly between,” “adjacent” vs. “directly adjacent,” etc.). As used in this specification, the term “and / or” includes any combination with respect to one or more of the enumerated items relating to the relationship, and all combinations thereof.

[0072] Spatially relative terms such as "inside," "outside," "back," "below," "low," "above," and "high" are used here to facilitate descriptions of the relationship between one element or feature and other elements or features, as illustrated. Spatially relative terms may be intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. For example, if the device in the drawing is turned upside down, an element described as "below" or "directly below" another element or feature will be oriented "above" the other element or feature. Thus, the term "below" can encompass both up and down orientations. The device may also be oriented in other directions (it may be rotated 90 degrees or in other directions), and the spatially relative descriptors used in this specification will be interpreted accordingly.

[0073] While the IGBT11 was shown as an example of a vertical element, the design is not limited to this. An IGBT with a reverse-parallel connection of a freewheeling diode, i.e., an RC-IGBT, may also be used. RC stands for Reverse Conducting.

[0074] An example of a trench-structured gate electrode 20 has been shown, but the invention is not limited to this. The gate electrode 20 may also be configured to be placed on one surface 11a of the semiconductor substrate 11 via a gate insulating film 19.

[0075] Although the n-conductivity type is designated as the first conductivity type and the p-conductivity type as the second conductivity type, the model is not limited to this arrangement. The p-conductivity type may also be designated as the first conductivity type and the n-conductivity type as the second conductivity type.

[0076] (Disclosure of technical ideas) This specification discloses several technical concepts, as listed in the following paragraphs. Some paragraphs are written in a multiple dependent form, where subsequent paragraphs optionally refer to preceding paragraphs. Furthermore, some paragraphs are written in a multiple dependent form, referring to other multiple dependent forms. These paragraphs written in multiple dependent forms define several technical concepts.

[0077] <Technical philosophy 1> A first conductive drift layer (14) and A second conductive base layer (15) is disposed on the drift layer and provides one surface (11a) of the semiconductor substrate (11), A first conductivity type emitter region (16) formed on the surface layer of the base layer on one side, A gate electrode (20) facing the base layer is located between the drift layer and the emitter region, via a gate insulating film (19), A second conductive collector layer (12) is arranged on the opposite side of the drift layer from the base layer and provides the back surface (11b) of the semiconductor substrate, A first-conductivity type field stop layer (13) is disposed between the collector layer and the drift layer and has a higher carrier concentration than the drift layer, An emitter electrode (21) is arranged on the aforementioned surface and electrically connected to the base layer and the emitter region, A collector electrode (25) is disposed on the back surface and electrically connected to the collector layer, Equipped with, The collector layer has a total dose of 1 × 10 13 / cm 2 It is less than, The aforementioned collector layer has multiple peaks in carrier concentration. A semiconductor device wherein at least a portion of the collector layer is configured such that the dose amount contained within ±3σp of the deepest peak, which is the deepest peak relative to the back surface, accounts for 13% or more of the total dose amount.

[0078] <Technical philosophy 2> The semiconductor device according to Technical Concept 1, wherein the distance from the back surface to the maximum peak where the carrier concentration is maximum in the field stop layer is 0.8 μm or more.

[0079] <Technical philosophy 3> The minimum concentration from the back surface to the deepest peak is 1 × 10 16 / cm 3 The above describes the semiconductor device described in Technical Concept 1 or Technical Concept 2.

[0080] <Technical philosophy 4> The aforementioned semiconductor substrate is The collector layer satisfies the above conditions, and the maximum peak where the carrier concentration is highest in the collector layer is located in a first element region (31) which is biased toward the drift layer side rather than the center of the collector layer, The collector layer does not satisfy the above conditions, and the second element region (32) is located such that the maximum peak is biased toward the collector electrode side rather than the center, A semiconductor device comprising the features described in any one of the technical concepts 1 to 3.

[0081] <Technical philosophy 5> A semiconductor device according to technical concept 4, wherein the first element region and the second element region are arranged alternately. [Explanation of Symbols]

[0082] 10...Semiconductor device, 11...Semiconductor substrate, 11a...One side, 11b...Back side, 12,121,122...Collector layer, 12a,12b...Peak, 12c...Lowest concentration position, 13...FS layer, 14...Drift layer, 15...Base layer, 16...Emitter region, 17...Base contact region, 18...Trench, 19...Gate insulating film, 20...Gate electrode, 21...Emitter electrode, 22...Interlayer insulating film, 23...Pad, 24...Protective film, 241,242...Aperture, 25...Collector electrode, 31...First element region, 32...Second element region

Claims

1. A first conductive drift layer (14), A second conductive base layer (15) is disposed on the drift layer and provides one surface (11a) of the semiconductor substrate (11), A first conductivity type emitter region (16) formed on the surface layer of the base layer on one side, A gate electrode (20) facing the base layer is located between the drift layer and the emitter region, via a gate insulating film (19), A second conductive collector layer (12) is arranged on the opposite side of the drift layer from the base layer and provides the back surface (11b) of the semiconductor substrate, A first conductivity type field stop layer (13) is disposed between the collector layer and the drift layer and has a higher carrier concentration than the drift layer, An emitter electrode (21) is arranged on the aforementioned surface and electrically connected to the base layer and the emitter region, A collector electrode (25) is arranged on the back surface and electrically connected to the collector layer, Equipped with, The collector layer has a total dose of 1 × 10 １３ / cm ２ It is less than, The aforementioned collector layer has multiple peaks in carrier concentration. A semiconductor device wherein at least a portion of the collector layer is configured such that the dose amount contained within ±3σp of the deepest peak, which is the deepest peak relative to the back surface, accounts for 13% or more of the total dose amount.

2. The semiconductor device according to claim 1, wherein the distance from the back surface to the maximum peak where the carrier concentration is maximum in the field stop layer is 0.8 μm or more.

3. The minimum concentration from the back surface to the deepest peak is 1 × 10 １６ / cm ３ The semiconductor device according to claim 1 or claim 2.

4. The aforementioned semiconductor substrate is The collector layer satisfies the above conditions, and the maximum peak where the carrier concentration is highest in the collector layer is located in a first element region (31) which is biased toward the drift layer side rather than the center of the collector layer, The collector layer does not satisfy the above conditions, and the second element region (32) is located such that the maximum peak is biased toward the collector electrode side rather than the center, A semiconductor device according to claim 1, comprising:

5. The semiconductor device according to claim 4, wherein the first element region and the second element region are arranged alternately.

Images