Method for forming SOI substrate
The method addresses high leakage current issues in SOI substrates by using a high-temperature H2 treatment and mixed precursors to form a stopper and semiconductor layer, enhancing surface roughness and reducing defects, thus improving the leakage current characteristics of memory devices.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- SK HYNIX INC
- Filing Date
- 2025-10-24
- Publication Date
- 2026-06-05
AI Technical Summary
The high integration of memory devices, particularly in DRAMs, leads to difficulties in ensuring sufficient capacitance due to reduced unit cell area, and the channel of the SOI substrate in vertical memory cells experiences high leakage current characteristics.
A method for forming an SOI substrate involves a high-temperature H2 heat treatment on a pre-treated sacrificial wafer, followed by forming a stopper layer and semiconductor layer using a mixed precursor of monosilane and dichlorosilane to prevent crystal defects and improve surface roughness, thereby reducing leakage current.
The method effectively reduces crystal defects and leakage current characteristics by improving surface roughness and sharpness of the interface between Si and SiGe layers, eliminating the need for separate polishing processes.
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Figure 2026092666000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for forming a SOI (Silicon on Insulator) substrate, and more particularly to a method for forming a SOI substrate capable of reducing the leakage current of a channel.
Background Art
[0002] A unit cell of a memory device includes at least one transistor and at least one information storage device. For example, a unit cell of a DRAM (Dynamic Random Access Memory) uses a capacitor as the information storage device.
[0003] With the high integration of memory devices, various technical problems have arisen. As an example, in DRAMs, it has become difficult to ensure sufficient capacitance due to the reduction in the area of the unit cell. Thus, vertical memory cells have been proposed.
[0004] When forming a transistor of a vertical memory cell, the application of a SOI substrate is essential. A SOI substrate includes a semiconductor material (e.g., silicon) layer separated from a wafer by an insulating material layer, and during the formation of a cell transistor, the semiconductor material layer of the SOI substrate operates as a channel.
[0005] The channel (i.e., the semiconductor material layer) of the SOI substrate applied to a vertical memory cell is in a floating body state, and thus has a problem of having high leakage current characteristics.
Summary of the Invention
Problems to be Solved by the Invention
[0006] An embodiment of the present invention is to provide a method for forming a SOI substrate including a semiconductor layer with improved leakage current characteristics.
Means for Solving the Problems
[0007] A method for forming an SOI substrate according to an embodiment of the present invention includes the steps of performing a high-temperature H2 heat treatment on a pre-treated sacrificial wafer, and sequentially forming a stopper layer and a semiconductor layer on a first surface of the heat-treated sacrificial wafer. The stopper layer and the semiconductor layer can be formed by epitaxial growth using a mixed precursor consisting of monosilane (MS) and dichlorosilane (DCS), respectively. [Effects of the Invention]
[0008] According to embodiments of the present invention, by performing a pretreatment step of cleaning and drying the sacrificial wafer before forming an epitaxial SiGe / Si layer on the sacrificial wafer, it is possible to prevent the occurrence of crystal defects due to oxide-series impurities in the stopper layer and semiconductor layer formed by the subsequent epitaxial process.
[0009] According to embodiments of the present invention, by performing a high-temperature H2 heat treatment on the sacrificial wafer before forming a stopper layer (SiGe) on the sacrificial wafer, residual oxygen on the surface of the sacrificial wafer can be completely removed, and silicon migration (Si migration) can occur from the surface of the sacrificial wafer from which residual oxygen has been completely removed, thereby improving the surface roughness.
[0010] According to embodiments of the present invention, by mixing a monosilane (MS) precursor and a dichlorosilane (DCS) precursor to form a stopper layer (SiGe) and a semiconductor layer (Si), SiGe / Si grain growth can be prevented during the decomposition of DCS by the chlorine (Cl) etching effect. Furthermore, by improving the surface roughness of SiGe / Si and reducing silicon dangling bonds, crystal defects can be reduced, thereby improving the leakage current characteristics of the memory device. [Brief explanation of the drawing]
[0011] [Figure 1] This is a cross-sectional view showing a process for forming an SOI substrate according to an embodiment of the present invention. [Figure 2] This is a cross-sectional view showing a process for forming an SOI substrate according to an embodiment of the present invention. [Figure 3] This is a cross-sectional view showing a process for forming an SOI substrate according to an embodiment of the present invention. [Figure 4] This is a cross-sectional view showing a process for forming an SOI substrate according to an embodiment of the present invention. [Figure 5] This is a cross-sectional view showing a process for forming an SOI substrate according to an embodiment of the present invention. [Figure 6] This is a cross-sectional view showing a process for forming an SOI substrate according to an embodiment of the present invention. [Figure 7] This is a cross-sectional view showing a process for forming an SOI substrate according to an embodiment of the present invention. [Modes for carrying out the invention]
[0012] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the examples described below in detail, along with the accompanying drawings. However, the present invention is not limited to the examples disclosed below and can be embodied in a variety of different forms. These examples are provided, however, to ensure that the disclosure of the present invention is complete and that a person with ordinary skill in the art to which the invention belongs can accurately recognize the category of the invention, and the present invention is defined only by the category of the claims. In the figures, the size and relative size of layers and areas may be exaggerated for clarity of explanation. Throughout the specification, the same reference numerals refer to the same components.
[0013] Figures 1 to 7 are cross-sectional views showing the process of forming an SOI substrate according to an embodiment of the present invention.
[0014] Referring to Figure 1, a sacrificial wafer 110 and a reference wafer 120 can be provided. For example, the sacrificial wafer 110 and the reference wafer 120 may each contain at least one material selected from Si, Ge, SiC, Group IV-IV, Group III-V, or Group II-VI semiconductor compounds, and piezoelectric materials (e.g., LiNbO3, LiTaO3, etc.).
[0015] In the embodiment, the sacrificial wafer 110 may be in a state where a pretreatment step has been performed. The pretreatment step of the sacrificial wafer 110 may include a cleaning step to remove the native oxide and organic matter from the polished wafer, and a drying step to prevent oxide regrowth.
[0016] In the embodiment, the cleaning process of the sacrificial wafer 110 can be carried out using a DHF (Dilute HF) cleaning method. For example, the cleaning process of the sacrificial wafer 110 can be carried out using a cleaning solution in which hydrogen fluoride (HF) is diluted in ultrapure water (DI water, DIW) at a ratio of 100:1 to 200:1. In addition, in the embodiment, the drying process of the sacrificial wafer 110 can be carried out using N2 gas.
[0017] As mentioned above, by performing a pretreatment process on the sacrificial wafer 110, it is possible to prevent the occurrence of crystal defects due to oxide-series impurities in the stopper layer (see Figure 2) 111 and semiconductor layer (see Figure 2) 112 formed by the subsequent epitaxial process.
[0018] Referring to Figure 2, the stopper layer 111 and the semiconductor layer 112 can be sequentially formed on the first surface (or top surface) of the pre-treated sacrificial wafer 110. In this embodiment, the stopper layer 111 and the semiconductor layer 112 can be formed in situ by epitaxial growth.
[0019] In an embodiment, before forming the stopper layer 111, a high-temperature H2 heat treatment can be performed on the sacrificial wafer 110. In an embodiment, the H2 heat treatment of the sacrificial wafer 110 can be performed at 900°C to 1200°C. By performing the high-temperature H2 heat treatment on the sacrificial wafer 110 in this way, silicon migration (Si Migration) occurs from the surface of the sacrificial wafer 110, and the roughness of the surface of the sacrificial wafer 110 can be improved. In addition, by removing oxide series impurities present on the surface of the sacrificial wafer 110 by H2, crystal defects can be reduced, and the leakage current characteristics of the memory device can be improved.
[0020] The stopper layer 111 can prevent the semiconductor layer 112 from flowing out when the sacrificial wafer 110 is removed in a subsequent process. For this purpose, the stopper layer 111 can be formed using a material having different etching selectivity ratios with respect to the sacrificial wafer 110 and the semiconductor layer 112. In addition, the stopper layer 111 can be formed using a material having a small physical property difference with respect to the semiconductor layer 112. In an embodiment, the stopper layer 111 can be a single-crystalline silicon germanium (SiGe) layer.
[0021] In an embodiment, the stopper layer 111 can be formed by an epitaxial growth method using a precursor in which monosilane and dichlorosilane (DCS) are mixed as source gases and GeH4 as a reaction gas in an environment of 600°C to 800°C. At this time, the partial pressure ratio of monosilane (MS) and dichlorosilane (DCS) can be 3:1.
[0022] During the decomposition of DCS, the chlorine (Cl) etching effect can prevent the growth of SiGe crystal grains (grain growth). By improving the roughness of the surface of SiGe and reducing silicon dangling bonds (Si Dangling bond), crystal defects can be reduced, and the leakage current characteristics of the memory device can be improved.
[0023] For example, when the stopper layer 111, i.e., the SiGe layer, is formed by epitaxial growth, island growth may occur due to compressive stress caused by lattice mismatch between Si and SiGe in the sacrificial wafer 110. Island growth can worsen the surface roughness characteristics of the SiGe, potentially degrading the sharpness characteristics of the interface between Si (e.g., semiconductor layer 112) and SiGe formed on the SiGe in the subsequent epitaxial growth process. Furthermore, island growth can increase silicon dangling bonds, potentially degrading the electrical characteristics of the memory device.
[0024] In this embodiment, by mixing MS(SiH4) and DCS(SiH2Cl2) and using them as a Si source, after the Si epitaxial reaction (for example, Si adsorption onto the sacrificial wafer 110), the protruding portions of Si adsorbed onto the sacrificial wafer 110 are removed by the Cl attached and detached from the DCS. As a result, the occurrence of island-like growth is prevented, improving the surface roughness characteristics of SiGe and the sharpness characteristics of the interface between Si and SiGe, and reducing silicon dangling bonds. By improving the surface roughness characteristics of SiGe and the sharpness characteristics of the interface between Si and SiGe in this way, the surface roughness characteristics of the semiconductor layer 112 can be improved when the stopper layer 111 is removed in the subsequent process, thus eliminating the need for separate CMP (Chemical Mechanical Polishing) and treatment processes for the semiconductor layer 112.
[0025] In the examples, the stopper layer 111 may have a germanium (Ge) concentration of 10% to 30% and a thickness of 300 Å to 1000 Å, but is not limited thereto.
[0026] In the embodiment, once the formation of the stopper layer 111 is complete, a purging process using H2 gas can be performed. By performing the purging process, all gas remaining in the chamber is removed, and at the same time, defects (e.g., Si Dangling Bond) present on the surface of the stopper layer 111 are reduced by hydrogen passivation (H2 passivation).
[0027] Referring again to Figure 2, a semiconductor layer 112 can be formed on the stopper layer 111. For example, the semiconductor layer 112 may be a single-crystal silicon (Si) layer.
[0028] In the example, the semiconductor layer 112 can be formed by an epitaxial growth method using a precursor mixed with monosilane and dichlorosilane in an environment of 600°C to 800°C. At this time, the partial pressure ratio of monosilane and dichlorosilane may be 3:1.
[0029] During the decomposition of DCS, the chlorine (Cl) etching effect can prevent Si grain growth, improving the roughness of Si and reducing silicon dangling bonds, thereby reducing crystal defects and improving the leakage current characteristics of the memory device.
[0030] As mentioned above, in this embodiment, when forming the semiconductor layer 112, by using MS(SiH4) and DCS(SiH2Cl2) together, the portions protruding from the surface of the semiconductor layer 112 can be removed by the Cl deposited and desorbed from the DCS after the Si epitaxial reaction. As a result, the occurrence of island-like growth is prevented, improving the surface roughness characteristics of the semiconductor layer 112 and reducing silicon dangling bonds.
[0031] Referring to Figure 3, a blocking oxide layer 113 and a first bonding insulating layer 114 can be sequentially formed on the semiconductor layer 112.
[0032] In the examples, the blocking oxide layer 113 may include, but is not limited to, a silicon oxide layer (SiO2 layer) or a silicon oxynitride layer (SiON layer).
[0033] Referring again to Figure 3, a first bonding insulating layer 114 can be formed on the blocking oxide layer 113 on the sacrificial wafer 110. A second bonding insulating layer 124 can also be formed on the reference wafer 120. In this embodiment, the formation of the first bonding insulating layer 114 and the second bonding insulating layer 124 can be carried out simultaneously in the same chamber or simultaneously in different chambers, but is not limited to this.
[0034] In the examples, the first and second bonding insulating layers 114 and 124 may include, but are not limited to, silicon carbonitride layers (SiCN layers).
[0035] When the formation of the first and second bonding insulating layers 114 and 124 is completed, the first structure A, which includes a sacrificial wafer 110, a stopper layer 111 sequentially stacked on the sacrificial wafer 110, a semiconductor layer 112, a blocking oxide layer 113, and the first bonding insulating layer 114, and the second structure B, which includes a reference wafer 120 and a second bonding insulating layer 124 formed on the reference wafer 120, can be completed.
[0036] Referring to Figure 4, the first structure A and the second structure B are bonded such that the first bonding insulating layer 114 and the second bonding insulating layer 124 are in contact. In this embodiment, the bonding of the first structure A and the second structure B may include a fusion bonding step between the interfaces of the first bonding insulating layer 114 and the second bonding insulating layer 124, performed at room temperature, and an annealing step to strengthen the bonding force between the interfaces of the first bonding insulating layer 114 and the second bonding insulating layer 124. For example, the annealing step can be performed at 400°C to 650°C using N2 gas.
[0037] As shown in Figure 4, by bonding the first structure A to the second structure B in the reverse direction, the second surface (or bottom surface) of the sacrificial wafer 110 of the first structure A can be exposed.
[0038] Referring to Figure 5, the exposed sacrificial wafer 110 can have a portion of its edge removed by wafer trimming. This is to prevent cracking and chipping during the subsequent polishing process of the sacrificial wafer 110.
[0039] Referring to Figure 6, the polishing process can remove the sacrificial wafer 110 to a predetermined thickness (or height). In this embodiment, the thickness of the remaining sacrificial wafer 110R may be 3 μm, but is not limited to this.
[0040] Referring to Figure 7, the residual sacrificial wafer (see Figure 6) 110R and the stopper layer 111 can be removed sequentially.
[0041] In the embodiment, the residual sacrificial wafer 110R can be removed by a wet cleaning method and a dry cleaning method. For example, the residual sacrificial wafer 110R can be removed by a drying process carried out using an IPA dryer after performing a DHF (Dilute HF) pre-treatment cleaning step and a wet alkali (Diluted NH4OH, TMAH:(CH3)4N(OH), KOH, etc.) post-treatment cleaning step in succession.
[0042] Furthermore, in the examples, the stopper layer 111 can be removed by a wet cleaning method and a dry cleaning method. For example, the stopper layer 111 can be removed by a wet alkaline (Diluted NH4OH, TMAH:(CH3)4N(OH), KOH, etc.) cleaning process and a dry cleaning method using a fluorine compound.
[0043] As described above, by sequentially removing the residual sacrificial wafer 110R and the stopper layer 111, an SOI substrate 100 can be completed which includes a reference wafer 120, a second bonding insulating layer 124 sequentially laminated on the reference wafer 120, a first bonding insulating layer 114, a blocking oxide layer 113, and a semiconductor layer 112.
[0044] Removing the stopper layer 111 exposes the surface of the semiconductor layer 112. A further cleaning process can be performed to improve the surface roughness of the exposed semiconductor layer 112.
[0045] Although the present invention has been described in detail above with reference to preferred embodiments, the present invention is not limited to the above embodiments, and can be modified in various ways by persons with ordinary skill in the art within the scope of the technical idea of the present invention. [Explanation of Symbols]
[0046] 110 Sacrificial wafers 111 Stopper layer 112 Semiconductor layer 113 Blocking Oxide Layer 114 First bonding insulating layer 120 Reference wafers 124 Second bonding insulating layer
Claims
1. High temperature H for pre-treated sacrificial wafer ２ Steps for carrying out heat treatment, The process includes the step of sequentially forming a stopper layer and a semiconductor layer on a first surface of a heat-treated sacrificial wafer. A method for forming an SOI substrate, wherein the stopper layer and the semiconductor layer are formed by an epitaxial growth method using a mixed precursor consisting of monosilane (MS) and dichlorosilane (DCS), respectively.
2. The pretreatment of the sacrificial wafer is as follows: A step of performing a cleaning process to remove the native oxide film and organic matter from the polished wafer, A method for forming an SOI substrate according to claim 1, comprising the step of performing a drying step to prevent the regrowth of the oxide film.
3. The method for forming an SOI substrate according to claim 2, wherein the cleaning step is carried out using a cleaning solution in which hydrogen fluoride (HF) is diluted in ultrapure water at a ratio of 100:1 to 200:
1.
4. The drying process is N ２ A method for forming an SOI substrate according to claim 2, which is carried out using a gas.
5. The method for forming an SOI substrate according to claim 1, wherein the partial pressure ratio of the monosilane and the dichlorosilane constituting the mixed precursor is 3:
1.
6. The stopper layer contains single-crystal silicon germanium (SiGe), The step of forming the stopper layer is performed by GeH ４ A method for forming an SOI substrate according to claim 1, comprising the step of supplying as a reaction gas.
7. The method for forming an SOI substrate according to claim 6, wherein the stopper layer is formed to have a germanium (Ge) concentration of 10% to 30% and a thickness of 300 Å to 1000 Å.
8. Before forming the semiconductor layer on the stopper layer, H ２ A method for forming an SOI substrate according to claim 1, comprising the step of performing a purging process using gas.
9. A method for forming an SOI substrate according to claim 1, further comprising the step of forming the semiconductor layer, and then sequentially forming a blocking oxide layer and a first bonding insulating layer on the semiconductor layer to form a first structure.
10. A method for forming an SOI substrate according to claim 9, further comprising the step of forming a second bonding insulating layer on a reference wafer to form a second structure.
11. A method for forming an SOI substrate according to claim 10, further comprising the step of bonding the first structure and the second structure such that the first bonding insulating layer and the second bonding insulating layer are in contact.
12. The step of bonding the first structure and the second structure is: The steps include performing fusion bonding between the interfaces of a first bonding insulating layer and a second bonding insulating layer at room temperature, A method for forming an SOI substrate according to claim 11, comprising the step of performing annealing to strengthen the bonding force between the interface of a first bonding insulating layer and a second bonding insulating layer.
13. The steps include removing a portion of the edge of the sacrificial wafer of the first structure by wafer trimming, A method for forming an SOI substrate according to claim 11, further comprising the step of forming a residual sacrificial wafer layer having a predetermined thickness on the stopper layer by a polishing step.
14. The steps include removing the residual sacrificial wafer layer by a wet cleaning method to expose the stopper layer, A method for forming an SOI substrate according to claim 13, further comprising the step of removing the exposed stopper layer by a dry cleaning method to expose the semiconductor layer.
15. The method for forming an SOI substrate according to claim 14, further comprising the step of cleaning the surface of the exposed semiconductor layer by a wet cleaning method.