Imaging device

Abstract

The present invention provides an imaging device that can appropriately determine whether or not a pixel is saturated. [Solution] The imaging device includes a pixel that accumulates charge according to the intensity of received light, a lamp voltage generator that generates a lamp voltage, a saturation determination voltage generator that generates a saturation determination voltage from the lamp voltage, and an analog / digital conversion unit that uses the lamp voltage to convert an analog signal indicating the amount of charge into a digital signal, and determines whether the pixel is saturated or not based on a comparison result between the voltage of the analog signal and the saturation determination voltage.

Description

Technical Field

[0001] This disclosure relates to an imaging device.

Background Art

[0002] Patent Document 1 discloses an imaging device. In the imaging device, a pixel outputs the potential of first imaging data. A circuit adds the potential of the output first imaging data to a reference potential to supply a potential signal. The circuit compares the signal potential of the supplied potential signal with the reference potential to determine whether the node of the pixel is saturated. The reference potential is a certain potential corresponding to the saturation of the node of the pixel. When the circuit determines that the node is not saturated, the circuit outputs the result of comparing the signal potential with a ramp wave to a counter circuit. The counter circuit outputs digital data corresponding to the first imaging data (paragraphs 0053, 0057, 0060, 0062, and 0063).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the imaging device disclosed in Patent Document 1, the reference potential used when determining whether the node of the pixel is saturated is a certain potential. Therefore, the reference potential does not change even when the slope of the ramp wave changes. Therefore, when the slope of the ramp wave changes, there is a possibility that it may not be possible to appropriately determine whether the node of the pixel is saturated.

[0005] One aspect of this disclosure has been made in view of this problem. One aspect of this disclosure aims to provide, for example, an imaging device that can appropriately determine whether a pixel is saturated.

Means for Solving the Problems

[0006] An imaging device according to one aspect of this disclosure is: A pixel that accumulates an electric charge corresponding to the intensity of the light it receives, A lamp voltage generator that generates lamp voltage, A saturation determination voltage generator that generates a saturation determination voltage from the aforementioned lamp voltage, An analog / digital conversion unit that uses the lamp voltage to perform analog / digital conversion on an analog signal indicating the amount of charge, and determines whether the pixel is saturated based on a comparison between the voltage of the analog signal and the saturation determination voltage. It is equipped with. [Brief explanation of the drawing]

[0007] [Figure 1] This is a block diagram of the imaging device according to the first embodiment. [Figure 2] This graph shows the waveforms of the pixel signal voltage, ramp voltage, and saturation determination voltage input to the analog / digital conversion unit provided in the imaging device of the first embodiment. [Figure 3] This is a timing chart showing the waveforms of the ramp voltage and saturation determination voltage input to the analog / digital conversion unit provided in the imaging device of the first embodiment. [Figure 4] This is a circuit diagram of a saturation determination voltage generator provided in the imaging device of the first embodiment. [Modes for carrying out the invention]

[0008] The embodiments of this disclosure will be described below with reference to the drawings. In the drawings, the same or equivalent elements are denoted by the same reference numerals, and redundant descriptions are omitted.

[0009] 1. First Embodiment 1.1 Imaging device Figure 1 is a block diagram of the imaging device according to the first embodiment.

[0010] The imaging device 1 of the first embodiment shown in Figure 1 captures an image and outputs an image signal corresponding to the captured image. The imaging device 1 is a solid-state imaging device. This solid-state imaging device is a complementary metal-oxide-semiconductor (CMOS) image sensor. The techniques described below may be employed in imaging devices other than CMOS image sensors.

[0011] As shown in Figure 1, the imaging device 1 comprises a pixel unit 101, a vertical scanning circuit 102, a lamp voltage generator 103, a saturation determination voltage generator 104, an analog / digital conversion unit 105, and a controller 106.

[0012] As shown in Figure 1, the pixel unit 101 comprises m × n pixels 111, m row selection lines 112, and n vertical signal lines 113. m and n are integers of 2 or greater.

[0013] The m × n pixels 111 are arranged in a matrix. Therefore, the m × n pixels 111 constitute an m x n pixel array. Thus, the m × n pixels 111 have m rows 121 and n columns 122. Each row 121 in the m rows 121 contains n pixels 111. Each column 122 in the n columns 122 contains m pixels 111. Each pixel 111 in the m × n pixels 111 is equipped with a photodiode. The photodiode receives light, generates a signal charge corresponding to the intensity of the received light, and stores the generated signal charge. There is an upper limit to the amount of signal charge that a photodiode can store. Each pixel 111 discharges its stored signal charge when a row selection pulse is applied to it.

[0014] Each of the m row selection lines 112 corresponds to each of the m rows 121. Each row selection line 112 included in the m row selection lines 112 is electrically connected to the vertical scanning circuit 102, and each row selection line 112 is electrically connected to the n pixels 111 belonging to the row 121 to which it corresponds. Therefore, each row selection line 112 transmits the row selection pulse 131 output by the vertical scanning circuit 102 from the vertical scanning circuit 102 to the n pixels 111, and provides the transmitted row selection pulse 131 to the n pixels 111.

[0015] Each of the n vertical signal lines 113 corresponds to one of the n columns 122. Each vertical signal line 113 is electrically connected to m pixels 111 belonging to the corresponding column 122, and is electrically connected to the analog / digital conversion unit 105. Therefore, each vertical signal line 113 transmits an analog signal 132, which indicates the amount of signal charge emitted by the m pixels 111, from the pixel 111 to the analog / digital conversion unit 105, and provides the transmitted analog signal 132 to the analog / digital conversion unit 105. The provided analog signal 132 has a voltage corresponding to the intensity of light received by the pixel 111. The voltage of the analog signal 132 decreases as the intensity of light received by the pixel 111 increases. The absolute value of the voltage of the analog signal 132 increases as the intensity of light received by the pixel 111 increases.

[0016] The vertical scanning circuit 102 scans the pixel section 101 in the vertical direction. The vertical scanning circuit 102 selects one row selection line 112 from m row selection lines 112 and transmits a row selection pulse 131 to the selected row selection line 112. The vertical scanning circuit 102 sequentially changes the row selection line 112 to be selected.

[0017] As a result, the pixel unit 101 and the vertical scanning circuit 102 provide the analog-to-digital conversion unit 105 with n analog signals 132 representing the amount of signal charge output by n pixels 111 belonging to one row 121 selected from m rows 121. The pixel unit 101 and the vertical scanning circuit 102 sequentially change the row 121 to be selected. As a result, the pixel unit 101 and the vertical scanning circuit 102 provide the analog-to-digital conversion unit 105 with m × n analog signals representing the amount of signal charge output by m × n pixels 111.

[0018] The lamp voltage generator 103 generates a lamp voltage 133 and outputs the generated lamp voltage 133. The output lamp voltage 133 serves as a reference voltage for analog-to-digital conversion of the analog signal 132 into the digital signal 135.

[0019] The saturation determination voltage generator 104 generates a saturation determination voltage 134 and outputs the generated saturation determination voltage 134. The output saturation determination voltage 134 serves as a reference voltage for determining whether the pixel 111 is saturated.

[0020] The analog-to-digital conversion unit 105 performs analog-to-digital conversion of each analog signal 132 included in the given n analog signals 132 into the digital signal 135 using the output lamp voltage 133 and outputs the digital signal 135. The gradation value represented by the output digital signal 135 increases as the voltage of each analog signal 132 decreases, and increases as the absolute value of the voltage of the analog signal 132 increases.

[0021] Based on the comparison result between each given analog signal 132 and the output saturation determination voltage 134, the analog-to-digital conversion unit 105 determines whether the pixel 111 that output each analog signal 132 is saturated. The fact that the pixel 111 is saturated means that even if the intensity of the light received by the pixel 111 increases, the amount of signal charge accumulated by the pixel 111 does not increase, and even if the intensity of the light received by the pixel 111 increases, the gradation value represented by the digital signal 135 does not increase.

[0022] The grayscale value represented by the digital signal 135 will not increase even if the intensity of light received by the pixel 111 increases when the voltage of the analog signal 132 output by the pixel 111 falls below the lower limit of the voltage range in which analog / digital conversion can be performed, as determined by the lamp voltage 133. For this reason, the lamp voltage 133 must be taken into consideration when determining whether or not the pixel 111 is saturated. However, if the lamp voltage 133 is not taken into consideration and the saturation determination voltage 134 is fixed, and the saturation determination voltage 134 does not change even though the lamp voltage 133 changes, there is a possibility that the pixel 111 may be incorrectly determined to be saturated when it is not actually saturated, and conversely, there is a possibility that the pixel 111 may be incorrectly determined to be not saturated when it is actually saturated. Therefore, in the imaging device 1, the saturation determination voltage generator 104 generates the saturation determination voltage 134 from the lamp voltage 133. The saturation determination voltage generator 104 increases the saturation determination voltage 134 when the lower limit of the voltage range in which analog / digital conversion can be performed increases, and decreases the saturation determination voltage 134 when the lower limit of the voltage range in which analog / digital conversion can be performed decreases.

[0023] The analog signal 132 output by the pixel unit 101 may be processed, and the processed analog signal may be supplied to the analog-to-digital conversion unit 105. The processed analog signal also indicates the amount of signal charge discharged by the pixel 111.

[0024] The controller 106 controls the pixel unit 101, the vertical scanning circuit 102, the ramp voltage generator 103, the saturation determination voltage generator 104, and the analog / digital conversion unit 105 to perform the processes described below. The controller 106 is composed of electronic circuits.

[0025] If pixel 111 is saturated, the gradation value represented by the digital signal 135 will not increase even if the intensity of light received by pixel 111 increases. Therefore, if pixel 111 is saturated, gradation cannot be represented by the digital signal 135. For this reason, if pixel 111 is saturated, measures are taken such as expanding the range of gradation expression using high dynamic range (HDR) technology, changing the conditions for accumulating signal charge so that the gradation value represented by the digital signal 135 falls within the range of gradation expression, or resetting the photodiode provided in pixel 111 and then continuing to accumulate signal charge in the photodiode. If the determination of whether or not pixel 111 is saturated is incorrect, it will be impossible to appropriately determine the necessity and timing of the measures, and gradation cannot be correctly represented. Therefore, it is desirable to suppress such incorrect determination. If a saturation determination voltage 134 is generated from the lamp voltage 133 and the saturation determination voltage 134 follows the lamp voltage 133, such incorrect determination can be suppressed, and it will be possible to appropriately determine whether or not pixel 111 is saturated.

[0026] 1.2 Analog / Digital Conversion Section As shown in Figure 1, the analog-to-digital conversion unit 105 includes a ramp voltage transmission line 141, a saturation determination voltage transmission line 142, n switching circuits 143, n comparators 144, n latch counters 145, and a scanning / transfer circuit 146. Each of the n switching circuits 143 includes a first input terminal 143a, a second input terminal 143b, and an output terminal 143c. Each of the n comparators 144 includes a non-inverting input terminal 144a, an inverting input terminal 144b, and an output terminal 144c.

[0027] The lamp voltage transmission line 141 is electrically connected to the lamp voltage generator 103 and electrically connected to the first input terminal 143a of the n switching circuits 143. Therefore, the lamp voltage transmission line 141 transmits the lamp voltage 133 output by the lamp voltage generator 103 from the lamp voltage generator 103 to the first input terminal 143a of the n switching circuits 143, and inputs the transmitted lamp voltage 133 to the first input terminal 143a of the n switching circuits 143.

[0028] The saturation determination voltage transmission line 142 is electrically connected to the saturation determination voltage generator 104 and electrically connected to the second input terminal 143b of the n switching circuits 143. Therefore, the saturation determination voltage transmission line 142 transmits the saturation determination voltage 134 output by the saturation determination voltage generator 104 from the saturation determination voltage generator 104 to the second input terminal 143b of the n switching circuits 143, and inputs the transmitted saturation determination voltage 134 to the second input terminal 143b of the n switching circuits 143.

[0029] Each switching circuit 143 switches the destination to which the output terminal 143c of each switching circuit 143 is electrically connected between the first input terminal 143a and the second input terminal 143b of each switching circuit 143. As a result, each switching circuit 143 switches the voltage output from the output terminal 143c of each switching circuit 143 between the ramp voltage 133 and the saturation determination voltage 134.

[0030] Each of the n comparators 144 corresponds to one of the n vertical signal lines 113, and each corresponds to one of the n switching circuits 143. The non-inverting input terminal 144a of each comparator 144 is electrically connected to the vertical signal line 113 corresponding to that comparator 144. As a result, the analog signal 132 provided by the vertical signal line 113 corresponding to that comparator 144 is input to the non-inverting input terminal 144a of each comparator 144. The inverting input terminal 144b of each comparator 144 is electrically connected to the output terminal 143c of the switching circuit 143 corresponding to that comparator 144. As a result, the ramp voltage 133 or saturation determination voltage 134 output from the output terminal 143c of the switching circuit 143 is input to the inverting input terminal 144b of each comparator 144.

[0031] Each comparator 144 sets the voltage output from its output terminal 144c to a voltage corresponding to the comparison result between the voltage input to its non-inverting input terminal 144a and the voltage input to its inverting input terminal 144b. For example, if the voltage input to its non-inverting input terminal 144a is higher than the voltage input to its inverting input terminal 144b, each comparator 144 sets the voltage output from its output terminal 144c to the relatively higher voltage VH. If the voltage input to its non-inverting input terminal 144a is lower than the voltage input to its inverting input terminal 144b, each comparator 144 sets the voltage output from its output terminal 144c to the relatively lower voltage VL. Therefore, when a ramp voltage 133 is input to the inverting input terminal 144b of each comparator 144, the voltage output from the output terminal 144c of each comparator 144 will be a voltage corresponding to the comparison result between the voltage of the analog signal 132 transmitted by the corresponding vertical signal line 113 of each comparator 144 and the input ramp voltage 133. When a saturation determination voltage 134 is input to the inverting input terminal 144b of each comparator 144, the voltage output from the output terminal 144c of each comparator 144 will be a voltage corresponding to the comparison result between the voltage of the analog signal 132 transmitted by the corresponding vertical signal line 113 of each comparator 144 and the input saturation determination voltage 134.

[0032] Each of the n latch counters 145 corresponds to each of the n comparators 144. Each latch counter 145 is electrically connected to the output terminal 144c of the comparator 144 to which it corresponds. As a result, each latch counter 145 receives the voltage output from the output terminal 144c of the comparator 144 to which it corresponds.

[0033] Each latch counter 145 counts the number of clocks, latches the counted number of clocks at the timing when the comparison result indicated by the input voltage changes, and outputs a digital signal 135 corresponding to the number of latched clocks. For example, each latch counter 145 latches the counted number of clocks at the timing when the input voltage changes from a relatively high voltage VH to a relatively low voltage VL, and outputs a digital signal 135 representing a grayscale value corresponding to the number of latched clocks. The number of latched clocks corresponds to the voltage of the analog signal 132 input to the non-inverting input terminal 144a of the comparator 144 corresponding to each latch counter 145. Therefore, the grayscale value represented by the output digital signal 135 is the grayscale value corresponding to the voltage of the analog signal 132 input to the non-inverting input terminal 144a of the comparator 144 corresponding to each latch counter 145. As a result, the n latch counters 145 each output n digital signals 135 corresponding to the voltages of the n analog signals 132 input to the non-inverting input terminals 144a of the n comparators 144.

[0034] The scanning and transfer circuit 146 is electrically connected to n latch counters 145. As a result, the scanning and transfer circuit 146 receives n digital signals 135 output from the n latch counters 145. The scanning and transfer circuit 146 scans the n latch counters 145. The scanning and transfer circuit 146 selects one latch counter 145 from the n latch counters 145 and transfers the digital signal 135 output by the selected latch counter 145. The scanning and transfer circuit 146 sequentially changes the selected latch counter 145. The transferred digital signals 135 constitute an image signal.

[0035] 1.3 Waveforms of Pixel Signal Voltage, Ramp Voltage, and Saturation Judgment Voltage Figure 2 is a graph showing the waveforms of the pixel signal voltage, ramp voltage, and saturation determination voltage input to the analog-to-digital conversion unit of the imaging device of the first embodiment. In the graph of Figure 2, time is plotted on the horizontal axis and voltage is plotted on the vertical axis.

[0036] During a single-row readout operation period 151, the imaging device 1 reads out n analog signals 132 from n pixels 111 belonging to one row 121 selected from m rows 121, converts the readout n analog signals 132 into n digital signals 135, and outputs the n digital signals 135.

[0037] As shown in Figure 2, the single-line read operation period 151 includes a reset period 161, a saturation determination period 162, an analog-to-digital conversion period 163, a sampling period 164, and a signal processing period 165.

[0038] (Reset period) During the reset period 161, the vertical scanning circuit 102 resets a pixel 111 belonging to one of the m rows 121 selected from the m rows 121. The reset pixel 111 discharges noise charge and then signal charge. As a result, the voltage 181 of the pixel signal output by the pixel 111 decreases to a voltage VN corresponding to the amount of noise charge discharged, and then decreases to a voltage VS corresponding to the amount of signal charge discharged. Therefore, the pixel signal includes an analog signal 132 having a voltage VS corresponding to the amount of signal charge discharged.

[0039] During the reset period 161, the lamp voltage generator 103 maintains the lamp voltage 133.

[0040] During the reset period 161, the saturation determination voltage generator 104 holds the constant voltage 192 sampled during the sampling period 164 included in the previous row read operation period 151, and generates a saturation determination voltage 134 corresponding to the held constant voltage 192.

[0041] (Saturation judgment period) During the saturation determination period 162 following the reset period 161, the switching circuit 143 sets the output terminal 143c of the switching circuit 143 to the second input terminal 143b of each switching circuit 143. As a result, the saturation determination voltage 134 is input to the inverting input terminal 144b of each comparator 144. If the pixel signal is a non-saturated signal and the voltage VS of the analog signal 132 is higher than the saturation determination voltage 134, as shown by the solid line, the voltage output from the output terminal 144c of each comparator 144 is set to the relatively higher voltage VH. If the pixel signal is a saturated signal and the voltage VS of the analog signal is lower than the saturation determination voltage 134, as shown by the dashed line, the voltage output from the output terminal 144c of each comparator 144 is set to the relatively lower voltage VL.

[0042] During the saturation determination period 162, the lamp voltage generator 103 sets the lamp voltage 133 as the starting voltage V1.

[0043] During the saturation determination period 162, the saturation determination voltage generator 104 holds the constant voltage 192 sampled during the sampling period 164 included in the previous row read operation period 151, and generates a saturation determination voltage 134 corresponding to the held constant voltage 192.

[0044] (Analog / Digital Conversion Period) In the analog / digital conversion period 163 following the saturation determination period 162, the switching circuit 143 sets the first input terminal 143a of each switching circuit 143 to which the output terminal 143c of the switching circuit 143 is electrically connected. As a result, the ramp voltage 133 is input to the inverting input terminal 144b of each comparator 144. If the voltage 182 of the analog signal 132 is higher than the ramp voltage 133, each comparator 144 sets the voltage output from its output terminal 144c to the relatively higher voltage VH, and if the voltage of the analog signal 132 is lower than the ramp voltage 133, the voltage output from its output terminal 144c to the relatively higher voltage VL.

[0045] During the analog-to-digital conversion period 163, the ramp voltage generator 103 lowers the ramp voltage 133 from the starting voltage V1 to the ending voltage V2 at a constant rate of change over time. Therefore, the ramp voltage 133 includes a slope voltage 191 that has a constant rate of change over time. The starting voltage V1 is higher than the voltage VN corresponding to the amount of noise charge discharged. The ending voltage V2 is lower than the saturation determination voltage 134. Therefore, as shown by the solid line, if the pixel signal is a non-saturated signal, the high and low of the slope voltage 191 and the voltage 182 of the analog signal 132 are reversed during the analog-to-digital conversion period 163. However, as shown by the dashed line, if the pixel signal is a saturated signal, the high and low of the slope voltage 191 and the voltage 182 of the analog signal 132 may not be reversed during the analog-to-digital conversion period 163.

[0046] During the analog / digital conversion period 163, the latch counter 145 begins counting the number of clocks in synchronization with the start of lowering the ramp voltage 133 from the start voltage V1 to the end voltage V2. The latch counter latches the number of clocks in synchronization with the inversion of the high and low of the slope voltage 191 and the voltage 182 of the analog signal 132, causing the voltage output from the output terminal 144c of each comparator 144 to change from a relatively high voltage VH to a relatively low voltage VL, and outputs a digital signal 135 corresponding to the number of latched clocks. In this way, when the analog signal 132 is converted from analog to digital to digital to digital based on the timing TM of the inversion of the high and low of the slope voltage 191 and the voltage 182 of the analog signal 132, the larger the absolute value of the rate of change of the voltage value of the slope voltage 191 over time, the lower the end voltage V2 becomes, and the lower limit of the voltage range R in which analog / digital conversion can be performed becomes.

[0047] During the analog / digital conversion period 163, the saturation determination voltage generator 104 holds the constant voltage 192 sampled during the sampling period 164 included in the previous row read operation period 151, and generates a saturation determination voltage 134 corresponding to the held constant voltage 192.

[0048] If the saturation determination voltage 134 is changed in accordance with the change in the rate of change of the voltage value of the slope voltage 191, it is possible to suppress the misdetermination of whether or not the pixel 111 is saturated, due to the fact that the lower limit of the voltage range R in which analog / digital conversion can be performed becomes lower as the absolute value of the rate of change of the voltage value of the slope voltage 191 becomes larger.

[0049] (Sampling period) In the sampling period 164 following the analog / digital conversion period 163, the ramp voltage generator 103 sets the ramp voltage 133 to a constant voltage 192 having a constant voltage value. Therefore, the ramp voltage 133 includes the constant voltage 192 having a constant voltage value. The constant voltage value of the constant voltage 192 is the same as the voltage value of the termination voltage V2. The ramp voltage generator 103 generates the constant voltage 192 following the slope voltage 191. As mentioned above, the termination voltage V2 decreases as the absolute value of the rate of change of the voltage value of the slope voltage 191 over time increases. Therefore, the constant voltage 192, which has the same constant voltage value as the voltage value of the termination voltage V2, decreases as the absolute value of the rate of change of the voltage value of the slope voltage 191 over time increases.

[0050] During the sampling period 164, the saturation determination voltage generator 104 samples the constant voltage 192 and generates a saturation determination voltage 134 from the sampled constant voltage 192. The generated saturation determination voltage 134 is a voltage corresponding to the sampled constant voltage 192. For example, the saturation determination voltage 134 is generated by amplifying or shifting the sampled constant voltage 192. As mentioned above, the constant voltage 192 that forms the basis for generating the saturation determination voltage 134 becomes lower as the absolute value of the rate of change of the voltage value of the slope voltage 191 over time increases. Therefore, the saturation determination voltage 134 becomes lower as the absolute value of the rate of change of the voltage value of the slope voltage 191 over time increases.

[0051] (Signal processing period) In the signal processing period 165 following the sampling period 164, the scanning and transfer circuit 146 selects one latch counter 145 from n latch counters 145 and transfers the digital signal output by the selected latch counter 145. The scanning and transfer circuit 146 sequentially changes the latch counter 145 that it selects.

[0052] During the signal processing period 165, the lamp voltage generator 103 increases the lamp voltage 133 and then maintains the lamp voltage 133.

[0053] During the signal processing period 165, the saturation determination voltage generator 104 holds the constant voltage 192 sampled during the sampling period 164 and generates a saturation determination voltage 134 corresponding to the held constant voltage 192.

[0054] 1.4 Relationship between ramp voltage and saturation detection voltage Figure 3 is a timing chart showing the waveforms of the ramp voltage and saturation determination voltage input to the analog-to-digital conversion unit provided in the imaging device of the first embodiment. In the timing chart of Figure 3, time is represented on the horizontal axis and voltage on the vertical axis.

[0055] The rate of change of the voltage value of the slope voltage 191 changes. Therefore, as shown in Figure 3, the slope voltage 191 can be a first slope voltage 211 having a first rate of change of voltage value, a second slope voltage 212 having a second rate of change of voltage value that is more abrupt than the first rate of change of voltage value, a third slope voltage 213 having a third rate of change of voltage value that is more abrupt than the second rate of change of voltage value, and so on. Therefore, the constant voltage 192 that is generated and sampled following the slope voltage 191 can be a first constant voltage 221, a second constant voltage 222 that is lower than the first constant voltage 221, a third constant voltage 223 that is lower than the second constant voltage 222, and so on. The saturation determination voltage generator 104 sets the saturation determination voltage 134 to the first saturation determination voltage 231, the second saturation determination voltage 232 which is lower than the first saturation determination voltage 231, the third saturation determination voltage 233 which is lower than the second saturation determination voltage 232, etc., when the constant voltage 192 becomes the first constant voltage 221, the second constant voltage 222, the third constant voltage 223, etc., so that it can be appropriately determined whether or not the pixel 111 is saturated even when the slope voltage 191 becomes the first slope voltage 211, the second slope voltage 212, the third slope voltage 213, etc.

[0056] 1.5 Waveforms of Analog Signals, Ramp Voltage, and Saturation Judgment Voltage Figure 4 is a circuit diagram of a saturation determination voltage generator provided in the imaging device of the first embodiment.

[0057] The saturation determination voltage generator 104 shown in Figure 4 samples the input constant voltage 192, holds the sampled constant voltage 192, shifts the held constant voltage 192 to generate a saturation determination voltage 134, and outputs the generated saturation determination voltage 134.

[0058] The saturation determination voltage generator 104 includes an input terminal 241, a switch 242, a capacitor 243, an operational amplifier 244, a voltage source 245, and an output terminal 246. The switch 242 has one terminal 242a and the other terminal 242b. The capacitor 243 has one terminal 243a and the other terminal 243b. The operational amplifier 244 has a non-inverting input terminal 244a, an inverting input terminal 244b, and an output terminal 244c. The voltage source 245 has a positive electrode 245a and a negative electrode 245b.

[0059] Input terminal 241 is electrically connected to the lamp voltage generator 103. One terminal 242a of switch 242 is electrically connected to input terminal 241. One terminal 243a of capacitor 243 and the non-inverting input terminal 244a of operational amplifier 244 are electrically connected to the other terminal 242b of switch 242. The other terminal 243b of capacitor 243 is grounded.

[0060] Switch 242 is closed during the sampling period 164 shown in Figure 2 and opened during the hold period 171 shown in Figure 2. The hold period 171 is the period other than the sampling period 164. As a result, during the sampling period 164, the other terminal 242b of switch 242 conducts to the other terminal 242a of switch 242, and a constant voltage 192 is applied to one terminal 243a of capacitor 243 via the input terminal 241 and switch 242, and a charge having an amount corresponding to the constant voltage 192 is accumulated in capacitor 243.

[0061] During the hold period 171, the other terminal 242b of the switch 242 does not conduct to the other terminal 242a of the switch 242. A voltage corresponding to the amount of charge stored in the capacitor 243 is generated at one terminal 243a of the capacitor 243, and this generated voltage is input to the non-inverting input terminal 244a of the operational amplifier 244. The voltage generated at one terminal 243a of the capacitor 243 and input to the non-inverting input terminal 244a of the operational amplifier 244 matches the constant voltage 192.

[0062] The negative terminal 245b of the voltage source 245 is electrically connected to the inverting input terminal 244b of the operational amplifier 244. The positive terminal 245a of the voltage source 245 is electrically connected to the output terminal 244c of the operational amplifier 244. The output terminal 246 is electrically connected to the output terminal 244c of the operational amplifier 244 and the positive terminal 245a of the voltage source 245. As a result, the voltage output from the output terminal 244c of the operational amplifier 244 is the sum of the constant voltage 192 input to the non-inverting input terminal 244a of the operational amplifier 244 and the voltage generated by the voltage source 245, i.e., the voltage obtained by shifting the constant voltage 192 input to the non-inverting input terminal 244a of the operational amplifier 244. Consequently, the voltage obtained by shifting the constant voltage 192 is output from the output terminal 246.

[0063] This disclosure is not limited to the embodiments described above, and may be replaced with configurations that are substantially the same as those shown in the embodiments, configurations that produce the same effects, or configurations that can achieve the same purpose. [Explanation of symbols]

[0064] 1. Imaging device 101 pixel section 102 Vertical scanning circuit 103 Lamp Voltage Generator 104 Saturation detection voltage generator 105 Analog / Digital Conversion Section 106 Controllers 111 pixels 112 row selection lines 113 Vertical signal line 121 lines 122 columns 131 row selection pulse 132 Analog signals 133 Lamp voltage 134 Saturation detection voltage 135 Digital signals 141 Lamp voltage transmission line 142 Saturation determination voltage transmission line 143 Switching Circuit 143a First input terminal 143b Second input terminal 143c output terminal 144 Comparator 144a Non-inverting input terminal 144b Inverting input terminal 144c output terminal 145 Latch Counter 146 Scanning and Transfer Circuits 151 Line read operation period 161 Reset period 162 Saturation judgment period 163 Analog / Digital Conversion Period 164 sampling period 165 Signal Processing Period 171 Holding period 181 Pixel signal voltage 182 Analog signal voltage 191 Slope Voltage 192 Constant Voltage 201 Unsaturated signal 202 Saturation signal 211 First slope voltage 212 Second slope voltage 213 Third slope voltage 221 First constant voltage 222 Second constant voltage 223 Third constant voltage 231 First saturation determination voltage 232 Second saturation determination voltage 233 Third saturation determination voltage 241 Input terminals 242 switches 242a One terminal 242b Other terminal 243 Capacitors 243a One terminal 243b The other terminal 244 operational amplifier 244a Non-inverting input terminal 244b Inverting input terminal 244c output terminal 245 Voltage Source 245a positive electrode 245b negative electrode 246 output terminals

Claims

1. A pixel that accumulates an electric charge corresponding to the intensity of the light it receives, A lamp voltage generator that generates lamp voltage, A saturation determination voltage generator that generates a saturation determination voltage from the aforementioned lamp voltage, An analog / digital conversion unit that uses the lamp voltage to perform analog / digital conversion on an analog signal indicating the amount of charge, and determines whether the pixel is saturated based on a comparison between the voltage of the analog signal and the saturation determination voltage. An imaging device equipped with the following features.

2. The aforementioned ramp voltage includes a slope voltage having a constant rate of change over time and a constant voltage having a constant voltage value. The ramp voltage generator generates the constant voltage following the slope voltage, Converting the analog signal to the digital signal using the ramp voltage includes converting the analog signal to the digital signal based on the timing at which the slope voltage and the voltage of the analog signal are reversed. Generating the saturation determination voltage from the ramp voltage includes generating the saturation determination voltage from the constant voltage. The imaging apparatus according to claim 1.

3. Generating the saturation determination voltage from the constant voltage includes generating the saturation determination voltage by amplifying or shifting the constant voltage. The imaging apparatus according to claim 2.

4. The aforementioned ramp voltage includes a slope voltage having a constant voltage value and time rate of change. Converting the analog signal to the digital signal using the ramp voltage includes converting the analog signal to the digital signal based on the timing at which the slope voltage and the voltage of the analog signal are reversed. Generating the saturation determination voltage from the ramp voltage includes changing the saturation determination voltage in accordance with the change in the rate of change of the voltage value of the slope voltage over time. The imaging apparatus according to any one of claims 1 to 3.

Images