Imaging device and camera system

Abstract

To provide an imaging device, etc., that can improve the conversion gain. [Solution] The imaging device comprises a semiconductor substrate 60A, a photoelectric conversion unit 12 located on the first surface s1 side of the semiconductor substrate 60A and converting light into signal charge, a through electrode 81 that penetrates the semiconductor substrate 60A and is electrically connected to the photoelectric conversion unit 12, an amplifying transistor 22 located on the second surface s2 of the semiconductor substrate 60A and including a gate 22e that is electrically connected to the through electrode 81 and outputs a signal corresponding to the signal charge, and an insulating layer 82 that covers the through electrode 81. The semiconductor substrate 60A includes an n-type impurity region 71n to which the signal output by the amplifying transistor 22 is input, and an n-type impurity region 80n that covers the through electrode 81 via the insulating layer 82. The n-type impurity region 71n is electrically connected to the n-type impurity region 80n within the semiconductor substrate 60A.

Description

Technical Field

[0001] The present disclosure relates to an imaging device and a camera system.

Background Art

[0002] In digital cameras and the like, imaging devices such as CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors are widely used.

[0003] Also, an imaging device is known in which a through electrode penetrating a semiconductor substrate electrically connects a photoelectric conversion unit and a detection circuit for detecting signal charges converted by the photoelectric conversion unit (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The parasitic capacitance of a conductor electrically connected to a detection circuit for detecting signal charges converted by a photoelectric conversion unit functions as a capacitance for accumulating signal charges. Therefore, when the photoelectric conversion unit and the detection circuit are electrically connected by a conductor, if the parasitic capacitance of the conductor increases, it becomes difficult for a potential change due to signal charges to occur, and the conversion gain decreases. For example, when a long conductor such as the above through electrode is connected to a detection circuit, the parasitic capacitance of the through electrode tends to be large, leading to a decrease in the conversion gain.

[0006] Therefore, the present disclosure provides an imaging device and the like capable of improving the conversion gain.

Means for Solving the Problems

[0007] An imaging device according to one aspect of the present disclosure comprises a semiconductor substrate having a first surface and a second surface opposite to the first surface; a photoelectric conversion unit located on the first surface side of the semiconductor substrate and converting light into a signal charge; a through electrode penetrating the semiconductor substrate and electrically connected to the photoelectric conversion unit; a first transistor located on the first or second surface of the semiconductor substrate and including a gate electrically connected to the through electrode, which outputs a signal corresponding to the signal charge; and an insulating layer covering the through electrode within the semiconductor substrate, wherein the semiconductor substrate includes a first impurity region to which the signal output by the first transistor is input, and a second impurity region having the same conductivity type as the first impurity region and covering the through electrode via the insulating layer, and the first impurity region is electrically connected to the second impurity region within the semiconductor substrate.

[0008] An imaging apparatus according to one aspect of the present disclosure comprises a semiconductor substrate, a wiring layer laminated on the semiconductor substrate and including a plurality of wirings, a photoelectric conversion unit that converts light into signal charges, a charge storage region for storing the signal charges, and a first transistor that includes a gate electrically connected to the charge storage region and outputs a signal corresponding to the signal charges, wherein the semiconductor substrate includes a first impurity region to which the signal output by the first transistor is input, and the plurality of wirings include a first wiring electrically connected to the gate of the first transistor and a second wiring electrically connected to the first impurity region, the second wiring being adjacent to the first wiring via an insulator.

[0009] A camera system relating to one aspect of this disclosure includes the above-mentioned imaging device. [Effects of the Invention]

[0010] According to this disclosure, it is possible to provide an imaging device, etc., that can improve the conversion gain. [Brief explanation of the drawing]

[0011] [Figure 1]Figure 1 is a diagram showing the configuration of the imaging device according to Embodiment 1. [Figure 2] Figure 2 is a diagram showing the circuit configuration of a pixel according to Embodiment 1. [Figure 3] Figure 3 is a plan view showing an example of the layout within a pixel according to Embodiment 1. [Figure 4] Figure 4 is a schematic cross-sectional view of the pixel device structure according to Embodiment 1. [Figure 5] Figure 5 is a plan view showing an example of a pixel layout according to a modified example 1 of Embodiment 1. [Figure 6] Figure 6 is a schematic cross-sectional view of the device structure of a pixel according to a modified example 1 of Embodiment 1. [Figure 7] Figure 7 is a plan view showing an example of the layout within a pixel according to a modified example 2 of Embodiment 1. [Figure 8] Figure 8 shows the circuit configuration of a pixel according to a modified example 3 of Embodiment 1. [Figure 9] Figure 9 is a plan view showing an example of the layout within a pixel according to a modified example 3 of Embodiment 1. [Figure 10] Figure 10 is a diagram showing the circuit configuration of a pixel according to a modified example 4 of Embodiment 1. [Figure 11] Figure 11 is a plan view showing an example of a pixel layout according to a modified example 4 of Embodiment 1. [Figure 12] Figure 12 is a schematic cross-sectional view of the pixel device structure according to a modified example 4 of Embodiment 1. [Figure 13] Figure 13 is a plan view showing an example of a pixel layout according to a modified example 5 of Embodiment 1. [Figure 14] Figure 14 is another plan view showing an example of a pixel layout according to a modified example 5 of Embodiment 1. [Figure 15] Figure 15 is a schematic cross-sectional view of the pixel device structure according to Modification 5 of Embodiment 1. [Figure 16] Figure 16 is a schematic cross-sectional view of the pixel device structure according to a modified example 6 of Embodiment 1. [Figure 17]FIG. 17 is a plan view showing an example of the wiring layout within a pixel according to Embodiment 2. [Figure 18] FIG. 18 is a schematic cross-sectional view of the device structure of a pixel according to Embodiment 2. [Figure 19] FIG. 19 is a plan view showing another example of the wiring layout within a pixel according to Embodiment 2. [Figure 20] FIG. 20 is a plan view showing yet another example of the wiring layout within a pixel according to Embodiment 2. [Figure 21] FIG. 21 is a block diagram showing an example of the configuration of a camera system according to Embodiment 3.

Embodiments for Carrying Out the Invention

[0012] (Summary of the Present Disclosure) As an overview of one aspect of the present disclosure, examples of an imaging device and a camera system according to the present disclosure are shown below.

[0013] For example, an imaging device according to a first aspect of the present disclosure includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a photoelectric conversion unit located on the first surface side of the semiconductor substrate that converts light into signal charges, a through electrode that penetrates the semiconductor substrate and is electrically connected to the photoelectric conversion unit, a first transistor located on the first surface or the second surface of the semiconductor substrate, including a gate electrically connected to the through electrode, and outputting a signal corresponding to the signal charges, and an insulating layer covering the through electrode within the semiconductor substrate. The semiconductor substrate includes a first impurity region into which the signal output by the first transistor is input, and a second impurity region of the same conductivity type as the first impurity region that covers the through electrode via the insulating layer. The first impurity region is electrically connected to the second impurity region within the semiconductor substrate.

[0014] As a result, the first impurity region and the second impurity region, to which the signal output by the first transistor is input, are electrically connected. Therefore, the potential of the second impurity region changes in synchronization with the potential of the through-electrode electrically connected to the gate of the first transistor. Consequently, even if signal charges are generated, the potential difference between the second impurity region and the through-electrode does not increase significantly, reducing the capacitance of the node where signal charges are accumulated, and improving the conversion gain in the imaging device. Furthermore, since the first and second impurity regions are electrically connected within the semiconductor substrate, they are connected without the need for wiring or contact plugs outside the semiconductor substrate. This reduces parasitic resistance in the electrical connection between the first and second impurity regions. It also enables miniaturization of the imaging device.

[0015] Furthermore, for example, an imaging apparatus according to a second aspect of this disclosure is an imaging apparatus according to a first aspect, wherein the first impurity region functions as the source or drain of the first transistor.

[0016] As a result, the first impurity region, to which the signal output by the first transistor is directly input, and the second impurity region are electrically connected, so that even if a signal charge is generated, the potential difference between the second impurity region and the through-electrode can be made smaller.

[0017] Furthermore, for example, an imaging apparatus according to a third aspect of the present disclosure is an imaging apparatus according to a first aspect, further comprising a second transistor connected in series with the first transistor, wherein the first impurity region functions as the source or drain of the second transistor.

[0018] This allows the source or drain of the second transistor, which is connected in series with the first transistor, to be used for electrical connection with the second impurity region, thereby increasing the flexibility of the layout.

[0019] Furthermore, for example, the imaging apparatus according to the fourth aspect of this disclosure is an imaging apparatus according to any one of the first to third aspects, wherein the first transistor is located on the second surface of the semiconductor substrate.

[0020] As a result, the first transistor is not placed between the semiconductor substrate and the photoelectric conversion unit, and the distance between the semiconductor substrate and the photoelectric conversion unit can be shortened.

[0021] Furthermore, for example, an imaging apparatus according to a fifth aspect of the present disclosure is an imaging apparatus according to any one of the first to fourth aspects, wherein the semiconductor substrate includes a third impurity region having the same conductivity type as the first impurity region, which electrically connects the first impurity region and the second impurity region.

[0022] This allows the first and second impurity regions to be electrically connected via the third impurity region, thereby increasing the flexibility of the layout.

[0023] Furthermore, for example, the imaging apparatus according to the sixth aspect of this disclosure is an imaging apparatus according to any one of the first to fourth aspects, wherein at least a portion of the second impurity region overlaps with the first impurity region in a plan view.

[0024] This allows the first and second impurity regions to overlap, enabling a miniaturization of the imaging device.

[0025] Furthermore, for example, an imaging apparatus according to the seventh aspect of the present disclosure is an imaging apparatus according to any one of the first to sixth aspects, further comprising a wiring layer laminated on the first or second surface of the semiconductor substrate and including a plurality of wirings, wherein the plurality of wirings include a first wiring electrically connected to the through electrode and a second wiring electrically connected to the first impurity region, and the second wiring is adjacent to the through electrode or the first wiring via an insulator.

[0026] As a result, the first impurity region and the second wiring are electrically connected, so the potential of the through-electrode or the second wiring adjacent to the first wiring changes in synchronization with the potential of the through-electrode and the first wiring. Therefore, the capacitance of the node where the signal charge connected to the gate of the first transistor is accumulated can be reduced.

[0027] Furthermore, for example, an imaging device according to the eighth aspect of the present disclosure is an imaging device according to any one of the first to seventh aspects, wherein the semiconductor substrate includes a charge storage region located on the second surface for accumulating the signal charge.

[0028] As a result, the charge storage region is located on the second side of the semiconductor substrate, opposite to the first side of the semiconductor substrate where the photoelectric conversion unit is placed. This suppresses the generation of noise caused by light incident on the charge storage region.

[0029] Furthermore, for example, an imaging apparatus according to a ninth aspect of the present disclosure comprises a semiconductor substrate, a wiring layer laminated on the semiconductor substrate and including a plurality of wirings, a photoelectric conversion unit that converts light into signal charges, a charge storage region for storing the signal charges, and a first transistor that includes a gate electrically connected to the charge storage region and outputs a signal corresponding to the signal charges, wherein the semiconductor substrate includes a first impurity region to which the signal output by the first transistor is input, and the plurality of wirings include a first wiring electrically connected to the gate of the first transistor and a second wiring electrically connected to the first impurity region, the second wiring being adjacent to the first wiring via an insulator.

[0030] As a result, the first impurity region to which the signal output by the first transistor is input is electrically connected to the second wiring. Therefore, the potential of the second wiring adjacent to the first wiring electrically connected to the gate of the first transistor changes in synchronization with the potential of the first wiring. Consequently, even if signal charges are generated, the potential difference between the first and second wiring does not increase, reducing the capacitance of the node where signal charges connected to the gate of the first transistor are accumulated, and improving the conversion gain in the imaging device.

[0031] Furthermore, for example, a camera system according to the tenth aspect of this disclosure comprises an imaging device according to any one of the first to ninth aspects.

[0032] As a result, the camera system according to this embodiment, equipped with the above-mentioned imaging device, can improve the conversion gain.

[0033] Embodiments of this disclosure will be described in detail below with reference to the drawings. The embodiments described below are either comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure. The various embodiments described herein can be combined with each other as long as they do not conflict. Furthermore, components in the following embodiments that are not described in an independent claim will be described as optional components. In each figure, components having substantially the same function are indicated by a common reference numeral, and redundant descriptions may be omitted or simplified.

[0034] Furthermore, the various elements shown in the drawings are for illustrative purposes only, and their dimensional ratios and appearance may differ from those of the actual object. In other words, each drawing is a schematic representation and not necessarily a strictly accurate depiction. Therefore, for example, the scale in each drawing may not necessarily match.

[0035] Furthermore, in this specification, terms indicating relationships between elements, such as parallel or coincident, terms indicating the shape of elements, such as rectangles, and numerical ranges do not represent only strict meanings, but also include substantially equivalent ranges, such as differences of a few percent.

[0036] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception, but rather to terms defined by the relative positional relationship based on the stacking order in the stacked configuration. Specifically, the light-receiving side of the imaging device is defined as "upper," and the side opposite the light-receiving side is defined as "lower." It should be noted that terms such as "upper" and "lower" are used solely to specify the relative arrangement of components and are not intended to limit the orientation of the imaging device when in use. Moreover, the terms "upper" and "lower" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close proximity and touching each other.

[0037] Furthermore, in this specification, "planar view" refers to a view of the semiconductor substrate from a direction perpendicular to the main surface (in other words, in the thickness direction of the semiconductor substrate).

[0038] Furthermore, in this specification, "connection" means an electrical connection unless otherwise specified, and refers to a state of being electrically connected at all times. Also, in this specification, the term "node" means an electrical connection point between multiple elements in an electrical circuit, and is a concept that includes wiring and the like that which are responsible for the electrical connection between those multiple elements.

[0039] Furthermore, in this specification, when a transistor is located on a surface of a semiconductor substrate, it means that the gate, source, and drain of the transistor are positioned across that surface.

[0040] Furthermore, in this specification, ordinal numbers such as "first," "second," etc., do not mean the number or order of components unless otherwise specified, but are used to avoid confusion and to distinguish similar components.

[0041] (Embodiment 1) The imaging device according to Embodiment 1 will now be described.

[0042] [Overall structure] First, the overall configuration of the imaging device according to this embodiment will be described.

[0043] Figure 1 is a diagram showing the configuration of the imaging device 100 according to this embodiment. As shown in Figure 1, the imaging device 100 according to this embodiment comprises a plurality of pixels 10 formed on a pixel substrate 60 and peripheral circuits 40 formed on a logic substrate 90. Each pixel 10 includes a photoelectric conversion unit 12 located above the pixel substrate 60. In other words, a stacked type imaging device 100 will be described as an example of the imaging device according to this disclosure. Furthermore, as will be described later, the pixel substrate 60 is stacked on the logic substrate 90.

[0044] In the example shown in Figure 1, multiple pixels 10 are arranged in an m x n matrix, where m and n are integers greater than or equal to 2. The multiple pixels 10 are arranged, for example, in two dimensions on the pixel substrate 60 to form an imaging area. In this embodiment, the photoelectric conversion unit 12 is a photoelectric conversion structure including a photoelectric conversion layer positioned above the pixel substrate 60. The imaging area is defined as the region of the pixel substrate 60 covered by the photoelectric conversion unit 12. In Figure 1, the photoelectric conversion unit 12 of each pixel 10 is shown spatially separated from each other for ease of explanation, but the photoelectric conversion units 12 of multiple pixels 10 can be arranged above the pixel substrate 60 without any spacing between them. The photoelectric conversion unit 12 may also be a photodiode formed on a semiconductor substrate included in the pixel substrate 60.

[0045] The number and arrangement of pixels 10 are not limited to the example shown. Also, in this example, the center of each pixel 10 is located on a grid point of a square grid, but the arrangement of pixels 10 does not have to be so. For example, multiple pixels 10 may be arranged such that each center is located on a grid point of a triangular grid, a hexagonal grid, or the like. Furthermore, if the pixels 10 are arranged in one dimension, the imaging device 100 can be used as a line sensor.

[0046] In the example shown in Figure 1, the peripheral circuit 40 includes a vertical scanning circuit 42 and a horizontal signal readout circuit 44. In addition, in the example shown in Figure 1, the peripheral circuit 40 may include a control circuit 46 and a voltage supply circuit 48. The peripheral circuit 40 is connected to a plurality of pixels 10 and is a circuit for acquiring signals from each pixel 10. The peripheral circuit may further include a load circuit, a signal processing circuit, an output circuit, a memory, and a power supply that supplies a predetermined voltage to each pixel 10. In the example shown in Figure 1, the peripheral circuit 40 is formed on the logic board 90, but at least a portion of the peripheral circuit 40 may be formed in the area surrounding the imaging area on the pixel board 60. Alternatively, the imaging device 100 may not have a logic board 90, and all of the peripheral circuit 40 may be formed in the area surrounding the imaging area on the pixel board 60.

[0047] The vertical scanning circuit 42, also called a row scanning circuit, has connections to address signal lines 34 provided for each row of the multiple pixels 10. As will be described later, the signal lines provided for each row of the multiple pixels 10 are not limited to address signal lines 34. Multiple types of signal lines may be connected to the vertical scanning circuit 42 for each row of the multiple pixels 10.

[0048] The horizontal signal readout circuit 44, also called a column scanning circuit, reads the signals output to the vertical signal lines 35 provided corresponding to each column of the multiple pixels 10. In the example shown in Figure 1, one vertical signal line 35 is provided for each row of the multiple pixels 10, but two or more vertical signal lines 35 may be provided for each row of the multiple pixels 10.

[0049] The control circuit 46 receives command data, a clock, etc., from an external source, for example, and controls the entire imaging device 100. The control circuit 46 includes, for example, a timing generator. The control circuit 46 supplies drive signals to the vertical scanning circuit 42, the horizontal signal readout circuit 44, and the voltage supply circuit 48, etc. In Figure 1, the arrows extending from the control circuit 46 schematically represent the flow of output signals from the control circuit 46. The control circuit 46 can be implemented, for example, by a microcontroller or one or more processors. The microcontroller may include one or more processors. The functions of the control circuit 46 may be implemented by a combination of general-purpose processing circuits and software, or by hardware specialized for such processing.

[0050] The voltage supply circuit 48 supplies a predetermined voltage to each pixel 10 via the storage control line 31. The voltage supply circuit 48 is not limited to a specific power supply circuit. The voltage supply circuit 48 may be a circuit that converts a voltage supplied from a power source such as a battery to a predetermined voltage, or it may be a circuit that generates a predetermined voltage. The voltage supply circuit 48 may also be part of the vertical scanning circuit 42 or control circuit 46 described above.

[0051] The imaging device 100 may have multiple pixel substrates 60. In this case, the circuit elements of the pixel 10 are formed separately on multiple pixel substrates 60. The imaging device 100 may also have multiple logic boards 90. In this case, the circuit elements of the peripheral circuit 40 are formed separately on multiple logic boards 90.

[0052] [Pixel configuration] Next, the configuration of the pixels 10 of the imaging device 100 according to this embodiment will be described.

[0053] First, the circuit configuration of the pixel 10 according to this embodiment will be described. Figure 2 is a diagram showing the circuit configuration of the pixel 10 according to this embodiment. Each of the multiple pixels 10 has, for example, the circuit configuration shown in Figure 2.

[0054] As described above, the pixel 10 includes a photoelectric conversion unit 12. The photoelectric conversion unit 12 generates positive and negative charges upon incident light. In other words, the photoelectric conversion unit 12 converts light into charge. Positive and negative charges are typically hole-electron pairs. The photoelectric conversion unit 12 includes a pixel electrode 12a, a photoelectric conversion layer 12b, and a counter electrode 12c. The pixel electrode 12a of the photoelectric conversion unit 12 is connected to a charge storage node FD. The counter electrode 12c of the photoelectric conversion unit 12 is connected to a storage control line 31, and a predetermined storage control voltage VITO is applied to the storage control line 31 by a voltage supply circuit 48 when the imaging device 100 is operating. By the voltage supply circuit 48 applying the predetermined storage control voltage VITO to the storage control line 31, one of the positive and negative charges generated by photoelectric conversion can be selectively stored as a signal charge in the charge storage node FD. In the following explanation, unless otherwise specified, the example will be one in which the positive charge, i.e., a hole, is used as the signal charge among the positive and negative charges generated by photoelectric conversion.

[0055] Pixel 10 is electrically connected to the photoelectric conversion unit 12 and includes a signal detection circuit that detects a signal based on the signal charge generated by the photoelectric conversion unit 12. In the example shown in Figure 2, the signal detection circuit includes an amplifying transistor 22 and an addressing transistor 24. The amplifying transistor 22 is also called a readout transistor. The addressing transistor 24 is also called a row selection transistor. The amplifying transistor 22 is an example of a first transistor, and the addressing transistor 24 is an example of a second transistor. Pixel 10 also includes a reset transistor 26 and an overflow transistor 28.

[0056] As will be explained in detail later with reference to the drawings, the amplification transistor 22, address transistor 24, reset transistor 26, and overflow transistor 28 are, for example, field-effect transistors (FETs) formed on a semiconductor substrate included in the pixel substrate 60 supporting the photoelectric conversion unit 12. In the example shown in Figure 2, each of the amplification transistor 22, address transistor 24, reset transistor 26, and overflow transistor 28 is an N-channel MOSFET (Metal Oxide Semiconductor FET). Note that which of the two impurity regions of the FET corresponds to the source and which corresponds to the drain is determined by the polarity of the FET and the potential level at that time. Therefore, which is the source and which is the drain can vary depending on the operating state of the FET. In other words, the source and drain of each transistor described below may be reversed depending on the operating state of the FET.

[0057] As schematically shown in Figure 2, the gate of the amplification transistor 22 is connected to the charge storage node FD, which in turn is connected to the photoelectric conversion unit 12. The signal charge generated by the photoelectric conversion unit 12 is stored as signal charge in the charge storage node FD between the photoelectric conversion unit 12 and the amplification transistor 22. Therefore, the potential of the charge storage node FD corresponds to the amount of signal charge stored in the charge storage node FD.

[0058] The amplification transistor 22 outputs a signal corresponding to the signal charge converted by the photoelectric conversion unit 12. One of the sources and drains of the amplification transistor 22 is connected to the power line 32 that supplies the power supply voltage VDD to each pixel 10 when the imaging device 100 is operating. The power supply voltage VDD is, for example, about 3.3V, but is not limited to this. The amplification transistor 22 outputs a signal voltage corresponding to the amount of signal charge generated by the photoelectric conversion unit 12. The other of the sources and drains of the amplification transistor 22 is connected to one of the sources and drains of the address transistor 24.

[0059] The address transistor 24 is connected in series with the amplification transistor 22. A vertical signal line 35 is connected to the source and the other drain of the address transistor 24. A load circuit that forms a source follower circuit together with the amplification transistor 22, and a column signal processing circuit are connected to the vertical signal line 35.

[0060] An address signal line 34 is connected to the gate of the address transistor 24. An address signal line 34 is provided for each row of multiple pixels 10. The address signal line 34 is connected to a vertical scanning circuit 42, which applies a row selection signal SEL to the address signal line 34 to control the on and off states of the address transistor 24. This causes the row to be read to be scanned vertically (i.e., in the column direction) and the row to be read to be selected. By controlling the on and off states of the address transistor 24 via the address signal line 34, the vertical scanning circuit 42 can read the output of the amplification transistor 22 of the selected pixel 10 to the corresponding vertical signal line 35. The arrangement of the address transistor 24 is not limited to the example shown in Figure 2, and may be between the source and drain of the amplification transistor 22 and the power line 32.

[0061] The signal voltage from the pixel 10, output to the vertical signal line 35 via the address transistor 24, is subjected to noise suppression signal processing and analog-to-digital conversion in a column signal processing circuit, for example, and then input to the horizontal signal readout circuit 44.

[0062] One of the sources and drains of the reset transistor 26 is connected to the charge storage node FD. A reset signal line 36, which has a connection to the vertical scanning circuit 42, is connected to the gate of the reset transistor 26. The reset signal line 36 is provided for each row of multiple pixels 10, similar to the address signal line 34. The vertical scanning circuit 42 applies a reset signal RST to the gate of the reset transistor 26 via the reset signal line 36, which controls the on and off states of the reset transistor 26. When the reset transistor 26 is turned on, the potential of the charge storage node FD is reset.

[0063] In the example shown in Figure 2, the source and the other drain of the reset transistor 26 are connected to a reset voltage line 37 that supplies a predetermined reset voltage VR to the pixel 10 when the pixel 10 is reset. That is, in this example, the reset voltage VR that initializes the signal charge generated by the photoelectric conversion unit 12 is supplied to the charge storage node FD via the reset transistor 26. The reset voltage VR may be a fixed voltage. Note that the configuration in which the source and the other drain of the reset transistor 26 are connected to the reset voltage line 37 is not limited. For example, the source and the other drain of the reset transistor 26 may be connected to a feedback line connected to the output of a feedback amplifier that feeds back the output from the pixel 10.

[0064] The source and drain of the overflow transistor 28, as well as its gate, are connected to the charge storage node FD. The other source and drain of the overflow transistor 28 are connected to a power line 38 that supplies a voltage VF to each pixel 10 when the imaging device 100 is operating. The voltage VF may be a fixed voltage such as the ground voltage or the power supply voltage, or it may be a variable voltage supplied from a voltage supply circuit that can change the supplied voltage. Note that the pixel 10 does not necessarily have to contain an overflow transistor.

[0065] When high-brightness light is incident on the photoelectric conversion unit 12, for example, if the amount of light incident on the photoelectric conversion unit 12 increases, the amount of holes accumulated in the charge storage node FD increases. In this case, the potential of the charge storage node FD rises excessively, which may damage the gate oxide film of the amplification transistor 22 connected to the charge storage node FD. The overflow transistor 28 turns on when the potential of the charge storage node FD rises above a predetermined potential. This allows the holes accumulated in the charge storage node FD to be discharged, thereby lowering the potential of the charge storage node FD.

[0066] In the example shown in Figure 2, the gate of the amplification transistor 22 connected to the charge storage node FD, one of the source and drain of the reset transistor 26, one of the source and drain of the overflow transistor 28, and the gate of the overflow transistor 28 all function as regions for storing signal charge generated by the photoelectric conversion unit 12. In this specification, the expression that an element is connected to the charge storage node FD may also include the case that an element is part of the charge storage node FD.

[0067] Furthermore, as shown in Figure 2, the charge storage node FD includes a through-electrode 81. As will be described in detail later, the through-electrode 81 is a conductor that penetrates the semiconductor substrate contained in the pixel substrate 60. Also, as shown in Figure 2, a parasitic capacitance Cp is formed between the through-electrode 81 and the n-type impurity region 80n in the semiconductor substrate. The n-type impurity region 80n is electrically connected to the source and the other drain of the amplification transistor 22. As a result, the potential of the n-type impurity region 80n changes in synchronization with the potential of the through-electrode 81 connected to the gate of the amplification transistor 22. Specifically, the potential difference between the potential of the n-type impurity region 80n and the potential of the through-electrode 81 is maintained to be the gate-source voltage of the amplification transistor 22. Therefore, even if a signal charge is generated, the potential difference between the n-type impurity region 80n and the through-electrode 81 does not increase, the capacitance of the charge storage node FD is reduced, and the conversion gain in the imaging device 100 can be improved.

[0068] Next, the device structure of the pixel 10 according to this embodiment will be described. Figure 3 is a plan view showing an example of the layout within the pixel 10 according to this embodiment. Figure 4 is a schematic cross-sectional view of the device structure of the pixel 10 according to this embodiment. Figure 4 is a cross-sectional view when the pixel 10 is cut along the line IV-IV in Figure 3 and unfolded in the direction of the arrow. Figure 3 schematically shows the layout of the transistor and impurity region located on the second surface s2 of the semiconductor substrate 60A when the pixel 10 is viewed along the thickness direction of the semiconductor substrate 60A.

[0069] Figure 3 also shows the arrangement of the through-electrode 81, the insulating layer 82, and the contact plug cps formed on the impurity region. For clarity, Figure 3 uses the same shading as Figure 4 for each component. In Figure 4, for clarity, shading indicating cross-sections has been omitted for insulating layers such as insulating layers 14, 51, 52, 82, and the interlayer insulating layer 60i. Furthermore, Figure 4 omits a detailed illustration of the logic board 90. These same considerations apply to the plan view and cross-sectional view described later.

[0070] Furthermore, Figure 3 shows the layout corresponding to two adjacent pixels 10. In the example shown in Figure 3, the layout of the two adjacent pixels 10 is symmetrical along the boundary line between the two pixels 10. This layout allows the two pixels 10 to share a portion of the impurity region, thus enabling miniaturization of the pixels 10.

[0071] As shown in Figure 4, the pixel 10 generally includes a pixel substrate 60, a photoelectric conversion unit 12 laminated on the pixel substrate 60, a through electrode 81, and an insulating layer 82. Also as shown in Figure 4, the pixel substrate 60 is laminated on the logic substrate 90. The pixel substrate 60 and the logic substrate 90 are joined, for example, by a metal-dielectric hybrid junction. The pixel substrate 60 is formed continuously, for example, over at least the entire imaging area. The pixel substrate 60 is shared by multiple pixels 10. The pixel substrate 60 is located above the logic substrate 90. The photoelectric conversion unit 12 is located above the pixel substrate 60.

[0072] The pixel substrate 60 includes a semiconductor substrate 60A and a wiring layer 60B. The semiconductor substrate 60A has a first surface s1 and a second surface s2 opposite to the first surface s1. The first surface s1 and the second surface s2 are the main surfaces of the semiconductor substrate 60A, perpendicular to the thickness direction of the semiconductor substrate 60A. In the example shown in Figure 4, the first surface s1 is the top surface of the semiconductor substrate 60A, and the second surface s2 is the bottom surface of the semiconductor substrate 60A. The wiring layer 60B is laminated on the second surface s2 side of the semiconductor substrate 60A. As shown in Figures 3 and 4, the amplification transistor 22, address transistor 24, reset transistor 26, and overflow transistor 28 are located on the second surface s2. In the example shown in Figure 4, the photoelectric conversion unit 12 is located on the first surface s1 side of the semiconductor substrate 60A.

[0073] As shown in Figure 4, the semiconductor substrate 60A includes a p-type semiconductor layer 60p. The p-type semiconductor layer 60p is a p-type well region in the semiconductor substrate 60A. The p-type semiconductor layer 60p is the semiconductor layer on which the second surface s2 of the semiconductor layers included in the semiconductor substrate 60A is located. In the example shown in Figure 4, the first surface s1 is also located on the p-type semiconductor layer 60p.

[0074] The p-type semiconductor layer 60p is a semiconductor layer containing p-type impurities. The p-type semiconductor layer 60p is formed, for example, by ion implantation of impurities into the semiconductor layer. A p-type impurity is, for example, boron.

[0075] As shown in Figures 3 and 4, the semiconductor substrate 60A includes n-type impurity regions 70n, 71n, 72n, 73n, 74n, 75n, and 80n, a p-type impurity region 79p, and an element isolation region 50. The n-type impurity region 71n is an example of a first impurity region. The n-type impurity region 80n is an example of a second impurity region with the same conductivity as the first impurity region. The n-type impurity regions 70n, 71n, 72n, 73n, 74n, 75n, and 80n are impurity regions where n-type impurities have diffused. Examples of n-type impurities are arsenic or phosphorus. The p-type impurity region 79p is an impurity region where p-type impurities have diffused. The n-type impurity regions 70n, 71n, 72n, 73n, 74n, and 75n, the p-type impurity region 79p, and the element isolation region 50 are located on the second surface s2. Although the element isolation region 50 is not shown in Figure 3, the unpatterned area around the transistor and impurity region is, for example, the element isolation region 50.

[0076] In the n-type impurity regions 70n, 71n, 72n, 73n, 74n, and 75n, the same type of n-type impurity diffuses as the main component. Here, the main component is the impurity with the highest concentration among the impurities contained in the impurity region. For example, the main component of the n-type impurity that diffuses into the n-type impurity regions 70n, 71n, 72n, 73n, 74n, and 75n is arsenic. In the n-type impurity region 80n, a different type of n-type impurity diffuses as the main component than the n-type impurity that diffuses as the main component in the n-type impurity regions 70n, 71n, 72n, 73n, 74n, and 75n. For example, the main component of the n-type impurity that diffuses into the n-type impurity region 80n is phosphorus. Note that the same type of n-type impurity may diffuse as the main component in the n-type impurity regions 70n, 71n, 72n, 73n, 74n, and 75n and the n-type impurity region 80n.

[0077] The n-type impurity regions 70n, 71n, 72n, 73n, 74n, 75n, and 80n, the p-type impurity region 79p, and the device isolation region 50 are formed within the p-type semiconductor layer 60p. The n-type impurity regions 70n, 71n, 72n, 73n, 74n, 75n, and 80n, as well as the p-type impurity region 79p, are formed, for example, by impurities being injected into the p-type semiconductor layer 60p from the second surface s2 side.

[0078] As shown in Figures 3 and 4, the amplification transistor 22, address transistor 24, reset transistor 26, and overflow transistor 28 are located on the second surface s2 of the semiconductor substrate 60A. Each of the amplification transistor 22, address transistor 24, reset transistor 26, and overflow transistor 28 is an N-channel MOSFET formed on the p-type semiconductor layer 60p.

[0079] The amplification transistor 22 includes an n-type impurity region 70n that functions as one of the source and drain, an n-type impurity region 71n that functions as the other of the source and drain, and a gate 22e. In the example shown in Figure 3, the n-type impurity region 70n is shared by two adjacent pixels 10. The signal output by the amplification transistor 22 is input to the n-type impurity region 71n. In this specification, the expression "an impurity region to which the signal output by the amplification transistor 22 is input" also includes the impurity region that functions as the other of the source and drain of the amplification transistor 22.

[0080] The address transistor 24 includes an n-type impurity region 71n that functions as one of the source and drain, an n-type impurity region 72n that functions as the other of the source and drain, and a gate 24e. In the example shown in Figure 3, the address transistor 24 is electrically connected to the amplifier transistor 22 by sharing the n-type impurity region 71n with the amplifier transistor 22.

[0081] The reset transistor 26 includes an n-type impurity region 73n that functions as one source and one drain, an n-type impurity region 74n that functions as the other source and one drain, and a gate 26e. The n-type impurity region 73n is an example of a charge storage region that stores signal charge. In the example shown in Figure 3, the n-type impurity region 74n is shared by two adjacent pixels 10. In the example shown in Figure 3, the gate length of the reset transistor 26 is longer than the gate length of the amplification transistor 22 and the gate length of the address transistor 24.

[0082] The overflow transistor 28 includes an n-type impurity region 73n that functions as one source and one drain, an n-type impurity region 75n that functions as the other source and one drain, and a gate 28e. In the example shown in Figure 3, the overflow transistor 28 is electrically connected to the reset transistor 26 by sharing the n-type impurity region 73n with the reset transistor 26. Also in the example shown in Figure 3, the n-type impurity region 75n is shared by two adjacent pixels 10.

[0083] Gates 22e, 24e, 26e, and 28e are gate electrodes formed from, for example, impurity-doped polysilicon. Gates 22e, 24e, 26e, and 28e are doped with, for example, n-type impurities. Gates 22e, 24e, 26e, and 28e may also be doped with p-type impurities.

[0084] The p-type impurity region 79p functions as a well contact region of the p-type semiconductor layer 60p. A p-well voltage Vp is applied to the p-type semiconductor layer 60p via the p-type impurity region 79p. This makes it possible to control the potential of the p-type semiconductor layer 60p via the p-type impurity region 79p when the imaging device 100 is in operation. In the example shown in Figure 3, the p-type impurity region 79p is shared by two adjacent pixels 10. Note that the p-type impurity region 79p does not have to be formed for each pixel 10. Also, the p-type impurity region 79p does not have to be located in the region where the pixels 10 are formed. For example, the p-type impurity region 79p may be located in the region surrounding the area where multiple pixels 10 are formed on the semiconductor substrate 60A.

[0085] The n-type impurity region 80n covers the through electrode 81 from the circumferential direction via the insulating layer 82. In a plan view, the n-type impurity region 80n surrounds the through electrode 81 with the insulating layer 82 in between. The n-type impurity region 80n and the through electrode 81 are electrically insulated by the insulating layer 82. The n-type impurity region 80n is formed from the second surface s2 to the first surface s1. The n-type impurity region 80n is directly electrically connected to the n-type impurity region 71n. In the example shown in Figures 3 and 4, a portion of the n-type impurity region 80n overlaps with the n-type impurity region 71n in a plan view. This enables miniaturization of the pixel 10.

[0086] The element isolation region 50 is arranged, for example, in a plan view, to surround each of the following: the amplifier transistor 22, the address transistor 24 and the set of n-type impurity region 80n, the reset transistor 26 and the overflow transistor 28, and the p-type impurity region 79p, thereby electrically isolating them from one another. The element isolation region 50 is, for example, an STI (Shallow Trench Isolation) structure. The STI structure is formed on the semiconductor substrate 60A by an STI process. At least a portion of the element isolation region 50 may be an implanted isolation region in which impurities are implanted at a high concentration. In this embodiment, the impurities in the implanted isolation region are p-type impurities.

[0087] As shown in Figure 4, the wiring layer 60B includes an insulating layer 51, an interlayer insulating layer 60i, a plurality of wirings including wiring 83, a plurality of contact plugs cps, and gates 22e, 24e, 26e, and 28e. The plurality of wirings, the plurality of contact plugs cps, and gates 22e, 24e, 26e, and 28e are formed in the interlayer insulating layer 60i. In addition, some of the contact plugs cps penetrate the insulating layer 51 for connection to the semiconductor substrate 60A.

[0088] The interlayer insulating layer 60i is laminated on the semiconductor substrate 60A via the insulating layer 51. Although not shown in Figure 4, the interlayer insulating layer 60i has a laminated structure of multiple insulating layers. Wiring included in the wiring layer 60B is arranged on each of the multiple insulating layers. The wiring is a layered conductor extending in a direction perpendicular to the thickness direction of the interlayer insulating layer 60i. Electrical connections between wirings arranged on different insulating layers are made, for example, vias. Vias are columnar conductors extending in the thickness direction of the interlayer insulating layer 60i. The wiring and vias are formed from metals such as copper or tungsten, or metal compounds such as metal nitrides or metal oxides. The number of insulating layers in the interlayer insulating layer 60i can be arbitrarily set. The interlayer insulating layer 60i and the insulating layer 51 are formed from insulating materials such as silicon oxide.

[0089] The electrical connection between the amplification transistor 22, address transistor 24, reset transistor 26, overflow transistor 28, and the p-type impurity region 79p and the wiring contained in the wiring layer 60B is made via contact plugs cps formed in the interlayer insulating layer 60i. The contact plugs cps are formed from polysilicon doped with impurities such as n-type impurities, for example. The contact plugs cps may also be formed from metals such as copper or tungsten, or metal compounds such as metal nitrides or metal oxides.

[0090] As shown in Figure 4, the photoelectric conversion unit 12 is located on the first surface s1 side of the semiconductor substrate 60A. The photoelectric conversion unit 12 is placed on an insulating layer 52 on the first surface s1 of the semiconductor substrate 60A. The insulating layer 52 is formed of an insulating material such as silicon oxide.

[0091] The photoelectric conversion unit 12 includes a pixel electrode 12a formed on an insulating layer 52, a counter electrode 12c facing the pixel electrode 12a, and a photoelectric conversion layer 12b located between the pixel electrode 12a and the counter electrode 12c. The photoelectric conversion layer 12b is formed from an organic material or an inorganic material such as amorphous silicon, and receives light incident via the counter electrode 12c to generate positive and negative charges through photoelectric conversion. The photoelectric conversion layer 12b is formed continuously, for example, across a plurality of pixels 10. In other words, the photoelectric conversion layer 12b is shared by a plurality of pixels 10. The photoelectric conversion layer 12b may also include a layer made of an organic material and a layer made of an inorganic material. The photoelectric conversion layer 12b may also be provided separately for each of one or more pixels 10.

[0092] The counter electrode 12c is formed from a transparent conductive material such as ITO (Indium Tin Oxide) and is positioned on the light-receiving side of the photoelectric conversion layer 12b. The counter electrode 12c is a film-like electrode and, for example, is formed continuously across multiple pixels 10, similar to the photoelectric conversion layer 12b. In other words, the counter electrode 12c is shared by multiple pixels 10. The counter electrode 12c may be provided separately for each of one or more pixels 10.

[0093] Although not shown in Figure 4, the counter electrode 12c is connected to the accumulation control line 31 described above. When the imaging device 100 is in operation, the potential of the accumulation control line 31 is controlled to make the potential of the counter electrode 12c different from the potential of the pixel electrode 12a, thereby allowing the signal charge generated by photoelectric conversion to be collected by the pixel electrode 12a. For example, the potential of the accumulation control line 31 is controlled so that the potential of the counter electrode 12c is higher than the potential of the pixel electrode 12a. Specifically, when the imaging device 100 is in operation, an accumulation control voltage VITO, which is different from the reset voltage VR, is applied to the counter electrode 12c via the accumulation control line 31. The accumulation control voltage VITO is, for example, a positive voltage of about 10V. As a result, among the hole-electron pairs generated in the photoelectric conversion layer 12b, the holes can be collected as signal charges by the pixel electrode 12a. The n-type impurity region 73n is electrically connected to the pixel electrode 12a. The signal charge collected by the pixel electrode 12a is accumulated in the n-type impurity region 73n. The n-type impurity region 73n is an example of a charge accumulation region. When electrons are used as the signal charge, an accumulation control voltage VITO is applied to the counter electrode 12c such that the potential of the counter electrode 12c is lower than the potential of the pixel electrode 12a.

[0094] The pixel electrode 12a is a film-like electrode formed from a metal such as aluminum or copper, a metal nitride, or polysilicon that has been doped with impurities to impure conductivity. The pixel electrode 12a is electrically isolated from the pixel electrodes 12a of other adjacent pixels 10 by being spatially separated from them.

[0095] In the example shown in Figure 4, the pixel 10 further includes a shield electrode 13, an insulating layer 14, a color filter 15, and a microlens 16.

[0096] The shield electrode 13 is a film-like electrode formed from a metal such as aluminum or copper, a metal nitride, or polysilicon that has been doped with impurities to impure conductivity. The shield electrode 13 is placed between the pixel electrodes 12a of adjacent pixels 10, and when a predetermined voltage is applied, it suppresses the movement of signal charge between adjacent pixels 10. An insulating layer is placed between the shield electrode 13 and the pixel electrodes 12a. The insulating layer 14 is placed above the photoelectric conversion unit 12.

[0097] The insulating layer 14 is an insulating film that protects the photoelectric conversion unit 12. The color filter 15 is positioned above the insulating layer 14. The color filter 15 is formed, for example, as an on-chip color filter by patterning, and is made of a photosensitive resin in which dyes or pigments are dispersed. The microlens 16 is positioned above the color filter 15 and has a light-gathering function that focuses light onto the photoelectric conversion unit 12. The microlens 16 is formed, for example, as an on-chip microlens, and is made of an ultraviolet photosensitive material.

[0098] The through-electrode 81 is a columnar conductor that penetrates the semiconductor substrate 60A and the insulating layers 51 and 52. The through-electrode 81 is electrically connected to the photoelectric conversion unit 12, the gate 22e of the amplification transistor 22, and the n-type impurity region 73n. In the example shown in Figure 4, the upper end of the through-electrode 81 is in contact with and connected to the pixel electrode 12a. The lower end of the through-electrode 81 is in contact with and connected to the wiring 83 within the interlayer insulating layer 60i. The through-electrode 81 is connected to the gate 22e and the n-type impurity region 73n via the wiring 83 and contact plug cps. The through-electrode 81 is formed from, for example, a metal such as copper or tungsten, polysilicon doped with impurities, or a metal compound such as a metal nitride or metal oxide.

[0099] The insulating layer 82 covers the through electrode 81 from the circumferential direction within the semiconductor substrate 60A. In a plan view, the insulating layer 82 surrounds the through electrode 81. The insulating layer 82 completely covers the outer surface of the through electrode 81 within the semiconductor substrate 60A. The insulating layer 82 is formed of an insulating material such as silicon oxide.

[0100] In the example shown in Figure 3, the outer edge shapes of the contact plug cps, through electrode 81, and insulating layer 82 in plan view are rectangular, but other shapes such as circular may also be used.

[0101] The connection structure, such as wiring, that electrically connects the pixel electrode 12a, gate 22e, gate 28e, and n-type impurity region 73n corresponds to the charge storage node FD described above. The pixel electrode 12a, through electrode 81, wiring 83, gates 22e and 28e, and n-type impurity region 73n of the photoelectric conversion unit 12 function as regions for accumulating signal charge generated by the photoelectric conversion unit 12.

[0102] In the example shown in Figure 4, the parasitic capacitance Cp shown in Figure 2 is formed by the n-type impurity region 80n, the through electrode 81, and the insulating layer 82. The n-type impurity region 80n is electrically connected to the n-type impurity region 71n, which functions as the other half of the source and drain of the amplifying transistor 22, within the semiconductor substrate 60A. Therefore, as explained using Figure 2, the potential of the n-type impurity region 80n changes in synchronization with the potential of the through electrode 81 connected to the gate 22e of the amplifying transistor 22, thereby reducing the capacitance of the charge storage node FD and improving the conversion gain of the imaging device 100. Furthermore, in the imaging device 100, the n-type impurity region 80n and the n-type impurity region 71n are electrically connected within the semiconductor substrate 60A. This reduces the parasitic resistance in the electrical connection between the n-type impurity region 80n and the n-type impurity region 71n.

[0103] Furthermore, in the conventional configuration, the parasitic capacitance of the through-electrode 81 portion in the charge storage node FD becomes large because it is the capacitance to ground. Therefore, in the conventional configuration, the parasitic capacitance of the through-electrode 81 portion in the charge storage node FD can be reduced by increasing the thickness of the insulating layer 82. On the other hand, in the imaging device 100, since the potential of the n-type impurity region 80n changes in synchronization with the potential of the through-electrode 81, it is possible to reduce the parasitic capacitance caused by the through-electrode 81 without increasing the thickness of the insulating layer 82, thus enabling miniaturization of the pixel 10. In addition, since the n-type impurity region 80n and the n-type impurity region 71n are connected without using wiring and contact plugs cps, the pixel 10 can be miniaturized.

[0104] [Example 1] Next, we will describe a modified example of Embodiment 1. In the following, we will focus on the differences from Embodiment 1 described above, and omit or simplify the explanation of the common points.

[0105] Figure 5 is a plan view showing an example of the layout within pixel 10A according to this modified example. Figure 6 is a schematic cross-sectional view of the device structure of pixel 10A according to this modified example. Figure 6 is a cross-sectional view obtained when pixel 10A is cut along the line VI-VI in Figure 5. Figure 5 schematically shows the layout of transistors and impurity regions located on the second surface s2 of the semiconductor substrate 60A when pixel 10A is viewed along the thickness direction of the semiconductor substrate 60A.

[0106] The imaging device according to this modified example has a configuration in which the plurality of pixels 10 of the imaging device 100 according to Embodiment 1 are replaced with a plurality of pixels 10A. The circuit configuration of the pixels 10A is, for example, the same as the circuit configuration of the pixels 10 shown in Figure 2.

[0107] As shown in Figures 5 and 6, the pixel 10A in this modified example differs from the pixel 10 in Embodiment 1 mainly in that, in a plan view, the entire n-type impurity region 80n overlaps with the n-type impurity region 71n. In the pixel 10A, the n-type impurity region 71n surrounds the through electrode 81 with the insulating layer 82 in between in a plan view.

[0108] In this modified example, the entire n-type impurity region 80n overlaps with the n-type impurity region 71n in a planar view, making further miniaturization of the pixel 10A possible.

[0109] [Differentiation 2] Next, a modified example of Embodiment 1, Part 2, will be described. In the following, the differences between Embodiment 1 and Modified Example 1 of Embodiment 1 will be the main focus of the explanation, and the explanation of the common points will be omitted or simplified.

[0110] Figure 7 is a plan view showing an example of the layout within pixel 10B according to this modified example. Figure 7 schematically shows the layout of the transistor and impurity region located on the second surface s2 of the semiconductor substrate 60A when pixel 10B is viewed along the thickness direction of the semiconductor substrate 60A.

[0111] The imaging device according to this modified example has a configuration in which the plurality of pixels 10 of the imaging device 100 according to Embodiment 1 are replaced with a plurality of pixels 10B. The circuit configuration of the pixels 10B is, for example, the same as the circuit configuration of the pixels 10 shown in Figure 2.

[0112] As shown in Figure 7, the pixel 10B in this modified example differs from the pixel 10 in Embodiment 1 mainly in that the semiconductor substrate 60A further includes n-type impurity regions 76n and 77n. The n-type impurity region 76n is an example of a third impurity region of the same conductivity type as the first impurity region.

[0113] The n-type impurity regions 76n and 77n are located on the second surface s2 of the semiconductor substrate 60A. The n-type impurity regions 76n and 77n are formed within the p-type semiconductor layer 60p. As shown in Figure 7, the n-type impurity region 77n functions as one of the source and drain of the address transistor 24. In the pixel 10B, the address transistor 24 does not share the n-type impurity region 71n with the amplifier transistor 22, but is electrically connected to the amplifier transistor 22 via the n-type impurity region 76n.

[0114] Furthermore, in pixel 10B, n-type impurity regions 71n and 77n are electrically connected to n-type impurity region 80n via n-type impurity region 76n. This increases the degree of freedom in the layout of pixel 10B.

[0115] [Difference 3] Next, we will describe a modified example of Embodiment 1, Part 3. In the following, we will focus on the differences between Embodiment 1 and Modified Examples 1 and 2 of Embodiment 1, and will omit or simplify the explanation of the common points.

[0116] Figure 8 shows the circuit configuration of pixel 10C according to this modified example. Figure 9 is a plan view showing an example of the layout within pixel 10C according to this modified example. Figure 9 schematically shows the layout of transistors and impurity regions located on the second surface s2 of the semiconductor substrate 60A when pixel 10C is viewed along the thickness direction of the semiconductor substrate 60A.

[0117] The imaging device according to this modified example has a configuration in which the plurality of pixels 10 of the imaging device 100 according to Embodiment 1 are changed to a plurality of pixels 10C.

[0118] As shown in Figures 8 and 9, the pixel 10C in this modified example differs from the pixel 10 in Embodiment 1 mainly in that the n-type impurity region 72n, rather than the n-type impurity region 71n, is electrically connected to the n-type impurity region 80n. In this modified example, the n-type impurity region 72n is an example of a first impurity region.

[0119] A parasitic capacitance Cp is formed between the through-electrode 81 and the n-type impurity region 80n in the semiconductor substrate 60A. The n-type impurity region 80n is electrically connected to the n-type impurity region 72n, which functions as the other source and drain of the amplification transistor 22 within the semiconductor substrate 60A. As a result, when reading out the signal charge that turns on the address transistor 24, the potential of the n-type impurity region 80n changes in synchronization with the potential of the through-electrode 81 connected to the gate 22e of the amplification transistor 22. Therefore, even if the signal charge is accumulated in the charge storage node FD, the potential difference between the n-type impurity region 80n and the through-electrode 81 does not increase when reading out the signal charge, and the capacitance of the charge storage node FD is reduced. Thus, the conversion gain in the imaging device can be improved.

[0120] In addition, in pixel 10C, the n-type impurity region 72n may be electrically connected to the n-type impurity region 80n within the semiconductor substrate 60A via another n-type impurity region.

[0121] [Differentiation Example 4] Next, we will describe a modified example of Embodiment 1, Part 4. In the following, we will focus on explaining the differences between Embodiment 1 and Modified Examples 1 to 3 of Embodiment 1, and will omit or simplify the explanation of the common points.

[0122] Figure 10 is a diagram showing the circuit configuration of pixel 10D according to this modified example. Figure 11 is a plan view showing an example of the layout within pixel 10D according to this modified example. Figure 12 is a schematic cross-sectional view of the device structure of pixel 10D according to this modified example. Figure 12 is a cross-sectional view obtained when pixel 10D is cut along the line XII-XII in Figure 11 and unfolded in the direction of the arrow. Figure 11 also schematically shows the layout of the transistor and impurity region located on the second surface s2 of the semiconductor substrate 60AD when pixel 10D is viewed along the thickness direction of the semiconductor substrate 60AD.

[0123] The imaging device according to this modified example has a configuration in which the plurality of pixels 10 of the imaging device 100 according to Embodiment 1 are changed to a plurality of pixels 10D.

[0124] As shown in Figures 10 to 12, the pixel 10D according to this modified example differs from the pixel 10 according to Embodiment 1 mainly in that it has an amplifying transistor 22D, an addressing transistor 24D, and a resetting transistor 26D instead of an amplifying transistor 22, an addressing transistor 24, and a resetting transistor 26, and does not have an overflow transistor 28.

[0125] In the examples shown in Figures 10 to 12, the amplification transistor 22D, the address transistor 24D, and the reset transistor 26D are P-channel MOSFETs.

[0126] As shown in Figure 12, the device structure of pixel 10D has a configuration in which the pixel substrate 60 in pixel 10, which includes the semiconductor substrate 60A and wiring layer 60B, is changed to a pixel substrate 60D which includes the semiconductor substrate 60AD and wiring layer 60B.

[0127] The semiconductor substrate 60AD includes an n-type well region, an n-type semiconductor layer 60n, p-type impurity regions 70p, 71p, 72p, 73p, 74p, and 80p, an n-type impurity region 79n, and an element isolation region 50. In this modified example, the p-type impurity region 71p is an example of a first impurity region. Also in this modified example, the p-type impurity region 80p is an example of a second impurity region with the same conductivity type as the first impurity region.

[0128] The n-type semiconductor layer 60n, p-type impurity regions 70p, 71p, 72p, 73p, 74p, and 80p, and the n-type impurity region 79n are described in the same way as the p-type semiconductor layer 60p, n-type impurity regions 70n, 71n, 72n, 73n, 74n, and 80n, and the p-type impurity region 79p in the semiconductor substrate 60A, except that "p-type" and "n-type" are swapped.

[0129] The amplifying transistor 22D includes a p-type impurity region 70p that functions as one of the source and drain, a p-type impurity region 71p that functions as the other of the source and drain, and a gate 22e.

[0130] The address transistor 24D includes a p-type impurity region 71p that functions as one of the source and drain regions, a p-type impurity region 72p that functions as the other of the source and drain regions, and a gate 24e.

[0131] The reset transistor 26D includes a p-type impurity region 73p that functions as one of the source and drain, a p-type impurity region 74p that functions as the other of the source and drain, and a gate 26e. The p-type impurity region 73p is an example of a charge storage region that stores signal charge.

[0132] The n-type impurity region 79n functions as a well contact region of the n-type semiconductor layer 60n. The n-well voltage Vn is applied to the n-type semiconductor layer 60n via the n-type impurity region 79n. This makes it possible to control the potential of the n-type semiconductor layer 60n via the n-type impurity region 79n during the operation of the imaging device 100.

[0133] During exposure of the imaging device, the n-well voltage Vn is the voltage between the storage control voltage VITO and the reset voltage VR. When the signal charge is a hole, the n-well voltage Vn is higher than the reset voltage VR and lower than the storage control voltage VITO. As a result, the potential of the charge storage node FD rises excessively, and when the potential of the charge storage node FD exceeds the n-well voltage Vn, a forward bias voltage is applied to the pn junction between the p-type impurity region 73p where the signal charge is stored and the n-type semiconductor layer 60n. Consequently, the signal charge is discharged from the p-type impurity region 73p to the n-type semiconductor layer 60n, thereby lowering the potential of the charge storage node FD. Furthermore, in pixel 10D, the signal charge is discharged when the potential of the charge storage node FD rises excessively without using the overflow transistor 28. Therefore, the capacitance of the gate 28e of the overflow transistor 28, which functions as a region for storing signal charge, and the wiring connected to the gate 28e are eliminated, making it possible to improve the conversion gain.

[0134] Although the above example described a case where the signal charge is a hole, the signal charge may also be an electron. In this case, the signal charge emission effect described above can be obtained by swapping the p-type and n-type components of each element in the semiconductor substrate 60AD.

[0135] Furthermore, in pixel 10D, the p-type impurity region 72p may be electrically connected to the p-type impurity region 80p within the semiconductor substrate 60AD via another p-type impurity region. Also, in pixel 10D, the entire p-type impurity region 80p may overlap with the p-type impurity region 71p in a plan view.

[0136] [Difference 5] Next, we will describe a modified example 5 of Embodiment 1. In the following, we will focus on explaining the differences between Embodiment 1 and Modified Examples 1 to 4 of Embodiment 1, and will omit or simplify the explanation of the common points.

[0137] Figure 13 is a plan view showing an example of the layout within pixel 10E according to this modified example. Figure 14 is another plan view showing an example of the layout within pixel 10E according to this modified example. Figure 15 is a schematic cross-sectional view of the device structure of pixel 10E according to this modified example. Figure 15 is a cross-sectional view when pixel 10E is cut along the XV-XV line in Figures 13 and 14. Figure 13 also schematically shows the layout of transistors and impurity regions located on the second surface s12 of semiconductor substrate 61A when pixel 10E is viewed along the thickness direction of semiconductor substrate 61A. Figure 14 also schematically shows the layout of transistors and impurity regions located on the first surface s21 of semiconductor substrate 62A when pixel 10E is viewed along the thickness direction of semiconductor substrate 62A.

[0138] The imaging device according to this modified example has a configuration in which the plurality of pixels 10 of the imaging device 100 according to Embodiment 1 are replaced with a plurality of pixels 10E. The circuit configuration of the pixels 10E is, for example, the same as the circuit configuration of the pixels 10 shown in Figure 2.

[0139] As shown in Figures 13 to 15, the pixel 10E according to this modified example differs from the pixel 10A according to Modification 1 of Embodiment 1 mainly in that it includes a first pixel substrate 61 and a second pixel substrate 62 instead of the pixel substrate 60.

[0140] As shown in Figure 15, the first pixel substrate 61 and the second pixel substrate 62 are stacked on the logic substrate 90. The second pixel substrate 62 is located above the logic substrate 90. The first pixel substrate 61 is located above the second pixel substrate 62. The photoelectric conversion unit 12 is located above the first pixel substrate 61. The second pixel substrate 62 and the logic substrate 90 are joined, for example, by fusion bonding. The first pixel substrate 61 and the second pixel substrate 62 are joined, for example, by a metal-dielectric hybrid junction. The first pixel substrate 61 and the second pixel substrate 62 are formed continuously, for example, over at least the entire imaging area. The first pixel substrate 61 and the second pixel substrate 62 are shared by a plurality of pixels 10E. In a pixel 10E, the transistors included in the pixel 10E are separated and arranged on the first pixel substrate 61 and the second pixel substrate 62. Therefore, the imaging device can be miniaturized.

[0141] As shown in Figure 15, the first pixel substrate 61 includes a semiconductor substrate 61A and a wiring layer 61B. The semiconductor substrate 61A has a first surface s11 and a second surface s12 opposite to the first surface s11. The first surface s11 and the second surface s12 are the main surfaces of the semiconductor substrate 61A, perpendicular to the thickness direction of the semiconductor substrate 61A. In the example shown in Figure 15, the first surface s11 is the top surface of the semiconductor substrate 61A, and the second surface s12 is the bottom surface of the semiconductor substrate 61A. The wiring layer 61B is laminated on the second surface s12 side of the semiconductor substrate 61A. Also, as shown in Figures 13 and 15, the amplification transistor 22 and the address transistor 24 are located on the second surface s12. The photoelectric conversion unit 12 is located on the first surface s11 side of the semiconductor substrate 61A.

[0142] As shown in Figure 15, the semiconductor substrate 61A includes a p-type semiconductor layer 61p. The p-type semiconductor layer 61p is a p-type well region in the semiconductor substrate 61A. The p-type semiconductor layer 61p is the semiconductor layer on which the second surface s12 of the semiconductor layers included in the semiconductor substrate 61A is located. In the example shown in Figure 15, the first surface s11 is also located on the p-type semiconductor layer 61p.

[0143] As shown in Figures 13 and 15, the semiconductor substrate 61A includes n-type impurity regions 70n, 71n, 72n, and 80n, a p-type impurity region 79p1, and an element isolation region 50 (not shown). The n-type impurity regions 70n, 71n, and 72n, the p-type impurity region 79p1, and the element isolation region 50 are located on the second surface s12. The n-type impurity regions 70n, 71n, 72n, and 80n, the p-type impurity region 79p1, and the element isolation region 50 are formed within the p-type semiconductor layer 61p.

[0144] The amplification transistor 22 and the address transistor 24 are located on the second surface s12 of the semiconductor substrate 61A. Each of the amplification transistor 22 and the address transistor 24 is an N-channel MOSFET formed on the p-type semiconductor layer 61p.

[0145] The p-type impurity region 79p1 functions as a well contact region of the p-type semiconductor layer 61p. The p-well voltage Vp is applied to the p-type semiconductor layer 61p via the p-type impurity region 79p1.

[0146] As shown in Figure 15, the wiring layer 61B includes an insulating layer 51, an interlayer insulating layer 61i, a plurality of wirings including wirings 84, 85, 86, and 87, a plurality of contact plugs cps, and gates 22e and 24e. The plurality of wirings, the plurality of contact plugs cps, and gates 22e and 24e are formed in the interlayer insulating layer 61i. In addition, some of the contact plugs cps penetrate the insulating layer 51 for connection to the semiconductor substrate 61A.

[0147] The interlayer insulating layer 61i is laminated on the semiconductor substrate 61A via the insulating layer 51. Although not shown in Figure 15, the interlayer insulating layer 61i has a laminated structure of multiple insulating layers. Wiring included in the wiring layer 61B is arranged on each of the multiple insulating layers.

[0148] As shown in Figure 15, the second pixel substrate 62 includes a semiconductor substrate 62A and a wiring layer 62B. The semiconductor substrate 62A has a first surface s21 and a second surface s22 opposite to the first surface s21. The first surface s21 and the second surface s22 are the main surfaces of the semiconductor substrate 62A, perpendicular to the thickness direction of the semiconductor substrate 62A. In the example shown in Figure 15, the first surface s21 is the top surface of the semiconductor substrate 62A, and the second surface s22 is the bottom surface of the semiconductor substrate 62A. The wiring layer 62B is laminated on the first surface s21 side of the semiconductor substrate 62A. Also, as shown in Figures 14 and 15, the reset transistor 26 and the overflow transistor 28 are located on the first surface s21. In the example shown in Figure 15, the logic substrate 90 is located on the second surface s22 side of the semiconductor substrate 62A.

[0149] As shown in Figure 15, the semiconductor substrate 62A includes a p-type semiconductor layer 62p. The p-type semiconductor layer 62p is a p-type well region in the semiconductor substrate 62A. The p-type semiconductor layer 62p is the semiconductor layer on which the first surface s21 of the semiconductor layers included in the semiconductor substrate 62A is located. In the example shown in Figure 15, the second surface s22 is also located on the p-type semiconductor layer 62p.

[0150] As shown in Figures 14 and 15, the semiconductor substrate 62A includes n-type impurity regions 73n, 74n, and 75n, a p-type impurity region 79p2, and an element isolation region 50 (not shown). The n-type impurity regions 73n, 74n, and 75n, the p-type impurity region 79p2, and the element isolation region 50 are located on the first surface s21. The n-type impurity regions 73n, 74n, and 75n, the p-type impurity region 79p2, and the element isolation region 50 are formed within the p-type semiconductor layer 62p.

[0151] The reset transistor 26 and the overflow transistor 28 are located on the first surface s21 of the semiconductor substrate 62A. Each of the reset transistor 26 and the overflow transistor 28 is an N-channel MOSFET formed on the p-type semiconductor layer 62p.

[0152] The p-type impurity region 79p2 functions as a well contact region of the p-type semiconductor layer 62p. A p-well voltage Vp is applied to the p-type semiconductor layer 62p via the p-type impurity region 79p2. The p-well voltage Vp applied to the p-type semiconductor layer 61p and the p-well voltage Vp applied to the p-type semiconductor layer 62p may be the same or different.

[0153] As shown in Figure 15, the wiring layer 62B includes an insulating layer 53, an interlayer insulating layer 62i, a plurality of wirings, a plurality of contact plugs cps, and gates 26e and 28e. The plurality of wirings, the plurality of contact plugs cps, and gates 26e and 28e are formed in the interlayer insulating layer 62i. In addition, some of the contact plugs cps penetrate the insulating layer 53 for connection to the semiconductor substrate 62A.

[0154] The interlayer insulating layer 62i is laminated on the semiconductor substrate 62A via the insulating layer 53. Although not shown in Figure 15, the interlayer insulating layer 62i has a laminated structure of multiple insulating layers. Wiring included in the wiring layer 62B is arranged on each of the multiple insulating layers.

[0155] In pixel 10E, the photoelectric conversion unit 12 is located on the first surface s11 side of the semiconductor substrate 61A. The photoelectric conversion unit 12 is arranged on the insulating layer 52 on the first surface s11 of the semiconductor substrate 61A.

[0156] Furthermore, in pixel 10E, the through-electrode 81 penetrates the semiconductor substrate 61A and the insulating layers 51 and 52. In the example shown in Figure 15, the upper end of the through-electrode 81 is in contact with and connected to the pixel electrode 12a. The lower end of the through-electrode 81 is in contact with and connected to the wiring 84 within the interlayer insulating layer 61i. The through-electrode 81 is connected to the gate 22e via the wiring 84 and the contact plug cps. The through-electrode 81 is also connected to the n-type impurity region 73n via the wiring 84 and 86 and the contact plug cps.

[0157] In the pixel 10E, the pixel electrode 12a, through electrode 81, wiring 84 and 86, gates 22e and 28e, and n-type impurity region 73n of the photoelectric conversion unit 12 function as regions for accumulating signal charge generated by the photoelectric conversion unit 12.

[0158] In the example shown in Figure 15, the n-type impurity region 80n is electrically connected to the n-type impurity region 71n, which functions as the source and drain of the amplifying transistor 22 within the semiconductor substrate 61A. Therefore, parasitic capacitance caused by the through-electrode 81 is reduced, similar to the pixel 10 described above. Thus, the conversion gain of the imaging device can be improved.

[0159] As shown in Figure 15, wires 84 and 86 are electrically connected to the through electrode 81, gates 22e and 28e, and the n-type impurity region 73n. Wires 84 and 86 are examples of first wiring. Wires 85 and 87 are electrically connected to the n-type impurity region 71n. In Figure 15, the electrical connection between wire 85 and the n-type impurity region 71n, which is not shown in the cross-section shown in Figure 15, is schematically shown. Wires 85 and 87 are examples of second wiring. Wire 88 is electrically connected to the n-type impurity region 72n. Wire 88 is part of the vertical signal line 35 described above.

[0160] Wiring 84 and wiring 85 are arranged in the same layer such that they are the same distance from the semiconductor substrate 61A. Wiring 85 is adjacent to wiring 84 via an insulator that is part of the interlayer insulating layer 61i. The space between wiring 84 and wiring 85 is occupied by an insulator, and there are no conductors. Since wiring 85 is electrically connected to the n-type impurity region 71n, its potential fluctuates in sync with wiring 84, similar to the n-type impurity region 80n. Therefore, compared to the case where wiring 84 is adjacent to wiring other than wiring 85 (e.g., power wiring) where the potential difference with wiring 84 may be larger than that with wiring 85, the parasitic capacitance of wiring 84, which functions as a region for accumulating signal charge, can be reduced.

[0161] Wires 86, 87, and 88 are arranged in the same layer such that they are all the same distance from the semiconductor substrate 61A. In the example shown in Figure 15, wire 87 is located between wires 86 and 88. Wire 87 is adjacent to wire 86 via an insulator that is part of the interlayer insulating layer 61i. The space between wires 86 and 87 is occupied by an insulator, and there are no conductors. Since wire 87 is electrically connected to the n-type impurity region 71n, its potential fluctuates in sync with wire 86, similar to the n-type impurity region 80n. Therefore, compared to the case where wire 86 is adjacent to a wire that may have a larger potential difference from wire 87 (e.g., a power supply wire), the parasitic capacitance of wire 86, which functions as a region for accumulating signal charge, can be reduced. In addition, a portion of wire 87 overlaps with wire 84 in a plan view. This portion of wire 87 is adjacent to wire 84 via an insulator that is part of the interlayer insulating layer 61i. This reduces the parasitic capacitance of wire 84.

[0162] Furthermore, the multiple wirings included in the wiring layer 61B may include a second wiring that is electrically connected to the n-type impurity region 71n and adjacent to the through electrode 81 via an insulator.

[0163] Furthermore, in pixel 10E, the layout of the n-type impurity region electrically connected to the n-type impurity region 80n may be the same as that of pixels 10, 10B, or 10C.

[0164] Furthermore, pixel 10E may include a reset transistor 26D instead of the reset transistor 26, and may not include an overflow transistor 28. In this case, the n-type and p-type semiconductor substrate 62A are swapped. This makes it possible to discharge signal charge without using the overflow transistor 28, similar to pixel 10D.

[0165] Furthermore, in pixels 10, 10A, 10B, 10C, or 10D, a second wiring adjacent to the through electrode 81 or wiring 83 may be provided via an insulator.

[0166] [Modification 6] Next, we will describe a modified example 6 of Embodiment 1. In the following, we will focus on explaining the differences between Embodiment 1 and Modified Examples 1 to 5 of Embodiment 1, and will omit or simplify the explanation of the common points.

[0167] Figure 16 is a schematic cross-sectional view of the device structure of pixel 10F according to this modified example. Figure 16 is a cross-sectional view at the position corresponding to Figure 15.

[0168] The imaging device according to this modified example has a configuration in which the plurality of pixels 10 of the imaging device 100 according to Embodiment 1 are replaced with a plurality of pixels 10F. The circuit configuration of the pixels 10F is the same as, for example, the circuit configuration of the pixels 10 shown in Figure 2.

[0169] As shown in Figure 16, the pixel 10F in this modified example has a structure in which the first pixel substrate 61 is inverted vertically compared to the pixel 10E in Modification 5 of Embodiment 1. The layout within the pixel 10F is the same as the layout within the pixel 10E shown in Figures 13 and 14.

[0170] In pixel 10F, the wiring layer 61B is stacked on the first surface s11 side of the semiconductor substrate 61A. The photoelectric conversion unit 12 is stacked on the semiconductor substrate 61A via the wiring layer 61B. The n-type impurity regions 70n, 71n, and 72n, the p-type impurity region 79p1, and the element isolation region 50 are located on the first surface s11. The amplification transistor 22 and the address transistor 24 are located on the first surface s11.

[0171] In pixel 10F, the through-electrode 81 is electrically connected to the pixel electrode 12a of the photoelectric conversion unit 12 via wirings 84 and 86. In pixel 10F, the arrangement of impurity regions in the semiconductor substrate 61A and the arrangement of wiring in the wiring layer 61B are the same as in pixel 10E, so the conversion gain can be improved in the same way as in pixel 10E.

[0172] (Embodiment 2) Next, we will describe the imaging device according to Embodiment 2. In the following, we will focus on explaining the differences between Embodiment 1 and its various modifications, and will omit or simplify the explanation of the common points.

[0173] Figure 17 is a plan view showing an example of the wiring layout within a pixel 110 according to this embodiment. Figure 18 is a schematic cross-sectional view of the device structure of the pixel 110 according to this embodiment. Figure 18 is a cross-sectional view obtained when the pixel 110 is cut along the line XVIII-XVIII in Figure 17. Figure 17 schematically shows the layout of some of the wirings among the multiple wirings arranged in the wiring layer 63B when the pixel 110 is viewed along the thickness direction of the semiconductor substrate 63A. In Figure 17, the dotted rectangles indicate the arrangement of vias connected to the wirings. Also, Figure 17 shows the layouts corresponding to two adjacent pixels 110. Hereafter, two adjacent pixels 110 may be distinguished and referred to as pixel 110a and pixel 110b.

[0174] The imaging device according to this embodiment has a configuration in which the plurality of pixels 10 of the imaging device 100 according to Embodiment 1 are changed to a plurality of pixels 110.

[0175] As shown in Figure 18, the pixel 110 according to this embodiment differs from the pixel 10 according to Embodiment 1 mainly in that it includes a pixel substrate 63 instead of a pixel substrate 60, and does not include an n-type impurity region 80n, a through electrode 81, and an insulating layer 82. The circuit configuration of the pixel 110 is the same as the circuit configuration of the pixel 10 shown in Figure 2, except that, for example, a parasitic capacitance Cp is not formed between the through electrode 81 and the n-type impurity region 80n. In the example shown in Figure 18, the pixel substrate 63 is not laminated on the logic substrate 90, and the peripheral circuit 40 is formed, for example, in the region surrounding the imaging area on the pixel substrate 63. The pixel substrate 63 may be laminated on the logic substrate 90 on which the peripheral circuit 40 is formed.

[0176] The pixel substrate 63 is formed continuously, for example, over at least the entire imaging area. The pixel substrate 63 is shared by multiple pixels 110. The photoelectric conversion unit 12 is located above the pixel substrate 63.

[0177] The pixel substrate 63 includes a semiconductor substrate 63A and a wiring layer 63B. The semiconductor substrate 63A has a first surface s31 and a second surface s32 opposite to the first surface s31. The first surface s31 and the second surface s32 are the main surfaces of the semiconductor substrate 63A, perpendicular to the thickness direction of the semiconductor substrate 63A. In the example shown in Figure 18, the first surface s31 is the top surface of the semiconductor substrate 63A, and the second surface s32 is the bottom surface of the semiconductor substrate 63A. The wiring layer 63B is laminated on the first surface s31 side of the semiconductor substrate 63A. The photoelectric conversion unit 12 is laminated on the semiconductor substrate 63A via the wiring layer 63B. The amplification transistor 22, address transistor 24, and reset transistor 26 are located on the first surface s31. Although not shown in Figure 18, the overflow transistor 28 may also be located on the first surface s31. Furthermore, the photoelectric conversion unit 12 is located on the first surface s31 side of the semiconductor substrate 63A.

[0178] As shown in Figure 18, the semiconductor substrate 63A includes a support substrate 63s and a p-type semiconductor layer 63p. Here, a p-type silicon (Si) substrate is given as an example of the support substrate 63s. The p-type semiconductor layer 63p is a p-type well region in the semiconductor substrate 63A. The p-type semiconductor layer 63p is provided on the support substrate 63s. The p-type semiconductor layer 63p is the semiconductor layer on which the first surface s31 of the semiconductor layers included in the semiconductor substrate 63A is located.

[0179] As shown in Figure 18, the semiconductor substrate 63A includes n-type impurity regions 70n, 71n, 72n, 73n, and 74n, and an element isolation region 50. Although not shown in Figure 18, the semiconductor substrate 63A may include at least one of the n-type impurity region 75n and the p-type impurity region 79p. The n-type impurity regions 70n, 71n, 72n, 73n, 74n, and 75n, the p-type impurity region 79p, and the element isolation region 50 are located on the first surface s31. The n-type impurity regions 70n, 71n, 72n, 73n, 74n, and 75n, the p-type impurity region 79p, and the element isolation region 50 are formed within the p-type semiconductor layer 63p.

[0180] As shown in Figures 17 and 18, the wiring layer 63B includes an insulating layer 51, an interlayer insulating layer 63i, multiple wirings including wirings 121, 122, 123, 131 and 132, multiple contact plugs cps, and gates 22e, 24e and 26e. Although not shown in Figures 17 and 18, the wiring layer 63B may also include gate 28e. The multiple wirings, multiple contact plugs cps, and gates 22e, 24e, 26e and 28e are formed in the interlayer insulating layer 63i. Some of the multiple contact plugs cps penetrate the insulating layer 51 for connection to the semiconductor substrate 63A.

[0181] The interlayer insulating layer 63i is laminated on the semiconductor substrate 63A via the insulating layer 51. Although not shown in Figure 18, the interlayer insulating layer 63i has a laminated structure of multiple insulating layers. Wiring included in the wiring layer 63B is arranged on each of the multiple insulating layers.

[0182] In the pixel 110, the pixel electrode 12a, wiring 121, gates 22e and 28e, and the n-type impurity region 73n of the photoelectric conversion unit 12 function as regions for accumulating signal charge generated by the photoelectric conversion unit 12.

[0183] As shown in Figures 17 and 18, wiring 121 is electrically connected to gate 22e and n-type impurity region 73n. Wiring 121 is an example of a first wiring. Wiring 122 is electrically connected to n-type impurity region 71n. Wiring 122 is an example of a second wiring. Wiring 123 is electrically connected to n-type impurity region 72n via wiring not shown in Figure 18. Wiring 123 is part of the vertical signal line 35 described above. In the example shown in Figures 17 and 18, wiring 123a, which is part of the vertical signal line 35 connected to pixel 110a, and wiring 123b, which is part of the vertical signal line 35 connected to pixel 110b, are located within the interlayer insulating layer 63i. Wirings 131 and 132 are wirings with a fixed potential, such as power supply wiring.

[0184] Wires 121, 122, 123a, 123b, 131, and 132 are arranged in the same layer such that they are all the same distance from the semiconductor substrate 63A. In the examples shown in Figures 17 and 18, in a plan view, wire 122 is arranged to surround wire 121 on three sides. Part of wire 122 is located between wire 121 and wire 123a, and another part of wire 122 is located between wire 121 and wire 123b. Wire 122 is adjacent to wire 121 via an insulator that is part of the interlayer insulating layer 63i. The space between wire 121 and wire 122 is occupied by the insulator, and there are no conductors. Wire 122 is electrically connected to the n-type impurity region 71n, which functions as the source and drain of the amplifying transistor 22, and therefore its potential fluctuates in sync with wire 121. In other words, the potential difference between wire 121 and wire 122 does not become large. Therefore, compared to the case where wiring 121 is adjacent to wiring such as power wiring, where the potential difference with wiring 121 may be greater than that with wiring 122, the parasitic capacitance of wiring 121, which functions as a region for accumulating signal charge, can be reduced.

[0185] In this embodiment, the wiring 122 may be electrically connected to the n-type impurity region 72n instead of the n-type impurity region 71n. Also, the pixel 110 may include an amplifying transistor 22D, an addressing transistor 24D, and a resetting transistor 26D instead of the amplifying transistor 22, an addressing transistor 24, and a resetting transistor 26. In this case, the n-type and p-type in the semiconductor substrate 63A are swapped.

[0186] Furthermore, the wiring layout in pixel 110 is not limited to the example shown in Figure 17. Figure 19 is a plan view showing another example of the wiring layout within pixel 110 according to this embodiment. Figure 20 is a plan view showing yet another example of the wiring layout within pixel 110 according to this embodiment. Figures 19 and 20 schematically show the layout of some of the wirings among a plurality of wirings arranged in the wiring layer 63B when viewing pixel 110 along the thickness direction of the semiconductor substrate 63A. In Figures 19 and 20, the dotted rectangles indicate the arrangement of vias connected to the wiring.

[0187] In the example shown in Figure 19, wiring 133 is placed between wiring 122 and wiring 123b. Also, wiring 134 is placed between wiring 122 and wiring 123a. Wires 133 and 134 are wirings with a fixed potential, such as power supply wiring. At pixel 110a, wiring 133 can suppress capacitive coupling between wiring 122 and wiring 123b through which the signal of another pixel, pixel 110b, is propagated. At pixel 110b, wiring 134 can suppress capacitive coupling between wiring 122 and wiring 123a through which the signal of another pixel, pixel 110a, is propagated.

[0188] Furthermore, in the example shown in Figure 19, wiring 122 is placed between wiring 121 and wiring 133 so that wiring 133 is not adjacent to wiring 121. Also, wiring 122 is placed between wiring 121 and wiring 134 so that wiring 134 is not adjacent to wiring 121. This reduces the parasitic capacitance of wiring 121, which functions as a region for accumulating signal charge.

[0189] Furthermore, in the example shown in Figure 20, only wiring 133 is placed in pixel 110a, out of wiring 133 and wiring 134. Similarly, only wiring 134 is placed in pixel 110b, out of wiring 133 and wiring 134. In other words, wiring 133 or 134, which has a fixed potential, is placed between wiring 123a or 123b, through which signals from other pixels are propagated, and wiring 121. However, wiring 133 or 134, which has a fixed potential, is not placed between wiring 123a or 123b, through which signals from the current pixel are propagated, and wiring 121.

[0190] Furthermore, in the example shown in Figure 20, in pixel 110a, wiring 122 is located only on the wiring 123b side of wiring 121. Also, in pixel 110b, wiring 122 is located only on the wiring 123a side of wiring 121. This shortens the length of wiring 122 adjacent to wiring 121, further reducing the parasitic capacitance between wiring 121 and wiring 122, and further improving the conversion gain.

[0191] (Embodiment 3) Next, Embodiment 3 will be described. Embodiment 3 describes a camera system equipped with an imaging device according to the present disclosure.

[0192] Figure 21 is a block diagram showing an example of the configuration of the camera system 400 according to this embodiment.

[0193] As shown in Figure 21, the camera system 400 according to this embodiment comprises a lens optical system 601, an imaging device 602, a system controller 603, and a camera signal processing circuit 604. The camera system 400 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

[0194] The lens optical system 601 focuses light onto the imaging surface of the imaging device 602. The lens optical system 601 may include, for example, a lens group including an autofocus lens and a zoom lens, and an aperture. As the imaging device 602, for example, an imaging device according to any of the above-described embodiments 1, each of the modifications of embodiment 1, and embodiment 2 may be used.

[0195] The system controller 603 controls the entire camera system 400. The system controller 603 is, for example, a semiconductor integrated circuit, and a specific example is a CPU (Central Processing Unit).

[0196] The camera signal processing circuit 604 has the function of processing the output signal from the imaging device 602. The camera signal processing circuit 604 receives output data such as differential digital signals from the imaging device 602 and performs processing such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The camera signal processing circuit 604 is, for example, a DSP (Digital Signal Processor). The imaging device 602 and the camera signal processing circuit 604 may be realized as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). With such a configuration, the electronic device that includes the imaging device 602 as part can be made smaller.

[0197] (Other embodiments) The imaging apparatus and camera system relating to this disclosure have been described above based on embodiments, but this disclosure is not limited to these embodiments. Without departing from the spirit of this disclosure, various modifications to the embodiments that a person skilled in the art could conceive, as well as other forms constructed by combining some of the components of the embodiments, are also included in the scope of this disclosure.

[0198] For example, in the above embodiment, the potential of the charge storage node FD was reset by the reset transistor 26 or 26D, but is not limited to this. For example, the potential of the charge storage node FD may be reset via the photoelectric conversion unit 12 by a voltage applied to the counter electrode 12c. In this case, the imaging device does not need to be equipped with reset transistors 26 and 26D.

[0199] Furthermore, each of the above embodiments can be modified, replaced, added, or omitted in various ways within the scope of the claims or their equivalents. [Industrial applicability]

[0200] The imaging device relating to this disclosure is useful for, for example, image sensors and digital cameras. The imaging device relating to this disclosure can be used in medical cameras, robot cameras, security cameras, cameras mounted on vehicles, and the like. [Explanation of symbols]

[0201] 10, 10A, 10B, 10C, 10D, 10E, 10F, 110, 110a, 110b pixels 12 Photoelectric conversion unit 12a Pixel electrode 12b Photoelectric conversion layer 12c counter electrode 13 Shielding electrodes 14, 51, 52, 53, 82 Insulating layer 15 Color Filters 16 Microlenses 22, 22D Amplifying Transistors 22e, 24e, 26e, 28e gates 24, 24D Address Transistors 26, 26D Reset Transistor 28 Overflow Transistors 31. Accumulation control line 32, 38 power line 34 Address signal line 35 Vertical signal lines 36 Reset signal line 37 Reset voltage line 40 Peripheral Circuits 42 Vertical scanning circuit 44 Horizontal signal readout circuit 46 Control circuits 48 Voltage supply circuit 50 element isolation region 60, 60D, 63 pixel substrate 60A, 60AD, 61A, 62A, 63A Semiconductor Substrates 60B, 61B, 62B, 63B wiring layer 60i, 61i, 62i, 63i Interlayer Insulation Layer 60n n-type semiconductor layer 60p, 61p, 62p, 63p p-type semiconductor layer 61. First Pixel Substrate 62 Second Pixel Substrate 63s support board 70n, 71n, 72n, 73n, 74n, 75n, 76n, 77n, 79n, 80n n-type impurity region 70p, 71p, 72p, 73p, 74p, 79p, 79p1, 79p2, 80p p-type impurity region 81 Through electrode Wiring for 83, 84, 85, 86, 87, 88, 121, 122, 123, 123a, 123b, 131, 132, 133, 134 90 Logic board 100, 602 Imaging device 400 Camera System 601 Lens Optics 603 System Controller 604 Camera signal processing circuit CPS contact plug FD charge storage node s1, s11, s21, s31 1st page s2, s12, s22, s32 2nd side

Claims

1. A semiconductor substrate having a first surface and a second surface opposite to the first surface, A photoelectric conversion unit located on the first surface side of the semiconductor substrate, which converts light into signal charge, A through electrode that penetrates the semiconductor substrate and is electrically connected to the photoelectric conversion unit, A first transistor located on the first or second surface of the semiconductor substrate, including a gate electrically connected to the through electrode, which outputs a signal corresponding to the signal charge, An insulating layer covering the through electrode within the semiconductor substrate, Equipped with, The aforementioned semiconductor substrate is A first impurity region to which the signal output by the first transistor is input, A second impurity region with the same conductivity as the first impurity region covers the through electrode via the insulating layer, Includes, The first impurity region is electrically connected to the second impurity region within the semiconductor substrate. Imaging device.

2. The first impurity region functions as the source or drain of the first transistor. The imaging apparatus according to claim 1.

3. The system further comprises a second transistor connected in series with the first transistor, The first impurity region functions as the source or drain of the second transistor. The imaging apparatus according to claim 1.

4. The first transistor is located on the second surface of the semiconductor substrate, The imaging apparatus according to claim 1.

5. The semiconductor substrate includes a third impurity region having the same conductivity type as the first impurity region, which electrically connects the first impurity region and the second impurity region. The imaging apparatus according to claim 1.

6. At least a portion of the second impurity region overlaps with the first impurity region in a plan view. The imaging apparatus according to claim 1.

7. The semiconductor substrate further comprises a wiring layer laminated on the first or second surface, which includes a plurality of wirings, The plurality of wirings include a first wiring electrically connected to the through electrode and a second wiring electrically connected to the first impurity region. The second wiring is adjacent to the through electrode or the first wiring via an insulator. The imaging apparatus according to claim 1.

8. The semiconductor substrate is located on the second surface and includes a charge storage region for accumulating the signal charge, The imaging apparatus according to claim 1.

9. Semiconductor substrate and The semiconductor substrate is laminated with a wiring layer containing multiple wirings, A photoelectric conversion unit that converts light into signal charge, A charge storage region for accumulating the aforementioned signal charge, A first transistor includes a gate electrically connected to the charge storage region and outputs a signal corresponding to the signal charge, Equipped with, The semiconductor substrate includes a first impurity region to which the signal output by the first transistor is input. The plurality of wirings include a first wiring electrically connected to the gate of the first transistor and a second wiring electrically connected to the first impurity region. The second wiring is adjacent to the first wiring via an insulator. Imaging device.

10. The imaging device comprises the imaging device described in any one of claims 1 to 9. Camera system.

Images