Imaging device

Abstract

To provide an imaging device with reduced noise. [Solution] The imaging device comprises a plurality of pixels 24. Each of the plurality of pixels 24 includes a lower electrode 2, an upper electrode 5 positioned opposite the lower electrode 2, a photoelectric conversion layer 4 located between the lower electrode 2 and the upper electrode 5 and containing a donor semiconductor material and an acceptor semiconductor material that generates a signal charge, a charge blocking layer 3 located between the photoelectric conversion layer 4 and the lower electrode 2, and a charge storage region electrically connected to the lower electrode 2 and accumulating signal charges. When the thickness of the charge blocking layer 3 is D and the area of ​​the lower electrode 2 in a plan view is S, the condition D / √S≧0.07 is satisfied.

Description

Technical Field

[0001] The present disclosure relates to an imaging device.

Background Art

[0002] A stacked imaging device has been proposed as a MOS (Metal Oxide Semiconductor) type imaging device. In the stacked imaging device, a photoelectric conversion element including a photoelectric conversion layer is stacked above a semiconductor substrate, and charges generated by photoelectric conversion in the photoelectric conversion layer are collected by electrodes and stored in a charge storage region. For example, Patent Document 1 discloses a stacked imaging device that reads charges stored in a charge storage region using a CCD (Charge Coupled Device) circuit or a CMOS (Complementary MOS) circuit in a semiconductor substrate.

[0003] The photoelectric conversion element used in an imaging device may have a structure in which a plurality of functional layers such as a photoelectric conversion layer that absorbs light and generates signal charges and a charge blocking layer that suppresses charge injection from electrodes are stacked. For example, Patent Document 2 discloses an imaging device using a photoelectric conversion element having a structure in which a photoelectric conversion layer and a charge blocking layer are stacked.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] Imaging devices are used in a variety of environments. For example, imaging devices used in environments where brightness changes significantly, such as surveillance or in-vehicle applications, are required to capture high-quality images regardless of the environment. In other words, a wide dynamic range is crucial for the performance of an imaging device. The dynamic range is determined by the saturation signal amount and noise of the imaging device, and can be achieved by increasing the saturation signal amount and / or reducing the noise. Furthermore, reducing noise is also important in improving the quality of the captured image.

[0006] Therefore, this disclosure provides an imaging device with reduced noise. [Means for solving the problem]

[0007] An imaging device according to one aspect of the present disclosure comprises a plurality of pixels, each of which includes a first electrode, a second electrode positioned opposite the first electrode, a photoelectric conversion layer located between the first electrode and the second electrode and comprising a donor semiconductor material and an acceptor semiconductor material for generating a signal charge, an intermediate layer located between the photoelectric conversion layer and the first electrode, and a charge storage region electrically connected to the first electrode for accumulating the signal charge, wherein the thickness of the intermediate layer is D and the area of ​​the first electrode in a plan view is S, such that D / √S ≥ 0.07 is satisfied.

[0008] Furthermore, an imaging device according to one aspect of the present disclosure comprises a plurality of pixels, each of which includes a first electrode, a second electrode positioned opposite the first electrode, a photoelectric conversion layer located between the first electrode and the second electrode and comprising a donor semiconductor material and an acceptor semiconductor material for generating a signal charge, an intermediate layer located between the photoelectric conversion layer and the first electrode, and a charge storage region electrically connected to the first electrode for accumulating the signal charge, wherein the planar shape of the first electrode is a square, and when the thickness of the intermediate layer is D and the length of one side of the square in the planar shape of the first electrode is L, the condition D / L ≥ 0.07 is satisfied. [Effects of the Invention]

[0009] According to this disclosure, an imaging device with reduced noise can be provided. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a schematic cross-sectional view showing the configuration of a photoelectric conversion element according to an embodiment. [Figure 2] Figure 2 is an exemplary energy band diagram of a photoelectric conversion element according to an embodiment. [Figure 3] Figure 3 is a schematic cross-sectional view showing the configuration of another photoelectric conversion element according to an embodiment. [Figure 4] Figure 4 shows an example of the circuit configuration of an imaging device according to an embodiment. [Figure 5] Figure 5 is a schematic cross-sectional view showing the device structure of a pixel in an imaging device according to an embodiment. [Figure 6] Figure 6 is a plan view showing an exemplary electrode layout in an imaging device. [Figure 7] Figure 7 illustrates the case where an intermediate level occurs in a photoelectric conversion element having the energy band configuration shown in Figure 2. [Figure 8] Figure 8 is an illustrative diagram showing the distribution of the amount of charge accumulated in the charge storage node. [Figure 9] Figure 9 shows the relationship between D / √S and random noise in the imaging devices of the examples and comparative examples. [Figure 10] Figure 10 shows the relationship between D / L and random noise in the imaging devices of the examples and comparative examples. [Modes for carrying out the invention]

[0011] (Knowledge that led to one form of this disclosure) The inventors of the present invention have found the following problems in order to provide an imaging device with reduced noise.

[0012] When using a structure in which a plurality of functional layers are stacked as a photoelectric conversion element provided in an imaging device, it is necessary to optimize the energy level design for the materials contained in each layer. For example, the energy level of the material contained in the photoelectric conversion layer that absorbs light and generates signal charges greatly affects the sensitivity of the imaging device. In addition, the energy level of the material contained in the intermediate layer provided between the photoelectric conversion layer such as the charge blocking layer and the electrode greatly affects the extraction efficiency of the signal charges. In a photoelectric conversion element, near the interface between adjacent layers, an intermediate level is likely to occur due to the influence of film formation conditions and the polarization effect between materials. In particular, since the roles of the intermediate layer located between the photoelectric conversion layer and the electrode and the photoelectric conversion layer are different in the photoelectric conversion element, it is difficult to predict the occurrence of the intermediate level when designing the energy level of the material. The existence of the intermediate level makes it easier for electrons to be excited to the intermediate level, and charges are more likely to be generated by thermal excitation even in the dark state, separately from the signal charges generated by light. In the case of an imaging device having a plurality of pixels, charges are generated in the region near the interface between the adjacent layers existing in each pixel and are taken into the electrodes of a specific pixel with a certain probability, which can be a cause of noise.

[0013] The present disclosure has been made based on such findings, and provides an imaging device with reduced noise by reducing the influence of charges generated by thermal excitation.

[0014] (Summary of the Present Disclosure) As an overview of one aspect of the present disclosure, an example of the imaging device according to the present disclosure is shown below.

[0015] The imaging device according to the first aspect of the present disclosure includes a plurality of pixels. Each of the plurality of pixels includes a first electrode, a second electrode disposed opposite to the first electrode, a photoelectric conversion layer located between the first electrode and the second electrode and including a donor semiconductor material and an acceptor semiconductor material for generating signal charges, an intermediate layer located between the photoelectric conversion layer and the first electrode, and a charge storage region electrically connected to the first electrode for storing the signal charges. When the thickness of the intermediate layer is D and the area of the first electrode in plan view is S, D / √S≧0.07 is satisfied.

[0016] According to the configuration of this aspect, an imaging device with reduced noise can be realized.

[0017] Specifically, the charges generated by thermal excitation near the interface between the photoelectric conversion layer and the intermediate layer depend on the size of the interface. That is, the larger the area of the first electrode related to the substantial interface size in plan view, the larger the amount of charges generated by thermal excitation. Since the noise is proportional to the square root of the amount of charges stored in the charge storage region, the noise increases as the charges generated by thermal excitation increase. On the other hand, if the thickness of the intermediate layer is large, it becomes difficult for the charges generated by thermal excitation to be taken into the first electrode. Generally, the charges generated in the photoelectric conversion layer conduct by hopping between the materials included in each layer, are taken out to the first electrode, and are stored in the charge storage region. In this case, the charges generated by thermal excitation will conduct by hopping at least the thickness of the intermediate layer, but the probability of deactivation increases as the hopping conduction distance becomes longer, and the contribution of the charges generated by thermal excitation to the noise becomes smaller. Therefore, the noise can be reduced by adjusting the relationship between the thickness of the intermediate layer and the area of the first electrode. When the thickness of the intermediate layer is D and the area of the first electrode is S, sufficient noise reduction can be achieved if D / √S≧0.07.

[0018] Also, for example, the imaging device according to the second aspect of the present disclosure is the imaging device according to the first aspect, and the thickness of the intermediate layer is 10 nm or more.

[0019] This makes it possible to suppress leakage current from the first electrode to the photoelectric conversion layer, even if a large potential difference occurs between the first electrode and the second electrode.

[0020] Furthermore, for example, an imaging apparatus according to a third aspect of the present disclosure is an imaging apparatus according to the first or second aspect, wherein the signal charge is a hole, the intermediate layer includes a first semiconductor material, and the difference between the ionization potential of the first semiconductor material included in the intermediate layer and the ionization potential of the donor semiconductor material included in the photoelectric conversion layer is 1 eV or less.

[0021] Furthermore, for example, an imaging device according to a fourth aspect of the present disclosure is an imaging device according to the first or second aspect, wherein the signal charge is an electron, the intermediate layer includes a first semiconductor material, and the difference between the electron affinity of the first semiconductor material included in the intermediate layer and the electron affinity of the acceptable semiconductor material included in the photoelectric conversion layer is 1 eV or less.

[0022] As a result, the signal charge generated in the photoelectric conversion layer during light irradiation is more easily transported from the photoelectric conversion layer to the first electrode via the intermediate layer, improving the efficiency of signal charge extraction.

[0023] Furthermore, for example, an imaging device according to a fifth aspect of the present disclosure is an imaging device according to any one of the first to fourth aspects, wherein each of the plurality of pixels is located between the second electrode and the photoelectric conversion layer and further comprises a charge blocking layer.

[0024] This makes it possible to suppress leakage current from the second electrode to the photoelectric conversion layer.

[0025] Furthermore, for example, the imaging apparatus according to the sixth aspect of this disclosure is the imaging apparatus according to the fifth aspect, wherein the thickness of the charge blocking layer is 5 nm or more.

[0026] This makes it possible to suppress leakage current from the second electrode to the photoelectric conversion layer, even if a large potential difference occurs between the first electrode and the second electrode.

[0027] Furthermore, for example, an imaging device according to the seventh aspect of this disclosure is an imaging device according to the fifth or sixth aspect, wherein the signal charge is a hole, the charge blocking layer includes a second semiconductor material, and the difference between the electron affinity of the second semiconductor material included in the charge blocking layer and the electron affinity of the acceptable semiconductor material included in the photoelectric conversion layer is 1 eV or less.

[0028] Furthermore, for example, an imaging apparatus according to the eighth aspect of this disclosure is an imaging apparatus according to the fifth or sixth aspect, wherein the signal charge is an electron, the charge blocking layer includes a second semiconductor material, and the difference between the ionization potential of the second semiconductor material included in the charge blocking layer and the ionization potential of the donor semiconductor material included in the photoelectric conversion layer is 1 eV or less.

[0029] As a result, when light is irradiated, charges of opposite polarity to the signal charge generated in the photoelectric conversion layer are more easily transported from the photoelectric conversion layer to the second electrode via the charge blocking layer. This makes it difficult for charges of opposite polarity to the signal charge generated in the photoelectric conversion layer to recombine with the signal charge, thus suppressing a decrease in sensitivity.

[0030] Furthermore, for example, the imaging device according to the ninth aspect of this disclosure is an imaging device according to any one of the first to eighth aspects, wherein D / √S≧0.14 is satisfied.

[0031] This makes it possible to create an imaging device with even lower noise levels.

[0032] Furthermore, for example, the imaging device according to the tenth aspect of this disclosure is an imaging device according to any one of the first to ninth aspects, wherein D / √S≧0.21 is satisfied.

[0033] This makes it possible to create an imaging device with even lower noise levels.

[0034] Furthermore, for example, an imaging device according to an eleventh aspect of the present disclosure comprises a plurality of pixels, each of which comprises a first electrode, a second electrode positioned opposite the first electrode, a photoelectric conversion layer located between the first electrode and the second electrode and comprising a donor semiconductor material and an acceptor semiconductor material for generating a signal charge, an intermediate layer located between the photoelectric conversion layer and the first electrode, and a charge storage region electrically connected to the first electrode for accumulating the signal charge, wherein the planar shape of the first electrode is a square, and when the thickness of the intermediate layer is D and the length of one side of the square in the planar shape of the first electrode is L, the condition D / L ≥ 0.07 is satisfied.

[0035] This configuration also makes it possible to realize an imaging device with reduced noise, similar to the imaging device according to the first embodiment.

[0036] The embodiments will be described below with reference to the drawings.

[0037] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure. Furthermore, any components in the following embodiments that are not described in an independent claim will be described as optional components.

[0038] Furthermore, the figures are not necessarily strictly accurate. In each figure, substantially identical components are denoted by the same reference numerals, and redundant explanations may be omitted or simplified.

[0039] Furthermore, in this specification, terms indicating relationships between elements such as verticals, terms indicating the shape of elements such as rectangles, and numerical ranges are not expressions that represent only strict meanings, but also expressions that include substantially equivalent ranges.

[0040] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception, but rather are used as terms defined by the relative positional relationship based on the stacking order in the stacked configuration. It should be noted that terms such as "upper" and "lower" are used solely to specify the relative arrangement of components and are not intended to limit the orientation when the imaging device is in use. Moreover, the terms "upper" and "lower" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close proximity and touching each other.

[0041] Furthermore, in this specification, "plan view" means a view taken from a direction perpendicular to the main surface of the photoelectric conversion layer, unless otherwise specified. Also, in this specification, the main surface is the surface perpendicular to the thickness direction, and the direction perpendicular to the main surface of the photoelectric conversion layer coincides with the thickness direction of each layer or electrode in the photoelectric conversion element.

[0042] Furthermore, in this specification, electromagnetic waves in general, including visible light, infrared rays, and ultraviolet rays, will be referred to as "light" for convenience.

[0043] (Embodiment) The following describes this embodiment.

[0044] [Photoelectric conversion element] First, the photoelectric conversion element provided in the imaging device according to this embodiment will be described using Figure 1. The photoelectric conversion element according to this embodiment is a charge readout type photoelectric conversion element. Figure 1 is a schematic cross-sectional view showing the configuration of the photoelectric conversion element 10 according to this embodiment.

[0045] As shown in Figure 1, the photoelectric conversion element 10 is supported on a support substrate 1 and comprises a pair of electrodes, an upper electrode 5 and a lower electrode 2, a photoelectric conversion layer 4 located between the upper electrode 5 and the lower electrode 2, and a charge blocking layer 3 located between the lower electrode 2 and the photoelectric conversion layer 4. In this embodiment, the lower electrode 2 is an example of a first electrode, and the upper electrode 5 is an example of a second electrode. The charge blocking layer 3 is an example of an intermediate layer.

[0046] The photoelectric conversion element 10 is used in a configuration in which, for example, light transmitted through the upper electrode 5 is incident on the photoelectric conversion layer 4.

[0047] The following describes each component of the photoelectric conversion element 10 according to this embodiment.

[0048] The support substrate 1 can be any substrate commonly used to support photoelectric conversion elements, such as a glass substrate, quartz substrate, semiconductor substrate, or plastic substrate.

[0049] The lower electrode 2 and the upper electrode 5 are membrane-like electrodes positioned opposite each other.

[0050] The lower electrode 2 collects the signal charge generated in the photoelectric conversion layer 4. The lower electrode 2 is formed from a metal, metal nitride, metal oxide, or conductive polysilicon. Examples of metals include aluminum, copper, titanium, and tungsten. An example of a method for imparting conductivity to polysilicon is doping it with impurities.

[0051] The upper electrode 5 is positioned opposite the lower electrode 2, with the photoelectric conversion layer 4 in between. The upper electrode 5 is a transparent electrode formed from, for example, a transparent conductive material. Examples of materials for the upper electrode 5 include transparent conductive oxide (TCO), ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), AZO (Aluminum-doped Zinc Oxide), FTO (Florine-doped Tin Oxide), SnO2, and TiO2. The upper electrode 5 may also be fabricated by combining TCO and metallic materials such as aluminum (Al) and gold (Au), either individually or in combination, depending on the desired transmittance.

[0052] Furthermore, the materials for the lower electrode 2 and the upper electrode 5 are not limited to the conductive materials described above, and other materials may be used. For example, the lower electrode 2 may be a transparent electrode.

[0053] Various methods can be used to fabricate the lower electrode 2 and the upper electrode 5, depending on the materials used. For example, when using ITO, chemical reaction methods such as electron beam method, sputtering method, resistance heating deposition method, sol-gel method, or coating of indium tin oxide dispersion may be used. In this case, after forming the ITO film, the lower electrode 2 and the upper electrode 5 may be subjected to further treatments such as UV-ozone treatment or plasma treatment.

[0054] The photoelectric conversion layer 4 generates electrons and holes by absorbing light. One of these electrons or holes is used as a signal charge. In other words, the photoelectric conversion layer 4 converts light into a signal charge.

[0055] The photoelectric conversion layer 4 includes, for example, a donor semiconductor material and an acceptor semiconductor material. The photoelectric conversion layer 4 is fabricated using, for example, an organic semiconductor material. The photoelectric conversion layer 4 can be fabricated using wet methods such as coating methods such as spin coating, or dry methods such as vacuum deposition. Vacuum deposition is a method in which the layer material is vaporized by heating under vacuum and deposited on the substrate. The charge blocking layer 3 can also be fabricated using the same method as the photoelectric conversion layer 4.

[0056] Furthermore, the photoelectric conversion layer 4 is a mixed film of a bulk heterostructure containing, for example, a donor semiconductor material such as a donor organic semiconductor material and an acceptor semiconductor material such as an acceptor organic semiconductor material. The photoelectric conversion layer 4 may also have a laminated structure in which a layer of donor semiconductor material and a layer of acceptor semiconductor material are stacked.

[0057] The photoelectric conversion layer 4 is easily formed as a thin film by including a donor organic semiconductor material and an acceptor organic semiconductor material. Specific examples of the donor organic semiconductor material and the acceptor organic semiconductor material are given below.

[0058] Examples of donor organic semiconductor materials include triarylamine compounds, benzidine compounds, pyrazoline compounds, styrylamine compounds, hydrazone compounds, triphenylmethane compounds, carbazole compounds, polysilane compounds, thiophene compounds, phthalocyanine compounds, naphthalocyanine compounds, subphthalocyanine compounds, cyanine compounds, merocyanine compounds, oxonol compounds, polyamine compounds, indole compounds, pyrrole compounds, pyrazole compounds, biphenyl compounds, terphenyl compounds, polyarylene compounds, condensed aromatic carbocyclic compounds, and metal complexes having nitrogen-containing heterocyclic compounds as ligands.

[0059] Examples of condensed aromatic carbocyclic compounds include naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, tetracene derivatives, pyrene derivatives, perylene derivatives, and fluorantene derivatives.

[0060] Examples of acceptable organic semiconductor materials include fullerenes, fullerene derivatives, condensed aromatic carbocyclic compounds, 5- to 7-membered heterocyclic compounds containing nitrogen, oxygen, and sulfur atoms, polyarylene compounds, fluorene compounds, cyclopentadiene compounds, silyl compounds, and metal complexes having nitrogen-containing heterocyclic compounds as ligands.

[0061] Examples of fullerenes include C60 fullerene and C70 fullerene.

[0062] Examples of fullerene derivatives include PCBM (phenyl C61 methyl butyrate) and ICBA (indene C60 bis adduct).

[0063] Examples of 5- to 7-membered heterocyclic compounds containing nitrogen, oxygen, and sulfur atoms include pyridine, pyrazine, pyrimidine, pyridazine, triazine, quinoline, quinoxaline, quinazoline, phthalazine, cinnoline, isoquinoline, pteridine, acridine, phenazine, phenanthroline, tetrazole, pyrazole, imidazole, thiazole, oxazole, indazole, benzimidazole, benzodriazole, benzoxazole, benzothiazole, carbazole, purine, triazolopyridazine, triazolopyrimidine, tetrazaindene, oxadiazole, imidazopyridine, pyrrolidine, pyrrolopyridine, thiadiazolopyridine, dibenzazepine, and tripenzuazepine.

[0064] The donor organic semiconductor material and acceptor organic semiconductor material are not limited to the examples above. Any organic compound that can be formed as a photoelectric conversion layer by either a dry or wet method, including low-molecular-weight compounds and high-molecular-weight compounds, may be used as the donor organic semiconductor material and acceptor organic semiconductor material constituting the photoelectric conversion layer 4.

[0065] Furthermore, the photoelectric conversion layer 4 may contain semiconductor materials other than organic semiconductor materials as donor semiconductor materials and acceptor semiconductor materials. The photoelectric conversion layer 4 may contain silicon semiconductors, compound semiconductors, quantum dots, perovskite materials, carbon nanotubes, etc., or a mixture of two or more of these as semiconductor materials.

[0066] The photoelectric conversion element 10 according to this embodiment includes a charge blocking layer 3 provided between the lower electrode 2 and the photoelectric conversion layer 4, as described above. The charge blocking layer 3 is in contact with, for example, the lower electrode 2 and the photoelectric conversion layer 4.

[0067] The charge blocking layer 3 includes, for example, a first semiconductor material. The first semiconductor material is, for example, an organic semiconductor material. The organic semiconductor material is, for example, the donor organic semiconductor material or the acceptor organic semiconductor material described above. The first semiconductor material forming the charge blocking layer 3 is not limited to an organic semiconductor material, but may be an oxide semiconductor or a nitride semiconductor, or a composite material thereof. The material forming the charge blocking layer 3 may be a metal oxide such as aluminum oxide.

[0068] Furthermore, the charge blocking layer 3 may have a structure in which multiple layers are stacked. In this case, the materials constituting the multiple layers may be the same or may be different from each other.

[0069] The thickness of the charge blocking layer 3 is set according to the size of the lower electrode 2, as described later, but is, for example, 10 nm or more. From the viewpoint of effectively suppressing dark current and noise, the thickness of the charge blocking layer 3 may be 100 nm or more, 150 nm or more, or 200 nm or more. Furthermore, from the viewpoint of suppressing a decrease in sensitivity, the thickness of the charge blocking layer 3 may be 1000 nm or less, or 600 nm or less.

[0070] Figure 2 is an exemplary energy band diagram for the photoelectric conversion element shown in Figure 1. In Figure 2, the energy bands of each layer are shown as rectangles. Also in Figure 2, electrons are shown as black circles and holes as white circles, schematically illustrating some of the movement of electrons and holes.

[0071] The photoelectric conversion layer 4 generates excitons internally upon irradiation with light. The generated excitons diffuse through the photoelectric conversion layer 4 and are separated into electrons and holes at the interface between the acceptor semiconductor material and the donor semiconductor material. The separated electrons and holes move to the lower electrode 2 side or the upper electrode 5 side, respectively, according to the electric field applied to the photoelectric conversion layer 4. When a voltage is applied between the upper electrode 5 and the lower electrode 2 such that the potential of the upper electrode 5 is higher than the potential of the lower electrode 2, electrons move to the upper electrode 5 side and holes move to the lower electrode 2 side. When the photoelectric conversion element 10 is used in an imaging device, for example, holes are collected by the lower electrode 2 and stored as signal charges in a charge storage node electrically connected to the lower electrode 2. The charge storage node is an example of a charge storage region that stores signal charges collected by the lower electrode 2. In this way, the photoelectric conversion layer 4 converts light into signal charges, and the lower electrode 2 collects the signal charges generated in the photoelectric conversion layer 4. Furthermore, the upper electrode 5 collects charges of opposite polarity to the signal charge. Below, we will explain the case where holes move to the lower electrode 2 side and holes are used as the signal charge. Note that electrons may also be used as the signal charge. In this case, a voltage is applied between the upper electrode 5 and the lower electrode 2 such that the potential of the upper electrode 5 is lower than the potential of the lower electrode 2, causing holes to move to the upper electrode 5 side and electrons to move to the lower electrode 2 side.

[0072] Here, among the electron-hole pairs generated by absorbing light, the material that donates the electron to the other material is called the donor material, and the material that accepts the electron is called the acceptor material. In this embodiment, the donor semiconductor material is the donor material, and the acceptor semiconductor material is the acceptor material. When using two different types of organic semiconductor materials, which one becomes the donor material and which becomes the acceptor material is generally determined by the relative positions of the HOMO (Highest-Occupied-Molecular-Orbital) and LUMO (Lowest-Unoccupied-Molecular-Orbital) energy levels of the two organic semiconductor materials at the contact interface. In Figure 2, the upper end of the rectangle showing the energy band is the LUMO energy level, and the lower end is the HOMO energy level. The energy difference between the vacuum level and the LUMO energy level is called the electron affinity. The energy difference between the vacuum level and the HOMO energy level is called the ionization potential. In Figure 2, the electron affinity and ionization potential are greater the lower the point is located.

[0073] As shown in Figure 2, of the two semiconductor materials contained in the photoelectric conversion layer 4, the one with a shallower LUMO energy level, i.e., lower electron affinity, is the donor semiconductor material 4A. The other semiconductor material with a deeper LUMO energy level, i.e., higher electron affinity, is the acceptor semiconductor material 4B. Note that in Figure 2, the energy bands of the donor semiconductor material 4A and the acceptor semiconductor material 4B are shown shifted horizontally; this is for clarity and does not mean that the donor semiconductor material 4A and the acceptor semiconductor material 4B are distributed separately in the thickness direction of the photoelectric conversion layer 4. Also, the energy band of the acceptor semiconductor material 4B is shown as a dashed rectangle; this is also for clarity and is not intended to distinguish it from a solid rectangle.

[0074] The ionization potential of the donor semiconductor material 4A is smaller than, for example, the ionization potential of the acceptor semiconductor material 4B.

[0075] The charge blocking layer 3 is configured to transport signal charges and block charges of the opposite polarity to the signal charges. When holes are used as signal charges, as shown in Figure 2, the electron affinity of the charge blocking layer 3 is less than or equal to the electron affinity of the acceptor semiconductor material 4B of the photoelectric conversion layer 4. Furthermore, the electron affinity of the charge blocking layer 3 is smaller than the work function of the lower electrode 2. As a result, the charge blocking layer 3 suppresses the injection of charges (specifically electrons) of the opposite polarity to the signal charges from the lower electrode 2 to the photoelectric conversion layer 4. Consequently, noise signals due to dark current that adversely affect the signal-to-noise ratio (SNR) can be reduced. Note that if the charge blocking layer 3 has a structure in which multiple layers are stacked, the electron affinity of at least one of the layers is less than or equal to the electron affinity of the acceptor semiconductor material 4B of the photoelectric conversion layer 4, and is also smaller than the work function of the lower electrode 2.

[0076] Furthermore, for example, the difference between the ionization potential of the charge blocking layer 3 and the ionization potential of the donor semiconductor material 4A is 1 eV or less. This improves the efficiency of extracting signal charges (specifically holes) by the lower electrode 2. Note that if the charge blocking layer 3 has a structure in which multiple layers are stacked, for example, the difference between the ionization potential of any of the layers and the ionization potential of the donor semiconductor material 4A is 1 eV or less.

[0077] In Figure 2, the electron affinity and ionization potential of the charge blocking layer 3 are, for example, the electron affinity and ionization potential of the first semiconductor material contained in the charge blocking layer 3.

[0078] Furthermore, when electrons are used as the signal charge, the ionization potential of the charge blocking layer 3 is greater than, for example, the ionization potential of the donor semiconductor material 4A of the photoelectric conversion layer 4, in order to suppress the injection of holes from the lower electrode 2 into the photoelectric conversion layer 4. Also, when electrons are used as the signal charge, the ionization potential of the charge blocking layer 3 is greater than the work function of the lower electrode 2.

[0079] Furthermore, when electrons are used as the signal charge, the difference between the electron affinity of the charge blocking layer 3 and the electron affinity of the acceptor semiconductor material 4B is 1 eV or less. This improves the efficiency of extracting the signal charge (specifically electrons) by the lower electrode 2.

[0080] [Another example of a photoelectric conversion element] Furthermore, the photoelectric conversion element according to this embodiment may also include a charge blocking layer between the upper electrode 5 and the photoelectric conversion layer 4. Figure 3 is a schematic cross-sectional view showing the configuration of another photoelectric conversion element 11 according to this embodiment. As shown in Figure 3, the photoelectric conversion element 11 further includes a charge blocking layer 6 between the upper electrode 5 and the photoelectric conversion layer 4, in addition to the configuration of the photoelectric conversion element 10. The charge blocking layer 6 is in contact with, for example, the upper electrode 5 and the photoelectric conversion layer 4.

[0081] The charge blocking layer 6 includes, for example, a second semiconductor material. The second semiconductor material is, for example, an organic semiconductor material. The organic semiconductor material is, for example, the donor organic semiconductor material or the acceptor organic semiconductor material described above. The second semiconductor material forming the charge blocking layer 6 is not limited to an organic semiconductor material, but may be an oxide semiconductor or a nitride semiconductor, or a composite material thereof. The material forming the charge blocking layer 6 may be a metal oxide such as aluminum oxide. The charge blocking layer 6 may contain the same material as the charge blocking layer 3.

[0082] Furthermore, the charge blocking layer 6 may have a structure in which multiple layers are stacked. In this case, the materials constituting the multiple layers may be the same or may be different from each other.

[0083] The thickness of the charge blocking layer 6 is, for example, 5 nm or more. From the viewpoint of effectively suppressing dark current and noise, the thickness of the charge blocking layer 6 may be 10 nm or more, 20 nm or more, or 30 nm or more. Furthermore, from the viewpoint of suppressing a decrease in sensitivity, the thickness of the charge blocking layer 6 may be 500 nm or less, or 300 nm or less.

[0084] The charge blocking layer 6 is configured to transport charges of opposite polarity to the signal charge, thereby blocking the signal charge. When holes are used as the signal charge, the ionization potential of the charge blocking layer 6 is greater than or equal to the ionization potential of, for example, the donor semiconductor material 4A of the photoelectric conversion layer 4. Furthermore, the ionization potential of the charge blocking layer 6 is greater than the work function of the upper electrode 5. As a result, the charge blocking layer 6 suppresses the injection of signal charge (specifically holes) from the upper electrode 5 into the photoelectric conversion layer 4. Consequently, noise signals caused by dark current, which adversely affect the signal-to-noise ratio, can be reduced. Note that if the charge blocking layer 6 has a structure in which multiple layers are stacked, the ionization potential of at least one of the layers is greater than or equal to the ionization potential of the donor semiconductor material 4A of the photoelectric conversion layer 4, and is also greater than the work function of the upper electrode 5.

[0085] Furthermore, for example, the difference between the electron affinity of the charge blocking layer 6 and the electron affinity of the acceptor semiconductor material 4B is 1 eV or less. This improves the transport efficiency of charges (specifically electrons) with opposite polarity to the signal charge to the upper electrode 5. Note that if the charge blocking layer 6 has a structure in which multiple layers are stacked, for example, the difference between the electron affinity of any of the layers and the electron affinity of the acceptor semiconductor material 4B is 1 eV or less.

[0086] The electron affinity and ionization potential of the charge blocking layer 6 are, for example, the electron affinity and ionization potential of the second semiconductor material contained in the charge blocking layer 6. The second semiconductor material contained in the charge blocking layer 6 may be the same as the donor semiconductor material 4A contained in the photoelectric conversion layer 4.

[0087] Furthermore, when electrons are used as the signal charge, the electron affinity of the charge blocking layer 6 is less than or equal to the electron affinity of the acceptor semiconductor material 4B of the photoelectric conversion layer 4, in order to suppress the injection of electrons from the upper electrode 5 into the photoelectric conversion layer 4. Also, when electrons are used as the signal charge, the electron affinity of the charge blocking layer 6 is smaller than the work function of the upper electrode 5.

[0088] Furthermore, when electrons are used as the signal charge, the difference between the ionization potential of the charge blocking layer 6 and the ionization potential of the donor semiconductor material 4A is 1 eV or less. This improves the efficiency of charge transfer to the upper electrode 5 with the opposite polarity to the signal charge (specifically, holes). Also, when electrons are used as the signal charge, the second semiconductor material included in the charge blocking layer 6 may be the same material as the acceptor semiconductor material 4B included in the photoelectric conversion layer 4.

[0089] [Imaging device] Next, the imaging device according to this embodiment will be described with reference to Figures 4 and 5. Figure 4 is a diagram showing an example of the circuit configuration of the imaging device 100, which is equipped with a photoelectric conversion unit 10A using the photoelectric conversion element 10 shown in Figure 1. Figure 5 is a schematic cross-sectional view showing an example of the device structure of a pixel 24 in the imaging device 100 according to this embodiment. Note that the auxiliary electrode 7 shown in Figure 5 is omitted from the illustration in Figure 4.

[0090] As shown in Figures 4 and 5, the imaging device 100 according to this embodiment comprises a semiconductor substrate 40, a charge detection circuit 35 provided on the semiconductor substrate 40, a photoelectric conversion unit 10A provided on the semiconductor substrate 40, and a plurality of pixels 24, each having a charge storage node 34 electrically connected to the charge detection circuit 35 and the photoelectric conversion unit 10A. The photoelectric conversion unit 10A of the plurality of pixels 24 is composed of the photoelectric conversion element 10 described above. In other words, each of the plurality of pixels 24 has a lower electrode 2, an upper electrode 5, a photoelectric conversion layer 4, and a charge blocking layer 3. In this embodiment, the charge storage node 34 is an example of a charge storage region. The photoelectric conversion unit 10A may be composed of a photoelectric conversion element 11. In other words, each of the plurality of pixels 24 may further have a charge blocking layer 6 in addition to the above configuration.

[0091] In the photoelectric conversion unit 10A, the upper electrode 5, photoelectric conversion layer 4, charge blocking layer 3, and lower electrode 2 are arranged in that order from the side where light is incident on the imaging device 100. In this embodiment, light that has passed through the upper electrode 5 is incident on the photoelectric conversion layer 4. Also in this embodiment, the side where light is incident on the imaging device 100 is opposite to the semiconductor substrate 40 side of the photoelectric conversion unit 10A. Furthermore, in this embodiment, the side where light is incident is the upper side.

[0092] The charge storage node 34 stores the signal charge generated by the photoelectric conversion unit 10A, and the charge detection circuit 35 detects the signal charge stored in the charge storage node 34. The charge detection circuit 35 provided on the semiconductor substrate 40 may be provided on the semiconductor substrate 40 or directly provided in the semiconductor substrate 40.

[0093] As shown in Figure 4, the imaging device 100 comprises a plurality of pixels 24 and peripheral circuits. The imaging device 100 is, for example, an image sensor implemented on a single-chip integrated circuit and has a pixel array PA including a plurality of pixels 24 arranged in two dimensions.

[0094] Multiple pixels 24 are arranged in two dimensions, i.e., in the row and column directions, on the semiconductor substrate 40 to form a photosensitive area which is a pixel area. Figure 4 shows an example in which the pixels 24 are arranged in a 2x2 matrix. The arrangement of pixels 24 is not limited to 2x2, and the number of rows and columns of pixels 24 is not particularly limited. Note that in Figure 4, for the sake of illustration, the circuit for individually setting the sensitivity of the pixels 24 (e.g., a pixel electrode control circuit) is omitted from the illustration. The imaging device 100 may also be a line sensor. In that case, the multiple pixels 24 may be arranged in one dimension. Note that in this specification, the row direction and column direction refer to the directions in which the rows and columns extend, respectively. That is, in Figure 4, the vertical direction on the paper is the column direction, and the horizontal direction is the row direction.

[0095] As shown in Figures 4 and 5, each pixel 24 has a photoelectric conversion unit 10A, a charge detection circuit 35, and a charge storage node 34 electrically connected to the photoelectric conversion unit 10A and the charge detection circuit 35. The charge detection circuit 35 includes an amplification transistor 21, a reset transistor 22, and an address transistor 23.

[0096] The photoelectric conversion unit 10A comprises a lower electrode 2 provided as a pixel electrode and an upper electrode 5 provided as a counter electrode facing the lower electrode 2. The entire photoelectric conversion unit 10A does not need to be an independent element for each pixel 24; a part of the photoelectric conversion unit 10A may span multiple pixels 24. A voltage for applying a predetermined bias voltage is supplied to the upper electrode 5 via the counter electrode signal line 26.

[0097] The lower electrode 2 is connected to the gate electrode 21G of the amplifying transistor 21, and the signal charge collected by the lower electrode 2 is stored in a charge storage node 34 located between the lower electrode 2 and the gate electrode 21G of the amplifying transistor 21. For example, if the signal charge is a hole, the charge storage node 34 is electrically connected to the lower electrode 2 and stores the holes among the excitons generated in the photoelectric conversion layer 4.

[0098] A voltage corresponding to the amount of signal charge stored in the charge storage node 34 is applied to the gate electrode 21G of the amplifying transistor 21. The amplifying transistor 21 amplifies this voltage, and it is selectively read out as a signal voltage by the address transistor 23. The reset transistor 22 has its source / drain electrodes connected to the lower electrode 2 via the charge storage node 34 and resets the signal charge stored in the charge storage node 34. In other words, the reset transistor 22 resets the potential of the gate electrode 21G and the lower electrode 2 of the amplifying transistor 21.

[0099] To selectively perform the above-described operations on multiple pixels 24, the imaging device 100 has a power supply line 31, a vertical signal line 27, an address signal line 36, and a reset signal line 37, each of which is connected to a pixel 24. Specifically, the power supply line 31 is connected to the source / drain electrodes of the amplification transistor 21, the vertical signal line 27 is connected to the source / drain electrodes of the address transistor 23, the address signal line 36 is connected to the gate electrode 23G of the address transistor 23, and the reset signal line 37 is connected to the gate electrode 22G of the reset transistor 22.

[0100] The peripheral circuitry includes a voltage supply circuit 19, a vertical scanning circuit 25, a horizontal signal readout circuit 20, multiple column signal processing circuits 29, multiple load circuits 28, and multiple differential amplifiers 32.

[0101] The voltage supply circuit 19 is electrically connected to the upper electrode 5 via the counter electrode signal line 26. The voltage supply circuit 19 applies a voltage to the upper electrode 5, thereby creating a potential difference between the upper electrode 5 and the lower electrode 2; in other words, it applies a voltage between the upper electrode 5 and the lower electrode 2. When the lower electrode 2 collects holes as signal charges, the voltage supply circuit 19 supplies a voltage to the upper electrode 5 such that the potential of the upper electrode 5 becomes higher than the potential of the lower electrode 2. When the lower electrode 2 collects electrons as signal charges, the voltage supply circuit 19 supplies a voltage to the upper electrode 5 such that the potential of the upper electrode 5 becomes lower than the potential of the lower electrode 2.

[0102] The sensitivity of the photoelectric conversion unit 10A is controlled by switching the voltage supplied from the voltage supply circuit 19 to the upper electrode 5 between a plurality of different voltages. The voltage supply circuit 19 is not limited to a specific power supply circuit, and may be a circuit that generates a predetermined voltage, or a circuit that converts a voltage supplied from another power source to a predetermined voltage. The imaging device 100 does not necessarily have a voltage supply circuit 19. For example, the upper electrode 5 may be supplied with voltage from an external power source.

[0103] The vertical scanning circuit 25 is connected to the address signal line 36 and the reset signal line 37, and selects multiple pixels 24 arranged in each row on a row-by-row basis, reads out the signal voltage, and resets the potential of the lower electrode 2. The power supply wiring 31, which is a source follower power supply, supplies a predetermined power supply voltage to each pixel 24. The horizontal signal readout circuit 20 is electrically connected to multiple column signal processing circuits 29. The column signal processing circuits 29 are electrically connected to the pixels 24 arranged in each column via vertical signal lines 27 corresponding to each column. The load circuit 28 is electrically connected to each vertical signal line 27. The load circuit 28 and the amplifying transistor 21 form a source follower circuit.

[0104] Multiple differential amplifiers 32 are provided, corresponding to each row. The inverting input terminals of the differential amplifiers 32 are connected to the corresponding vertical signal lines 27. The output terminals of the differential amplifiers 32 are connected to the pixels 24 via feedback lines 33 corresponding to each row.

[0105] The vertical scanning circuit 25 applies a row selection signal to the gate electrode 23G of the address transistor 23 via the address signal line 36, which controls the on / off state of the address transistor 23. As a result, the row to be read is scanned and selected. A signal voltage is read from the pixel 24 of the selected row to the vertical signal line 27. The vertical scanning circuit 25 also applies a reset signal to the gate electrode 22G of the reset transistor 22 via the reset signal line 37, which controls the on / off state of the reset transistor 22. As a result, the row of pixel 24 to be reset is selected. The vertical signal line 27 transmits the signal voltage read from the pixel 24 selected by the vertical scanning circuit 25 to the column signal processing circuit 29.

[0106] The column signal processing circuit 29 performs noise suppression signal processing, such as correlated double sampling, and analog-to-digital conversion (AD conversion).

[0107] The horizontal signal readout circuit 20 sequentially reads signals from multiple column signal processing circuits 29 to a horizontal common signal line.

[0108] The differential amplifier 32 is connected to the drain electrode of the reset transistor 22 via a feedback line 33. Therefore, the differential amplifier 32 receives the output value of the address transistor 23 at its inverting input terminal. The differential amplifier 32 performs feedback operation so that the gate potential of the amplifying transistor 21 becomes a predetermined feedback voltage. At this time, the output voltage value of the differential amplifier 32 is, for example, a positive voltage of 0V or near 0V. The feedback voltage refers to the output voltage of the differential amplifier 32.

[0109] As shown in Figure 5, the pixel 24 includes a semiconductor substrate 40, a charge detection circuit 35, a photoelectric conversion unit 10A, an auxiliary electrode 7, and a charge storage node 34 (see Figure 4).

[0110] The semiconductor substrate 40 may be an insulating substrate or the like, with a semiconductor layer provided on the surface on which the photosensitive region is formed, for example, a p-type silicon substrate. The semiconductor substrate 40 has impurity regions 21D, 21S, 22D, 22S, and 23S, and element isolation regions 41 for electrical isolation between pixels 24. The impurity regions 21D, 21S, 22D, 22S, and 23S are, for example, n-type regions. Here, the element isolation region 41 is provided between the impurity region 21D and the impurity region 22D. This suppresses leakage of signal charge accumulated at the charge storage node 34. The element isolation region 41 is formed, for example, by ion implantation of acceptors under predetermined implantation conditions.

[0111] The impurity regions 21D, 21S, 22D, 22S, and 23S are, for example, diffusion regions formed within the semiconductor substrate 40. As shown in Figure 5, the amplifying transistor 21 includes the impurity regions 21S and 21D and the gate electrode 21G. The impurity regions 21S and 21D function, for example, as the source region and drain region of the amplifying transistor 21. The channel region of the amplifying transistor 21 is formed between the impurity regions 21S and 21D.

[0112] Similarly, the address transistor 23 includes an impurity region 23S and an impurity region 21S, and a gate electrode 23G connected to the address signal line 36. In this example, the amplification transistor 21 and the address transistor 23 are electrically connected to each other by sharing the impurity region 21S. The impurity region 23S functions, for example, as the source region of the address transistor 23. The impurity region 23S has a connection to the vertical signal line 27 shown in Figure 4.

[0113] An interlayer insulating layer 50 is laminated on the semiconductor substrate 40 so as to cover the amplification transistor 21, the address transistor 23, and the reset transistor 22. In Figure 5, for the sake of clarity, the cross-sectional area of ​​the interlayer insulating layer 50 is omitted.

[0114] Furthermore, a wiring layer (not shown) may be placed within the interlayer insulating layer 50. The wiring layer may be formed from a metal such as copper, and may include wiring such as the vertical signal line 27 described above as part of its structure. The number of insulating layers within the interlayer insulating layer 50 and the number of layers included in the wiring layer placed within the interlayer insulating layer 50 can be arbitrarily set.

[0115] Within the interlayer insulating layer 50 are a contact plug 53 connected to the gate electrode 21G of the amplifying transistor 21, a contact plug 54 connected to the impurity region 22D of the reset transistor 22, a contact plug 51 connected to the lower electrode 2, and wiring 52 connecting contact plugs 51, 54, and 53. This electrically connects the impurity region 22D of the reset transistor 22 to the gate electrode 21G of the amplifying transistor 21. In the configuration illustrated in Figure 5, the contact plugs 51, 53, and 54, the wiring 52, the gate electrode 21G of the amplifying transistor 21, and the impurity region 22D of the reset transistor 22 constitute at least a portion of the charge storage node 34.

[0116] The charge detection circuit 35 detects the signal charge collected by the lower electrode 2 and outputs a signal voltage. The charge detection circuit 35 includes an amplifying transistor 21, a reset transistor 22, and an address transistor 23, and is formed on a semiconductor substrate 40.

[0117] The amplifying transistor 21 is formed within a semiconductor substrate 40 and includes an impurity region 21D and an impurity region 21S that function as a drain electrode and a source electrode, respectively, a gate insulating layer 21X formed on the semiconductor substrate 40, and a gate electrode 21G formed on the gate insulating layer 21X.

[0118] The reset transistor 22 is formed within the semiconductor substrate 40 and includes an impurity region 22D and an impurity region 22S that function as a drain electrode and a source electrode, respectively, a gate insulating layer 22X formed on the semiconductor substrate 40, and a gate electrode 22G formed on the gate insulating layer 22X.

[0119] The address transistor 23 is formed within the semiconductor substrate 40 and includes impurity regions 21S and 23S that function as drain and source electrodes, respectively, a gate insulating layer 23X formed on the semiconductor substrate 40, and a gate electrode 23G formed on the gate insulating layer 23X. The impurity region 21S is connected in series with the amplifying transistor 21 and the address transistor 23.

[0120] The photoelectric conversion unit 10A described above is arranged on the interlayer insulating layer 50. In other words, in this embodiment, a plurality of pixels 24 constituting the pixel array PA are formed on the semiconductor substrate 40. The plurality of pixels 24 arranged two-dimensionally on the semiconductor substrate 40 form a photosensitive region. The charge blocking layer 3, the photoelectric conversion layer 4, and the upper electrode 5 are formed, for example, across a plurality of pixels 24. On the other hand, the lower electrode 2 is provided for each pixel 24 and is electrically isolated from the lower electrode 2 of other adjacent pixels 24 by being spatially separated from the lower electrode 2 of other pixels 24. As described above, the upper electrode 5 has a connection to a counter electrode signal line 26 connected to the voltage supply circuit 19. Therefore, it is possible to apply a voltage of a desired magnitude to a plurality of pixels 24 all at once from the voltage supply circuit 19 via the counter electrode signal line 26. Note that if a voltage of a desired magnitude can be applied from the voltage supply circuit 19, the upper electrode 5 may be provided separately for each pixel 24. Similarly, the photoelectric conversion layer 4 and the charge blocking layer 3 may be provided separately for each pixel 24.

[0121] The dimensions of the lower electrode 2 in the photoelectric conversion section 10A, such as the length L of one side, and the thickness D of the charge blocking layer 3 will be described later. As shown in Figure 5, the thickness D of the charge blocking layer 3 is also the shortest distance between the lower electrode 2 and the photoelectric conversion layer 4.

[0122] Here, the layout of the lower electrode 2, which is one of the multiple pixel electrodes of the imaging device 100, will be described. Figure 6 is a plan view showing an exemplary electrode layout in the imaging device 100. Figure 6 is a plan view when the components above the lower electrode 2 and auxiliary electrode 7 are viewed through. Also, in Figure 6, for ease of viewing, the lower electrode 2 and auxiliary electrode 7 are given the same shading as the lower electrode 2 and auxiliary electrode 7 shown in the cross-section of Figure 5.

[0123] The pixel electrode region 24A shown in Figure 6 corresponds to a single pixel 24 in a plan view. In the example shown in Figure 6, the pixel electrode region 24A is provided with a lower electrode 2 and an auxiliary electrode 7.

[0124] As shown in Figure 6, the lower electrodes 2 are arranged, for example, in an array. The auxiliary electrodes 7 are positioned between adjacent lower electrodes 2 in a plan view. In the illustrated example, the auxiliary electrodes 7 surround the lower electrodes 2 in a plan view. Specifically, the auxiliary electrodes 7 are arranged in a grid in a plan view, with the lower electrodes 2 positioned within each grid. The auxiliary electrodes 7 are formed collectively, for example, across multiple pixels 24, and all pixels 24 are at the same potential. The auxiliary electrodes 7 may be provided separately for each pixel 24, or separately for each pixel block consisting of two or more pixels 24 from among the multiple pixels 24.

[0125] In the example shown in Figure 6, the plan view shape of the lower electrode 2 is square, but the plan view shape of the lower electrode 2 is not particularly limited. The plan view shape of the lower electrode 2 may be a polygon such as a rectangle, hexagon, or octagon.

[0126] The auxiliary electrode 7 is connected to, for example, a voltage supply circuit or ground (not shown in the figure) and is maintained at a predetermined potential. The auxiliary electrode 7 and the lower electrode 2 are electrically isolated. The potential of the auxiliary electrode 7 is, for example, a fixed potential, but may be variable.

[0127] The auxiliary electrode 7 is provided to suppress electrical color mixing. Between pixels with significantly different amounts of signal charge stored in the charge storage node 34, the potential difference in the charge storage node 34 becomes large, causing mutual influence and degrading resolution, etc. The auxiliary electrode 7 reduces the mutual influence between adjacent pixels.

[0128] Furthermore, if the signal charge is a hole, the potential of the auxiliary electrode 7 is set to be higher than, for example, the potential of the charge storage node 34 when the signal charge is reset. This suppresses the movement of signal charge to adjacent pixels and allows for highly efficient extraction of signal charge generated near the auxiliary electrode 7, thereby improving sensitivity. The potential of the auxiliary electrode 7 may also be set to be lower than the potential of the charge storage node 34 when the signal charge is reset. In this case as well, signal charge can be collected at the auxiliary electrode 7, and the movement of signal charge to adjacent pixels can be suppressed.

[0129] The auxiliary electrode 7 is formed from a metal, metal nitride, metal oxide, or conductive polysilicon. Examples of metals include aluminum, copper, titanium, and tungsten. An example of a method for imparting conductivity to polysilicon is doping it with impurities. The auxiliary electrode 7 may be made of the same material as the lower electrode 2.

[0130] Referring again to Figure 5, a color filter 60 is formed above the photoelectric conversion unit 10A, and a microlens 61 is formed above it. The color filter 60 is formed, for example, as an on-chip color filter by patterning, and a photosensitive resin in which dyes or pigments are dispersed is used. The microlens 61 is formed, for example, as an on-chip microlens, and an ultraviolet photosensitive material is used.

[0131] The imaging device 100 can be manufactured using general semiconductor manufacturing processes. In particular, when a silicon substrate is used as the semiconductor substrate 40, it can be manufactured using various silicon semiconductor processes.

[0132] The imaging device 100 may operate in a rolling shutter manner, for example, in which multiple pixels 24 are sequentially exposed row by row and the signal is read out, or it may operate in a global shutter manner, in which the exposure period of multiple pixels 24 is unified. When operating in a rolling shutter manner, the voltage supply circuit 19 continues to supply a voltage to the upper electrode 5 that causes sensitivity in the photoelectric conversion unit 10A during imaging, for example, and the signal charge is read out sequentially row by row. When operating in a global shutter manner, the voltage supply circuit 19 supplies a voltage to the upper electrode 5 that allows imaging with the desired sensitivity during the exposure period, and supplies a voltage to the upper electrode 5 that does not cause sensitivity in the photoelectric conversion unit 10A during the non-exposure period. Therefore, the photoelectric conversion efficiency of multiple pixels 24 during the exposure period is different from the photoelectric conversion efficiency of multiple pixels 24 during the non-exposure period, and specifically, it is higher than the photoelectric conversion efficiency of multiple pixels 24 during the non-exposure period. This exposure period is the period for accumulating signal charge in the charge storage node 34. Furthermore, during the non-exposure period, the signal charge accumulated in the charge storage node 34 during the exposure period is read out sequentially for each pixel row. Note that the readout operation of the imaging device 100 is not limited to this operation; known readout operations of imaging devices may be applied.

[0133] [Thickness of the charge blocking layer and size of the lower electrode] In the imaging device 100 according to this embodiment, noise can be reduced by having a predetermined relationship between the thickness of the charge blocking layer 3 and the size of the lower electrode 2.

[0134] First, we will explain the factors that cause noise in the imaging device 100.

[0135] Figure 7 illustrates the occurrence of intermediate energy levels in a photoelectric conversion element 10 having the energy band configuration shown in Figure 2. Near the interface between the charge blocking layer 3 and the photoelectric conversion layer 4, intermediate energy levels are likely to occur due to the influence of the film deposition conditions and polarization between materials. As shown in Figure 7, intermediate energy levels occur, for example, in the acceptor semiconductor material 4B contained in the photoelectric conversion layer 4.

[0136] Comparing the energy difference between the HOMO energy level of the donor semiconductor material 4A and the LUMO energy level of the acceptor semiconductor material 4B in the photoelectric conversion layer 4, the energy difference between the HOMO energy level of the donor semiconductor material 4A and the intermediate energy level is small. Therefore, due to the presence of the intermediate energy level, electrons and holes are more easily generated in the photoelectric conversion layer 4 via the intermediate energy level, even with thermal energy which is normally small compared to light energy.

[0137] When the signal charge is a hole, electrons generated by thermal energy are extracted to the upper electrode 5 via the acceptor semiconductor material 4B. Holes generated by thermal energy are also extracted to the lower electrode 2 via the donor semiconductor material 4A and the charge blocking layer 3. The holes extracted to the lower electrode 2 are stored in the charge storage node 34, and the variation in the amount of charge stored in the charge storage node 34 increases according to the average value of the charge, becoming a source of noise. This noise is a type of shot noise, a random noise proportional to the square root of the average value of the charge. In the following, among the charges generated via the intermediate level, charges of the same polarity as the signal charge, such as the holes described above, may be referred to as noise charges.

[0138] Figure 8 illustrates the distribution of the amount of charge accumulated in the charge storage node 34. In Figure 8, the horizontal axis represents the amount of charge accumulated in the charge storage node 34. The vertical axis represents the number of charge storage nodes 34 that accumulated the amount of charge shown on the horizontal axis when charge is accumulated in multiple charge storage nodes 34 under the same conditions, or the number of times the amount of charge shown on the horizontal axis was accumulated in the charge storage node 34 when charge is accumulated in the charge storage node 34 multiple times at regular intervals under the same conditions.

[0139] Furthermore, in Figure 8, the solid line graph exemplifies the distribution when the amount of charge accumulated in the charge storage node 34 is large. Also, in Figure 8, the dashed line graph exemplifies the distribution when the amount of charge accumulated in the charge storage node 34 is small. Here, as described above, the variability of the amount of charge is proportional to the square root of the average value of the amount of charge, so as the average value on the horizontal axis decreases, the distribution also narrows. Thus, noise is reduced.

[0140] Intermediate energy levels tend to occur near the interface between the charge blocking layer 3 and the photoelectric conversion layer 4. Therefore, the amount of noise charge generated via intermediate energy levels depends on the size of the interface between the charge blocking layer 3 and the photoelectric conversion layer 4. Consequently, in each pixel 24, the amount of noise charge generated via intermediate energy levels depends on the size of the effective region of the photoelectric conversion layer 4 and charge blocking layer 3 from which the charge can be extracted by the lower electrode 2. In each pixel 24, since the photoelectric conversion layer 4 and charge blocking layer 3 are stacked over the entire surface of the lower electrode 2, the size of the effective region of the photoelectric conversion layer 4 and charge blocking layer 3 is determined by the size of the lower electrode 2 in a plan view. For example, in each pixel 24, the larger the area of ​​the lower electrode 2 in a plan view, the more likely the amount of noise charge accumulated in the charge storage node 34 is to increase, and this variation is represented by a physical quantity calculated based on the square root of the amount of noise charge.

[0141] Furthermore, some of the noise charge generated via the intermediate level recombines with a charge of the opposite polarity to the noise charge and becomes inactive. In this case, the longer the distance to which the noise charge is extracted to the lower electrode 2, that is, the greater the thickness of the charge blocking layer 3, the easier it becomes for the noise charge to combine with a charge of the opposite polarity to the noise charge, and as a result, the amount of noise charge accumulated in the charge storage node 34 decreases.

[0142] Thus, the variation in the amount of noise charge generated via the intermediate level and accumulated in the charge storage node 34 depends on the area of ​​the lower electrode 2 in a plan view and the thickness of the charge blocking layer 3. Therefore, an imaging device 100 with reduced noise can be realized by satisfying a predetermined condition in the ratio of the area of ​​the lower electrode 2 in a plan view to the thickness of the charge blocking layer 3. Specifically, in the imaging device 100, if the thickness of the charge blocking layer 3 is D and the area of ​​the lower electrode 2 in a plan view is S, then an imaging device 100 with reduced noise can be realized by satisfying D / √S≧0.07. In other words, in the imaging device 100, the thickness D of the charge blocking layer 3 is 7% or more of the square root of the area S of the lower electrode 2. Furthermore, from the viewpoint of reducing noise, in the imaging device 100, D / √S≧0.14 may be satisfied, and D / √S≧0.21 may also be satisfied. In the example shown in Figure 6, the planar shape of the lower electrode 2 is a square. Therefore, if L is the length of one side of the square in the planar shape of the lower electrode 2, the imaging device 100 satisfies D / L ≥ 0.07. Furthermore, from the viewpoint of reducing noise, the imaging device 100 may also satisfy D / L ≥ 0.14 or D / L ≥ 0.21.

[0143] Furthermore, from the viewpoint of suppressing the decrease in electric field strength applied to the photoelectric conversion unit 10A and maintaining the sensitivity of the photoelectric conversion unit 10A, the upper limits of D / √S and D / L may be 0.50 or 0.25. In other words, D / √S≦0.50 and D / L≦0.50 may be satisfied, and D / √S≦0.25 and D / L≦0.25 may be satisfied.

[0144] Furthermore, the impact of providing the auxiliary electrode 7 on noise is small. As mentioned above, when the signal charge is a hole, for example, the potential of the auxiliary electrode 7 is set to be higher than the potential of the charge storage node 34 where the signal charge has been reset. In other words, most of the charge generated in the photoelectric conversion unit 10A is extracted to the lower electrode 2 regardless of the presence or absence of the auxiliary electrode 7. Therefore, the same applies to the noise charge generated via the intermediate level, and the impact of providing the auxiliary electrode 7 on noise is small.

[0145] Next, referring to Figure 4, we will explain the saturation signal amount of the imaging device 100 and the dynamic range, which is the ratio of the saturation signal amount to the noise. Here, we will explain the case where holes are used as the signal charge.

[0146] In Figure 4, as described above, the holes generated by the photoelectric conversion unit 10A are stored in the charge storage node 34. As holes accumulate, the potential of the charge storage node 34 rises. In other words, in this case, the maximum potential corresponding to the amount of charge that the charge storage node 34 can hold becomes the saturation signal amount in the imaging device 100. Generally, a voltage amplitude of about 3V is allowed in the charge storage node 34, which corresponds to the gate voltage of the amplification transistor 21. In that case, for example, if the conversion gain is 50μV / e - In the imaging device, 6e - Even when noise occurs, a dynamic range of 80 dB, equivalent to that of the human eye, can be secured. In the imaging device 100 according to this embodiment, as described above, noise charges generated via intermediate levels are less likely to accumulate in the charge storage node 34, thus reducing noise and enabling a wide dynamic range. [Examples]

[0147] The imaging apparatus according to this disclosure will be specifically described in the following examples, but this disclosure is not limited in any way to the following examples. Specifically, an imaging apparatus according to this disclosure and an imaging apparatus for characteristic comparison were fabricated and noise was measured.

[0148] (Fabrication of imaging device) Imaging devices for the examples and comparative examples were fabricated.

[0149] [Comparative Example 1] First, in the device structure of the pixel 24 and the layout of the lower electrode 2 shown in Figures 5 and 6, an interlayer insulating layer 50 was laminated onto the semiconductor substrate 40 on which the charge detection circuit 35 was formed, and the lower electrode 2 connected to the charge detection circuit 35 via a charge storage node 34 was formed on the interlayer insulating layer 50 using TiN. Furthermore, the length of one side L of the square shape of the lower electrode 2 in plan view was set to 2.1 μm. Therefore, the area S of the lower electrode 2 in plan view was 4.41 μm². 2 That is the case.

[0150] Next, a charge-blocking layer 3 was formed on the lower electrode 2 by vacuum deposition of 9,9′-[1,1′-Biphenyl]-4,4′-diylbis[3,6-bis(1,1-dimethylethyl)]-9H-carbazole. The thickness D of this charge-blocking layer was set to 50 nm.

[0151] Next, a photoelectric conversion layer 4 was formed on the charge blocking layer 3 by co-depositing subphthalocyanine, a donor semiconductor material, and fullerene C60, an acceptor semiconductor material, using a vacuum deposition method. The subphthalocyanine used had boron (B) as the central metal, with chloride ions coordinated to B as ligands.

[0152] Next, an ITO film was formed on the photoelectric conversion layer 4 as the upper electrode 5 by sputtering, and then an Al2O3 film was formed on the upper electrode 5 as a sealing film by atomic layer deposition to obtain the imaging device of Comparative Example 1. In the imaging device of Comparative Example 1, D / L = D / √S = 0.024.

[0153] [Example 1] Except for setting the thickness D of the charge blocking layer 3 to 150 nm, the same procedure as in Comparative Example 1 was performed to obtain the imaging device in Example 1. In the imaging device in Example 1, D / L = D / √S = 0.071.

[0154] [Example 2] Except for setting the thickness D of the charge blocking layer 3 to 300 nm, the same process as in Comparative Example 1 was performed to obtain the imaging device in Example 2. In the imaging device in Example 2, D / L = D / √S = 0.14.

[0155] [Example 3] Except for setting the thickness D of the charge blocking layer 3 to 450 nm, the same procedure as in Comparative Example 1 was followed to obtain the imaging device in Example 3. In the imaging device in Example 3, D / L = D / √S = 0.21.

[0156] (Measurement of random noise) In the imaging apparatus of the examples and comparative examples, the output detected by the charge detection circuit 35 of each pixel 24 was acquired in order to evaluate the noise. Specifically, with no light incident on the imaging apparatus, the output detected by the charge detection circuit 35 was acquired based on the amount of charge accumulated in the charge storage node 34 after a predetermined period of time had elapsed since the potential of the charge storage node 34 of each pixel 24 was reset. At this time, a voltage of -1V was applied between the lower electrode 2 and the upper electrode 5, with the potential of the lower electrode 2 as the reference. In other words, a voltage was applied between the lower electrode 2 and the upper electrode 5 such that the potential of the upper electrode 5 was lower than the potential of the lower electrode 2. Then, the standard deviation of the output from each pixel 24 was calculated as random noise.

[0157] Figure 9 shows the relationship between D / √S and random noise in the imaging devices of the examples and comparative examples. Figure 10 shows the relationship between D / L and random noise in the imaging devices of the examples and comparative examples. In Figures 9 and 10, the vertical axis represents random noise. The random noise value on the vertical axis is normalized to 1 when the random noise value corresponds to a dynamic range of 80 dB, which corresponds to the human eye, relative to the saturation signal amount of the imaging devices in the examples and comparative examples. The dynamic range in this case is 20log 10 This is (saturation signal amount / random noise). Also, in Figure 9, the horizontal axis is D / √S, and in Figure 10, the horizontal axis is D / L.

[0158] As shown in Figures 9 and 10, in imaging devices that satisfy D / √S≧0.07 and D / L≧0.07, such as the imaging devices in Examples 1 to 3, the random noise of the imaging device is reduced, and since the random noise is 1 or less, it is possible to achieve a wide dynamic range of 80 dB or more, which corresponds to the human eye.

[0159] Thus, in the imaging apparatus according to this disclosure, as in the imaging apparatuses of Examples 1 to 3, a noise-reduced imaging apparatus can be realized by satisfying D / √S≧0.07 and D / L≧0.07. This is thought to be because, as mentioned above, even if noise charge is generated via the intermediate level, noise charge is less likely to accumulate in the charge storage node 34.

[0160] The imaging apparatus relating to this disclosure has been described above based on embodiments and examples, but this disclosure is not limited to these embodiments and examples. Without departing from the spirit of this disclosure, various modifications to the embodiments and examples that a person skilled in the art could conceive of, as well as other forms constructed by combining some of the components of the embodiments and examples, are also included in the scope of this disclosure. [Industrial applicability]

[0161] The imaging device described herein can be applied to various camera systems and sensor systems, including medical cameras, surveillance cameras, in-vehicle cameras, rangefinder cameras, microscope cameras, drone cameras, and robot cameras. [Explanation of Symbols]

[0162] 1. Support substrate 2 Lower electrode 3, 6 Charge blocking layer 4. Photoelectric conversion layer 4A Donor semiconductor materials 4B Acceptable semiconductor materials 5 Upper electrode 7 Auxiliary electrode 10, 11 Photoelectric conversion elements 10A Photoelectric Conversion Unit 19 Voltage supply circuit 20 Horizontal signal readout circuit 21 Amplifying transistors 22 Reset transistor 23 Address Transistors 21D, 21S, 22D, 22S, 23S impurity region 21G, 22G, 23G gate temperature 21X, 22X, 23X gate insulation layer 24 pixels 24A Pixel electrode region 25 Vertical scanning circuit 26 Opposite electrode signal line 27 Vertical signal lines 28 Load circuit 29-column signal processing circuit 31 Power wiring 32 Differential Amplifiers 33 Feedback Line 34 Charge Storage Nodes 35 Charge detection circuit 36 Address signal lines 37 Reset signal line 40 Semiconductor substrates 41 Element isolation region 50 interlayer insulating layer 51, 53, 54 Contact plugs 52 Wiring 60 Color Filters 61 Microlenses 100 Imaging device

Claims

1. Equipped with multiple pixels, Each of the aforementioned plurality of pixels is First electrode and, A second electrode is positioned opposite the first electrode, A photoelectric conversion layer located between the first electrode and the second electrode, comprising a donor semiconductor material and an acceptor semiconductor material, which generates a signal charge, An intermediate layer located between the photoelectric conversion layer and the first electrode, It has a charge storage region that is electrically connected to the first electrode and stores the signal charge, When the thickness of the intermediate layer is D and the area of ​​the first electrode in a plan view is S, D / √S ≥ 0.07 The condition is met. Imaging device.

2. The thickness of the aforementioned intermediate layer is 10 nm or more. The imaging apparatus according to claim 1.

3. The aforementioned signal charge is a hole, The aforementioned intermediate layer includes a first semiconductor material, The difference between the ionization potential of the first semiconductor material contained in the intermediate layer and the ionization potential of the donor semiconductor material contained in the photoelectric conversion layer is 1 eV or less. The imaging apparatus according to claim 1 or 2.

4. The aforementioned signal charge is an electron, The aforementioned intermediate layer includes a first semiconductor material, The difference between the electron affinity of the first semiconductor material contained in the intermediate layer and the electron affinity of the acceptor semiconductor material contained in the photoelectric conversion layer is 1 eV or less. The imaging apparatus according to claim 1 or 2.

5. Each of the plurality of pixels is located between the second electrode and the photoelectric conversion layer and further has a charge blocking layer. The imaging apparatus according to claim 1.

6. The thickness of the charge blocking layer is 5 nm or more. The imaging apparatus according to claim 5.

7. The aforementioned signal charge is a hole, The charge blocking layer comprises a second semiconductor material, The difference between the electron affinity of the second semiconductor material contained in the charge blocking layer and the electron affinity of the acceptor semiconductor material contained in the photoelectric conversion layer is 1 eV or less. The imaging apparatus according to claim 5 or 6.

8. The aforementioned signal charge is an electron, The charge blocking layer comprises a second semiconductor material, The difference between the ionization potential of the second semiconductor material contained in the charge blocking layer and the ionization potential of the donor semiconductor material contained in the photoelectric conversion layer is 1 eV or less. The imaging apparatus according to claim 5 or 6.

9. D / √S≧0.14 is satisfied, The imaging apparatus according to any one of claims 1, 2, 5, and 6.

10. D / √S≧0.21 is satisfied, The imaging apparatus according to any one of claims 1, 2, 5, and 6.

11. Equipped with multiple pixels, Each of the aforementioned plurality of pixels is First electrode and, A second electrode is positioned opposite the first electrode, A photoelectric conversion layer located between the first electrode and the second electrode, comprising a donor semiconductor material and an acceptor semiconductor material, which generates a signal charge, An intermediate layer located between the photoelectric conversion layer and the first electrode, It has a charge storage region that is electrically connected to the first electrode and stores the signal charge, The first electrode has a square shape in plan view. If the thickness of the intermediate layer is D, and the length of one side of the square in the plan view of the first electrode is L, D / L ≥ 0.07 The condition is met. Imaging device.

Images