Semiconductor equipment

Abstract

To provide a semiconductor device that is inexpensive and can suppress malfunctions caused by parasitic elements. [Solution] The semiconductor device comprises a GND reference circuit 33 that references the GND potential and a floating reference circuit 13 that references a potential higher than the GND potential, and includes a lead frame 71, a first semiconductor substrate 1 disposed on the lead frame 71 and provided with the GND reference circuit 33, and a second semiconductor substrate 2 disposed on the lead frame 71 and provided with the floating reference circuit 13, wherein either the first semiconductor substrate 1 or the second semiconductor substrate 2 is disposed on the lead frame 71 via an insulating material 3.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device in which a GND reference circuit and a floating reference circuit are formed on different semiconductor substrates to suppress malfunctions caused by parasitic elements. Patent Document 2 discloses a semiconductor device in which a GND reference circuit is formed on a first substrate and a floating reference circuit is formed on a second substrate which is an SOI substrate, and the first and second substrates are mounted on the same lead frame. Patent Document 3 discloses an intelligent power module (IPM). [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2001-237381 [Patent Document 2] Japanese Patent Publication No. 2010-154721 [Patent Document 3] Japanese Patent Publication No. 2018-191011 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] In Patent Document 1, it is necessary to place each substrate, which forms the GND reference circuit and the floating reference circuit, on different lead frames, which limits the available lead frame patterns. In Patent Document 2, each substrate, which forms the GND reference circuit and the floating reference circuit, is placed on the same lead frame, but SOI substrates are expensive, increasing costs.

[0005] In view of the above issues, this disclosure aims to provide a semiconductor device that is inexpensive and can suppress malfunctions caused by parasitic elements. [Means for solving the problem]

[0006] One aspect of the present disclosure is a semiconductor device including a GND reference circuit based on the GND potential and a floating reference circuit based on a potential higher than the GND potential. The semiconductor device includes a lead frame, a first semiconductor substrate disposed on the lead frame and provided with the GND reference circuit, and a second semiconductor substrate disposed on the lead frame and provided with the floating reference circuit. The gist is that either the first semiconductor substrate or the second semiconductor substrate is disposed on the lead frame via an insulating material.

Effect of the Invention

[0007] According to the present disclosure, it is possible to provide a semiconductor device that is inexpensive and can suppress malfunction due to parasitic elements.

Brief Description of the Drawings

[0008] [Figure 1] It is a circuit diagram of a semiconductor device according to the first embodiment. [Figure 2] It is a plan view of a semiconductor device according to the first embodiment. [Figure 3] It is a cross-sectional view of the first substrate according to the first embodiment. [Figure 4] It is a cross-sectional view taken along line A-A' of FIG. 2. [Figure 5] It is another plan view of a semiconductor device according to the first embodiment. [Figure 6] It is a plan view of a semiconductor device according to a comparative example. [Figure 7] It is a cross-sectional view of a semiconductor device according to a comparative example. [Figure 8] It is a cross-sectional view of a semiconductor device according to the second embodiment. [Figure 9] It is a circuit diagram of a semiconductor device according to the third embodiment. [Figure 10] It is a plan view of a semiconductor device according to the third embodiment. [Figure 11] It is a plan view of a semiconductor device according to the fourth embodiment. [Figure 12]Cross-sectional view of the semiconductor device according to the fifth embodiment.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, the first to fifth embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and redundant descriptions are omitted. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. may be different from the actual ones. Also, there may be portions where the dimensional relationships and ratios are different between the drawings. Further, the first to fifth embodiments shown below illustrate devices and methods for embodying the technical idea of the present disclosure, and the technical idea of the present disclosure does not specify the materials, shapes, structures, arrangements, etc. of the components as follows.

[0010] In this specification, the "carrier supply region" means a semiconductor region that supplies majority carriers constituting the main current, such as the source region of a field-effect transistor (FET) or a static induction transistor (SIT), or the emitter region of an insulated gate bipolar transistor (IGBT). Also, in a diode, a static induction (SI) thyristor, or a gate turn-off (GTO) thyristor, the anode region is the carrier supply region. Further, the "carrier receiving region" means a semiconductor region that receives majority carriers constituting the main current, such as the drain region of an FET or a SIT, or the collector region of an IGBT. In a diode, an SI thyristor, or a GTO thyristor, the cathode region functions as the carrier receiving region.

[0011] Also, in this specification, the definitions of directions such as up and down are merely for convenience of explanation and do not limit the technical idea of the present disclosure. For example, if the object is rotated 90° and observed, up and down are read as left and right, and if it is rotated 180° and observed, up and down are read in reverse, of course.

[0012] Furthermore, in this specification, the case where the first conductivity type is p-type and the second conductivity type is n-type will be explained exemplarily. However, the conductivity types may be selected in the reverse relationship, with the first conductivity type being n-type and the second conductivity type being p-type. Also, the "+" and "-" attached to the "n" in n-type and the "p" in p-type indicate semiconductor regions with relatively higher or lower impurity concentrations, respectively, compared to semiconductor regions without the "+" and "-" markings. However, even if two semiconductor regions are marked with the same "n," this does not mean that the impurity concentrations of each semiconductor region are exactly the same. Furthermore, in the following explanation, the members and regions to which the limitations "first conductivity type," "second conductivity type," "n-type," and "p-type" are applied mean members and regions made of semiconductor material even without explicit limitation. Also, in the claims, "n-type" refers to the same "n-type" and "n" as in this specification. - "Type" and "n + "Type" encompasses "type", and "p type" is "p type", "p - "type" and "p + It includes the "type".

[0013] (First Embodiment) <Semiconductor device circuit> As shown in Figure 1, the semiconductor device according to the first embodiment comprises a high-voltage integrated circuit (HVIC) 10 and gate-driven switching elements 21 and 22 for power, which are controlled by the HVIC 10. The semiconductor device according to the first embodiment may be an intelligent power module (IPM). The HVIC 10 and the switching elements 21 and 22 are mounted in the same package. The semiconductor device according to the first embodiment may include the HVIC 10 but not the switching elements 21 and 22. Alternatively, the semiconductor device according to the first embodiment may include the HVIC 10 and the switching elements 21 and 22.

[0014] The low-potential switching element (low-potential switching element) 21 and the high-potential switching element (high-potential switching element) 22 are connected in series with each other to form a half-bridge circuit. Figure 1 illustrates the case where the low-potential switching element 21 and the high-potential switching element 22 are insulated-gate bipolar transistors (IGBTs), but other switching elements such as metal-oxide-semiconductor field-effect transistors (MOSFETs) may also be used. Although not shown in Figure 1, freewheeling diodes (FWDs) may be connected in antiparallel to the IGBTs or MOSFETs that make up the low-potential switching element 21 and the high-potential switching element 22.

[0015] The drain of the high-potential switching element 22 is connected to the high-potential HV potential of a high-voltage power supply (not shown). The source of the low-potential switching element 21 is connected to the low-potential ground potential (GND potential). The midpoint potential C, which is the floating potential at the connection point between the source of the high-potential switching element 22 and the drain of the low-potential switching element 21, is defined as the VS potential. A load (not shown), such as a three-phase motor, can be connected to the connection point between the source of the high-potential switching element 22 and the drain of the low-potential switching element 21, and a signal OUT corresponding to the midpoint potential C is output to the load.

[0016] The HVIC10 includes a low-side circuit (GND reference circuit) 33 and a high-side circuit (floating reference circuit) 13. The GND reference circuit 33 uses the GND potential as its reference potential and operates with the VCC potential, which is approximately 15V higher than the GND potential, as its power supply potential. The floating reference circuit 13 uses the VS potential, which is higher than the GND potential, as its reference potential and operates with the VB potential, which is higher than the VS potential, as its power supply potential.

[0017] The VB potential is the highest potential applied to the HVIC10, and under normal conditions unaffected by noise, it is maintained approximately 15V higher than the VS potential. The VS potential fluctuates between 0V and several hundred V as the high-potential HV potential (e.g., approximately 100V to 400V) and the low-potential GND potential of the high-voltage power supply are switched on and off complementaryly by the high-potential switching element 22 and the low-potential switching element 21. Note that the VS potential may also be negative.

[0018] The GND reference circuit 33 and the floating reference circuit 13 are electrically connected via level shift circuits (31, 32). The level shift circuits (31, 32) transmit signals between the GND reference circuit 33 and the floating reference circuit 13. The level shift circuits (31, 32) include a level up circuit 31 and a level down circuit 32. The level up circuit 31 outputs the signal from the GND reference circuit 33 to the floating reference circuit 13. The level down circuit 32 outputs the signal from the floating reference circuit 13 to the GND reference circuit 33.

[0019] The GND reference circuit 33 comprises a control circuit 11 and a drive circuit 12. An external microcomputer (not shown) is connected to the control circuit 11. The control circuit 11 outputs a control signal to the drive circuit 12 that is referenced to the GND potential in order to control the on / off state of the gate of the low-potential switching element 21, in response to an input signal from the microcomputer. The control circuit 11 also outputs a control signal to the floating reference circuit 13 via the level-up circuit 31 that is referenced to the GND potential in order to control the on / off state of the gate of the high-potential switching element 22, in response to an input signal from the microcomputer.

[0020] The control circuit 11 may have the function of outputting alarm signals, etc., to a microcomputer, or outputting control signals to turn off the low-potential switching element 21 and the high-potential switching element 22, in response to alarm signals, etc., input from the floating reference circuit 13 via the level-down circuit 32.

[0021] The drive circuit 12 applies a drive signal to the gate of the low-potential-side switching element 21 in response to a control signal from the control circuit 11.

[0022] The level-up circuit 31 converts a control signal from the control circuit 11 of the GND reference circuit 33, which is referenced to the GND potential, into a control signal referenced to the VS potential, and outputs the converted control signal to the floating reference circuit 13. The level-up circuit 31 includes a level-shifting element (level shifter) 14 and a resistor (level-shifting resistor) 15. The level shifter 14 is made up of, for example, a high-voltage n-channel MOSFET (HVNMOS). A control signal referenced to the GND potential from the GND reference circuit 33 is applied to the gate of the level shifter 14. The source of the level shifter 14 is connected to the GND potential. The drain of the level shifter 14 is connected to the floating reference circuit 13 and one end of the level-shifting resistor 15. The other end of the level-shifting resistor 15 is connected to the VB potential, which is the positive terminal side of the power supply 19.

[0023] The level-down circuit 32 converts a signal referenced to the VS potential from the floating reference circuit 13 into a signal referenced to the GND potential, and outputs the converted signal to the control circuit 11 of the GND reference circuit 33. The level-down circuit 32 includes a level-shifting element (level shifter) 17 and a resistor (level-shifting resistor) 18. The level shifter 17 is made of, for example, a high-voltage p-channel MOSFET (HVPMOS). A signal referenced to the VS potential from the floating reference circuit 13 is applied to the gate of the level shifter 17. The source of the level shifter 17 is connected to the other end of the level-shifting resistor 15 and to the VB potential, which is the positive terminal side of the power supply 19. The drain of the level shifter 17 is connected to the control circuit 11 of the GND reference circuit 33 and to one end of the level-shifting resistor 18. The other end of the level-shifting resistor 18 is connected to the GND potential. Note that the level-down circuit 32 is not necessarily required.

[0024] The floating reference circuit 13 includes, for example, a CMOS circuit composed of an n-channel MOSFET and a p-channel MOSFET in its output stage. The floating reference circuit 13 outputs a drive signal to the gate of the high-potential-side switching element 22 to drive the high-potential-side switching element 22 in response to a control signal that references the VS potential from the level-up circuit 31. The floating reference circuit 13 may detect temperature or overcurrent, etc., and based on this detection information, output an alarm signal, etc., to the control circuit 11 via the level-down circuit 32.

[0025] As schematically shown by the dashed lines in Figure 1, the HVIC10 is formed on a first semiconductor substrate (first substrate) 1 and a second semiconductor substrate (second substrate) 2. The first substrate 1 has a GND reference circuit 33, a level shifter 14 for the level-up circuit 31, and a level shifter 17 and a level shift resistor 18 for the level-down circuit 32. On the other hand, the second substrate has a level shift resistor 15 for the level-up circuit 31 and a floating reference circuit 13.

[0026] Furthermore, the level shifter 14 of the level-up circuit 31 may be formed on the second substrate 2 instead of the first substrate 1. Also, the level shifter 17 of the level-down circuit 32 may be formed on the second substrate 2 instead of the first substrate 1.

[0027] <Structure of a semiconductor device> Figure 2 shows the planar layout of HVIC10. As shown in Figure 2, HVIC10 is a first conductivity type (p - Type) First substrate 1 and first conductive type (p - The device comprises a second substrate 2 of type (111112222). The first substrate 1 and the second substrate 2 are made of, for example, silicon (Si) substrates. The first substrate 1 and the second substrate 2 may be made of semiconductor substrates made of wide bandgap semiconductors with a wider band gap than Si, such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), gallium arsenide (GaAs), diamond (C), etc.

[0028] The first substrate 1 and the second substrate 2 may be composed of a semiconductor substrate and an epitaxial growth layer provided on the semiconductor substrate. In this case, the impurity concentration of the epitaxial growth layer may be substantially the same as the impurity concentration of the semiconductor substrate, may be higher than the impurity concentration of the semiconductor substrate, or may be lower than the impurity concentration of the semiconductor substrate.

[0029] FIG. 3 shows a cross-section of the left portion of the cross-section along the line A-A' in FIG. 2 of the first substrate 1. As shown in FIG. 3, the first substrate 1 is disposed on a lead frame 71 to which a GND potential is applied. As shown in FIGS. 2 and 3, on the upper surface side of the first substrate 1, a well region 51 of the second conductivity type (n - -type) is provided. The well region 51 has a substantially rectangular planar pattern. The planar pattern and the arrangement position of the well region 51 are not particularly limited.

[0030] As shown in FIG. 3, on the upper surface side of the n - -type well region 51, an n + -type pickup region (contact region) 54 having a higher impurity concentration than the well region 51 is provided. A VCC electrode 61 is electrically connected to the pickup region 54. A VCC potential, which is the power supply potential of the GND reference circuit 33, is applied to the VCC electrode 61. The VCC electrode 61 and the pickup region 54 shown in FIG. 3 are not shown in FIG. 2. The planar pattern and the arrangement position of the VCC electrode 61 and the pickup region 54 are not particularly limited.

[0031] On the upper surface side of the first substrate 1, a p + -type pickup region (contact region) 55 having a higher impurity concentration than the first substrate 1 is provided. A GND electrode 62 is electrically connected to the pickup region 55. A GND potential, which is the reference potential of the GND reference circuit 33, is applied to the GND electrode 62. The GND electrode 62 and the pickup region 55 shown in FIG. 3 are not shown in FIG. 2. The planar pattern and the arrangement position of the GND electrode 62 and the pickup region 55 are not particularly limited.

[0032] A GND reference circuit 33 is formed in the region of the first substrate 1 that includes the pickup region 55 and the well region 51. In Figures 2 and 3, the various elements included in the GND reference circuit 33 are not shown.

[0033] Here, the HVIC10 is broadly classified into wire bonding method (WB method) and self-shielding method (SS method) depending on the method of forming the level shifters 14 and 17. In the WB method, the level shifters 14 and 17 are formed in a region separate from the HVJT, and the level shifters 14 and 17 are connected to the floating reference circuit 13 by metal wires formed by wire bonding. In the SS method, the level shifters 14 and 17 are formed as an integrated unit with the HVJT. In the semiconductor device according to the first embodiment, the case in which the level shifters 14 and 17 are formed by the WB method is illustrated.

[0034] As shown in Figure 2, the first substrate 1 is equipped with two WB-type level shifters 14a and 14b. Level shifters 14a and 14b correspond to the level shifter 14 shown in Figure 1. Note that the level shifter 17 shown in Figure 1 is not shown in Figure 2. The level shifter 17 shown in Figure 1 will be described later. Level shifters 14a and 14b have a substantially circular planar pattern. Level shifters 14a and 14b are made of HVNMOS.

[0035] As shown in Figures 2 and 3, the level shifter 14a has a p-type base region 41a, p + Type pickup area (contact area) 42a, n + Type carrier supply region (source region) 43a, gate electrode 44a, n - Type drift regions 45a and n + The device includes a carrier receiving region (drain region) 46a. The base region 41a has an annular planar pattern. The pickup region 42a and source region 43a are located inside the base region 41a and have annular planar patterns. The drift region 45a is located adjacent to the base region 41a and has a circular planar pattern. The depth of the drift region 45a may be greater than or equal to the depth of the well region 51.

[0036] The gate electrode 44a is provided above an annular p-shaped base region 41a sandwiched between the source region 43a and the drift region 45a, via a gate insulating film (not shown). The drain region 46a is provided on the upper side of the drift region 45a and has a circular planar pattern. A drain electrode 47a is provided on the upper side of the drain region 46a. A pad 48a of the second substrate 2 is connected to the drain electrode 47a via a metal wire 89.

[0037] As shown in Figure 2, the level shifter 14b is a p-type base region 41b, p + Type pickup area (contact area) 42b, n + Type carrier supply region (source region) 43b, gate electrode 44b, n - Type drift regions 45b and n + The device includes a carrier receiving region (drain region) 46b. The base region 41b has an annular planar pattern. The pickup region 42b and source region 43b are located inside the base region 41b and have annular planar patterns. The drift region 45b is located adjacent to the base region 41b and has a circular planar pattern. The depth of the drift region 45b may be greater than or equal to the depth of the well region 51.

[0038] The gate electrode 44b is provided above an annular p-shaped base region 41b sandwiched between the source region 43b and the drift region 45b, via a gate insulating film (not shown). The drain region 46b is provided on the upper side of the drift region 45b and has a circular planar pattern. A drain electrode 47b is provided on the upper side of the drain region 46b. A pad 48b of the second substrate 2 is connected to the drain electrode 47b via a metal wire 90. The cross-sectional structure of the level shifter 14b is the same as the cross-sectional structure of the level shifter 14a shown in Figure 3.

[0039] On the other hand, as shown on the right side of Figure 2, the second substrate 2 is provided at a distance from the first substrate 1. An n-shaped well region 53 is provided on the upper surface of the second substrate 2. The well region 53 has a substantially rectangular planar pattern. The planar pattern and arrangement position of the well region 53 are not particularly limited. The well region 53 is subjected to a VB potential, which is the power supply potential of the floating reference circuit 13.

[0040] A p-shaped well region 52 is provided on the upper surface of the second substrate 2, separated from the well region 53. The well region 52 has a substantially rectangular planar pattern. The planar pattern and position of the well region 52 are not particularly limited. The VS potential, which is the reference potential of the floating reference circuit 13, is applied to the well region 52.

[0041] A floating reference circuit 13 is formed in the region of the second substrate that includes well region 53 and well region 52. In Figure 2, the various elements included in the floating reference circuit 13 are not shown.

[0042] Pads 48a and 48b are provided on the side of the second substrate 2 facing the first substrate 1. Pad 48a is electrically connected to one end of the level shift resistor 15a. The other end of the level shift resistor 15a is connected to the VB potential. Pad 48b is electrically connected to one end of the level shift resistor 15b. The other end of the level shift resistor 15b is connected to the VB potential. Level shift resistors 15a and 15b correspond to the level shift resistor 15 shown in Figure 1.

[0043] Figure 4 shows a cross-section including the portion along line AA' in Figure 2. In addition to the first substrate 1 and the second substrate 2, Figure 4 also shows the low-potential switching element 21 and the high-potential switching element 22. In Figure 4, the emitter electrodes 24 and 26 of the low-potential switching element 21 and the high-potential switching element 22 are schematically labeled "E", the gate electrodes 23 and 25 are labeled "G", and the collector electrode (not shown) is labeled "C".

[0044] As shown in Figure 4, the first substrate 1 and the second substrate 2 are arranged (mounted) on the same lead frame 71 to which the GND potential is applied. The first substrate 1 may be electrically connected to the lead frame 71 and fixed to the GND potential. The lower surface of the first substrate 1 may be provided on the lead frame 71 via a conductive adhesive. Electrodes may also be provided on the lower surface side of the first substrate 1, and the electrodes on the lower surface side of the first substrate 1 may be bonded (joined) to the lead frame 71 via solder, a sintered bonding material such as silver paste, or a conductive material such as a conductive adhesive. In Figure 4, the upper surface side of the first substrate 1 is n - Only the drift region 45a of the type is shown, and the other diffusion regions in the first substrate 1 shown in Figures 2 and 3 are omitted.

[0045] On the other hand, the second substrate 2 is provided on the lead frame 71 via an insulating material 3. The second substrate 2 may be bonded to the lead frame 71 by the insulating material 3. The second substrate 2 and the lead frame 71 are insulated from each other by the insulating material 3. Electrodes may be provided on the lower surface of the second substrate 2, and the electrodes on the lower surface of the second substrate 2 may be in contact with the insulating material 3. The insulating material 3 is composed of, for example, epoxy resin paste or dicing attachment film (DAF sheet). The first substrate 1 may also be provided on the lead frame 71 via an insulating material similar to the insulating material 3.

[0046] As shown in Figure 4, a VS electrode 63 electrically connected to the well region 52 is provided on the upper side of the second substrate 2. An HO electrode 64 is provided on the upper side of the second substrate 2. The HO electrode 64 is connected to the output of a CMOS circuit (not shown) formed in the floating reference circuit 13. A VB electrode 65 electrically connected to the well region 53 is provided on the upper side of the second substrate 2.

[0047] The low-potential switching element 21 is mounted on a lead frame 72 to which a VS potential is applied. The low-potential switching element 21 has a gate electrode 23 and an emitter electrode 24 on its upper side, and a collector electrode (not shown) on its lower side. The emitter electrode 24 of the low-potential switching element 21 is electrically connected to the lead frame 71 via a metal wire 81.

[0048] The high-potential switching element 22 is mounted on a lead frame 73 to which an HV potential is applied. The high-potential switching element 22 has a gate electrode 25 and an emitter electrode 26 on its upper side, and a collector electrode (not shown) on its lower side. The gate electrode 25 of the high-potential switching element 22 is electrically connected to the HO electrode 64 via a metal wire 83. The emitter electrode 26 of the high-potential switching element 22 is electrically connected to the VS electrode 63 via a metal wire 82 and electrically connected to the lead frame 72 via a metal wire 84.

[0049] Figure 5 is a planar layout of the HVIC10, omitting the illustration of the level shifters 14a, 14b and level shift resistors 15a, 15b of the level-up circuit 31 shown in Figure 2, and illustrating the level shifters 17a, 17b and level shift resistors 18a, 18b of the level-down circuit 32. The level shifters 17a, 17b correspond to the level shifter 17 shown in Figure 2, and the level shift resistors 18a, 18b correspond to the level shift resistor 18 shown in Figure 2. As shown in Figure 5, the level shifters 17a, 17b and level shift resistors 18a, 18b are provided on the first substrate 1. Pads 49a, 49b, 50a, 50b are provided on the second substrate 2.

[0050] One end of the level shift resistor 18a is electrically connected to the drain electrode D of the level shifter 17a. The drain electrode D of the level shifter 17a and the level shift resistor 18a may be electrically connected by a metal wire (not shown). The other end of the level shift resistor 18a is grounded. The source electrode S of the level shifter 17a is electrically connected to the pad 49a via a metal wire 96a. The gate electrode G of the level shifter 17a is electrically connected to the pad 50a via a metal wire 97a.

[0051] One end of the level shift resistor 18b is electrically connected to the drain electrode D of the level shifter 17b. The drain electrode D of the level shifter 17b and the level shift resistor 18b may be electrically connected by a metal wire (not shown). The other end of the level shift resistor 18b is grounded. The source electrode S of the level shifter 17b is electrically connected to the pad 49b via a metal wire 96b. The gate electrode G of the level shifter 17b is electrically connected to the pad 50b via a metal wire 97b.

[0052] <Comparative Example> Here, a semiconductor device relating to the comparative example will be described. Figure 6 shows the planar layout of the semiconductor substrate 1x of the semiconductor device relating to the comparative example, and Figure 7 shows the semiconductor substrate 1x of the semiconductor device relating to the comparative example, as well as the low-potential side switching element 21 and the high-potential side switching element 22. As shown in Figures 6 and 7, the semiconductor device relating to the comparative example is a single p - The semiconductor device according to the first embodiment shown in Figure 2 differs in that a GND reference circuit 33 and a floating reference circuit 13 are formed on the semiconductor substrate 1x of the type shown.

[0053] The semiconductor substrate 1x is mounted on a lead frame 71 to which a GND potential is applied. An n-type well region 51 is provided on the upper surface of the semiconductor substrate 1x. A VCC potential is applied to the well region 51. A GND reference circuit 33 is formed in a part of the semiconductor substrate 1x and in the well region 51.

[0054] An n-type well region 53 with a higher impurity concentration than the semiconductor substrate 1x is provided on the upper surface of the semiconductor substrate 1x. A VB potential is applied to the well region 53. A p-type well region 52 is provided on the upper surface of the well region 53. A VS potential is applied to the well region 52. A floating reference circuit 13 is formed in the well regions 52 and 53.

[0055] On the outer periphery of the well region 53, there is n with a lower impurity concentration than the well region 53. - A type of breakdown region 56 is provided. A high-voltage diode called a high-voltage junction (HVJT) is formed by the pn junction between the breakdown region 56 and the semiconductor substrate 1x. The HVJT ensures that the circuit operates normally even when the potential of the floating reference circuit 13 is several hundred volts higher than the potential of the GND reference circuit 33 region. At the bottom of the well region 53 is an n-ion junction with a higher impurity concentration than the well region 53. + A molded embedded area 57 is provided.

[0056] In the comparative example semiconductor device, there is a p-type well region 52 to which a VS potential is applied, an n-type well region 53 to which a VB potential is applied, and a p-type well region to which a GND potential is applied. - A vertical parasitic PNP bipolar transistor is formed on a semiconductor substrate 1x of type 1x. When the VS potential is high, noise can cause this parasitic PNP bipolar transistor to operate, resulting in a large current flow that can lead to destruction or malfunction. Therefore, a high-density embedded region 57 is formed at the bottom of the well region 53 to suppress the operation of this parasitic PNP bipolar transistor. However, this increases the number of steps required to form the embedded region 57, leading to increased substrate and process costs.

[0057] In contrast, according to the semiconductor device of the first embodiment, by forming the GND reference circuit 33 and the floating reference circuit 13 separately on the first substrate 1 and the second substrate 2, an HVJT for electrically isolating the GND reference circuit 33 and the floating reference circuit 13 becomes unnecessary, and vertical parasitic pnp bipolar transistors are not formed, thus suppressing damage and malfunctions caused by parasitic pnp bipolar transistors. Furthermore, it is not necessary to form an embedded region to suppress the operation of parasitic pnp bipolar transistors, thus suppressing the increase in man-hours and costs required to form the embedded region. In addition, since an HVJT is not required, the chip area can be reduced.

[0058] Furthermore, according to the semiconductor device of the first embodiment, the first substrate 1 and the second substrate 2 are arranged on the same lead frame 71. This improves the degree of freedom of the pattern on the lead frame 71, as well as the degree of freedom of the arrangement of the first substrate 1 and the second substrate 2 on the lead frame 71, compared to the case where the first substrate 1 and the second substrate 2 are arranged on different lead frames.

[0059] Furthermore, according to the semiconductor device of the first embodiment, the second substrate 2 is insulated from the lead frame 71 by an insulating material 3. This makes it possible to suppress cost increases compared to the case where an SOI substrate is used to insulate the second substrate 2 from the lead frame 71. In addition, the insulating material 3 offers greater freedom in material selection compared to an SOI substrate.

[0060] (Second Embodiment) The planar layout of the semiconductor device according to the second embodiment is the same as the planar layout of the semiconductor device according to the first embodiment shown in Figure 2. That is, as shown in Figure 2, the semiconductor device according to the second embodiment has a GND reference circuit 33 and a level shifter 14 of the level-up circuit 31 formed on the first substrate 1. On the other hand, the second substrate has a level shift resistor 15 of the level-up circuit 31 and a floating reference circuit 13 formed on it.

[0061] Figure 8 shows a cross-section of the semiconductor device according to the second embodiment, corresponding to the position of the cross-section of the semiconductor device according to the first embodiment shown in Figure 4. The semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment in that, as shown in Figure 8, the first substrate 1 and the second substrate 2 are provided on the same lead frame 72 to which the VS potential is applied.

[0062] The first substrate 1 is provided on the lead frame 72 via an insulating material 3. The first substrate 1 may be bonded to the lead frame 72 by the insulating material 3. The first substrate 1 and the lead frame 72 are insulated from each other by the insulating material 3. Electrodes may be provided on the lower side of the first substrate 1, and the electrodes on the lower side of the first substrate 1 may be in contact with the insulating material 3. The insulating material 3 is made of, for example, epoxy resin paste or dicing attachment film (DAF sheet). The GND electrode 62 on the upper side of the first substrate 1 is electrically connected to the lead frame 71 to which a GND potential is applied via a metal wire 85. Therefore, the first substrate 1 is fixed to the GND potential.

[0063] On the other hand, the second substrate 2 may be electrically connected to the lead frame 72 and fixed at the VS potential. The lower surface of the second substrate 2 may be provided on the lead frame 72 via a conductive adhesive. Electrodes may also be provided on the lower surface side of the second substrate 2, and these electrodes may be provided on the lead frame 72 via solder, a sintered bonding material such as silver paste, or a conductive material such as a conductive adhesive. Furthermore, the second substrate 2 may be provided on the lead frame 72 via an insulating material similar to the insulating material 3. Other configurations of the semiconductor device according to the second embodiment are substantially the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0064] According to the semiconductor device of the second embodiment, by forming the GND reference circuit 33 and the floating reference circuit 13 separately on the first substrate 1 and the second substrate 2, an HVJT for electrically isolating the GND reference circuit 33 and the floating reference circuit 13 becomes unnecessary, and vertical parasitic pnp bipolar transistors are not formed, thus suppressing damage and malfunctions caused by parasitic pnp bipolar transistors. Furthermore, it is not necessary to form an embedded region to suppress the operation of parasitic pnp bipolar transistors, thus suppressing the increase in man-hours and costs required to form the embedded region. In addition, since an HVJT is not required, the chip area can be reduced.

[0065] Furthermore, according to the semiconductor device of the second embodiment, the first substrate 1 and the second substrate 2 are arranged on the same lead frame 72. This improves the degree of freedom of the pattern on the lead frame 72, as well as the degree of freedom of the arrangement of the first substrate 1 and the second substrate 2 on the lead frame 72, compared to the case where the first substrate 1 and the second substrate 2 are arranged on different lead frames.

[0066] Furthermore, according to the semiconductor device of the second embodiment, the first substrate 1 is insulated from the lead frame 72 by an insulating material 3. This makes it possible to suppress cost increases compared to the case in which an SOI substrate is used to insulate the first substrate 1 from the lead frame 72.

[0067] (Third embodiment) <Semiconductor device circuit> As a semiconductor device according to the third embodiment, a configuration comprising three phases of HVIC and switching elements will be described. As shown in Figure 9, the semiconductor device 100 according to the third embodiment comprises semiconductor devices 101 to 104, high-potential switching elements (high-potential switching elements) 111 to 113, low-potential switching elements (low-potential switching elements) 114 to 116, and freewheeling diodes (FWDs) 121 to 126.

[0068] The semiconductor devices 101 to 103 are composed of HVIC and have the same configuration as the HVIC 100 shown in Figure 1. That is, each of the semiconductor devices 101 to 103 is equipped with a GND reference circuit 33, a floating reference circuit 13, and level shift circuits (31, 32). Each of the semiconductor devices 101 to 103 is equipped with a level-up circuit 31, but does not need to be equipped with a level-down circuit 32.

[0069] Semiconductor device 101 outputs a signal to the gate of the high-potential-side switching element 111 to drive the high-potential-side switching element 111. Terminals INHU, VCC, VB, COM, and U are connected to semiconductor device 101. Semiconductor device 102 outputs a signal to the gate of the high-potential-side switching element 112 to drive the high-potential-side switching element 112. Terminals INHV, VCC, VB, COM, and U are connected to semiconductor device 102. Semiconductor device 103 outputs a signal to the gate of the high-potential-side switching element 113 to drive the high-potential-side switching element 113. Terminals INHW, VCC, VB, COM, and U are connected to semiconductor device 103.

[0070] Input signals from an external microcomputer (not shown) are input to terminals INHU, INHV, and INHW. A GND potential is applied to the common terminal COM connected to semiconductor devices 101 to 103. A VCC potential is applied to terminals VCC, each connected to semiconductor devices 101 to 103. A VB potential is applied to terminal VB, each connected to semiconductor devices 101 to 103.

[0071] The semiconductor device 104 is composed of a low-voltage integrated circuit (LVIC). The semiconductor device 104 outputs signals to the gates of the low-potential switching elements 114 to 116 to drive them. Terminals INLU, INLV, INLW, VCC, and COM are connected to the semiconductor device 104. Input signals from an external microcomputer (not shown) are input to terminals INLU, INLV, and INLW. The VCC potential is applied to terminal VCC connected to the semiconductor device 104.

[0072] The high-potential switching elements 111-113 and the low-potential switching elements 114-116 are composed of, for example, insulated-gate bipolar transistors (IGBTs). The high-potential switching elements 111-113 and the low-potential switching elements 114-116 may be composed of other switching elements such as MOSFETs.

[0073] The collectors of the high-potential switching elements 111 to 113 are connected to terminal P. A high potential (HV) is applied to terminal P. The emitter of high-potential switching element 111 is connected to terminal U. The emitter of high-potential switching element 112 is connected to terminal V. The emitter of high-potential switching element 113 is connected to terminal W. Output signals are output to an external load from terminals U, V, and W.

[0074] The collector of the low-potential switching element 114 is connected to terminal U. The emitter of the low-potential switching element 114 is connected to terminal NU. The collector of the low-potential switching element 115 is connected to terminal V. The emitter of the low-potential switching element 115 is connected to terminal NV. The collector of the low-potential switching element 116 is connected to terminal W. The emitter of the low-potential switching element 116 is connected to terminal NW.

[0075] The freewheeling diodes 121-123 are connected in antiparallel to the high-potential switching elements 111-113. The freewheeling diodes 124-126 are connected in antiparallel to the low-potential switching elements 114-116.

[0076] As schematically shown by dashed lines in Figure 9, the high-potential switching element 111 and freewheeling diode 121 are formed on semiconductor chip 22u. The high-potential switching element 112 and freewheeling diode 122 are formed on semiconductor chip 22v. The high-potential switching element 113 and freewheeling diode 123 are formed on semiconductor chip 22w. The low-potential switching element 114 and freewheeling diode 124 are formed on semiconductor chip 21u. The low-potential switching element 115 and freewheeling diode 125 are formed on semiconductor chip 21v. The low-potential switching element 116 and freewheeling diode 126 are formed on semiconductor chip 21w. Semiconductor chips 21u, 21v, 21w, 22u, 22v, and 22w are reverse-conducting IGBTs.

[0077] <Structure of a semiconductor device> Figure 10 shows an example of the mounting configuration of the semiconductor device 100 according to the third embodiment. The semiconductor device 100 according to the third embodiment includes lead frames 74u, 75u, 76u, 74v, 75v, 76v, 74w, 75w, 76w, 71, 75, 78u, 78v, and 78w, as shown from left to right in the upper part of Figure 10. The lead frames 74u, 75u, 76u, 74v, 75v, 76v, 74w, 75w, 76w, 71, 75, 78u, 78v, 78w, and 71 are made of a conductive material such as aluminum or copper.

[0078] The lead frames 74u, 74v, and 74w shown in Figure 10 correspond to terminals VB of the U-phase, V-phase, and W-phase shown in Figure 9. The lead frames 75u, 75v, and 75w shown in Figure 10 correspond to terminals VCC of the U-phase, V-phase, and W-phase shown in Figure 9. The lead frame 75 shown in Figure 10 corresponds to terminal VCC connected to semiconductor device 104 shown in Figure 9. The lead frames 76u, 76v, and 76w shown in Figure 10 correspond to terminals INHU, INHV, and INHW shown in Figure 9. The lead frame 71 shown in Figure 9 corresponds to terminal COM shown in Figure 9. The lead frames 78u, 78v, and 78w shown in Figure 10 correspond to terminals INLU, INLV, and INLW shown in Figure 9.

[0079] Furthermore, the semiconductor device 100 according to the third embodiment includes lead frames 73, 72u, 72v, 72w, 79u, 79v, and 79w, as shown from left to right in the lower part of Figure 10. The lead frames 73, 72u, 72v, 72w, 79u, 79v, and 79w are made of a conductive material such as aluminum or copper.

[0080] The lead frame 73 shown in Figure 10 corresponds to terminal P shown in Figure 9. The lead frames 72u, 72v, and 72w shown in Figure 10 correspond to terminals U, V, and W shown in Figure 9. The lead frames 79u, 79v, and 79w shown in Figure 10 correspond to terminals NU, NV, and NW shown in Figure 9.

[0081] The die pad portion of lead frame 71 is located between the upper lead frames 74u, 75u, 76u, 74v, 75v, 76v, 74w, 75w, 76w, 75, 78u, 78v, 78w in Figure 10 and the lower lead frames 73, 72u, 72v, 72w, 79u, 79v, 79w in Figure 10.

[0082] A first substrate (semiconductor chip) 1u, 1v, 1w, a second substrate (semiconductor chip) 2u, 2v, 2w, and a semiconductor chip (semiconductor device) 104 are provided on the die pad portion of the lead frame 71. The first substrate 1u, 1v, 1w and the second substrate 2u, 2v, 2w are arranged in close proximity to each other on the same lead frame 71.

[0083] As schematically shown by dashed lines in Figure 10, the first substrate 1u and the second substrate 2u constitute semiconductor device 101, corresponding to semiconductor device 101 shown in Figure 9. The first substrate 1v and the second substrate 2v constitute semiconductor device 102, corresponding to semiconductor device 102 shown in Figure 9. The first substrate 1w and the second substrate 2w constitute semiconductor device 103, corresponding to semiconductor device 103 shown in Figure 9. Furthermore, the semiconductor chip 104 corresponds to semiconductor device 104 shown in Figure 9.

[0084] The first substrates 1u, 1v, and 1w have the same configuration as the first substrate 1 shown in Figures 2 to 4. That is, each of the first substrates 1u, 1v, and 1w has a GND reference circuit 33 and a level shifter 14 of the level-up circuit 31 formed thereon.

[0085] The first substrate 1u is electrically connected to the lead frame 75u via a metal wire 87u and to the lead frame 76u via a metal wire 88u. The back side of the first substrate 1u is electrically connected to the lead frame 71. The first substrate 1v is electrically connected to the lead frame 75v via a metal wire 87v and to the lead frame 76v via a metal wire 88v. The back side of the first substrate 1v is electrically connected to the lead frame 71. The first substrate 1w is electrically connected to the lead frame 75w via a metal wire 87w and to the lead frame 76w via a metal wire 88w. The bottom side of the first substrate 1w is electrically connected to the lead frame 71.

[0086] The second substrates 2u, 2v, and 2w are provided on the die pad portion of the lead frame 71 via an insulating material 3. In Figure 10, the second substrates 2u, 2v, and 2w are provided on the die pad portion of the lead frame 71 via a common insulating material 3, but they may also be provided on the die pad portion of the lead frame 71 via individual insulating materials. The second substrates 2u, 2v, and 2w have the same configuration as the second substrate 2 shown in Figures 2 and 4. That is, each of the second substrates 2u, 2v, and 2w has a level shift resistor 15 of the level-up circuit 31 and a floating reference circuit 13 formed thereon.

[0087] The second substrate 2u is electrically connected to the lead frame 74u via metal wire 86u, and to the first substrate 1 via metal wires 89u and 90u. The second substrate 2v is electrically connected to the lead frame 74v via metal wire 86v, and to the first substrate 1 via metal wires 89v and 90v. The second substrate 2w is electrically connected to the lead frame 74w via metal wire 86w, and to the first substrate 1 via metal wires 89w and 90w.

[0088] The semiconductor chip 104 is electrically connected to the lead frame 75 via metal wire 91, to the lead frame 78u via metal wire 92u, to the lead frame 78v via metal wire 92v, to the lead frame 78w via metal wire 92w, and to the lead frame 71 via metal wire 93.

[0089] Semiconductor chips 22u, 22v, and 22w are provided on the die pad portion of the lead frame 73. Semiconductor chip 22u corresponds to the high-potential switching element 111 and freewheeling diode 121 shown in Figure 9. Semiconductor chip 22v corresponds to the high-potential switching element 112 and freewheeling diode 122 shown in Figure 9. Semiconductor chip 22w corresponds to the high-potential switching element 113 and freewheeling diode 123 shown in Figure 9.

[0090] The collector electrode (not shown) on the lower side of the semiconductor chip 22u is electrically connected to the lead frame 73. The gate electrode 25u on the upper side of the semiconductor chip 22u is electrically connected to the second substrate 2u via a metal wire 83u. The emitter electrode 26u on the upper side of the semiconductor chip 22u is electrically connected to the second substrate 2u via a metal wire 82u and electrically connected to the lead frame 72u via a metal wire 84u.

[0091] The collector electrode (not shown) on the lower side of the semiconductor chip 22V is electrically connected to the lead frame 73. The gate electrode 25V on the upper side of the semiconductor chip 22V is electrically connected to the second substrate 2V via a metal wire 83V. The emitter electrode 26V on the upper side of the semiconductor chip 22V is electrically connected to the second substrate 2V via a metal wire 82V and electrically connected to the lead frame 72V via a metal wire 84V.

[0092] The collector electrode (not shown) on the lower side of the semiconductor chip 22w is electrically connected to the lead frame 73. The gate electrode 25w on the upper side of the semiconductor chip 22w is electrically connected to the second substrate 2w via a metal wire 83w. The emitter electrode 26w on the upper side of the semiconductor chip 22w is electrically connected to the second substrate 2w via a metal wire 82w and electrically connected to the lead frame 72w via a metal wire 84w.

[0093] A semiconductor chip 21u is provided on the die pad portion of the lead frame 72u. The semiconductor chip 21u corresponds to the low-potential switching element 114 and freewheeling diode 124 shown in Figure 9. The collector electrode (not shown) on the lower side of the semiconductor chip 21u is electrically connected to the lead frame 72u. The gate electrode 23u on the upper side of the semiconductor chip 21u is electrically connected to the semiconductor chip 104 via a metal wire 94u. The emitter electrode 24u on the upper side of the semiconductor chip 21u is electrically connected to the lead frame 71 via a metal wire 81u and to the lead frame 79u via a metal wire 95u.

[0094] A semiconductor chip 21v is provided on the die pad portion of the lead frame 72v. The semiconductor chip 21v corresponds to the low-potential switching element 115 and freewheeling diode 125 shown in Figure 9. The collector electrode (not shown) on the lower side of the semiconductor chip 21v is electrically connected to the lead frame 72v. The gate electrode 23v on the upper side of the semiconductor chip 21v is electrically connected to the semiconductor chip 104 via a metal wire 94v. The emitter electrode 24v on the upper side of the semiconductor chip 21v is electrically connected to the lead frame 71 via a metal wire 81v and to the lead frame 79v via a metal wire 95v.

[0095] A semiconductor chip 21w is provided on the die pad portion of the lead frame 72w. The semiconductor chip 21w corresponds to the low-potential switching element 116 and freewheeling diode 126 shown in Figure 9. The collector electrode (not shown) on the lower side of the semiconductor chip 21w is electrically connected to the lead frame 72w. The gate electrode 23w on the upper side of the semiconductor chip 21w is electrically connected to the semiconductor chip 104 via a metal wire 94w. The emitter electrode 24w on the upper side of the semiconductor chip 21w is electrically connected to the lead frame 71 via a metal wire 81w and to the lead frame 79w via a metal wire 95w.

[0096] According to the semiconductor device 100 of the third embodiment, in the three-phase semiconductor devices 101 to 103, by forming the GND reference circuit 33 and the floating reference circuit 13 separately on the first substrate 1u, 1v, 1w and the second substrate 2u, 2v, 2w, an HVJT for electrically isolating the GND reference circuit 33 and the floating reference circuit 13 becomes unnecessary, and vertical parasitic pnp bipolar transistors are not formed, thus suppressing damage and malfunctions caused by parasitic pnp bipolar transistors. Furthermore, it is not necessary to form an embedded region to suppress the operation of parasitic pnp bipolar transistors, thus suppressing the increase in man-hours and costs required to form the embedded region. In addition, since an HVJT is not required, the chip area can be reduced.

[0097] Furthermore, according to the semiconductor device 100 of the third embodiment, the first substrate 1u, 1v, 1w and the second substrate 2u, 2v, 2w are arranged on the same lead frame 71. This improves the degree of freedom of the pattern on the lead frame 71 compared to the case where the first substrate 1u, 1v, 1w and the second substrate 2u, 2v, 2w are arranged on different lead frames, and also improves the degree of freedom of the arrangement of the first substrate 1u, 1v, 1w and the second substrate 2u, 2v, 2w on the lead frame 71.

[0098] Furthermore, according to the semiconductor device 100 of the third embodiment, the second substrates 2u, 2v, and 2w are insulated from the lead frame 71 by the insulating material 3. This makes it possible to suppress cost increases compared to the case where SOI substrates are used to insulate the second substrates 2u, 2v, and 2w from the lead frame 71.

[0099] (Fourth Embodiment) The circuit configuration of the semiconductor device according to the fourth embodiment is the same as that of the semiconductor device 100 according to the third embodiment shown in Figure 9. Figure 11 shows an example of the mounting configuration of the semiconductor device 100 according to the fourth embodiment. The semiconductor device 100 according to the fourth embodiment differs from the semiconductor device according to the third embodiment shown in Figure 10 in that, as shown in Figure 11, the first substrate 1u, 1v, 1w and the second substrate 2u, 2v, 2w are not provided on the lead frame 71, but are provided on the lead frames 72u, 72v, 72w.

[0100] In the semiconductor device according to the fourth embodiment, the lead frames 72u, 72v, and 72w are further extended to reach the positions of the first substrate 1u, 1v, 1w and the second substrate 2u, 2v, 2w. The first substrate 1u and the second substrate 2u are located in close proximity to each other. The first substrate 1v and the second substrate 2v are located in close proximity to each other. The first substrate 1w and the second substrate 2w are located in close proximity to each other.

[0101] The first substrate 1u and the second substrate 2u constituting the semiconductor device 101 are arranged on the same lead frame 72u. The first substrate 1u is provided on the lead frame 72u via an insulating material 3u. The first substrate 1u is electrically connected to the lead frame 71 via a metal wire 85u. The other electrical connections of the first substrate 1u are the same as those of the semiconductor device according to the third embodiment, so a redundant explanation is omitted. The back side of the second substrate 2u is electrically connected to the lead frame 72u. The other electrical connections of the second substrate 2u are the same as those of the semiconductor device according to the third embodiment, so a redundant explanation is omitted.

[0102] The first substrate 1v and the second substrate 2v constituting the semiconductor device 102 are arranged on the same lead frame 72v. The first substrate 1v is provided on the lead frame 72v via an insulating material 3v. The first substrate 1v is electrically connected to the lead frame 71 via metal wires 85v. The other electrical connections of the first substrate 1v are the same as those of the semiconductor device according to the third embodiment, so a redundant explanation is omitted. The back side of the second substrate 2v is electrically connected to the lead frame 72v. The other electrical connections of the second substrate 2v are the same as those of the semiconductor device according to the third embodiment, so a redundant explanation is omitted.

[0103] The first substrate 1w and the second substrate 2w constituting the semiconductor device 103 are arranged on the same lead frame 72w. The first substrate 1w is provided on the lead frame 72w via an insulating material 3w. The first substrate 1w is electrically connected to the lead frame 71 via a metal wire 85w. The other electrical connections of the first substrate 1w are the same as those of the semiconductor device according to the third embodiment, so a redundant explanation is omitted. The back side of the second substrate 2w is electrically connected to the lead frame 72w. The other electrical connections of the second substrate 2w are the same as those of the semiconductor device according to the third embodiment, so a redundant explanation is omitted. The other configurations of the semiconductor device according to the fourth embodiment are substantially the same as those of the semiconductor device according to the third embodiment, so a redundant explanation is omitted.

[0104] According to the semiconductor device 100 of the fourth embodiment, in the three-phase semiconductor devices 101 to 103, by forming the GND reference circuit 33 and the floating reference circuit 13 separately on the first substrate 1u, 1v, 1w and the second substrate 2u, 2v, 2w, an HVJT for electrically isolating the GND reference circuit 33 and the floating reference circuit 13 becomes unnecessary, and vertical parasitic pnp bipolar transistors are not formed, thus suppressing damage and malfunctions caused by parasitic pnp bipolar transistors. Furthermore, it is not necessary to form an embedded region to suppress the operation of parasitic pnp bipolar transistors, thus suppressing the increase in man-hours and costs required to form the embedded region. In addition, since an HVJT is not required, the chip area can be reduced.

[0105] Furthermore, according to the semiconductor device 100 of the fourth embodiment, the first substrate 1u, 1v, 1w and the second substrate 2u, 2v, 2w are arranged on the same lead frame 72u, 72v, 72w. This improves the degree of freedom of the patterns on the lead frame 72u, 72v, 72w compared to the case where the first substrate 1u, 1v, 1w and the second substrate 2u, 2v, 2w are arranged on different lead frames, and also improves the degree of freedom of the arrangement of the first substrate 1u, 1v, 1w and the second substrate 2u, 2v, 2w on the lead frame 72u, 72v, 72w.

[0106] Furthermore, according to the semiconductor device 100 of the fourth embodiment, the first substrates 1u, 1v, and 1w are insulated from the lead frames 72u, 72v, and 72w by insulating materials 3u, 3v, and 3w. This makes it possible to suppress cost increases compared to the case where SOI substrates are used to insulate the first substrates 1u, 1v, and 1w from the lead frames 72u, 72v, and 72w.

[0107] (Fifth embodiment) Figure 12 shows a cross-section of the semiconductor device according to the fifth embodiment, corresponding to the position of the cross-section of the semiconductor device according to the first embodiment shown in Figure 4. As shown in Figure 12, the semiconductor device according to the fifth embodiment has a second substrate 2x of the opposite conductivity type to the first substrate 1.- The semiconductor device according to the first embodiment differs from the semiconductor device according to the fifth embodiment in that it is composed of a mold. The other configurations of the semiconductor device according to the fifth embodiment are substantially the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0108] According to the semiconductor device of the fifth embodiment, by forming the GND reference circuit 33 and the floating reference circuit 13 separately on the first substrate 1 and the second substrate 2x, an HVJT for electrically isolating the GND reference circuit 33 and the floating reference circuit 13 becomes unnecessary, and vertical parasitic pnp bipolar transistors are not formed, thus suppressing damage and malfunctions caused by parasitic pnp bipolar transistors. Furthermore, it is not necessary to form an embedded region to suppress the operation of parasitic pnp bipolar transistors, thus suppressing the increase in man-hours and costs required to form the embedded region. In addition, since an HVJT is not required, the chip area can be reduced.

[0109] Furthermore, according to the semiconductor device of the fifth embodiment, the first substrate 1 and the second substrate 2x are arranged on the same lead frame 71. This improves the degree of freedom of the pattern on the lead frame 71, as well as the degree of freedom of the arrangement of the first substrate 1 and the second substrate 2x on the lead frame 71, compared to the case where the first substrate 1 and the second substrate 2x are arranged on different lead frames.

[0110] Furthermore, according to the semiconductor device of the fifth embodiment, the second substrate 2x is insulated from the lead frame 71 by an insulating material 3. This makes it possible to suppress cost increases compared to the case in which an SOI substrate is used to insulate the second substrate 2x from the lead frame 71.

[0111] (Other embodiments) As described above, this disclosure is based on the First to Fifth Embodiments, but the statements and drawings that constitute part of this disclosure should not be understood as limiting this disclosure. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0112] For example, the configurations disclosed in the first to fifth embodiments can be appropriately combined within a range where no contradiction occurs. Thus, it is needless to say that the present disclosure includes various embodiments and the like that are not described herein. Therefore, the technical scope of the present disclosure is defined only by the invention-specific matters according to the legitimate claims from the above description.

Explanation of Reference Numerals

[0113] 1, 1u, 1v, 1w... First substrate 2, 2u, 2v, 2w... Second substrate 3, 3u, 3v, 3w... Insulating material 4... Semiconductor substrate 10... Semiconductor device 11... Control circuit 12... Drive circuit 13... Floating reference circuit 14, 14a, 14b... Level shifter 15, 15a, 15b... Level shift resistor 17, 17a, 17b... Level shifter 18, 18a, 18b... Level shift resistor 19... Power supply 21, 22... Switching element 21u, 21v, 21w... Semiconductor chip 22u, 22v, 22w... Semiconductor chip 23, 23u, 23v, 23w... Gate electrode 24, 24u, 24v, 24w... Emitter electrode 25, 25u, 25v, 25w... Gate electrode 26, 26u, 26v, 26w... Emitter electrode 31... Level-up circuit 32... Level-down circuit 33... GND reference circuit 41a, 41b... Base region 42a, 42b... Pickup region (contact region) 43a, 43b... Carrier supply region (source region) 44a, 44b... Gate electrode 45a, 45b... Drift region 46a, 46b... Carrier receiving region (drain region) 47a, 47b… Drain electrodes 48a, 48b, 49a, 49b, 50a, 50b… pads 51-53... Well area 54, 55... Pickup area (contact area) 56... Pressure resistance range 57…Embedded area 61...VCC electrode 62...GND electrode 63…VS electrode 64...HO electrode 65…VB electrode 71, 72, 72u, 72v, 72w, 73, 74u, 74v, 74w, 75, 75u, 75v, 75w, 76u, 76v, 76w, 78u, 78v, 78w, 79u, 79v, 79w… Lead frame 81, 81u, 81v, 81w, 82, 82u, 82v, 82w, 83, 83u, 83v, 83w, 84, 84u, 84v, 84w, 85u, 85v, 85w, 86u, 86v, 86w, 87u, 87v, 87w, 88u, 88v, 88w, 89, 89u, 89v, 89w, 90, 90u, 90v, 90w, 91, 92u, 92v, 92w, 93, 94u, 94v, 94w, 95u, 95v, 95w, 96a, 96b, 97a, 97b… Metal wire 100-104... Semiconductor equipment 111~116... Switching elements 121~126... Freewheeling diode

Claims

1. A semiconductor device comprising a GND reference circuit that uses the GND potential as a reference and a floating reference circuit that uses a potential higher than the GND potential as a reference, Lead frame and, A first semiconductor substrate, which is arranged on the lead frame and has the GND reference circuit provided on it, A second semiconductor substrate, which is arranged on the lead frame and on which the floating reference circuit is provided, Equipped with, Either the first semiconductor substrate or the second semiconductor substrate is placed on the lead frame via an insulating material. Semiconductor equipment.

2. The insulating material is an epoxy resin paste or a dicing attachment film sheet. The semiconductor device according to claim 1.

3. The GND reference circuit and the floating reference circuit are electrically connected via a level shift circuit. The semiconductor device according to claim 1 or 2.

4. The level shift circuit described above is An n-channel MOSFET provided on the first semiconductor substrate, A first resistor is provided on the second semiconductor substrate and connected to the drain of the n-channel MOSFET, It is equipped with a level-up circuit. The semiconductor device according to claim 3.

5. The drain of the n-channel MOSFET and the first resistor are electrically connected via a metal wire. The semiconductor device according to claim 4.

6. The level shift circuit described above is Two n-channel MOSFETs provided on the first semiconductor substrate, Two first resistors are provided on the second semiconductor substrate and are connected to the drains of the two n-channel MOSFETs, respectively. It is equipped with a level-up circuit. The semiconductor device according to claim 3.

7. The level shift circuit described above is A p-channel MOSFET provided on the first semiconductor substrate, A second resistor is provided on the first semiconductor substrate and connected to the drain of the p-channel MOSFET, Equipped with a level-down circuit. The semiconductor device according to claim 3.

8. The drain of the p-channel MOSFET and the second resistor are electrically connected via a metal wire. The semiconductor device according to claim 7.

9. The level shift circuit described above is Two p-channel MOSFETs provided on the first semiconductor substrate, Two first resistors are provided on the first semiconductor substrate and connected to the drains of the two p-channel MOSFETs, respectively. Equipped with a level-down circuit. The semiconductor device according to claim 3.

10. The GND potential is applied to the lead frame. The second semiconductor substrate is placed on the lead frame via the insulating material. The semiconductor device according to claim 1 or 2.

11. A potential higher than the GND potential is applied to the lead frame. The first semiconductor substrate is arranged on the lead frame via the insulating material. The semiconductor device according to claim 1 or 2.

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