Method and apparatus for using a storage system as main memory

Abstract

Reduce the cost of main memory. [Solution] The cache module includes an FLC controller and a main memory cache. Multiple cache modules function as main memory. The processor sends read / write requests to the cache modules. The cache module includes two or more stages, each stage including an FLC controller and DRAM. If the FLC module in the first stage does not contain a physical address, the request is forwarded to the FLC module in the second stage. If the FLC module in the second stage does not contain a physical address, the request is forwarded to a storage drive, and a partition is reserved for main memory. The FLC module in the first stage operates at high speed and lower power, while the FLC in the second stage is a low-cost implementation. Multiple FLC modules are connected to the processor in parallel.

Claims

1. A data storage and access system for use with a processor, A processor having a processor cache, wherein the processor is configured to generate data requests for data, An FLC cache system configured to function as main memory and to receive the data request, wherein the FLC system is A first FLC module having a first FLC controller and a first memory, wherein the first FLC module receives the data request from the processor, An FLC cache system comprising: a second FLC module having a second FLC controller and a second memory, wherein the second FLC module receives the data request from the first FLC module in response that the first FLC module does not have the data requested by the processor; A system comprising a storage drive having a user file storage portion and a main memory portion, configured to receive the data request in response that the second FLC module does not have the requested data.

2. The system according to claim 1, wherein the data request includes a physical address, and a loop-up table configured such that a first FLC controller rewrites the physical address to a first virtual address.

3. The system according to claim 2, wherein if the first FLC controller lookup table does not contain the physical address, the first FLC controller is configured to forward the data request having the physical address to the second FLC controller.

4. The system according to claim 3, wherein the second FLC controller includes a loop-up table configured to rewrite the physical address to a second virtual address.

5. The system according to claim 4, wherein the second FLC controller is configured to forward the data request having the physical address to the storage drive if the second FLC controller lookup table does not contain the physical address.

6. The system according to claim 1, wherein the first FLC module is faster and consumes less power than the second FLC module.

7. The system according to claim 1, wherein the first memory is a DRAM and includes a first memory controller, and the second memory is a DRAM and includes a second memory controller.

8. The system according to claim 1, wherein the storage drive is a magnetic disk driver, solid-state memory, or a hybrid drive.

9. The system according to claim 1, wherein the DRAM is a serial DRAM.

10. The system according to claim 1, wherein the first FLC module is at least twice as fast as the second FLC module.

11. The system according to claim 1, wherein the first FLC module and the second FLC module are configured to perform predictive fetching of data stored at addresses that are expected to be accessed in the future.

12. A method for operating a data access system, wherein the data access system comprises a processor having a processor cache, a storage drive, a first FLC module including a first FLC controller and a first DRAM, and a second FLC module including a second FLC controller and a second DRAM. The aforementioned processor generates a data request that includes a physical address, To provide the aforementioned data request to the first FLC module, The first FLC controller determines whether it includes the physical address, The first FLC controller, in response to including the physical address, retrieves the data from the first DRAM and provides the data to the processor, In response to the first FLC controller not including the physical address, it forwards the data request and the physical address to the second FLC module. The second FLC controller determines whether it includes the physical address, A method comprising: in response to the second FLC controller including the physical address, retrieving a cache line containing the data from the second DRAM and providing the cache line to the first FLC module.

13. The method according to claim 12, wherein determining whether the first FLC controller contains the physical address includes accessing an address cache in the first FLC controller that stores address entries in order to reduce the time required for the determination.

14. The method according to claim 12, further comprising forwarding the data request and the physical address to the storage drive in response that the second FLC controller does not include the physical address.

15. The method according to claim 14, further comprising the storage drive retrieving the data from a portion of the storage drive reserved as main memory and providing the data to the second FLC module.

16. The method according to claim 12, further comprising the first FLC controller including the physical address and updating a status register that reflects recent use of the cache line containing the data in response to the provision of the data to the processor.

17. The method according to claim 12, further comprising retrieving the data from the second DRAM and providing the data to the first FLC module, storing the physical address in the first FLC controller, and storing the data in the first DRAM.

18. The method according to claim 17, wherein if the first DRAM does not have available space, the most recently used data is deleted from the first DRAM to create space for the data.

19. A data storage and access system for use in a processor, A processor having a processor cache, wherein the processor is configured to generate a first data request for first data and a second data request for second data. A first FLC cache system that functions as a main memory cache and is configured to receive the first data request for the first data, and communicates with the processor, A second FLC cache system that functions as a main memory cache and is configured to receive the second data request for the second data, and communicates with the processor, A system comprising: a storage drive having a user file storage portion and a main memory partition, wherein the main memory partition of the storage drive is configured to function as main memory.

20. The system according to claim 19, further comprising a system bus, wherein the processor communicates with the first FLC cache system and the second FLC cache system via the system bus such that the addresses assigned to each FLC cache system are interleaved.

21. If the first data is not included in the first FLC cache system, the first data request is sent to the storage drive to retrieve the first data from the main memory partition of the storage drive. The system according to claim 19, wherein if the second data is not included in the second FLC cache system, the second data request is sent to the storage drive to retrieve the first data from the main memory partition of the storage drive.

22. The system according to claim 19, wherein the first FLC cache system comprises a first FLC module and a second FLC module, and the second FLC cache system comprises a third FLC module and a fourth FLC module.

23. The system according to claim 22, wherein each of the FLC modules comprises an FLC controller and a memory.

24. The system according to claim 23, wherein each of the FLC modules maintains a dedicated and unique lookup table.

25. A data storage and access system for use with a processor, An FLC cache system configured to function as a main memory cache and to receive data requests from a processing device, wherein the processor device comprises an FLC cache system having a processor cache, and the FLC system is A first FLC module having a first FLC controller and a first cache memory, wherein the first FLC module receives the data request from the processor, A second FLC module having a second FLC controller and a second cache memory, wherein the second FLC module is In response to the first FLC module not having the data requested by the processor, the second FLC module receives the data request from the first FLC module, A system comprising a second FLC module, configured such that, in response to the second FLC module not having the data requested by the processor, the second FLC module transmits the data request to a storage drive configured to have a portion acting as main memory.

26. The system according to claim 25, further comprising a storage drive having a user file storage portion and a main memory portion, configured to receive the data request in response from the second FLC module and to provide the requested data to the second FLC module.

27. The system according to claim 25, wherein the storage drive is accessed via a network connection.

28. The system according to claim 25, wherein the capacity of the second FLC module is at least eight times greater than the capacity of the first FLC module.

29. The system according to claim 25, wherein the first FLC module and the second FLC module store data in cache lines, the size of which the cache lines is the same as the operating system page size.

30. The system according to claim 25, wherein the first FLC controller lookup table is set-associative with a cache line size of at least 4KB, and the second FLC controller lookup table is fully associative.

31. The system according to claim 25, wherein the first FLC module includes a first DRAM, the second FLC module includes a second DRAM, and the first DRAM and the second DRAM are single-level cell type DRAMs.

32. The system according to claim 31, wherein the first memory is a DRAM and includes a first memory controller, and the second memory is a DRAM and includes a second memory controller.

33. The system according to claim 25, wherein the first FLC module and the second FLC module are configured to perform predictive fetching of data stored at addresses that are expected to be accessed in the future.

34. The system according to claim 25, wherein the first cache memory and the second cache memory each comprise DRAM and are configured such that one or more failed sections are locked out of use.

35. The system according to claim 25, wherein the first cache memory and the second cache memory each include DRAM, and one or more sections of the memory are configured to be temporarily disabled during a health check of the remaining sections of the memory.

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