A cache access method, system, medium and product

Abstract

The application discloses a cache access method and system, a medium and a product, and applies to the technical field of processors, and comprises the following steps: monitoring the memory access behavior of each processor core to a shared cache, each cache line in the shared cache is divided into a preset number of data subsegments, for each processor core, a unique corresponding state identifier is arranged for each data subsegment; after any processor core performs data writing on a target data subsegment of a target cache line in the shared cache, the target data subsegment is written back to a memory, and is loaded from the memory to a private cache of the any processor core, the state identifier of the target data subsegment of the any processor core is determined as a shared state, and the state identifier of the target data subsegment of a first processor core is determined as an invalid state. In this way, unnecessary memory data loading can be reduced, and the overall performance of a multi-core processor is improved.

Description

Technical Field

[0001] This invention relates to the field of processor technology, and in particular to a cache access method, system, medium, and product. Background Technology

[0002] Currently, when multiple cores access the shared cache, there is a significant issue of false sharing. This means that if one processor core modifies only a local portion of data in a cache line, the state of that cache line must be modified. When another processor core accesses that cache line, it needs to be reloaded from memory, even if the data accessed by that core is not the modified data in the cache line. This frequent false sharing leads to constant data loading from memory, increasing data access latency and significantly degrading the performance of multi-core processors.

[0003] Therefore, how to reduce unnecessary memory data loading and thus improve the overall performance of multi-core processors is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a cache access method, system, medium, and product that can reduce unnecessary memory data loading, thereby improving the overall performance of multi-core processors.

[0005] In a first aspect, the present invention provides a cache access method, comprising:

[0006] Monitor the memory access behavior of each processor core to the shared cache. Each cache line in the shared cache is divided into a preset number of data segments. For each processor core, each data segment is set with a unique corresponding status identifier.

[0007] After any processor core writes data to the target data segment of the target cache line in the shared cache, the target data segment is written back to memory and loaded from memory into the private cache of any processor core. The status flag of the target data segment of any processor core is determined to be in a shared state, and the status flag of the target data segment of the first processor core is determined to be in an invalid state.

[0008] The shared state indicates that the private cache is consistent with the data segment in the memory, and the invalid state indicates that when the processor core reads the target data segment, it needs to reload it from the memory to its own private cache. The first processor core belongs to a processor core other than any of the processor cores.

[0009] Optionally, determining the status flag of the target data segment of the first processor core as invalid includes:

[0010] All processor cores other than any of the aforementioned processor cores are designated as the first processor core, and the status identifier of the target data segment of the first processor core is determined to be invalid.

[0011] Optionally, determining the status flag of the target data segment of the first processor core as invalid includes:

[0012] The non-second processor core among the processor cores other than any of the processor cores is identified as the first processor core, and the status identifier of the target data segment of the first processor core is identified as invalid.

[0013] The second processor core is a processor core that has a first memory access behavior. The first memory access behavior is a memory access behavior for the target data segment that precedes the second memory access behavior. The second memory access behavior is the behavior of any processor core writing data to the target data segment of the target cache line in the shared cache.

[0014] Optional, also includes:

[0015] Determine the time interval between the first memory access and the second memory access;

[0016] If the time interval is higher than a preset interval threshold, the status identifier of the target data segment of the second processor core is determined to be invalid.

[0017] Optional, also includes:

[0018] If the time interval is less than or equal to the preset interval threshold, the target data segment is loaded into the private cache of the second processor core, and the status identifier of the target data segment of the second processor core is determined to be in a shared state.

[0019] Optionally, after any processor core writes data to the target data segment of the target cache line in the shared cache, the method further includes:

[0020] When the first processor core is detected reading the target data segment, the target data segment is loaded from the memory into the private cache of the first processor core, and the status identifier of the target data segment of the first processor core is determined to be in a shared state.

[0021] Optional, also includes:

[0022] If the memory access operation targets multiple consecutive cache lines of the shared cache, then the multiple consecutive cache lines are read out and merged to obtain a merged cache line;

[0023] The memory access behavior is responded to based on the merged cache line.

[0024] Optional, also includes:

[0025] If the length of the physical address corresponding to the memory access behavior is the length of multiple consecutive cache lines, and the unique tag value of multiple consecutive cache lines is hit, then the memory access behavior is determined to be multiple consecutive cache lines for the shared cache.

[0026] Optional, also includes:

[0027] Determine the consecutive incrementing number of physical addresses corresponding to the memory access behavior;

[0028] Based on the continuously increasing number and the number of bytes in a single address, it is determined whether the length of the physical address corresponding to the memory access behavior is the length of multiple consecutive cache lines.

[0029] Optionally, determining whether the length of the physical address corresponding to the memory access behavior is equal to the length of multiple consecutive cache lines based on the continuously increasing number and the number of bytes of a single address includes:

[0030] The number of cache lines corresponding to a memory access operation is determined based on the continuously increasing number, the number of bytes in a single address, and the number of bytes in a single cache line.

[0031] If the number of cache lines is greater than or equal to two, then the length of the physical address corresponding to the memory access is the length of multiple consecutive cache lines.

[0032] Optionally, the multiple consecutive cache lines are read and merged to obtain a merged cache line, including:

[0033] Based on the number of cache lines, the consecutive cache lines are read out and merged to obtain the merged cache line.

[0034] Secondly, the present invention provides a cache access system, comprising:

[0035] The monitoring module is used to monitor the memory access behavior of each processor core to the shared cache. Each cache line in the shared cache is divided into a preset number of data segments. For each processor core, each data segment is set with a unique corresponding status identifier.

[0036] The processing module is configured to, after any processor core writes data to the target data segment of the target cache line in the shared cache, write the target data segment back to memory, load it from memory into the private cache of any processor core, determine the status flag of the target data segment of any processor core as a shared state, and determine the status flag of the target data segment of the first processor core as an invalid state.

[0037] The shared state indicates that the private cache is consistent with the data segment in the memory, and the invalid state indicates that when the processor core reads the target data segment, it needs to reload it from the memory to its own private cache. The first processor core belongs to a processor core other than any of the processor cores.

[0038] Optional, also includes:

[0039] The cache line merging module is used to read out and merge the consecutive cache lines if the memory access operation targets multiple consecutive cache lines of the shared cache to obtain a merged cache line; and to respond to the memory access operation based on the merged cache line.

[0040] Thirdly, the present invention provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, it implements the aforementioned cache access method.

[0041] Fourthly, the present invention provides a computer program product, including a computer program / instruction that, when executed by a processor, implements the aforementioned cache access method.

[0042] As can be seen, the beneficial effects of this invention are as follows: Each cache line in the shared cache is divided into multiple data segments. For each processor core, each data segment is assigned a unique corresponding status identifier. The memory access behavior of each processor core to the shared cache is monitored. After any processor core writes data to the target data segment, only the target data segment is written back to memory and loaded from memory into the processor core's private cache. The status identifier of the target data segment of that processor core is determined to be in a shared state, while the status identifiers of the target data segments of other processor cores can be determined to be in an invalid state. In this way, segmented status management of each cache line, based on the monitored access behavior, reduces unnecessary memory data loading, thereby improving the overall performance of multi-core processors. Attached Figure Description

[0043] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a diagram of a multi-core RISC-V CPU architecture in the prior art;

[0045] Figure 2 A flowchart of a cache access method provided in an embodiment of the present invention;

[0046] Figure 3 A multi-core RISC-V CPU implementation architecture diagram provided in this embodiment of the invention;

[0047] Figure 4 A schematic diagram of a cache line dynamic state controller provided in an embodiment of the present invention;

[0048] Figure 5 A schematic diagram of a dynamic high-efficiency cache controller provided in an embodiment of the present invention;

[0049] Figure 6 This is a schematic diagram of a cache access system provided in an embodiment of the present invention. Detailed Implementation

[0050] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0051] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.

[0052] First, the technical terms involved in this invention will be explained:

[0053] Multi-core RISC-V (Reduced Instruction Set Computer - Five) CPU (Central Processing Unit): A multi-processor design based on the open-source RISC-V ISA (Instruction Set Architecture).

[0054] Cache coherence: Multi-core CPUs need to ensure that the cache data of different cores is consistent. Cache coherence is a core issue in multi-core processor design, ensuring that the cache data of multiple cores remains synchronized and avoiding data inconsistencies. In a multi-core system, each core has its own cache (L1 Cache, or Level 1 cache), and the data in memory may have copies in multiple caches. Without consistency management, this can lead to: Stale Read (core A modifies data, but core B still reads the old value), and Write Conflict (multiple cores modifying the same data simultaneously, resulting in incorrect final results).

[0055] The MESI (Modified, Exclusive, Shared, Invalid) protocol is one of the most widely used cache coherence protocols for maintaining cache data consistency in multi-core processors. It defines four states for cache lines and ensures that the memory view seen by multiple cores is consistent through state transition rules.

[0056] A cacheline is the smallest unit of data transfer and management in the CPU cache, and it's the basic block for data exchange between the CPU and main memory (RAM, or Random Access Memory). The functions of a cacheline are: 1. Reducing memory access latency: When the CPU accesses data, if the data is in the cache (Cache Hit), the speed is much faster than reading it from RAM (Cache Miss). 2. Improving data locality: Because programs typically exhibit temporal locality and spatial locality, cachelines can effectively utilize this characteristic to reduce the number of main memory accesses.

[0057] TLB (Translation Lookaside Buffer) is a hardware cache used to accelerate the translation of virtual addresses to physical addresses (i.e., page table lookups).

[0058] See Figure 1 As shown, Figure 1 This is a diagram of a multi-core RISC-V CPU architecture in the prior art, such as... Figure 1As shown, a traditional multi-core RISC-V CPU (i.e., a multi-core processor) contains multiple RISC-V Cores, each with its own instruction fetch unit, decode unit, execution unit, memory access unit, and write-back unit. Each Core corresponds to an L1 cache (Level 1 cache), which is exclusive to the RIC-V Core. Currently, mainstream multi-core RISC-V CPUs range from 2 cores to 128 cores. The L1 cache space is typically 32KB-64KB, while the L2 cache is shared by multiple RISC-V Cores, and its space is typically 256KB-2MB. The pseudo-sharing described above occurs at the L2 Cache (second-level cache) level. For example, if RISC-V Core0 modifies the first byte of Cacheline0 (64 bytes), the cacheline's state must be modified, and its data synchronized to memory. This causes the same cacheline in other cores to become invalid, requiring reloading from memory and resulting in numerous unnecessary cache synchronizations, even if other cores do not need to access the modified first byte of the cacheline. Each cacheline consists of three parts: a state segment, a flag segment, and a data segment. The data segment contains the actually cached data. Only the data segment is truly valid for the RISC-V Core in the cacheline, while the state and flag segments are used for control. In the MESI consistency protocol, each cacheline has four states to achieve the aforementioned cache synchronization. Figure 1 In this context, the memory can be DDR, which stands for DDRSDRAM (Double Data Rate Synchronous Dynamic Random Access Memory).

[0059] Currently, in traditional solutions, the size of the cacheline is fixed, most commonly 64 bytes. This means that a RISC-V core can only return a maximum of 64 bytes of data per cache access. Furthermore, false sharing frequently occurs in multi-core RISC-V CPUs. False sharing occurs when a RISC-V core modifies only a portion of the data in a cacheline, requiring a change to the cacheline's state. When another RISC-V core accesses this cacheline, it needs to be reloaded from memory, even if the data accessed is not the modified data in the cacheline. Traditional multi-core RISC-V CPU cache implementations have two major drawbacks: Drawback 1: In traditional solutions, when multiple cores access shared caches, such as L2 / L3 caches (i.e., level 3 caches), there is a significant amount of false sharing, especially in scenarios with frequent data interaction between cores. The consequence of this excessive false sharing is the need to constantly update data from memory to the cache, resulting in significant data access latency. This unnecessary latency leads to a substantial reduction in the performance of multi-core RISC-V CPUs. Disadvantage 2: In traditional solutions, the size of the cache line is fixed, usually 64 bytes by default. However, a fixed-length cache line is not very friendly to the scenario of continuous access to the cache by the RISC-V Core, resulting in low cache access efficiency and low effective data occupancy within the cache line, which is insufficient to efficiently meet the data needs of the RISC-V Core.

[0060] The first drawback is that when two threads (deployed on two RISC-V cores respectively) access different variables in the same cache line, even if these variables are logically unrelated, cache consistency issues can arise. If one RISC-V core modifies any data in the cache line, the same cache line in other cores will become invalid, requiring reloading from memory and causing a large amount of unnecessary cache synchronization. The second drawback is that data crossing cache line boundaries requires two cache accesses, especially in scenarios where RISC-V cores access the cache consecutively. Traditional fixed-length cache line designs cannot efficiently meet the requirements of fast data read and write operations for RISC-V cores. Therefore, this invention provides a cache access scheme that reduces the probability of false sharing in multi-core RISC-V CPUs, reduces unnecessary cache line data updates, reduces data access latency, optimizes the dynamic length changes of cache lines in specific scenarios, optimizes the cache line data acquisition process, further improves the cache access efficiency of multi-core RISC-V CPUs and the overall performance of RISC-V CPUs, and promotes the commercial application of multi-core RISC-V CPUs in high-performance processor scenarios.

[0061] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0062] Next, a cache access method provided by an embodiment of the present invention will be described in detail. Figure 2 A flowchart of a cache access method provided in an embodiment of the present invention is shown. The cache access method includes:

[0063] Step S11: Monitor the memory access behavior of each processor core to the shared cache. Each cache line in the shared cache is divided into a preset number of data segments. For each processor core, each data segment is set with a unique corresponding status identifier.

[0064] The shared cache can be an L2 (Level 2) or L3 (Level 3) cache, while the L1 (Level 1) cache is a private cache for each processor core. That is, each processor core has its own Level 1 cache, and processors share either the Level 2 or Level 3 cache. In this embodiment, the preset number is multiple, i.e., greater than or equal to 2. Each processor core has its own unique cache line state table, recording the state identifier of each data segment in each cache line of the shared cache. For example, the preset number is 8, using 8-byte units, dividing the 64-byte cache line in L2 into data segments 0 to 7, resulting in 8 states for each cache line.

[0065] In this embodiment, memory access behavior can include read and write behaviors. For read behavior, if the corresponding data does not exist in the private cache, the data is read from the shared cache, loaded into the private cache, and then returned. Write behavior can directly write to the shared cache. This embodiment can determine the data segment to be accessed based on the address information and control fields in the memory access instruction issued by the processor core.

[0066] Step S12: After any processor core writes data to the target data segment of the target cache line in the shared cache, the target data segment is written back to memory and loaded from memory into the private cache of any processor core. The status flag of the target data segment of any processor core is determined to be in a shared state, and the status flag of the target data segment of the first processor core is determined to be in an invalid state.

[0067] The shared state indicates that the private cache is consistent with the data segment in the memory, and the invalid state indicates that when the processor core reads the target data segment, it needs to reload it from the memory to its own private cache. The first processor core belongs to a processor core other than any of the processor cores.

[0068] In an optional implementation, determining the status identifier of the target data segment of the first processor core as invalid includes: determining all processor cores other than any of the processor cores as the first processor core, and determining the status identifier of the target data segment of the first processor core as invalid.

[0069] That is, in this embodiment of the invention, the status identifier of the target data segment of any processor core other than the processor core can be determined as invalid. When the target data segment is read, it needs to be reloaded from memory to its own private cache.

[0070] In an optional implementation, determining the status identifier of the target data segment of the first processor core as invalid includes: identifying a non-second processor core among the processor cores other than the first processor core as the first processor core, and determining the status identifier of the target data segment of the first processor core as invalid; wherein, the second processor core is a processor core that has a first memory access behavior, the first memory access behavior is the memory access behavior for the target data segment before the second memory access behavior, and the second memory access behavior is the behavior of the first processor core writing data to the target data segment of the target cache line in the shared cache.

[0071] That is, in this embodiment of the invention, if other processor cores have also written to the target data segment before any processor core writes data to the target data segment of the target cache line in the shared cache, then the other processor cores are determined to be the second processor core. The second processor core can be determined by searching memory access records within a preset time period before any processor core writes data to the target data segment of the target cache line in the shared cache; that is, premature actions can be disregarded.

[0072] Furthermore, it also includes: determining the time interval between the first memory access behavior and the second memory access behavior; if the time interval is higher than a preset interval threshold, then determining the status flag of the target data segment of the second processor core as invalid. If the time interval is less than or equal to the preset interval threshold, then loading the target data segment into the private cache of the second processor core, and determining the status flag of the target data segment of the second processor core as shared.

[0073] In this embodiment, considering processor design principles, if other processor cores have also operated on the data segment in a relatively recent period of time, there is a high probability that the processor core will operate on the data segment again.

[0074] Furthermore, in this embodiment of the invention, after any processor core writes data to the target data segment of the target cache line in the shared cache, the method further includes: when the reading behavior of the first processor core on the target data segment is detected, the target data segment is loaded from the memory into the private cache of the first processor core, and the status identifier of the target data segment of the first processor core is determined to be in a shared state.

[0075] In other words, when reading, the data is in an invalid state, and is loaded from memory into a private cache to ensure that accurate data is read.

[0076] In an optional embodiment, for all write operations, the following steps are performed: after any processor core writes data to the target data segment of the target cache line in the shared cache, the target data segment is written back to memory and loaded from memory into the private cache of any processor core, the status identifier of the target data segment of any processor core is determined to be in a shared state, and the status identifier of the target data segment of the first processor core is determined to be in an invalid state.

[0077] For example, suppose there are 8 cores, Cores 0 to 7. Core 0 writes data segment 0 to a cache line. After writing, it writes data segment 0 back to memory and loads it from memory into Core 0's private cache. The status of data segment 0 in Core 0 is set to shared, while the status of data segment 0 in other cores (Cores 1 to 7) is set to invalid. If Core 1's read behavior is monitored next, the data segment 0 is loaded from memory into Core 1's private cache, and the status of data segment 0 in Core 1 is set to shared, while the status of data segment 0 in Cores 2 to 7 remains invalid. If Core 1's write behavior is monitored next, after writing, the data segment 0 is loaded from memory into Core 1's private cache, and the status of data segment 0 in Core 1 is set to shared, while the status of data segment 0 in Cores 2 to 7 remains invalid. Based on the time interval between this write action and the aforementioned write action of Core0, if the time interval is greater than the time interval threshold, the status flag of the data segment 0 of Core0 is determined to be invalid; otherwise, the current data segment 0 is loaded from memory into the private cache of Core0, and the status flag of the data segment 0 of Core0 is determined to be shared.

[0078] In an optional embodiment, for the first write operation of a target data segment, after any processor core writes data to the target data segment of the target cache line in the shared cache, if this write is the first write of the target data segment, the status identifier of the target data segment of the other processor cores can remain unchanged if no memory access operation of the target data segment by other processor cores is detected. If a processor core reads the target data segment after the first write operation, the target data segment is written back to memory and loaded from memory into the private cache of that processor core. The status identifier of the target data segment of that processor core is determined to be in a shared state, and the status identifier of the target data segment of the other processor cores is determined to be in an invalid state. If a processor core writes to the target data segment after the first write operation, the target data segment is written back to memory and loaded from memory into the private cache of that processor core. The status identifier of the target data segment of that processor core is determined to be in a shared state, and the status identifier of the target data segment of the first processor core is determined to be in an invalid state. That is, for a non-first write to the target data segment, after any processor core writes data to the target data segment of the target cache line in the shared cache, if the write is not the first write to the target data segment, then the target data segment is written back to memory and loaded from memory into the private cache of any processor core. The status identifier of the target data segment of any processor core is determined to be in a shared state, and the status identifier of the target data segment of the first processor core is determined to be in an invalid state.

[0079] For example, suppose there are 8 cores, Cores 0 through 7. Core 0 writes data segment 0 to a cache line. This write is the first write operation for data segment 0. No subsequent memory access is detected, and the state of data segment 0 remains unchanged for Core 0 and the other cores. If Core 1's read operation (the first memory access for data segment 0 after the initial write) is detected, data segment 0 is written back to memory and loaded from memory into Core 1's private cache. The state of data segment 0 in Core 1 is then set to shared, while the state of data segment 0 in other cores is set to invalid. If Core 1's write operation (the first memory access for data segment 0 after the initial write) is detected, data segment 0 is written back to memory and loaded from memory into Core 1's private cache. The state of data segment 0 in Core 1 is then set to shared, while the state of data segment 0 in Cores 2 through 7 is set to invalid. Based on the time interval between this write operation and the first write operation of Core0, if the time interval is greater than the time interval threshold, the status flag of the data segment 0 of Core0 is determined to be invalid; otherwise, the current data segment 0 is loaded from memory into the private cache of Core0, and the status flag of the data segment 0 of Core0 is determined to be shared.

[0080] In an optional embodiment, the method may further include: if the memory access operation targets multiple consecutive cache lines of the shared cache, then reading out the multiple consecutive cache lines and merging them to obtain a merged cache line; and responding to the memory access operation based on the merged cache line.

[0081] Specifically, if the memory access is a read operation, the merged cache line is loaded into the private cache of the corresponding processor core, and then returned from the private cache to the processor core. If the memory access is a write operation, the merged cache line is loaded into memory, and then loaded from memory into the private cache of the corresponding processor core. This merging process improves memory access efficiency.

[0082] Furthermore, embodiments of the present invention may also include: if the length of the physical address corresponding to the memory access behavior is the length of multiple consecutive cache lines, and the unique tag value of multiple consecutive cache lines is hit, then the memory access behavior is determined to be multiple consecutive cache lines for the shared cache.

[0083] Among them, the unique tag value for hitting multiple consecutive cache lines indicates that there are multiple consecutive cache lines in the cache. The unique tag value is TAG, which means that the length of the physical address corresponding to the memory access line meets the condition, and the data is in the cache and can be merged.

[0084] Furthermore, embodiments of the present invention may also include: determining the number of consecutively increasing physical addresses corresponding to the memory access behavior; and determining whether the length of the physical address corresponding to the memory access behavior is the length of multiple consecutive cache lines based on the number of consecutively increasing physical addresses and the number of bytes of a single address.

[0085] One physical address represents 4 bytes of data. The number of bytes in a single cache line and the consecutive increments can determine whether the access line corresponds to multiple consecutive cache lines.

[0086] In an optional embodiment, determining whether the length of the physical address corresponding to the memory access behavior is the length of multiple consecutive cache lines based on the continuously increasing number and the number of bytes of a single address may include: determining the number of cache lines corresponding to the memory access behavior based on the continuously increasing number, the number of bytes of a single address, and the number of bytes of a single cache line; if the number of cache lines is greater than or equal to two, then the length of the physical address corresponding to the memory access behavior is the length of multiple consecutive cache lines.

[0087] The number of cache lines is obtained by multiplying the continuously increasing number by the number of bytes in a single address and then dividing by the number of bytes in a single cache line.

[0088] In an optional implementation, reading and merging the consecutive cache lines to obtain a merged cache line includes: reading and merging the consecutive cache lines based on the number of cache lines to obtain a merged cache line. For example, if the number of cache lines is 2, then 2 consecutive cache lines are read and merged.

[0089] In an optional implementation, reading and merging the consecutive cache lines to obtain a merged cache line includes: reading and merging the consecutive cache lines based on the number of bytes in the consecutive cache lines to obtain a merged cache line. The number of bytes in the consecutive cache lines is the number of cache lines multiplied by the number of bytes in a single cache line.

[0090] As can be seen, this embodiment of the invention divides each cache line in the shared cache into multiple data segments. For each processor core, each data segment is assigned a unique corresponding status identifier. The memory access behavior of each processor core to the shared cache is monitored. After any processor core writes data to the target data segment, only the target data segment is written back to memory and loaded from memory into the processor core's private cache. The status identifier of the target data segment of that processor core is determined to be in a shared state, while the status identifiers of the target data segments of other processor cores can be determined to be in an invalid state. In this way, segmented status management of each cache line, based on the monitored access behavior, reduces unnecessary memory data loading, thereby improving the overall performance of the multi-core processor. Furthermore, when memory access involves multiple consecutive cache lines, they are merged, improving memory access efficiency.

[0091] Further, see Figure 3 As shown, Figure 3 This invention provides an architecture diagram for a multi-core RISC-V CPU. It applies the cache access method provided by this invention. Two core modules are added: a dynamic cache line state controller and a dynamic high-efficiency cache controller. This enables efficient handling of cacheline consistency across multiple RISC-V cores. The dynamic state of the cacheline is designed and implemented, avoiding the false sharing phenomenon in traditional solutions. This significantly reduces unnecessary memory data loading and cacheline state updates, thereby improving the overall performance of the RISC-V CPU. Simultaneously, an efficient cache data acquisition mechanism for specific scenarios is optimized, achieving software-insensitive, hardware-adaptive dynamic adjustment of the cacheline length. This further improves the cache access efficiency of multi-core RISC-V CPUs and the overall performance of RISC-V CPUs, promoting the commercial application of multi-core RISC-V CPUs in high-performance processor scenarios.

[0092] See Figure 4 As shown, Figure 4 This diagram illustrates a cache line dynamic state controller according to an embodiment of the present invention. The cache line dynamic state controller dynamically maintains the state control of a cache line in a shared cache (such as L2 cache) after a single RISC-V core modifies that cache line. This reduces a large number of unnecessary write-backs of shared cache line data to memory and loads from memory to the private memory of other RISC-V cores, thus achieving a design that avoids false sharing. The cache line dynamic state controller may include a processor core memory access operation monitoring module and a cache line dynamic state table maintenance module.

[0093] The processor core memory access monitoring module monitors the address information and control fields in memory access instructions issued by all RISC-V cores in a multi-core RISC-V CPU. These fields include AWADDR, AWSIZE, ARADDR, and ARSIZE in the AXI (Advanced eXtensible Interface) protocol. Currently, the interface between the memory access unit and cache in multi-core RISC-V CPUs is generally the AXI interface. AWADDR is the cache address to be written, and AWSIZE is the size of the data to be written (in bytes; for example, a value of 2 indicates...). (i.e., 4 bytes). Similarly, ARADDR is the cache address to be read, and ARSIZE is the size of the data to be read (in bytes; for example, if its value is 3, it means...). (i.e., 8 bytes). This module is designed to monitor memory access information in the cache of each core's memory access unit. In other words, it can detect memory access behavior that is about to occur in the memory access unit in advance, so that subsequent modules can promptly perform relevant state changes and load memory data.

[0094] The function of the cache line dynamic state table maintenance module is to create and maintain the dynamic state table of the multi-core RISC-V CPU cacheline, i.e., the aforementioned cache line state table. Each RISC-V core maintains its own dynamic state table. It is worth noting that, for example, the cacheline dynamic state is in 8-byte units. In traditional schemes, a cacheline has only one state. In this embodiment of the invention, a cacheline has eight states (64 bytes / 8 bytes, calculated based on a 64-byte data segment). The 64-byte cacheline is divided into data segments 0 through 7, using 8-byte units. The decision to write or read a specific data segment is based on feedback from the preceding modules, i.e., based on monitored memory access behavior to determine the specific data segment to be written to the cacheline.

[0095] For example, in the front-end processor core memory access monitoring module, AWADDR=0x0001_0000 (this address is the physical address after TLB lookup and translation; the core actually issues a virtual address), AWSIZE=4, indicating that this write cache operation is at address 0x0001_0000, and the amount of data written is 16 bytes, that is, the write range is 0x0001_0000, 0x0001_0004, 0x0001_0008, 0x0001_000C, that is, the data field 0 and data field 1 of the cacheline starting at address 0x0001_0000 are written. The address range of the cacheline starting at address 0x0001_0000 is (occupying 64 bytes, divided into 8 sub-segments): Data sub-segment 0: 0x0001_0000, 0x0001_0004; Data sub-segment 1: 0x0001_0008, 0x0001_000C; Data sub-segment 2: 0x0001_0010, 0x0001_0014; Data sub-segment... Data segments 3: 0x0001_0018, 0x0001_001C; 4: 0x0001_0020, 0x0001_0024; 5: 0x0001_0028, 0x0001_002C; 6: 0x0001_0030, 0x0001_0034; 7: 0x0001_0038, 0x0001_003C. Therefore, this module needs to determine the specific cacheline data segments corresponding to the memory access operations of each RISC-V Core in order to implement dynamic state changes for each data segment of the cacheline. The application implements the maintenance of state changes for different data segments of each cacheline for each RISC-V Core, with each Core corresponding to a dynamic cacheline state table.

[0096] Further, see Figure 5 As shown, Figure 5 This diagram illustrates a dynamic high-efficiency cache controller provided in an embodiment of the present invention. The dynamic high-efficiency cache controller implements an efficient cache data acquisition mechanism for specific scenarios, achieving dynamic adjustment of the cacheline length with software-insensitive hardware adaptation, further improving the cache access efficiency of multi-core RISC-V CPUs and the overall performance of RISC-V CPUs. This module operates on cache lines of the shared cache and may include a translation-backup buffer parallel lookup module, a memory access unit address change monitoring module, a cache tag detection module, and a comprehensive adjustment control module.

[0097] The translation backup buffer parallel lookup module is responsible for converting the virtual address issued by the Core into a physical address and transmitting the physical address to the subsequent module.

[0098] The memory access unit address change monitoring module is used to monitor the address change patterns of memory access units of each RISC-V Core in a multi-core RISC-V CPU, and whether there are continuous change scenarios, such as whether the address of a read operation is continuously increasing, and whether the address of a write operation is a continuous address. For example, if the memory access behavior is detected to be 0x1000_0000, 0x1000_0004... and the number of consecutive increments CNT0, one address represents the storage of 4 bytes of data, and the number of consecutive increments CNT0 is the number of consecutively incremented physical addresses, i.e., the aforementioned number of consecutive increments.

[0099] The cache tag detection module queries the cache for TAG information based on the physical address corresponding to consecutive memory access instructions. If a TAG can be matched consecutively in the cache, meaning the corresponding data segment in the cacheline can be retrieved consecutively, the subsequent module is triggered. A cacheline caches 64 bytes of data by default. The number of consecutive matching cachelines is CNT1, which is the aforementioned number of cache lines. CNT1 <= CNT0 / 16, CNT1 = CNT0 4 / 64, rounded down. The tag segment of a cache line contains three parts: TAG (tag), INDEX (index), and OFFSET (offset). Each cacheline has a unique TAG value, which can be the physical address in memory of the data corresponding to that cacheline. INDEX is used to determine which group in the cache the searched data is in, such as which group in a 4-way set-associative cache. OFFSET is used to find the specific byte in a particular cacheline. For example, in a 32KB 4-way set-associative cache, the size of each path is the total cache size divided by the number of paths, i.e., 32KB / 4 = 8KB. The number of cachelines in each path is equal to the block size divided by the cacheline size. Assuming a cacheline is 64 bytes, then the number of cachelines in each path is 8KB / 64Byte = 128. In the cache encoded address, bits [5:0] are used to select data in the cache line, where bits [5:2] can be used to address 16 words, and bits [1:0] can be used to address bytes in each word. Bits [12:6] are used for index selection of each cacheline, and the remaining bits [31:13] are used as tags. The bits described above... The address is matched using the address issued by the RISC-V Core. A cache line contains multiple words, and a word contains 4 bytes. Bits [1:0] represent the range 0-3, thus indicating which byte in a word. Bits [5:2] are used to determine which word it is, because the total capacity of a cache line is 64 bytes, which is 64 / 4 = 16 words, and bits [5:2] represent the range 0-15, thus determining which word in the cache line it is. For example, bit [5:2] = 2, bit [1:0] = 1, indicating the 2nd byte of the 3rd word in the cache line (counting from 0). Bits [12:6] are used to determine which cache line it is, which can be considered as selecting which cache line. Therefore, [12:6] represents which cache line is selected, [5:2] represents which word in the corresponding cache line, and [1:0] represents which byte in the corresponding word.

[0100] Integrated adjustment control module: After this module is triggered, the configuration value CNT1 will be adjusted. The 64 or CNT1 and the enable signal `enable_large_cacheline` are passed to the memory access unit of the corresponding RISC-V Core. The memory access unit triggers an AXI burst read / write operation. Simultaneously, for the cacheline, the data from CNT1 cachelines is read and merged, avoiding the drawback of traditional solutions where accessing data across cacheline boundaries requires multiple cache accesses, effectively increasing the cacheline length. For example, if CNT1=2, the cacheline length becomes 128 bytes. After receiving consecutive memory access signals from the corresponding RISC-V Core, if it's a read operation, the merged data from multiple cachelines is returned in parallel. In this embodiment of the invention, the cacheline length is inconsistent for each RISC-V Core. For example, RISC-V Core0 uses a cacheline length of up to 128 bytes, while RISC-V Core1 still uses 64 bytes, depending on whether the results of the memory access unit address change monitoring module and the cache tag detection module issued by each Core meet the conditions for triggering the synthesis adjustment control module. This function is also a continuous monitoring function. When the conditions for triggering the comprehensive adjustment control module are no longer met, the cacheline length and corresponding control operations will be automatically restored, and continuous monitoring will continue.

[0101] Thus, this embodiment of the invention, by adding two core modules—a dynamic cache line state controller and a dynamic high-efficiency cache controller—achieves efficient handling of cacheline consistency across multiple RISC-V cores. It designs and implements dynamic cacheline states, avoiding the false sharing phenomenon in traditional solutions, and significantly reducing unnecessary memory data loading and cacheline state updates, thereby improving the overall performance of the RISC-V CPU. Simultaneously, it optimizes and implements an efficient cache data acquisition mechanism for specific scenarios, achieving software-insensitive, hardware-adaptive dynamic adjustment of cacheline length, further improving the cache access efficiency and overall performance of multi-core RISC-V CPUs, and promoting the commercial application of multi-core RISC-V CPUs in high-performance processor scenarios.

[0102] In optional implementations, hardware design can be implemented based on the above caching method. That is, this invention provides a hardware design method to improve the cache access efficiency of multi-core RISC-V CPUs, thereby improving cache data access efficiency, reducing performance degradation caused by false sharing, and improving the overall performance of multi-core RISC-V CPUs. The embodiments of this invention design and implement efficient processing of cacheline consistency across multiple RISC-V cores, and design and implement dynamic state changes of each data segment of the cacheline for different RISC-V cores, avoiding false sharing, unnecessary data write-back to memory, and memory data loading, greatly improving cache access efficiency. An efficient cache data acquisition method is implemented for specific scenarios, and a software-insensitive, hardware-adaptive dynamic adjustment mechanism for cacheline length is designed, greatly accelerating cache access efficiency and improving the overall performance of multi-core RISC-V CPUs.

[0103] See Figure 6 As shown, an embodiment of the present invention provides a cache access system, including:

[0104] The monitoring module 11 is used to monitor the memory access behavior of each processor core to the shared cache. Each cache line in the shared cache is divided into a preset number of data segments. For each processor core, each data segment is set with a unique corresponding status identifier.

[0105] Processing module 12 is used to write the target data segment back to memory after any processor core writes data to the target data segment of the target cache line in the shared cache, and load the target data segment from the memory into the private cache of any processor core, determine the status flag of the target data segment of any processor core as a shared state, and determine the status flag of the target data segment of the first processor core as an invalid state.

[0106] The shared state indicates that the private cache is consistent with the data segment in the memory, and the invalid state indicates that when the processor core reads the target data segment, it needs to reload it from the memory to its own private cache. The first processor core belongs to a processor core other than any of the processor cores.

[0107] In an optional embodiment, the processing module 12 may be specifically configured to identify all processor cores other than any of the processor cores as the first processor core, and to determine the status identifier of the target data segment of the first processor core as invalid.

[0108] In an optional embodiment, the processing module 12 may be specifically configured to identify a non-second processor core among the processor cores other than the stated processor core as the first processor core, and to determine the status identifier of the target data segment of the first processor core as invalid; wherein, the second processor core is a processor core that has a first memory access behavior, the first memory access behavior is the memory access behavior for the target data segment prior to the second memory access behavior, and the second memory access behavior is the behavior of the stated processor core writing data to the target data segment of the target cache line in the shared cache.

[0109] In an optional embodiment, the processing module 12 can further be configured to: determine the time interval between the first memory access and the second memory access; if the time interval is higher than a preset interval threshold, then determine the status flag of the target data segment of the second processor core as invalid; if the time interval is less than or equal to the preset interval threshold, then load the target data segment into the private cache of the second processor core, and determine the status flag of the target data segment of the second processor core as shared.

[0110] In an optional embodiment, the processing module 12 can also be used to: after any processor core writes data to the target data segment of the target cache line in the shared cache, when the reading behavior of the first processor core on the target data segment is detected, load the target data segment from the memory into the private cache of the first processor core, and determine the status identifier of the target data segment of the first processor core as a shared state.

[0111] Furthermore, the system also includes:

[0112] The cache line merging module is used to read out and merge the consecutive cache lines if the memory access operation targets multiple consecutive cache lines of the shared cache to obtain a merged cache line; and to respond to the memory access operation based on the merged cache line.

[0113] In an optional implementation, the cache line merging module can also be used to: if the length of the physical address corresponding to the memory access behavior is the length of multiple consecutive cache lines, and the unique tag value of multiple consecutive cache lines is hit, then determine that the memory access behavior is for multiple consecutive cache lines of the shared cache.

[0114] In an optional implementation, the cache line merging module can also be used to: determine the consecutive incrementing number of physical addresses corresponding to the memory access behavior; and determine whether the length of the physical address corresponding to the memory access behavior is the length of multiple consecutive cache lines based on the consecutive incrementing number and the number of bytes of a single address.

[0115] In an optional implementation, the cache line merging module can be specifically used to: determine the number of cache lines corresponding to a memory access behavior based on the continuously increasing number, the number of bytes in a single address, and the number of bytes in a single cache line; if the number of cache lines is greater than or equal to two, then the length of the physical address corresponding to the memory access behavior is the length of multiple consecutive cache lines.

[0116] In an optional implementation, the cache line merging module can be specifically used to: read out and merge the consecutive cache lines based on the number of cache lines to obtain merged cache lines.

[0117] In an optional implementation, the cache line dynamic status controller disclosed in the foregoing embodiments may include a monitoring module and a processing module. The functions of the monitoring module, namely the processor core memory access operation monitoring module and the cache line dynamic status table maintenance module, are implemented through the processing module. The dynamic and efficient cache controller may be the aforementioned cache line merging module.

[0118] As can be seen, this embodiment of the invention divides each cache line in the shared cache into multiple data segments. For each processor core, each data segment is assigned a unique corresponding status identifier. The memory access behavior of each processor core to the shared cache is monitored. After any processor core writes data to the target data segment, only the target data segment is written back to memory and loaded from memory into the processor core's private cache. The status identifier of the target data segment of that processor core is determined to be in a shared state, while the status identifiers of the target data segments of other processor cores can be determined to be in an invalid state. In this way, segmented status management of each cache line, based on the monitored access behavior, reduces unnecessary memory data loading, thereby improving the overall performance of the multi-core processor. Furthermore, when memory access involves multiple consecutive cache lines, they are merged, improving memory access efficiency.

[0119] Figure 6 For a description of the features in the corresponding embodiments, please refer to Figure 2 The relevant descriptions of the corresponding embodiments will not be repeated here.

[0120] It is understood that if the cache access method in the above embodiments is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the current technology, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drive, mobile hard drive, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, magnetic disk or optical disk, and other media capable of storing program code.

[0121] Based on this, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the cache access method described above.

[0122] Furthermore, embodiments of the present invention also provide a computer program product, including a computer program / instruction, which, when executed by a processor, implements the aforementioned cache access method.

[0123] The foregoing has provided a detailed description of a cache access method, system, medium, and product provided by embodiments of the present invention. The various embodiments are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0124] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0125] The foregoing has provided a detailed description of the cache access method, system, medium, and product provided by this invention. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of this invention.

Claims

1. A cache access method, characterized in that, include: Monitor the memory access behavior of each processor core to the shared cache. Each cache line in the shared cache is divided into a preset number of data segments. For each processor core, each data segment is set with a unique corresponding status identifier. After any processor core writes data to the target data segment of the target cache line in the shared cache, the target data segment is written back to memory and loaded from memory into the private cache of any processor core. The status flag of the target data segment of any processor core is determined to be in a shared state, and the status flag of the target data segment of the first processor core is determined to be in an invalid state. The shared state indicates that the private cache is consistent with the data segment in the memory, and the invalid state indicates that when the processor core reads the target data segment, it needs to reload it from the memory to its own private cache. The first processor core belongs to a processor core other than any of the processor cores.

2. The cache access method according to claim 1, characterized in that, Determining the status flag of the target data segment of the first processor core as invalid includes: All processor cores other than any of the aforementioned processor cores are designated as the first processor core, and the status identifier of the target data segment of the first processor core is determined to be invalid.

3. The cache access method according to claim 1, characterized in that, Determining the status flag of the target data segment of the first processor core as invalid includes: The non-second processor core among the processor cores other than any of the processor cores is identified as the first processor core, and the status identifier of the target data segment of the first processor core is identified as invalid. The second processor core is a processor core that has a first memory access behavior. The first memory access behavior is a memory access behavior for the target data segment that precedes the second memory access behavior. The second memory access behavior is the behavior of any processor core writing data to the target data segment of the target cache line in the shared cache.

4. The cache access method according to claim 3, characterized in that, Also includes: Determine the time interval between the first memory access and the second memory access; If the time interval is higher than a preset interval threshold, the status identifier of the target data segment of the second processor core is determined to be invalid.

5. The cache access method according to claim 4, characterized in that, Also includes: If the time interval is less than or equal to the preset interval threshold, the target data segment is loaded into the private cache of the second processor core, and the status identifier of the target data segment of the second processor core is determined to be in a shared state.

6. The cache access method according to claim 1, characterized in that, After any processor core writes data to the target data segment of the target cache line in the shared cache, the process further includes: When the first processor core is detected reading the target data segment, the target data segment is loaded from the memory into the private cache of the first processor core, and the status identifier of the target data segment of the first processor core is determined to be in a shared state.

7. The cache access method according to any one of claims 1 to 6, characterized in that, Also includes: If the memory access operation targets multiple consecutive cache lines of the shared cache, then the multiple consecutive cache lines are read out and merged to obtain a merged cache line; The memory access behavior is responded to based on the merged cache line.

8. The cache access method according to claim 7, characterized in that, Also includes: If the length of the physical address corresponding to the memory access behavior is the length of multiple consecutive cache lines, and the unique tag value of multiple consecutive cache lines is hit, then the memory access behavior is determined to be multiple consecutive cache lines for the shared cache.

9. The cache access method according to claim 8, characterized in that, Also includes: Determine the consecutive incrementing number of physical addresses corresponding to the memory access behavior; Based on the continuously increasing number and the number of bytes in a single address, it is determined whether the length of the physical address corresponding to the memory access behavior is the length of multiple consecutive cache lines.

10. The cache access method according to claim 9, characterized in that, Determining whether the length of the physical address corresponding to the memory access behavior is equal to the length of multiple consecutive cache lines based on the continuously increasing number and the number of bytes at a single address includes: The number of cache lines corresponding to a memory access operation is determined based on the continuously increasing number, the number of bytes in a single address, and the number of bytes in a single cache line. If the number of cache lines is greater than or equal to two, then the length of the physical address corresponding to the memory access is the length of multiple consecutive cache lines.

11. The cache access method according to claim 10, characterized in that, The multiple consecutive cache lines are read and merged to obtain a merged cache line, including: Based on the number of cache lines, the consecutive cache lines are read out and merged to obtain the merged cache line.

12. A cache access system, characterized in that, include: The monitoring module is used to monitor the memory access behavior of each processor core to the shared cache. Each cache line in the shared cache is divided into a preset number of data segments. For each processor core, each data segment is set with a unique corresponding status identifier. The processing module is configured to, after any processor core writes data to the target data segment of the target cache line in the shared cache, write the target data segment back to memory, load it from memory into the private cache of any processor core, determine the status flag of the target data segment of any processor core as a shared state, and determine the status flag of the target data segment of the first processor core as an invalid state. The shared state indicates that the private cache is consistent with the data segment in the memory, and the invalid state indicates that when the processor core reads the target data segment, it needs to reload it from the memory to its own private cache. The first processor core belongs to a processor core other than any of the processor cores.

13. The cache access system according to claim 12, characterized in that, Also includes: The cache line merging module is used to read out and merge the consecutive cache lines if the memory access operation targets multiple consecutive cache lines of the shared cache, so as to obtain a merged cache line. The memory access behavior is responded to based on the merged cache line.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the cache access method as described in any one of claims 1 to 11.

15. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instruction is executed by the processor, it implements the cache access method as described in any one of claims 1 to 11.

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