A cache access method, system, medium and product
By segmenting shared cache lines and setting status flags, the memory access behavior of multi-core processors can be monitored and managed, thus solving the false sharing problem and improving the performance and memory access efficiency of multi-core processors.
CN121901121BActive Publication Date: 2026-06-09SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
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Patent Information
- Application Number
- CN202610369228.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2026-03-25
- Publication Date
- 2026-06-09
- Estimated Expiration
- 2046-03-25
AI Technical Summary
Technical Problem
False sharing exists in multi-core processors, leading to unnecessary memory data loading, resulting in data access latency and performance degradation.
Method used
Each cache line in the shared cache is divided into multiple data segments, and each processor core is assigned a unique status identifier. The memory access behavior is monitored, and the target data segment is written back to memory after writing. The target data segments of other processor cores are marked as invalid, reducing unnecessary memory data loading.
Benefits of technology
By segmented state management and monitoring access behavior, unnecessary memory data loading is reduced, thereby improving the overall performance and memory access efficiency of multi-core processors.
✦ Generated by Eureka AI based on patent content.
Abstract
The application discloses a cache access method and system, a medium and a product, and applies to the technical field of processors, and comprises the following steps: monitoring the memory access behavior of each processor core to a shared cache, each cache line in the shared cache is divided into a preset number of data subsegments, for each processor core, a unique corresponding state identifier is arranged for each data subsegment; after any processor core performs data writing on a target data subsegment of a target cache line in the shared cache, the target data subsegment is written back to a memory, and is loaded from the memory to a private cache of the any processor core, the state identifier of the target data subsegment of the any processor core is determined as a shared state, and the state identifier of the target data subsegment of a first processor core is determined as an invalid state. In this way, unnecessary memory data loading can be reduced, and the overall performance of a multi-core processor is improved.
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