Clock modulation circuit and clock modulation method

Abstract

The objective is to provide a clock modulation circuit that can measure the characteristics of a clock with greater precision. [Solution] The clock modulation circuit of the embodiment includes a clock output circuit, a multiple frequency divider circuit that receives a clock from the clock output circuit and has a plurality of frequency divider circuits that divide the clock, and a frequency divider control circuit that controls the timing of the start of frequency division for each of the plurality of frequency divider circuits and controls the phase difference between at least one pair of output signals of the plurality of frequency divider circuits based on the period of the clock.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a clock modulation circuit and a clock modulation method. [Background technology]

[0002] Microcontroller Units (MCUs) and Micro Processing Units (MPUs) sometimes incorporate clocks with frequencies around GHz. Since the characteristics of the clock affect the chip's performance, it is desirable to measure its characteristics (such as jitter and duty cycle). When measuring the clock off-chip, the high frequency of the on-chip clock may be too high for external circuits to measure its characteristics. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2006 / 0103367 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] The problem that this invention aims to solve is to provide a clock modulation circuit that can measure the characteristics of a clock with higher precision. [Means for solving the problem]

[0005] The clock modulation circuit of the embodiment includes a clock output circuit, a multiple frequency divider circuit that receives a clock from the clock output circuit and has a plurality of frequency divider circuits that divide the clock, and a frequency divider control circuit that controls the timing of the start of frequency division for each of the plurality of frequency divider circuits and controls the phase difference between at least one pair of output signals of the plurality of frequency divider circuits based on the period of the clock.

[0006] In the clock modulation method of the embodiment, in a clock modulation circuit having a clock output circuit that outputs a frequency division control circuit, first frequency division circuit, and second frequency division circuit that output a clock, a first frequency division start signal output from the previous frequency division control circuit is transmitted to the first frequency division circuit, the first frequency division circuit outputs a first output signal obtained by dividing the clock, a second frequency division start signal output from the frequency division control circuit is transmitted to the second frequency division circuit, and the second frequency division circuit outputs a second output signal obtained by dividing the clock.

Brief Description of the Drawings

[0007] [Figure 1] It is a block diagram showing a clock modulation circuit according to a first embodiment. [Figure 2] It is an example of the circuit configuration of the clock modulation circuit according to the first embodiment. [Figure 3A] It is an example of the circuit configuration of the frequency division control circuit of the clock modulation circuit according to the first embodiment. [Figure 3B] It is an example of the circuit configuration of the frequency division control circuit of the clock modulation circuit according to the first embodiment. [Figure 4] It is a timing chart of the operation of the frequency division control circuit. [Figure 5] It is a timing chart of the operation of the clock modulation circuit according to the first embodiment. [Figure 6] It is a flowchart of the operation of the clock modulation circuit according to the first embodiment. [Figure 7] It is a flowchart of the operation of the clock modulation circuit according to the first modification of the first embodiment. [Figure 8A] It is a conceptual diagram showing an example of the statistical processing of the clock modulation circuit according to the first modification of the first embodiment. [Figure 8B] It is a conceptual diagram showing an example of the statistical processing of the clock modulation circuit according to the first modification of the first embodiment. [Figure 9] It is a timing chart of the operation of the clock modulation circuit according to the first modification of the first embodiment. [Figure 10] It is an example of the circuit configuration of the clock modulation circuit according to the second embodiment. [Figure 11] This is a timing chart of the operation of the clock modulation circuit according to the second embodiment. [Figure 12] This is an example of the circuit configuration of the clock modulation circuit according to the third embodiment. [Figure 13] This is a timing chart of the operation of the clock modulation circuit according to the third embodiment. [Figure 14] This is an example of the circuit configuration of the clock modulation circuit according to the fourth embodiment. [Figure 15] This is an example of the circuit configuration of the select circuit of the clock modulation circuit according to the fourth embodiment. [Figure 16] This is an example of the circuit configuration of a clock modulation circuit according to a modified example of the fourth embodiment. [Figure 17] This is an example of the circuit configuration of the clock modulation circuit according to the fifth embodiment. [Figure 18] This is a timing chart of the operation of the clock modulation circuit according to the fifth embodiment. [Figure 19] This is a timing chart of the operation of the clock modulation circuit according to the fifth embodiment. [Modes for carrying out the invention]

[0008] The embodiments of the present invention will be described below with reference to the drawings.

[0009] Please note that the drawings are schematic or conceptual, and the relationships between the thickness and width of each part, as well as the ratios of the sizes of the parts, are not necessarily identical to those of reality. Furthermore, even when representing the same part, the dimensions and ratios may differ between drawings.

[0010] In the following, the H state refers to a state where the voltage is 5V in a digital signal that transitions between, for example, 0V and 5V. On the other hand, the L state refers to a state where the voltage is 0V.

[0011] In this specification and in each figure, elements similar to those described above are denoted by the same reference numerals, and detailed explanations are omitted as appropriate.

[0012] (First Embodiment) Figure 1 is a block diagram of the clock modulation circuit 100 according to the first embodiment. Figure 2 shows an example of the circuit configuration of the clock modulation circuit 100 according to the first embodiment. Figures 3A and 3B are examples of the circuit configuration of the frequency divider control circuit 20 of the clock modulation circuit 100 according to the first embodiment. Figure 4 is a timing chart showing an example of the operation of the clock modulation circuit 100 according to the first embodiment. Figure 5 is a flowchart showing an example of the operation of the clock modulation circuit 100 according to the first embodiment. Hereinafter, Jitter includes Skew differences caused by differences in the signal transmission path and signal fluctuations caused by the circuit configuration of the clock modulation circuit 100. This embodiment has a configuration that facilitates the measurement of Jitter. Details will be explained in Figure 5.

[0013] As shown in Figure 1, the clock modulation circuit 100 according to this embodiment includes a clock output circuit CG, a multiplexer circuit 10 connected to the clock output circuit CG, and a frequency divider control circuit 20 connected to the clock output circuit CG and controlling the operation of the multiplexer circuit 10. The external circuit (measurement circuit) 40 receives the output signals OUT1, OUT2...OUTn from the multiplexer circuit 10 via the interface 30 and measures them, for example.

[0014] The clock modulation circuit 100 is formed on the same chip, for example, and mounted on an MCU or the like. Interface 30 transmits input and output signals from the clock modulation circuit 100 to the external circuit 40. The clock modulation circuit 100 and the external circuit 40 may have different operating voltages, for example. Interface 30 is, for example, a general-purpose I / O (Input / Output). The external circuit 40 receives signals from interface 30 and measures the waveform of the signals. The external circuit 40 is a circuit capable of measuring the time variation of voltage and includes, for example, an oscilloscope.

[0015] The clock output circuit CG outputs a clock CLK having a frequency of, for example, MHz to GHz. The clock output circuit CG may also include a circuit for generating the clock CLK.

[0016] The multiple frequency divider circuit 10 has two or more frequency dividers (first frequency divider circuit 10-1, second frequency divider circuit 10-2, ... nth frequency divider circuit 10-n, where n is a natural number greater than or equal to 2). The output signal of the clock output circuit CG is input to two or more frequency dividers, and the divided signal is output as output signals OUT1, OUT2, ... OUTn. The first frequency divider circuit 10-1 and the second frequency divider circuit 10-2 are connected, for example, in parallel with respect to the clock output circuit CG.

[0017] Here, frequency division refers to modulation that reduces the frequency of a signal. For example, "2-fold frequency division" means reducing the signal frequency to 1 / 2. Similarly, "n-fold frequency division" means reducing the signal frequency to 1 / n. If the frequency divider circuits included in the multiple frequency divider circuit 10 are circuits that perform n-fold frequency division, it is desirable that the multiple frequency divider circuit 10 has at least n frequency divider circuits.

[0018] The frequency divider control circuit 20 receives the clock CLK output from the clock output circuit CG and controls the start of the frequency division operation of the first frequency divider circuit 10-1, the second frequency divider circuit 10-2, ... the nth frequency divider circuit 10-n. The timing of the start of frequency division for the first frequency divider circuit 10-1, the second frequency divider circuit 10-2, ... the nth frequency divider circuit 10-n may differ by the period (reciprocal of frequency) of the clock CLK output by the clock output circuit CG, or the timing of the start of frequency division may be simultaneous. In the following, "simultaneous" refers to a time difference of less than or equal to one-quarter of the period of the clock CLK output by the clock output circuit CG. When we say "simultaneous," the time difference may be less than or equal to one-eighth of the period of the clock CLK output by the clock output circuit CG, or less than or equal to one-sixteenth. In other words, when we say the length of time is equal, it includes a difference in the length of time of less than or equal to one-quarter of the period of the clock CLK. When the timing of the start of frequency division between the first frequency divider circuit 10-1 and the second frequency divider circuit 10-2 is shifted by the period of the clock CLK, the absolute value of the time difference between the start of frequency division between the first frequency divider circuit 10-1 and the second frequency divider circuit 10-2 is, for example, between 3 / 4 and 5 / 4 of the period of the clock CLK. The frequency divider control circuit 20 controls the phase difference between at least one pair of output signals from the multiple frequency divider circuits based on the period of the clock.

[0019] Next, we will explain the operation of the clock modulation circuit 100.

[0020] First, the clock CLK is output from the clock output circuit CG. The clock CLK is input to the first frequency divider circuit 10-1, the second frequency divider circuit 10-2, ... the nth frequency divider circuit 10-n, but initially the first frequency divider circuit 10-1, the second frequency divider circuit 10-2, ... the nth frequency divider circuit 10-n are not performing frequency division operations. The first frequency divider circuit 10-1, the second frequency divider circuit 10-2, ... the nth frequency divider circuit 10-n may be performing frequency division operations, but as will be explained later with reference to Figure 5, the timing of the frequency division operations is not necessarily controlled.

[0021] Next, the frequency divider control circuit 20 starts operating. Based on the input of the clock CLK (details will be described later), the frequency divider control circuit 20 starts the frequency division operation of the first frequency divider circuit 10-1, the second frequency divider circuit 10-2, ..., the nth frequency divider circuit 10-n. For example, in a mode (Figure 5) in which the first frequency divider circuit 10-1, the second frequency divider circuit 10-2, ..., the nth frequency divider circuit 10-n each start frequency division at different timings equal to the period of the clock CLK, the frequency divider control circuit 20 controls the multiple frequency divider circuits to start dividing in sequence.

[0022] The clock CLK is converted into divided output signals OUT1, OUT2, ..., OUTn by the multiple frequency divider circuit 10. The frequencies of the output signals OUT1, OUT2, ..., OUTn are lower than the frequency of the clock CLK. The output signals OUT1, OUT2, ..., OUTn are input to the external circuit 40 via the interface 30, and the signal waveforms are measured. The characteristics of the clock CLK can be calculated from the measurement results of the external circuit 40.

[0023] Even when the clock CLK is fast (i.e., has a high frequency), the signal whose frequency has been reduced by the multiplexer 10 is input to the interface 30 and the external circuit 40. For example, even if the operating voltage of the interface 30 is greater than the operating voltage of the clock modulation circuit 100, and it is difficult to output a high-frequency signal compared to the clock modulation circuit 100, the frequency of the signal is reduced in the external circuit 40 so that it can be measured.

[0024] Figure 2 shows an example where the multiple frequency divider circuit 10 has two frequency divider circuits that divide the frequency by two. An example of a circuit configuration in which the frequency divider circuit is implemented using flip-flops is described, but it is not limited to this.

[0025] First, let's explain the definitions of each terminal in the reset-equipped D flip-flop shown in Figure 2. Terminal D is the data input terminal. Terminal CK is the clock input terminal. For example, the state (H state or L state) input to data input terminal D at the rising edge timing of the clock input to clock input terminal CK is output from output terminal Q. Inverting output terminal Q * (Hereafter, the bar indicating "inversion" in the drawings will be represented by an asterisk (*) in the specification.) The output from this terminal is inverted from the output of output terminal Q.

[0026] The clear terminal CLR is a terminal to which a signal controlling the start of the flip-flop's operation is input. For example, while a low (L) signal is input to the clear terminal CLR, input from the clock input terminal CK is accepted, and while a high (H) signal is input to the clear terminal CLR, input from the clock input terminal CK is not accepted.

[0027] The inverted output terminal Q of the flip-flop described above. * By connecting this to the data input terminal D, it can be made into a frequency divider circuit that divides the frequency by 2. The output terminal Q of the first frequency divider circuit 10-1 outputs the output signal OUT1. The state of the output signal OUT1 is inverted at the rising edge timing of the clock CLK input to the clock input terminal CK.

[0028] The timing of the start of frequency division in the first frequency divider circuit 10-1 is controlled by the first frequency division start signal Rc1 of the frequency divider control circuit 20. The timing of the start of frequency division in the second frequency divider circuit 10-2 is controlled by the second frequency division start signal Rc2 of the frequency divider control circuit 20.

[0029] Next, an example of the circuit configuration of the frequency divider control circuit 20 will be described with reference to Figure 3A. The frequency divider control circuit 20 includes a start circuit 21, a bit string generation circuit 22, and a frequency division start signal generation circuit 23. The frequency divider control circuit 20 shown in Figure 3A has a start signal EN as an input, which is not shown in Figure 1. The start signal EN is a signal that controls the start of operation of the frequency divider control circuit 20. The start circuit 21 inputs the clock CLK to the bit string generation circuit 22 while the start signal EN is, for example, in a high state. The start signal EN controls the turn-on / turn-off of the frequency divider control circuit 20.

[0030] The bit sequence generation circuit 22 receives a clock input CLK and outputs a first bit signal X1, a second bit signal X2, and a third bit signal X3. The bit sequence generation circuit 22 operates when n is the number of frequency dividers included in the multiple frequency divider circuit 10, and n ≤ 2. m - It is sufficient to have m or more outputs that satisfy 1. That is, the bit string generation circuit 22 has a first bit signal X1, a second bit signal X2, ... the mth bit signal Xm as outputs. Figure 3A shows three D flip-flops 22-1, 22-2, and 22-3, and when the number of frequency dividers included in the multiple frequency divider circuit 10 is n, n ≤ 2 m It has m or more D flip-flops that satisfy -1.

[0031] Note that the clock input terminal CK of the D flip-flop shown in Figure 3A receives an inverted clock signal. This is an example where the falling edge of the clock CLK triggers the frequency division start signals Rc1, Rc2, etc., and is not necessarily limited to this case.

[0032] The frequency division start signal generation circuit 23 receives the inputs of the first bit signal X1, the second bit signal X2, ... and outputs a frequency division start signal (first frequency division start signal Rc1, second frequency division start signal Rc2, ...). The frequency division start signal generation circuit 23 receives the inputs of the first bit signal X1, the second bit signal X2, ... and the m bit signal Xm as 2 m—Converts into a single frequency division start signal. In the example shown in Figure 3A, the frequency division start signal generation circuit 23 includes, for example, a 3-input 8-output decoder (for example, the decoder DC shown in Figure 3B). That is, the frequency division start signal generation circuit 23 takes, for example, a 3-bit signal (X1, X2, and X3) represented in binary as input and has 8 outputs corresponding to its decimal number.

[0033] The operation of the frequency divider control circuit 20 shown in Figure 3A will be further explained with reference to the timing chart in Figure 4. First, the start signal EN transitions to the H state, and the clock CLK is input to the bit sequence generation circuit 22, starting the operation of the frequency divider control circuit 20.

[0034] The D flip-flop 22-1 outputs a first bit signal X1, triggered by the falling edge of the clock CLK. The first bit signal X1 is the clock CLK divided by two.

[0035] The D flip-flop 22-2, to which the first bit signal X1 is input to the clock input terminal CK, outputs the second bit signal X2, triggered by the falling edge of the first bit signal X1. The second bit signal X2 is the clock signal CLK divided by 4.

[0036] The D flip-flop 22-3, to which the second bit signal X2 is input to the clock input terminal CK, outputs the third bit signal X3, triggered by the falling edge of the second bit signal X2. The third bit signal X3 is the clock signal CLK divided by 8.

[0037] The H / L states of the first bit signal X1, the second bit signal X2, and the third bit signal X3 can be considered as binary data, totaling 3 bits of information. Figure 4 shows the bit sequence (X3 X2 X1) obtained by arranging the first bit signal X1, the second bit signal X2, and the third bit signal X3 in ascending order from the ones place in binary. For example, when only the first bit signal X1 is in the H state, it corresponds to 001.

[0038] The bit sequence (X3 X2 X1) starts at 000 and switches every half cycle of the clock CLK as follows: 001, 010, 011, 100, 101, 110, 111, 000, 001, ... That is, from 0 to 2 in binary. 3 The system transitions through eight different states, up to state 1, in sequence.

[0039] As shown in Figures 3A and 4, when the signal includes three bit signals, the first bit signal X1, the second bit signal X2, and the third bit signal X3, it is possible to select from seven different triggers (other than the initial state of 000) as the frequency division start signal.

[0040] In the example shown in Figure 4, the first frequency division start signal Rc1 transitions to the L state when the bit sequence (X3 X2 X1) becomes 001. For all other bit sequences, it maintains its state. The second frequency division start signal Rc2 transitions to the L state when the bit sequence (X3 X2 X1) becomes 010. For all other bit sequences, it maintains its state.

[0041] Similarly, the timing of the transition to the L state for each frequency division start signal can be controlled by sequentially transitioning the third frequency division start signal Rc3 to the L state using 011 as a trigger, and the fourth frequency division start signal Rc4 to the L state using 100 as a trigger.

[0042] An example of a configuration in which the first frequency division start signal Rc1 retains its state for bit sequences other than (X3 X2 X1)001 will be described with reference to Figure 3B.

[0043] The frequency division start signal generation circuit 23 has a holding circuit 23h (for example, a D latch circuit) in addition to the decoder DC. The D latch circuit has a data input terminal Dh, a control input terminal Ch, an output terminal OUTh, and an inverting output terminal OUTh. *It has. While a signal in the H state is input to the control input terminal Ch, the signal input to the data input terminal Dh is output from the output terminal OUTh. The output is held while a signal in the L state is input to the control input terminal Ch. For example, the output of a decoder DC is input to the data input terminal Dh of the D latch circuit. A first frequency division start signal Rc1 is output from the output terminal OUTh of the D latch circuit. On the other hand, the inverted output signal OUTh of the D latch circuit * Based on this, the input signal to the control input terminal Ch is determined.

[0044] When the bit string (X3 X2 X1) becomes, for example, 001, the output from the decoder DC to the data input terminal Dh changes, and the output signal of the D latch circuit becomes the L state (that is, the first frequency division start signal Rc1 becomes the L state). At this time, the inverted output signal of the D latch circuit becomes the H state. The inverted output signal OUTh of the D latch circuit * is fed back to the control input terminal Ch. For example, the NAND output of the start signal EN and the inverted output signal OUTh * is input to the control input terminal Ch. That is, while the start signal EN is in the H state (the frequency division control circuit 20 is operating), after the first frequency division start signal Rc1 transitions to the L state, a signal in the L state is input to the control input terminal Ch, and the state of the first frequency division start signal Rc1 is held. While the start signal EN is in the L state (the frequency division control circuit 20 is not operating), the state of the first frequency division start signal Rc is not held.

[0045] The configuration in which the inverted output signal OUTh * is fed back to the control input terminal Ch may be a configuration having, for example, a select circuit or the like in addition to the NAND circuit. Also, in the above example, the case where the frequency division start signal generation circuit 23 has a D latch circuit has been described, but it may be replaced with other circuits as long as they have a configuration for holding states.

[0046] While referring to the timing chart of FIG. 5 and the flowchart of FIG. 6, the operation of the clock modulation circuit 100 will be further described.

[0047] The timing chart in Figure 5 shows the time evolution of the clock CLK shown in Figure 2, the first frequency division start signal Rc1, the second frequency division start signal Rc2, and the output signals OUT1 and OUT2.

[0048] First, the frequency divider control circuit 20 generates a frequency divider start signal using, for example, the configuration shown in Figure 3. As shown in Figure 4, the falling edge timing of the first frequency divider start signal Rc1 and the second frequency divider start signal Rc2 is shifted by the period of the clock CLK.

[0049] Next, referring again to Figure 2, when the first frequency division start signal Rc1 input to the clear terminal CLR is in the L state, the rising edge signal of the clock CLK is input to the clock input terminal CK, causing the output signal OUT1 to invert. At time t1 shown in Figure 5, the output signal OUT1 transitions from the L state to the H state. At time t2, when the next rising edge of the clock CLK is input, the output signal OUT1 transitions back to the L state.

[0050] The second frequency division start signal Rc2 has a falling edge timing that is delayed by the period of the clock CLK compared to the first frequency division start signal Rc1. Therefore, the transition of output signal OUT2 to the H state is delayed by the period of the clock CLK compared to the transition of output signal OUT1 to the H state. At time t2, output signal OUT2 transitions to the H state. At time t3, when the next rising edge of the clock CLK is input, output signal OUT2 transitions to the L state again.

[0051] In other words, output signals OUT1 and OUT2 are signals obtained by dividing the clock CLK by two, but their rising and falling edges are out of phase by the period of the clock CLK. To put it another way, output signals OUT1 and OUT2 are out of phase by the period of the clock CLK.

[0052] Furthermore, the example shown in Figure 4 is one in which output signals OUT1 and OUT2 are inverted at the rising edge of the clock CLK. In this case, it is desirable to trigger the frequency division start signal on the falling edge of the clock CLK. There is a margin of half a clock cycle between the transition of the frequency division start signal to the L state and the arrival of the next rising edge of the clock CLK, allowing for more reliable control of the rising edge timing of output signals OUT1 and OUT2.

[0053] Next, the flowchart shown in Figure 6 illustrates an example of a flow for measuring the characteristics of the clock CLK using the clock modulation circuit 100 according to this embodiment. The flow shown in Figure 5 is an example of measuring the jitter of the clock CLK. This will be explained with reference to Figure 2 as appropriate.

[0054] First, in step 110, the frequency divider control circuit 20 is turned on and begins operation. Here, "turning on" includes not only the case where the frequency divider control circuit 20 is switched from the off state to the on state, but also the case where the frequency divider control circuit 20 is switched from the on state to the off state and then to the on state. For example, the frequency divider control circuit 20 is turned on in conjunction with the timing when the measurement of the clock CLK begins.

[0055] In the following step 120, the frequency division control circuit 20 transitions the first frequency division start signal Rc1 to the L state.

[0056] In step 130, when the first frequency division start signal Rc1 is in the low state, the first frequency division circuit 10-1 performs the frequency division operation and outputs the output signal OUT1.

[0057] On the other hand, in step 140, the frequency divider control circuit 20 transitions the second frequency divider start signal Rc2 to the L state. The order of steps 130 and 140 is not limited to the order shown in Figure 5.

[0058] Next, in step 150, when the second frequency division start signal Rc2 is in the low state, the second frequency division circuit 10-2 performs the frequency division operation and outputs the output signal OUT2. The output signal OUT2 is phase-lag of the output signal OUT1 by the period of the clock CLK.

[0059] The output signals OUT1 and OUT2 are transmitted to the external circuit 40 via the interface 30. In step 160, the external circuit 40 measures the characteristics of the output signals OUT1 and OUT2 (signals whose frequency has been reduced by frequency division).

[0060] Referring to Figure 5, first, the first rising edge time t1 of output signal OUT1 is measured. Then, the first rising edge time t2 of output signal OUT2 is measured. Subsequently, the second rising edge time t1' of output signal OUT1 is measured, the second rising edge time t2' of output signal OUT2 is measured, and so on. By repeating this process, the rising edge times t1, t2, t1', t2', etc., of the clock CLK can be obtained.

[0061] For example, using time t1 as the reference (time zero), time t2 is determined and then calculated backward from the known frequency (or period) of the clock CLK to evaluate how much time t2 deviates compared to the ideal case where jitter is zero. Alternatively, for example, using time t1' as the reference (time zero), t2' is determined and then calculated backward from the known frequency (or period) of the clock CLK to evaluate how much time t2' deviates compared to the ideal case where jitter is zero. For example, jitter, one of the characteristics of the clock CLK, is evaluated as described above (step 170). Specifically, t2-t1 is calculated, and the known period of the clock CLK is subtracted to use as one of the data for evaluating jitter.

[0062] Note that the flow in Figure 6 is essentially the same even when the natural number n shown in Figure 2 is 3 or greater.

[0063] Even when n is 3 or more, the frequency division control circuit 20 sequentially transitions the n-th frequency division start signal Rcn to the L state. When the n-th frequency division start signal Rcn is in the L state, the n-th frequency division circuit 10-n performs a frequency division operation and outputs an output signal OUTn. Let i and j be natural numbers. The output signal OUTi and the output signal OUTj are, for example, out of phase by |i - j| times the period of the clock CLK.

[0064] Even when n is 3 or more, the first rising time t1 of the output signal OUT1 is measured, the first rising time t2 of the output signal OUT2 is measured, the first rising time t3 of the output signal OUT3 is measured, ··· the first rising time tn of the output signal OUTn is measured, the second rising time t(n + 1) of the output signal OUT1 is measured, ··· and the measurements are made. In this way, each rising time t1, t2, t3 ··· of the clock CLK can be obtained (see, for example, FIG. 13). By reproducing the waveform of the clock CLK from the rising times of the plurality of output signals OUT1 to OUTn and comparing it with an ideal clock period, the characteristics of the clock CLK can be evaluated. For example, based on the rising time of one output signal, the rising time of another output signal can be measured relatively and compared with an ideal clock period. Specifically, when there are n output signals (including 3 or more), for a natural number m where 1 ≤ m < n, the output signal OUT(m + 1) is evaluated with reference to the output signal OUTm (t(m + 1) - tm is measured).

[0065] These measurements can be repeated a plurality of times. Alternatively, not only t2 - t1 between the output signals OUT1 and OUT2, but also t2' - t1' shown in FIG. 5 can be used as one of the data for evaluating Jitter. In this way, for n output signals, a statistical distribution of n - 1 cases (t2 - t(1), t3 - t(2), ··· tn - t(n - 1)) evaluated relatively is obtained.

[0066] Let Δj1, Δj2, ....Δj(n-1) be the standard deviations of the distributions of n-1 statistics (t2-t1, t3-t2, .....tn-t(n-1)). The jitter of the entire multiple frequency divider circuit 10 is evaluated from the magnitude of the variability of the distributions of the n-1 statistics (t2-t1, t3-t2, .....tn-t(n-1)). For example, Δj = [(Δj1) 2 +(Δj2) 2 +(Δj3) 2 +···(Δj(n-1)) 2 ] 1 / 2 The variances of n-1 statistics are added together to obtain the variance Δj for the entire multiple frequency divider circuit 10. 2 The standard deviation Δj is also evaluated. The magnitude of the variation in the clock characteristics of the entire multiple frequency divider circuit 10 is not limited to the above formula, but can be evaluated based on the variation in the statistical quantities obtained from the output signals of each frequency divider circuit.

[0067] The statistics obtained from the output signals of each frequency divider circuit can be obtained by, for example, relatively evaluating one output signal relative to the other. For example, the rise time of each output signal can be evaluated relative to the rise time t1 of output signal OUT1. For example, for output signal OUTn, tn-t1 can be calculated and compared with the value for a clock with an ideal period ((n-1) times the original clock period) to use as one of the data for evaluating jitter.

[0068] The characteristics of the clock CLK are measured using statistical processing. That is, instead of comparing jitter, etc., for a single pulse, the rise times t1, t2, t3, etc., of the clock CLK are obtained, and the distribution of jitter, etc., for a large number of pulses is obtained. The distribution spread (e.g., standard deviation) is then used for evaluation. A smaller distribution spread of the clock CLK characteristics indicates a more stable clock quality, which is desirable.

[0069] According to the clock modulation circuit 100 of this embodiment, the frequency division control circuit 20 controls the timing of the start of frequency division in the multiple frequency divider circuit 10, thereby dividing the clock CLK to a frequency that can be output at the interface 30, and enabling high-precision measurement of the characteristics of the clock CLK.

[0070] Even when the frequency of the clock CLK is too high to be output by the interface 30, according to this embodiment, the clock CLK can be modulated into a measurable signal by the external circuit 40 by dividing the frequency and lowering the frequency. According to this embodiment, high-speed off-chip measurement of the clock CLK becomes possible.

[0071] Furthermore, in the example shown in Figure 5, which has two frequency divider circuits with a 2-division frequency, the divided signal is generated using the two output signals OUT1 and OUT2 without losing information about the signal characteristics of the clock CLK. In other words, instead of the frequency being halved, the amount of information is preserved by splitting it into two output signals. Note that if the multiple frequency divider circuit 10 has an n-division frequency divider circuit, instead of the frequency being 1 / n, the amount of information can be preserved by splitting it into n output signals.

[0072] The multiple frequency divider circuit 10 has at least two frequency dividers. Even when the multiple frequency divider circuit 10 has an n-division frequency divider, having two or more frequency dividers allows the clock characteristics to be estimated by measuring the time difference between multiple output signals. Furthermore, having two or more frequency dividers in the multiple frequency divider circuit 10 suppresses the decrease in information due to frequency reduction caused by division, and increases the amount of information obtained about the characteristics of the clock CLK. For example, it suppresses the decrease in the amount of information obtained from the divided signal per unit time or per a certain number of clock CLK pulses. However, when there is an n-division frequency divider, it is desirable for the multiple frequency divider circuit 10 to have n or more frequency dividers in order to measure the characteristics of the clock CLK comprehensively.

[0073] Increasing the amount of information obtained about the characteristics of the clock CLK improves the accuracy of statistical analysis and thus the accuracy of estimating the characteristics of the clock CLK when statistically evaluating its characteristics by increasing the number of measured samples. Alternatively, it reduces the time required to obtain a sufficient number of samples, allowing for more efficient and accurate measurements.

[0074] Furthermore, according to this embodiment, since the multiple frequency divider circuit 10 has a certain number or more frequency divider circuits, it is possible to estimate the rising edge time of the clock CLK without omission. Therefore, for example, even when performing n frequency division, n measurements (samples) are obtained for n pulses of the clock CLK. On the other hand, in the comparative example, when there is one frequency divider circuit for n frequency division, one measurement (sample) is obtained for n pulses of the clock CLK. This embodiment provides a larger number of measurement samples for the same number of clock pulses. Also, in the comparative example, it is necessary to repeat the measurement for n times in order to obtain the same number of samples.

[0075] Specifically, in Figure 5, the rising edges of output signals OUT1 and OUT2 correspond to the rising edges of the clock CLK, skipping one. For example, with only output signal OUT1, the number of rising edges of the pulse being measured in the external circuit 40 is half the number of rising edges of the clock CLK. On the other hand, the combined number of rising edges of pulses from output signals OUT1 and OUT2 is equivalent to the number of rising edges of the clock CLK, allowing for the accurate estimation of the rising edges of the clock CLK.

[0076] Furthermore, according to the clock modulation circuit 100 of this embodiment, the frequency divider control circuit 20 can reliably control the timing of the operation of multiple frequency divider circuits by shifting the timing of the transition of the frequency divider start signals (Rc1 and Rc2) to the L state by the period of the clock CLK. Moreover, the frequency divider start signals (Rc1 and Rc2) are triggered by the falling edge of the clock CLK, and the frequency divider circuit of the multiple frequency divider circuit 10 is triggered by the rising edge of the clock CLK. As shown in Figure 5, for example, a margin is created between the rising / falling times of the first frequency divider start signal Rc1 and the output signal OUT1, enabling stable control of the frequency divider operation. The falling edge of the frequency divider start signals (Rc1 and Rc2) and the trigger of the frequency divider circuit of the multiple frequency divider circuit 10 (the rising edge of the clock) are shifted by half a period of the clock CLK. For example, even if there is a timing difference smaller than half a period of the clock CLK between the frequency divider control circuit 20 and the clock CLK input to the multiple frequency divider circuit 10, the rising edge of the output signal can be controlled at the desired timing.

[0077] The frequency division start signals (Rc1 and Rc2) may be triggered by the rising edge of the clock CLK, while the frequency division circuit of the multiple frequency divider circuit 10 may be triggered by the falling edge of the clock CLK.

[0078] (First embodiment, first modified example) Figures 7, 8A, 8B, and 9 further illustrate a desirable measurement flow for more accurately measuring the characteristics of the clock CLK, as a first modification of the first embodiment.

[0079] Figure 7 shows a flow that, in addition to the flow shown in Figure 6, allows for more accurate measurement of the characteristics of the clock CLK.

[0080] First, in step 210, the frequency divider control circuit 20 is turned on. Here, "turning on" includes not only the case where the frequency divider control circuit 20 is transitioned from the off state to the on state, but also the case where the frequency divider control circuit 20 is transitioned from the on state to the off state once, and then transitioned to the on state.

[0081] Next, in step 220, the frequency divider control circuit 20 simultaneously transitions the first frequency divider start signal Rc1 and the second frequency divider start signal Rc2 to the L state (with a time difference shorter than one-quarter of the clock CLK period). Here, the operation of the frequency divider control circuit 20 is different from that of steps 120 and 140 shown in Figure 5. This can be achieved, for example, by adding a switch in the frequency divider start signal generation circuit 23 shown in Figure 3 that outputs the first frequency divider start signal Rc1 as the second frequency divider start signal Rc2. By switching the switch, it is possible to select whether the second frequency divider start signal Rc2 outputs the same signal as the first frequency divider start signal Rc1, or whether it outputs a signal triggered by a different bit sequence, as shown in Figure 4.

[0082] Next, in step 230, output signals OUT1 and OUT2 are output from the first frequency divider circuit 10-1 and the second frequency divider circuit 10-2. Ideally, the phase difference between output signals OUT1 and OUT2 is zero, but a phase difference between output signals OUT1 and OUT2 may occur due to the skew difference caused by the difference in the distance over which the clock CLK input to the first frequency divider circuit 10-1 and the second frequency divider circuit 10-2 is transmitted, and due to fluctuations in signal characteristics caused by the internal configuration of the first frequency divider circuit 10-1 and the second frequency divider circuit 10-2.

[0083] The output signals OUT1 and OUT2 are transmitted to the external circuit 40 via the interface 30. In step 240, the external circuit 40 measures the difference Δt between the rising edges of the divided and reduced-frequency output signals OUT1 and OUT2. Figure 7, which will be explained later, shows the time difference Δt for the first pulse, but the time difference Δt can be measured for each pulse.

[0084] In step 250, the phase difference between output signals OUT1 and OUT2 is measured. The skew difference caused by the difference in the distance over which the clock CLK input to the first frequency divider circuit 10-1 and the second frequency divider circuit 10-2 is transmitted, and the fluctuations in signal characteristics caused by the internal configuration of the first frequency divider circuit 10-1 and the second frequency divider circuit 10-2 are estimated. First, if a skew difference occurs, it can be detected as a phase difference offset, such as the output signal OUT2 being steadily outpaced by the output signal OUT1 due to the difference in the length of the signal paths.

[0085] On the other hand, the phase difference due to fluctuations in signal characteristics originating from the internal configuration of the first frequency divider 10-1 and the second frequency divider 10-2 is the portion that remains as a statistical distribution spread after removing the phase difference offset due to the skew difference. In step 250, the spread of the distribution of phase difference due to fluctuations in signal characteristics originating from the internal configuration of the first frequency divider 10-1 and the second frequency divider 10-2 is estimated.

[0086] Finally, in step 260, corrections are made to the time t1, t2, ... measured by the flow shown in steps 110-170 in Figure 5, based on the skew difference measured in step 250 and the fluctuations in signal characteristics originating from the internal configuration of the first frequency divider circuit 10-1 and the second frequency divider circuit 10-2. For example, if the skew difference is obtained in step 250, the effect of differences in signal transmission paths can be reduced when comparing the output signal OUT2 shown in Figure 5 with the output signal OUT1 by subtracting the delay of the skew difference from the measurement results at time t2 and t4.

[0087] Here, an example of a correction method based on the measurement results of the time difference Δt will be explained with reference to Figures 8A and 8B.

[0088] Figure 8A shows an example of the measurement results for the time difference Δt. Figure 8B shows an example of the measurement results for jitter.

[0089] As shown in Figure 8A, when the time difference Δt is measured, a distribution is obtained that has a width of fluctuation Δf of the signal characteristics inside the multiple frequency divider circuit 10, for example, centered on the skew difference Δs. The fluctuation Δf is, for example, the FWHM (Full Width at Half Maximum) of the distribution.

[0090] The Jitter characteristics shown in Figure 8B are estimated using the results of the estimation of the skew difference Δs and fluctuation Δf. First, the skew difference Δs is used to correct for the times t1, t2, t1', t2', etc., shown in Figure 4. For example, if the output signal OUT2 is delayed by the skew difference Δs compared with the output signal OUT1, the skew difference Δs is subtracted from the times t2, t2', etc., obtained from the output signal OUT2, and then a comparison is made with the output signal OUT1.

[0091] The result of correcting for the skew difference Δs is the jitter distribution shown by the dotted line in Figure 8B. The jitter distribution has a width centered around zero, for example. The width Δj of the jitter distribution shown by the dotted line is the FWHM.

[0092] Next, a correction is made based on the estimated fluctuation Δf. The width Δj includes both the jitter distribution of the clock CLK (FWHM is Δc) and the effect of the fluctuation Δf. Therefore, (Δj) 2 =(Δc) 2 +(Δf) 2 And Δc=[(Δj) 2 ―(Δf) 2 ] 1 / 2 Thus, the width Δc of the jitter distribution of the clock CLK can be estimated.

[0093] In this modified version, the width Δc of the jitter distribution of the clock CLK is estimated based on the skew difference Δs and fluctuation Δf.

[0094] Here, we will explain how to estimate the characteristics of the clock CLK when there are three or more output signals (when n is 3 or more). We will explain using four examples of output signals OUT1, OUT2, OUT3, and OUT4. Measuring the difference Δt between the rise times of output signals OUT1 and OUT2 is done as shown in Figure 9 below. In addition, we measure the difference between the rise times of output signals OUT2 and OUT3, and the difference between the rise times of output signals OUT3 and OUT4.

[0095] In this way, the skew difference Δs and fluctuation Δf are obtained between output signals OUT1 and OUT2, between output signals OUT2 and OUT3, and between output signals OUT3 and OUT4. Since the skew difference depends on the path difference, a correction is performed for each path to obtain the statistical distribution of jitter. In this way, fluctuations (Δf1, Δf2, Δf3) are obtained for the three paths between output signals OUT1 and OUT2, between output signals OUT2 and OUT3, and between output signals OUT3 and OUT4. From these fluctuations, the fluctuations of the signal characteristics originating from the internal configuration of the multiple frequency divider circuit 10 as a whole are estimated. For example, fluctuation Δf = [(Δf1) 2 +(Δf2) 2 +(Δf3) 2 ] 1 / 2 This is evaluated as fluctuations in the signal characteristics of the entire multiple frequency divider circuit 10, originating from its internal configuration.

[0096] Furthermore, by relatively measuring the rise time of each output signal, Δj1 is obtained by evaluating output signal OUT2 with respect to output signal OUT1, for example. Also, Δj2 is obtained by evaluating output signal OUT3 with respect to output signal OUT2, for example, and Δj3 is obtained by evaluating output signal OUT4 with respect to output signal OUT3, for example. Then, Δj = [(Δj1) 2 +(Δj2) 2 +(Δj3) 2 ] 1 / 2 This allows us to evaluate Δj, which is an indicator of the variation in the clock characteristics of the entire multiple frequency divider circuit 10.

[0097] The width Δc of the jitter distribution of the clock CLK itself is, for example, Δc = [(Δj)]2 ―(Δf) 2 ] 1 / 2 This is used to estimate Δc. In this way, the influence of the multiple frequency divider circuit 10 on clock characteristics such as jitter is reduced, and Δc can be evaluated as a characteristic of the clock CLK itself.

[0098] Figure 9 shows a timing chart of the operations corresponding to the flow described in Figure 7.

[0099] First, the first frequency division start signal Rc1 and the second frequency division start signal Rc2 simultaneously transition to the L state, triggered, for example, by the falling edge of the clock CLK. The first frequency divider circuit 10-1 and the second frequency divider circuit 10-2 then start operating simultaneously.

[0100] Since the first frequency division start signal Rc1 and the second frequency division start signal Rc2 are in the low state, output signals OUT1 and OUT2 simultaneously begin outputting the divided signals, triggered by the rising edge of the clock CLK.

[0101] Ideally, since the triggers are the rising edges of the clock CLK at the same timing, there should be no phase difference between the output signals OUT1 and OUT2. However, due to the difference in the clock signal paths between the clock output circuit CG and the first frequency divider circuit 10-1 and the second frequency divider circuit 10-2, the timing at which the clock CLK arrives in the first frequency divider circuit 10-1 and the second frequency divider circuit 10-2 is actually different. If the signal path between the clock output circuit CG and the second frequency divider circuit 10-2 is longer, the phase of the output signal OUT2 will lag behind that of the output signal OUT1. Thus, a time difference of Δt can occur between the rising edges of the output signals OUT1 and OUT2.

[0102] Furthermore, Δt may also include the phase difference caused by fluctuations in signal characteristics resulting from the internal configuration of the first frequency divider circuit 10-1 and the second frequency divider circuit 10-2.

[0103] According to the clock modulation method described in this modified version, the measurement accuracy of the clock CLK characteristics can be further improved by measuring the rise time difference Δt of the output signals OUT1 and OUT2 and estimating the skew difference, etc.

[0104] In the clock modulation method according to the first embodiment (Figure 6), the output signals OUT1 and OUT2 may include fluctuations in the signal characteristics of the clock CLK itself, as well as fluctuations in the signal characteristics arising from differences in the signal transmission path and the internal configurations of the first frequency divider circuit 10-1 and the second frequency divider circuit 10-2. In the first embodiment, the characteristics of the clock CLK can be estimated when the fluctuations in the signal characteristics arising from differences in the signal transmission path and the internal configurations of the first frequency divider circuit 10-1 and the second frequency divider circuit 10-2 are sufficiently small.

[0105] On the other hand, according to the clock modulation method of this modified example, even if, for example, the signal transmission path difference is large and the skew difference is large, the skew difference is estimated in advance using the flow shown in Figure 7. When measuring jitter etc. using the flow shown in Figure 6, the effect of the skew difference can be canceled out, and the characteristics of the clock CLK itself can be estimated with higher accuracy.

[0106] Furthermore, the more complex the internal circuit configuration of the multiple frequency divider 10 becomes (the more circuit elements it has), the greater the fluctuation in signal characteristics due to the internal configuration of the multiple frequency divider 10 may become. According to the clock modulation method of this modified example, as shown in Figure 8A, the fluctuation in signal characteristics due to the internal configuration of the multiple frequency divider 10 can be estimated as a fluctuation Δf. By correcting the distribution of the measured jitter results with the fluctuation Δf, the original jitter distribution of the clock CLK can be estimated. Therefore, the signal characteristics of the clock CLK can be measured with higher accuracy.

[0107] (Second Embodiment) Figure 10 shows an example of the circuit configuration of the clock modulation circuit 200 according to the second embodiment. Some parts that are common with the clock modulation circuit 100 according to the first embodiment will be omitted from the explanation.

[0108] This embodiment differs from the first embodiment in the circuit configuration of the multiple frequency divider circuit 10. The multiple frequency divider circuit 10 has at least two frequency dividers. The first frequency divider circuit 10-1 is a frequency divider circuit with a division of n (a natural number n ≥ 2). The second frequency divider circuit 10-2 is a reset-enabled D flip-flop. Although Figure 10 describes an example where the multiple frequency divider circuit 10 has two frequency dividers, it may have three or more frequency dividers (the third frequency divider circuit and subsequent circuits are reset-enabled D flip-flops).

[0109] The output signal OUT1 from the first frequency divider 10-1 is input to the data input terminal D of the D flip-flop, which is the second frequency divider 10-2.

[0110] The timing of the transitions of the frequency division start signals Rc1 and Rc2 to the L state is shown, for example, in Figure 11. The output signal OUT2 is the same as the output signal OUT1, obtained by dividing the clock CLK by n, but the rising edge timing is delayed by the period of the clock CLK compared to the output signal OUT1 due to the control of the frequency division start signals Rc1 and Rc2.

[0111] The operation of the clock modulation circuit 200 according to this embodiment will be described with reference to Figure 11. For simplicity, an example in which the first frequency divider circuit 10-1 is a circuit that divides the frequency by 4 will be described, but the invention is not limited to this.

[0112] First, the frequency division control circuit 20 controls the timing of the transition of the first frequency division start signal Rc1 and the second frequency division start signal Rc2 to the L state, similar to the first embodiment. For example, the falling edge of the clock CLK triggers the transition of the first frequency division start signal Rc1 and the second frequency division start signal Rc2 to the L state.

[0113] The first frequency division start signal Rc1 is in the low state, and the output signal OUT1 transitions to the high state at the timing when the clock CLK rises (time ta). In the example where the first frequency divider circuit 10-1 divides by 4, the frequency of the output signal OUT1 becomes one-quarter of the frequency of the clock CLK.

[0114] Next, the second frequency division start signal Rc2 transitions to the L state with a delay equal to the period of the clock CLK from the first frequency division start signal Rc1. When the second frequency division start signal Rc2 is in the L state and the clock CLK rises, the output signal OUT2 transitions to the H state, reflecting the state of the output signal OUT1 input to the data input terminal D (time tb).

[0115] Next, the output signal OUT1 remains in the high state for a duration twice the period of the clock CLK before transitioning to the low state (time tc). However, at the rising edge of the clock CLK at time tc, the output signal OUT2 does not transition to the low state. This is because, although not shown in Figure 11, the rising edge of the clock CLK input to the second frequency divider circuit 10-2 and the falling edge of the output signal OUT1 are not strictly at the same time; the rising edge of the clock CLK input to the second frequency divider circuit 10-2 occurs first. The falling edge of the output signal OUT1 is also originally triggered by the rising edge of the clock CLK, but because the output signal OUT1 is a signal generated through the first frequency divider circuit 10-1, its signal transmission path is longer than that of the clock CLK directly input to the second frequency divider circuit 10-2, and therefore transmission takes longer.

[0116] In other words, although the rising edge of the clock CLK and the falling edge of the output signal OUT1 appear to have no time difference in Figure 11, the output signal OUT1 is in a high state at the time of the rising edge of the clock CLK input to the second frequency divider circuit 10-2, so the output signal OUT2 also remains in a high state at time tc.

[0117] Finally, the output signal OUT2 remains in the high state for a duration twice the period of the clock CLK, after which the output signal OUT2 transitions to the low state (time td).

[0118] According to the clock modulation circuit 200 of this embodiment, by simplifying the internal circuit configuration of the multiple frequency divider circuit 10, fluctuations in signal characteristics originating from the internal circuit configuration of the multiple frequency divider circuit 10 can be reduced, and the accuracy of estimating the characteristics of the clock CLK can be further improved.

[0119] For comparison, if the multiple frequency divider circuit 10 has two n-frequency divider circuits, the second frequency divider circuit 10-2 may also contain multiple flip-flops in order to perform an n-frequency divider operation itself. The larger the number of circuit elements such as flip-flops included in the multiple frequency divider circuit 10, the greater the risk of fluctuations in the signal characteristics.

[0120] On the other hand, according to the clock modulation circuit 200 of this embodiment, the output signal OUT2 is a signal obtained by dividing the clock CLK by n, and the second frequency divider circuit 10-2 only needs to include one D flip-flop, thus reducing the number of circuit elements included in the multiple frequency divider circuit 10. The first frequency divider circuit 10-1 is a frequency divider circuit that divides by n, and the larger n is, the greater the effect of reducing the number of circuit elements by this embodiment.

[0121] Furthermore, even if n≧3 is the case for the first frequency divider circuit 10-1 which divides the frequency by n, the multiple frequency divider circuit 10 has at least two frequency divider circuits, making it possible to estimate the characteristics of the clock CLK, such as jitter, from the measurement results of the divided output signals OUT1 and OUT2.

[0122] (Third embodiment) Figure 12 shows an example of the circuit configuration of the clock modulation circuit 300 according to the third embodiment. Figure 13 is a timing chart showing an example of the operation of the clock modulation circuit 300 shown in Figure 12. Some parts that are common with the clock modulation circuit 100 according to the first embodiment will be omitted from the explanation.

[0123] The clock modulation circuit 300 according to this embodiment differs from the first embodiment in the circuit configuration of the multiple frequency divider circuit 10. The first frequency divider circuit 10-1 is a frequency divider circuit that divides the frequency by 4. Unlike the first embodiment, the example of dividing the frequency by 4 is described, but it is not limited to this. Also, although the example of the multiple frequency divider circuit 10 having four frequency dividers is described, it is sufficient to have two or more frequency dividers.

[0124] The output signal OUT1 of the first frequency divider circuit 10-1 is input to the data input terminal D of the flip-flop which is the second frequency divider circuit 10-2. The output signal OUT2 of the flip-flop which is the second frequency divider circuit 10-2 is input to the data input terminal D of the flip-flop which is the third frequency divider circuit 10-3. The output signal OUT3 of the flip-flop which is the third frequency divider circuit 10-3 is input to the data input terminal D of the flip-flop which is the fourth frequency divider circuit 10-4.

[0125] The frequency divide control circuit 20 inputs the first frequency divide start signal Rc1, the second frequency divide start signal Rc2, the third frequency divide start signal Rc3, and the fourth frequency divide start signal Rc4 to the first frequency divide circuit 10-1, the second frequency divide start circuit 10-2, the third frequency divide start circuit 10-3, and the fourth frequency divide start signal Rc4, respectively. The switching timing of the first frequency divide start signal Rc1, the second frequency divide start signal Rc2, the third frequency divide start signal Rc3, and the fourth frequency divide start signal Rc4 is controlled based on the clock CLK. For example, the first frequency divide start signal Rc1, the second frequency divide start signal Rc2, the third frequency divide start signal Rc3, and the fourth frequency divide start signal Rc4 are controlled based on the bit sequence (X3 X2 X1) shown in Figure 4, which is 001, 010, 011, and 100, respectively.

[0126] The operation of the clock modulation circuit 300 will be explained with reference to Figure 13.

[0127] The first frequency division start signal Rc1, the second frequency division start signal Rc2, the third frequency division start signal Rc3, and the fourth frequency division start signal Rc4 are shifted from the H state to the L state by the period of the clock CLK by the frequency division control circuit 20. The second frequency division start signal Rc2 transitions to the L state after the first frequency division start signal Rc1 by the period of the clock CLK. The third frequency division start signal Rc3 transitions to the L state after the second frequency division start signal Rc2 by the period of the clock CLK. The fourth frequency division start signal Rc4 transitions to the L state after the third frequency division start signal Rc3 by the period of the clock CLK.

[0128] When the first frequency division start signal Rc1 is in the low state, the first frequency division circuit 10-1 performs frequency division, and the output signal OUT1, which is the divided clock CLK, is output. The rising edge of the clock CLK triggers the rising edge of the output signal OUT1. The period of the output signal OUT1 is four times the period of the clock CLK.

[0129] The rising edge of output signal OUT2 is delayed by the period of clock CLK compared to the rising edge of output signal OUT1. The rising edge of output signal OUT3 is delayed by twice the period of clock CLK compared to the rising edge of output signal OUT1. The rising edge of output signal OUT4 is delayed by three times the period of clock CLK compared to the rising edge of output signal OUT1.

[0130] Refer to Figure 12 for a detailed explanation of the rise time.

[0131] The output signal OUT1 is input to the data input terminal D of the flip-flop in the second frequency divider circuit 10-2. The signal waveform of the output signal OUT2, which is in the L state, transitions to the H state when the second frequency divider start signal Rc2 is in the L state, the data input terminal D is receiving an H input, and the rising edge of the clock CLK is input to the clock input terminal CK. The second frequency divider start signal Rc2 transitions to the L state at a time between the rising edge of the output signal OUT1 and the rising edge of the pulse following the pulse that triggers the rising edge of the output signal OUT1. The output signal OUT2 of the second frequency divider circuit 10-2 rises at the rising edge of the pulse following the pulse that triggers the rising edge of the output signal OUT1. Thus, the rising edge timing of the output signal OUT2 is delayed by the period of the clock CLK compared to that of the output signal OUT1.

[0132] Similarly, the rising edge of the output signal OUT3 of the flip-flop, which is the third frequency divider circuit 10-3 to which the output signal OUT2 is input to the data input terminal D, is delayed by the period of the clock CLK compared to the rising edge of the output signal OUT2. The rising edge of the output signal OUT4 of the flip-flop, which is the fourth frequency divider circuit 10-4 to which the output signal OUT3 is input to the data input terminal D, is delayed by the period of the clock CLK compared to the rising edge of the output signal OUT3.

[0133] Referring again to Figure 13, by combining the output signals OUT1, OUT2, OUT3, and OUT4 after dividing the frequency by four, it is possible to accurately estimate the rising edge timing of the clock CLK from the rising edges of the output signals. In other words, by providing four output signals instead of reducing the frequency to one-quarter, the reduction in information can be suppressed.

[0134] In the clock modulation circuit 100 according to the first embodiment, for example, if the multiple frequency divider circuit 10 has a frequency divider that divides the frequency by 4, four such frequency dividers are provided. A frequency divider that divides the frequency by 4 can be realized by connecting two flip-flops, for example, but in the first embodiment, for example, 2 × 4 = 8 flip-flops may be used. It is known that the more elements included in the multiple frequency divider circuit 10, the greater the fluctuations in the signal characteristics caused by the internal configuration of the multiple frequency divider circuit 10.

[0135] According to the clock modulation circuit 300 of this embodiment, fluctuations in signal characteristics caused by the internal configuration of the multiple frequency divider circuit 10 can be suppressed, and the accuracy of estimating the characteristics of the clock CLK can be further improved. When the first frequency divider circuit 10-1 is an n-frequency divider circuit, by providing D flip-flops as the second frequency divider circuit 10-2, ..., the nth frequency divider circuit 10-n, the characteristics of the clock CLK can be measured without omission while suppressing an increase in the number of circuit elements.

[0136] In this embodiment, the clock modulation circuit 300 performs a 4-fold frequency division operation by, for example, providing two flip-flops in the first frequency divider circuit 10-1. The second frequency divider circuit 10-2, the third frequency divider circuit 10-3, and the fourth frequency divider circuit 10-4 are each replaced by a single flip-flop, resulting in a total of, for example, five flip-flops. Compared to the first embodiment, it is possible to reduce the number of elements included in the multiple frequency divider circuit 10. Therefore, fluctuations in signal characteristics caused by the internal configuration of the multiple frequency divider circuit 10 can be suppressed, and the accuracy of estimating the characteristics of the clock CLK can be further improved.

[0137] (Fourth Embodiment) Figure 14 shows an example of the circuit configuration of the clock modulation circuit 400 according to the fourth embodiment. Figure 15 shows an example of the circuit configuration of the select circuit S shown in Figure 14. Some parts that are common with the clock modulation circuit 200 according to the second embodiment will be omitted from the explanation.

[0138] This embodiment differs from the second embodiment in that the multiple frequency divider circuit 10 includes a select circuit S. While the example will be described using a multiple frequency divider circuit 10 having two frequency dividers, it is sufficient to have two or more frequency dividers. The first frequency divider circuit 10-1 is a frequency divider circuit with n division (n≧2). The second frequency divider circuit 10-2 is, for example, a reset-enabled D flip-flop.

[0139] First, let's explain the select circuit S connected to the second frequency divider circuit 10-2. The select circuit S is connected to the data input terminal D of a flip-flop, which is an example of the second frequency divider circuit 10-2. The select circuit S has three input terminals. The select circuit S receives the output signal OUT1 of the first frequency divider circuit 10-1 as input to terminal D0, the output of the select signal input circuit 50 as input to terminal SL, and the inverted output terminal Q of the flip-flop, which is an example of the second frequency divider circuit 10-2. * It has a terminal D1 to which the output from is input (see Figure 15).

[0140] The select signal input circuit 50 may, for example, be included in the clock modulation circuit 300 and provided on the same chip as the multiplexing circuit 10, but is not limited to this. The select signal input circuit 50 outputs a controlled signal that is either in an H state (1) or an L state (0).

[0141] The operation of the select circuit S will be explained with reference to Figure 15. Terminal D0 of the select circuit S is the terminal to which the output signal OUT1 is input in Figure 14. Terminal SL is the terminal to which the output of the select signal input circuit 50 is input in Figure 14. Terminal D1 is the inverting output terminal Q of the flip-flop, which is an example of the second frequency divider circuit 10-2 in Figure 14. * This is the terminal to which the output from is input.

[0142] The select circuit S outputs the signal input from either terminal D0 or D1 as the output signal OUT_S, based on the input signal from terminal SL. For example, when the input from terminal SL is in the low state (0), the input from terminal D0 is output as the output signal OUT_S. When the input from terminal SL is in the high state (1), the input from terminal D1 is output as the output signal OUT_S.

[0143] Referring again to Figure 14, an example of the operation of the select circuit S connected to the second frequency divider circuit 10-2 will be explained.

[0144] First, let's consider the case where the input from the select signal input circuit 50 is in the L state (0). At this time, the output signal OUT1 is input to the data input terminal D of the flip-flop, which is the second frequency divider circuit 10-2. Therefore, similar to Figure 10 showing the clock modulation circuit 200 according to the second embodiment, an output signal OUT2 is output, which has a different rising edge timing from the output signal OUT1. The phase difference between output signals OUT1 and OUT2 is equal to the period of the clock CLK, making it possible to estimate the characteristics of the clock CLK (e.g., jitter).

[0145] On the other hand, when the input from the select signal input circuit 50 is in the H state (1), the data input terminal D of the flip-flop, which is the second frequency divider circuit 10-2, is connected to the inverting output terminal Q. * The output from is input. Therefore, the second frequency divider circuit 10-2 performs frequency division operation based on the second frequency division start signal Rc2. The output signal OUT2 is a signal obtained by dividing the clock CLK by two. For example, as shown in Figure 9, the first frequency division start signal Rc1 and the second frequency division start signal Rc2 simultaneously transition to the L state (0), and by comparing the rising edges of the output signals OUT1 and OUT2, the time difference Δt caused by the signal transmission path difference, etc., can be measured. Note that the time difference Δt can be measured as long as the rising edge triggers of the output signals OUT1 and OUT2 are the same rising edge of the clock CLK, so the frequencies do not necessarily need to be equal.

[0146] In other words, by controlling whether the input from the select signal input circuit 50 is in an L state (0) or an H state (1), it is possible to switch between measuring Δt and measuring the characteristics of the clock CLK.

[0147] When the input from the select signal input circuit 50 is in the L state (0), the frequency divider control circuit 20, for example, counts the pulses of the clock CLK to shift the timing of the falling edges of the first frequency divider start signal Rc1 and the second frequency divider start signal Rc2.

[0148] When the input from the select signal input circuit 50 is in the H state (1), the frequency divider control circuit 20 controls the first frequency divider start signal Rc1 and the second frequency divider start signal Rc2 to rise simultaneously. The frequency divider control circuit 20 and the select signal input circuit 50 switch their operations in conjunction as described above. The configuration that links the frequency divider control circuit 20 and the select signal input circuit 50 includes, for example, a circuit in the frequency divider control circuit 20 that can switch the second frequency divider start signal Rc2 to the state of the first frequency divider start signal Rc1. The operation of switching the second frequency divider start signal Rc2 to the state of the first frequency divider start signal Rc1 is controlled by the input from the select signal input circuit 50. For example, in response to the input from the select signal input circuit 50, the select circuit selects a signal between the first frequency divider start signal Rc1 and the second frequency divider start signal Rc2, and then sets the selected signal back to the second frequency divider start signal Rc2.

[0149] The clock modulation circuit 300 according to this embodiment can suppress fluctuations in the signal waveform caused by the internal configuration of the multiple frequency divider circuit 10, thereby improving the accuracy of estimating the characteristics of the clock CLK. Furthermore, by providing a select circuit S, it is possible to switch between a mode for measuring Δt and a mode for measuring the characteristics of the clock CLK. By measuring fluctuations in the signal waveform caused by the internal configuration of the multiple frequency divider circuit 10 and the time difference Δt due to signal transmission path differences, the accuracy of estimating the characteristics of the clock CLK can be further improved.

[0150] In this embodiment, the second frequency divider circuit 10-2 (including the third frequency divider circuit 10-3 and the nth frequency divider circuit 10-n if n≧3) can be replaced with a flip-flop. By reducing the number of elements included in the circuit, fluctuations in the signal waveform caused by the internal configuration of the multiple frequency divider circuit 10 are suppressed.

[0151] Furthermore, by providing a select circuit S, the phase difference between output signals OUT1 and OUT2 (i.e., the timing of the pulse rise) can be controlled, enabling the measurement of the time difference Δt. For comparison, the configuration shown in Figure 10 has the advantage of further reducing the number of elements included in the multiple frequency divider circuit 10 compared to this embodiment (the select circuit S is not required), but the phase difference between output signals OUT1 and OUT2 is, for example, the length of the period of the clock CLK.

[0152] On the other hand, according to this embodiment, the select circuit S connects the data input terminal D of the flip-flop, which is the second frequency divider circuit 10-2, to the inverting output terminal Q. * When an output from is input, the phase difference between output signals OUT1 and OUT2 can be controlled by the frequency divider control circuit 20. Therefore, the clock modulation circuit 300 can measure the time difference Δt.

[0153] In this embodiment, the number of elements contained within the multiple frequency divider circuit 10 can be reduced, and the influence of the multiple frequency divider circuit 10 on the signal waveform can be corrected, thereby further improving the accuracy of estimating the characteristics of the clock CLK.

[0154] Furthermore, although the select signal input circuit 50 is included in the clock modulation circuit 400 in Figure 14, it is not limited to this. For example, as shown in Figure 16, which represents a modified clock modulation circuit 401, the select signal input circuit 50 may be provided on a different chip from the clock modulation circuit 400.

[0155] Furthermore, as shown in Figure 16, if a third frequency divider circuit 10-3 and a fourth frequency divider circuit 10-4 are present, a select circuit S is also provided for the third frequency divider circuit 10-3 and the fourth frequency divider circuit 10-4, respectively, and the signal from the select signal input circuit 50 is transmitted via point T.

[0156] In Figure 16, the third frequency divider circuit 10-3 and the fourth frequency divider circuit 10-4 can also be used to differentiate between measuring Δt and measuring the characteristics of the clock CLK by controlling whether the input from the select signal input circuit 50 is in an L state (0) or an H state (1).

[0157] (Fifth embodiment) Figure 17 shows an example of the circuit configuration of the clock modulation circuit 500 according to the fifth embodiment. Figures 18 and 19 are timing charts showing an example of the operation of the clock modulation circuit 500 shown in Figure 17. Some parts that are common with the clock modulation circuit 100 according to the first embodiment will be omitted from the explanation.

[0158] This embodiment differs from the first embodiment in that the multiple frequency divider circuit 10 includes an inverting switch circuit 60. While the example is given where the first frequency divider circuit 10-1 and the second frequency divider circuit 10-2 are 2-division frequency dividers, the embodiment is not limited to this. Furthermore, while the example is given where the multiple frequency divider circuit 10 has two frequency dividers, it is sufficient for it to have two or more frequency dividers.

[0159] An inverting switch circuit 60 is provided between at least one of the multiple frequency dividers included in the multiple frequency divider circuit 10 of the clock modulation circuit 400 and the clock output circuit CG. In the example shown in Figure 17, the inverting switch circuit 60 is provided between the second frequency divider circuit 10-2 and the clock output circuit CG. The inverting switch circuit 60 has an inverting circuit and a switch.

[0160] The inverting switch circuit 60 is connected to the inverting control circuit 70. The inverting control circuit 70 controls the switching of the switches in the inverting switch circuit 60. The inverting control circuit 70 is not included in the clock modulation circuit 500, as shown in Figure 17, for example, but the clock modulation circuit 500 and the inverting control circuit 70 may be formed on the same chip.

[0161] Figure 17 shows an example of the circuit configuration of the inverting switch circuit 60. The switch in the inverting switch circuit 60 switches whether or not the clock signal CLK passes through the inverting circuit. First, the operation when the clock signal CLK does not pass through the inverting circuit is the same as that of the clock modulation circuit 100 shown in Figure 2, for example, so it will be omitted. For example, it is possible to estimate the signal characteristics of the clock CLK, such as jitter.

[0162] Next, we will explain the operation when the clock signal CLK passes through the inverting circuit, referring to Figure 18. In the first frequency divider circuit 10-1, for example, the rising edge of the clock CLK acts as the trigger, while in the second frequency divider circuit 10-2, because the clock CLK is inverted, the falling edge of the clock CLK effectively acts as the trigger in Figure 18.

[0163] Compared to the first frequency division start signal Rc1, the second frequency division start signal Rc2 has a falling edge that is delayed by half the period of the clock CLK. When the first frequency division start signal Rc1 is in the low state and the clock CLK is rising, the output signal OUT1 transitions to the high state (1). Subsequently, when the second frequency division start signal Rc2 is in the low state and the clock CLK is falling, the output signal OUT2 transitions to the high state (1). The rising edge timings of output signals OUT1 and OUT2 differ by half the period of the clock CLK.

[0164] Here, the waveforms of the first frequency division start signal Rc1 and the second frequency division start signal Rc2 differ from those in Figure 4, for example. This can be achieved by a circuit having the following configuration, for example. For example, the frequency division control circuit 20 shown in Figure 3 is triggered by the falling edge of the clock, but by further having another frequency division control circuit that is triggered by the rising edge of the clock, the second frequency division start signal Rc2 shown in Figure 18 can be output.

[0165] Alternatively, this embodiment can be realized by a circuit having the following configuration, for example. In Figure 4, the bit sequence (X3 X2 X1) switches with each period of the clock CLK. For example, by adding the clock CLK itself to the bit sequence, a bit sequence can be generated that switches with each half-period of the clock CLK in the order of 0000, 0001, 0010, 0011, ...1111. If C is the bit that indicates the state of the clock CLK, then a 4-bit bit sequence X3 X2 X1 C is formed.

[0166] For example, a frequency divider control circuit 20 having a 4-input, 16-output decoder transitions the first frequency divider start signal Rc1 to the L state in bit sequence 0010, and the second frequency divider start signal Rc2 to the L state in bit sequence 0011, and so on. After half the period of the clock CLK has elapsed since the transition of the first frequency divider start signal Rc1 to the L state, the clock CLK transitions to the H state (1), and the second frequency divider start signal Rc2 transitions to the L state (see the waveforms of X3, X2, X1 and clock CLK in Figure 4).

[0167] The difference between the rising edge time t1 of output signal OUT1 and the rising edge time t2 of output signal OUT2 corresponds to the pulse width of the clock CLK. Similarly, by measuring the next rising edge time t3 of output signal OUT1 and the next rising edge time t4 of output signal OUT2, the pulse width of the clock CLK can be estimated.

[0168] Figure 19 also shows an example where an inverting switch circuit 60 is provided in the first frequency divider circuit 10-1. The output signal OUT1 is essentially triggered by the falling edge of the clock CLK. Conversely, the output signal OUT2 is triggered by the rising edge of the clock CLK.

[0169] By measuring the time difference between times t1 and t2 shown in Figure 19, the length of the valley between pulses in the clock CLK can be measured.

[0170] Therefore, the clock modulation circuit 500 according to this embodiment can estimate the duty cycle, which is one of the characteristics of the clock CLK. By switching the switch of the inverting switch circuit 60, it is possible to switch between a mode for measuring jitter and a mode for measuring the duty cycle, which are characteristics of the clock CLK.

[0171] According to the clock modulation circuit 500 of this embodiment, the duty cycle of the clock CLK can also be estimated, thereby enabling a more reliable evaluation of the characteristics of the clock CLK.

[0172] With the configuration of this embodiment, as described in the clock modulation method relating to the first modification of the first embodiment, the accuracy of the characteristics of the clock CLK can be further improved by estimating the skew difference Δs and fluctuation Δf.

[0173] According to at least one of the first to fifth embodiments of the semiconductor device described above, the reduction in the amount of information in the signal after dividing the clock CLK by the multiple frequency divider circuit 10 having multiple frequency divider circuits can be suppressed, and the characteristics of the clock CLK can be measured with higher precision.

[0174] The above explanation described transitions to the H state and the L state, but it is also possible to substitute the H state and the L state. For example, instead of starting the frequency division operation when the first frequency division start signal Rc1 transitions to the H state, the frequency division operation may also be started when the first frequency division start signal Rc1 transitions to the L state. Furthermore, it is also possible to choose whether to use the rising edge or falling edge of the pulse as the trigger. In the explanation above, the rising edges of the output signals OUT1, OUT2, etc. were compared, but it is also possible to compare the falling edges.

[0175] The embodiments have been described above with reference to specific examples. However, the embodiments are not limited to these specific examples. That is, designs modified by those skilled in the art are also included in the scope of the embodiments, as long as they retain the characteristics of the embodiments. The elements, their arrangement, materials, conditions, shapes, sizes, etc., of each of the above-described specific examples are not limited to those exemplified and can be modified as appropriate.

[0176] Furthermore, the elements of each embodiment described above can be combined to the extent that it is technically possible, and these combinations are also included in the scope of the embodiment insofar as they include the characteristics of the embodiment. In addition, within the realm of the concept of the embodiment, a person skilled in the art can conceive of various modifications and alterations, and it is understood that these modifications and alterations also fall within the scope of the embodiment.

[0177] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.

[0178] (Note 1) Clock output circuit and, A clock is input from the aforementioned clock output circuit, and a multiple frequency divider circuit has multiple frequency divider circuits that divide the clock, A frequency divider control circuit controls the timing of the start of frequency division for each of the plurality of frequency divider circuits, and controls the phase difference between at least one pair of output signals of the plurality of frequency divider circuits based on the period of the clock, A clock modulation circuit having the following features.

[0179] (Note 2) Clock output circuit and, A multiple frequency divider circuit to which a clock is input from the clock output circuit, the multiple frequency divider circuit having a first frequency divider circuit and a second frequency divider circuit, A frequency divider control circuit that transmits a first frequency divider start signal to the first frequency divider circuit and a second frequency divider start signal to the second frequency divider circuit, A clock modulation circuit having the following features.

[0180] (Note 3) The absolute value of the difference between the rising or falling timing of the first frequency division start signal and the second frequency division start signal is between 3 / 4 and 5 / 4 of the clock period. The clock modulation circuit described in Appendix 2.

[0181] (Note 4) The frequency divider control circuit receives the clock and controls the difference in the rising or falling timing of the first frequency divider start signal and the second frequency divider start signal. The clock modulation circuit described in Appendix 2.

[0182] (Note 5) The aforementioned frequency divider control circuit is A bit sequence generation circuit to which the aforementioned clock is input, A frequency divider start signal generation circuit that converts the m-bit signal (where m is a natural number satisfying m≧2) output by the bit string generation circuit into a first frequency divider start signal and a second frequency divider start signal, Having, The clock modulation circuit described in Appendix 2.

[0183] (Note 6) The frequency division start signal generation circuit includes a decoder. The clock modulation circuit described in Appendix 5.

[0184] (Note 7) For the aforementioned natural number m, 2 m -1 is greater than or equal to the number of frequency dividers in the multiple frequency divider circuit. The clock modulation circuit described in Appendix 5.

[0185] (Note 8) The first frequency divider circuit and the second frequency divider circuit are connected in parallel to the clock output circuit. The clock modulation circuit described in Appendix 2.

[0186] (Note 9) The output of the first frequency divider is input to the second frequency divider. The clock modulation circuit described in Appendix 2.

[0187] (Note 10) The aforementioned second frequency divider circuit is a flip-flop. The clock modulation circuit described in Appendix 9.

[0188] (Note 11) The circuit further includes a selector circuit to which the output of the first frequency divider and the inverted output of the second frequency divider are input. The output of the select circuit is input to the second frequency divider circuit. The clock modulation circuit described in Appendix 2.

[0189] (Note 12) An inverting switch circuit is provided between the second frequency divider circuit and the clock output circuit, which receives input from a switch and inverts the clock according to the state of the switch. The clock modulation circuit described in Appendix 2.

[0190] (Note 13) The aforementioned multiple frequency divider circuit has at least n frequency divider circuits, each dividing the frequency by n (n≧2). The semiconductor device described in Appendix 1 or 2.

[0191] (Note 14) A clock modulation circuit having a clock output circuit, a frequency divider control circuit, a first frequency divider circuit and a second frequency divider circuit, The first frequency division start signal output from the earlier frequency division control circuit is transmitted to the first frequency division circuit. The first frequency divider circuit outputs a first output signal obtained by dividing the clock frequency, The second frequency division start signal output from the frequency division control circuit is transmitted to the second frequency division circuit. The second frequency divider circuit outputs a second output signal obtained by dividing the clock frequency. Clock modulation method.

[0192] (Note 15) The frequency divider control circuit outputs a second frequency divider start signal whose absolute value of the difference in rising or falling timing compared to the first frequency divider start signal is between 3 / 4 and 5 / 4 of the clock period. The clock modulation method described in Appendix 14.

[0193] (Note 16) The frequency divider control circuit receives the clock, generates a bit sequence, and outputs the first and second frequency divider start signals that rise or fall in relation to different values ​​of the bit sequence. The clock modulation method described in Appendix 14.

[0194] (Note 17) The third frequency division start signal output from the earlier frequency division control circuit is transmitted to the first frequency division circuit. A fourth frequency division start signal, output from the frequency division control circuit and having a difference in rising or falling timing compared to the third frequency division start signal that is less than or equal to 1 / 4 of the clock period, is transmitted to the second frequency division circuit. The clock modulation method described in Appendix 14.

[0195] (Note 18) Upon receiving the initial third frequency division start signal, the first frequency divider circuit outputs a third output signal. The second frequency divider circuit, upon receiving the initial fourth frequency division start signal, outputs a fourth output signal whose phase difference with the third output signal is between 1 / 4 and 3 / 4 of the clock period. The clock modulation method described in Appendix 17.

[0196] (Note 19) The characteristics of the clock are estimated by measuring the rising or falling times of the first output signal and the second output signal. The clock modulation method according to any one of claims 14 to 18.

[0197] (Note 20) The rising or falling times of the third output signal and the fourth output signal are measured. By estimating the skew difference caused by differences in the signal transmission path and the signal fluctuations caused by the circuit configuration of the clock modulation circuit, The characteristics of the clock are estimated by measuring the rising or falling times of the first output signal and the second output signal. The clock modulation method described in Appendix 18. [Explanation of symbols]

[0198] CG... Clock output circuit 10...Multiple frequency divider circuit 10-1...1st frequency divider circuit 10-2...Second frequency divider circuit 20... Frequency divider control circuit 21...Start circuit 22-bit string generation circuit 23...Division start signal generation circuit 30. Interface 40...External circuit 50...Select signal input circuit 60... Reversing switch circuit 70... Reversal control circuit CLK...clock OUT1, OUT2... Output signals S...Select circuit Rc1...1st frequency division start signal Rc2...2nd frequency division start signal

Claims

1. Clock output circuit and, A clock is input from the aforementioned clock output circuit, and a multiple frequency divider circuit has multiple frequency divider circuits that divide the clock, A frequency divider control circuit controls the timing of the start of frequency division for each of the plurality of frequency divider circuits, and controls the phase difference between at least one pair of output signals of the plurality of frequency divider circuits based on the period of the clock, A clock modulation circuit having the following features.

2. Clock output circuit and, A multiple frequency divider circuit to which a clock is input from the clock output circuit, the multiple frequency divider circuit having a first frequency divider circuit and a second frequency divider circuit, A frequency divider control circuit that transmits a first frequency divider start signal to the first frequency divider circuit and a second frequency divider start signal to the second frequency divider circuit, A clock modulation circuit having the following features.

3. The absolute value of the difference between the rising or falling timing of the first frequency division start signal and the second frequency division start signal is between 3 / 4 and 5 / 4 of the clock period. The clock modulation circuit according to claim 2.

4. The frequency divider control circuit receives the clock and controls the difference in the rising or falling timing of the first frequency divider start signal and the second frequency divider start signal. The clock modulation circuit according to claim 2.

5. The aforementioned frequency divider control circuit is A bit sequence generation circuit to which the aforementioned clock is input, A frequency divider start signal generation circuit that converts the m-bit signal (where m is a natural number satisfying m≧2) output by the bit sequence generation circuit into a first frequency divider start signal and a second frequency divider start signal, Having, The clock modulation circuit according to claim 2.

6. The first frequency divider circuit and the second frequency divider circuit are connected in parallel to the clock output circuit. The clock modulation circuit according to claim 2.

7. The output of the first frequency divider is input to the second frequency divider. The clock modulation circuit according to claim 2.

8. The circuit further includes a selector circuit to which the output of the first frequency divider and the inverted output of the second frequency divider are input. The output of the select circuit is input to the second frequency divider circuit. The clock modulation circuit according to claim 2.

9. An inverting switch circuit is provided between the second frequency divider circuit and the clock output circuit, which receives input from a switch and inverts the clock according to the state of the switch. The clock modulation circuit according to claim 2.

10. A clock modulation circuit having a clock output circuit, a frequency divider control circuit, a first frequency divider circuit and a second frequency divider circuit, The first frequency division start signal output from the earlier frequency division control circuit is transmitted to the first frequency division circuit. The first frequency divider circuit outputs a first output signal obtained by dividing the clock frequency. The second frequency division start signal output from the frequency division control circuit is transmitted to the second frequency division circuit. The second frequency divider circuit outputs a second output signal obtained by dividing the clock frequency. Clock modulation method.

11. The frequency divider control circuit outputs a second frequency divider start signal whose absolute value of the difference in rising or falling timing compared to the first frequency divider start signal is between 3 / 4 and 5 / 4 of the clock period. The clock modulation method according to claim 10.

12. The third frequency division start signal output from the earlier frequency division control circuit is transmitted to the first frequency division circuit. A fourth frequency division start signal, output from the frequency division control circuit and having a difference in rising or falling timing compared to the third frequency division start signal that is 1 / 4 or less of the clock period, is transmitted to the second frequency division circuit. The clock modulation method according to claim 10.

13. Upon receiving the third frequency division start signal, the first frequency divider circuit outputs a third output signal. The second frequency divider circuit, upon receiving the initial fourth frequency division start signal, outputs a fourth output signal whose phase difference with the third output signal is between 1 / 4 and 3 / 4 of the clock period. The clock modulation method according to claim 12.

14. The rising or falling times of the third output signal and the fourth output signal are measured. By estimating the skew difference caused by differences in the signal transmission path and the signal fluctuations caused by the circuit configuration of the clock modulation circuit, The characteristics of the clock are estimated by measuring the rising or falling times of the first output signal and the second output signal. The clock modulation method according to claim 13.

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