Calculation unit, memory controller, and calculation method

Abstract

We provide a computing device that enables the implementation of large-scale, rewritable hardware at a low cost. [Solution] According to the embodiment, the arithmetic unit comprises a non-volatile memory and a memory controller. The non-volatile memory includes a plurality of memory cells, each of which can be in either a first state or a second state. The memory controller defines the first state as a state in which a first value is stored and the second state as a state in which a second value is stored, initializes the memory cells to the first state, maintains the current state of the memory cells in response to a request to write the first value, and transitions the memory cells to the second state in response to a request to write the second value. As a result, the arithmetic unit can perform logical operations, including N-input AND operations, N-input NAND operations, N-input OR operations, or N-input NOR operations, by reading the values ​​stored in the memory cells after writing the first or second value to the memory cells N times.

Description

Technical Field

[0001] Embodiments of the present invention relate to an arithmetic unit, a memory controller, and an arithmetic method.

Background Art

[0002] FPGA (Field Programmable Gate Array) is distributed as hardware that can perform specific arithmetic processing at high speed and can be rewritten, compared to a general-purpose CPU (Central Processing Unit).

[0003] However, as the number of gates inside the FPGA increases and it becomes large-scale, it becomes expensive, so it has remained at the development of prototypes and the adoption for small-scale production products.

[0004] For example, when developing large-scale and rewritable hardware, even in cases where arithmetic speed is not required, a relatively expensive product among FPGAs must be selected.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] One embodiment of the present invention provides an arithmetic unit, a memory controller, and an arithmetic method for realizing large-scale and rewritable hardware at low cost.

Means for Solving the Problems

[0007] According to the embodiment, the arithmetic unit comprises a non-volatile memory and a memory controller. The non-volatile memory includes a plurality of memory cells, each of which can be in either a first state or a second state. The memory controller controls the non-volatile memory. The memory controller defines the first state as a state in which a first value is stored and the second state as a state in which a second value is stored, initializes the memory cells to the first state, maintains the current state of the memory cells in response to a request to write a first value to the memory cells, transitions the memory cells to the second state in response to a request to write a second value to the memory cells, and retrieves either the first or second value stored in the memory cells, or the second or first value obtained by reversing the first or second value stored in the memory cells, as the value stored in the memory cells in response to a request to read a value stored in the memory cells. As a result, the arithmetic unit can perform logical operations, including N-input AND operations, N-input NAND operations, N-input OR operations, or N-input NOR operations, by writing a first or second value to the memory cell N times (where N is a natural number greater than or equal to 2), and then reading the value stored in the memory cell. [Brief explanation of the drawing]

[0008] [Figure 1] A diagram showing an example configuration of the computing device of the first embodiment. [Figure 2] The first diagram illustrates how the arithmetic unit of the first embodiment configures a two-input AND gate using flash memory cells. [Figure 3] A second diagram illustrating how the arithmetic unit of the first embodiment configures a two-input AND gate using the memory cells of flash memory. [Figure 4] A diagram illustrating how the arithmetic unit of the first embodiment configures a two-input NAND gate using flash memory cells. [Figure 5] The first diagram illustrates how the arithmetic unit of the first embodiment configures a two-input OR gate using flash memory cells. [Figure 6]A second diagram illustrating how the arithmetic unit of the first embodiment configures a two-input OR gate using flash memory cells. [Figure 7] A diagram illustrating how the arithmetic unit of the first embodiment configures a two-input NOR gate using memory cells of flash memory. [Figure 8] This figure shows an example in which the arithmetic unit of the first embodiment configures an adder using a combination of two-input NAND gates configured with flash memory cells. [Figure 9] This figure shows an example in which the arithmetic unit of the first embodiment connects several stages of adders, each composed of a combination of NAND gates. [Figure 10] This figure shows an example of instruction code used to create a program for performing arbitrary logical operations using flash memory in the arithmetic unit of the first embodiment. [Figure 11] A diagram showing an example of a program for configuring an adder using the flash memory used in the arithmetic unit of the first embodiment. [Figure 12] A flowchart illustrating the procedure by which the arithmetic unit of the first embodiment performs logical operations using the memory cells of flash memory. [Figure 13] A diagram illustrating how the arithmetic unit of the second embodiment configures a two-input AND gate using multilevel cell flash memory. [Figure 14] A diagram illustrating the parallel processing of logical operations in the arithmetic unit of the fourth embodiment. [Modes for carrying out the invention]

[0009] The embodiments will be described below with reference to the drawings.

[0010] (First Embodiment) First, the first embodiment will be described.

[0011] Figure 1 shows an example configuration of the computing device 1 of the first embodiment.

[0012] The arithmetic unit 1 includes a memory controller 10, a flash memory 20, and a program counter 30.

[0013] The memory controller 10 controls the flash memory 20. Specifically, the memory controller 10 controls the data writing process to the flash memory 20 and the data reading process from the flash memory 20.

[0014] The flash memory 20 is a non-volatile memory including a plurality of memory cells. The flash memory 20 may be of the NAND type or the NOR type. Furthermore, although an example in which the arithmetic unit 1 applies the flash memory 20 is shown here, the arithmetic unit 1 can also apply a non-volatile memory other than the flash memory 20 as will be described later.

[0015] The program counter 30 is a device that supplies an address to the memory controller 10 so that a program for logical operation, which will be described later and is stored in the flash memory 20, is read out one step at a time.

[0016] In the arithmetic unit 1 of the first embodiment, the memory controller 10 controls the writing process to the flash memory 20 and the reading process from the flash memory 20, thereby realizing the configuration of an arbitrary logic circuit at a much lower cost than an FPGA, like an FPGA. Hereinafter, this point will be described in detail. In the arithmetic unit 1 of the first embodiment, configuring an arbitrary logic circuit means performing a logical operation equal to that of an arbitrary logic circuit, that is, logically configuring an arbitrary logic circuit.

[0017] Here, referring to FIGS. 2 to 4, an example of a method for configuring a logic circuit by writing to and reading from the flash memory 20 will be described.

[0018] If we define the initial state of the memory cell of the flash memory 20 as "1," where no electrons are stored in the floating gate, then once a "0" is written by applying a voltage to the control gate to cause electrons to flow into the floating gate, the value will not change even if it is subsequently overwritten with "1." In other words, it will be ignored. Figure 2(A) shows the state transitions of the read values ​​of the memory cell of the flash memory 20 when a "0" or a "1" is written to the memory cell of the flash memory 20. Furthermore, erasing to return the memory cell to its initial state is achieved by applying a voltage to the silicon substrate, causing the electrons stored in the floating gate to flow out to the silicon substrate.

[0019] Figure 2(B) shows the values ​​read from the memory cells of the flash memory 20 after two write operations have been performed on the memory cells of the flash memory 20.

[0020] As shown in Figure 2(B), when "0" is written to the memory cell of flash memory 20 the first time, and then "0" is written to it the second time, the value read from the memory cell of flash memory 20 will be "0". Similarly, when "0" is written the first time and "1" the second time, the read value will be "0". Likewise, when "1" is written the first time and "0" the second time, the read value will be "0", and when "1" is written the first time and "1" the second time, the read value will be "1".

[0021] The arithmetic unit 1 of the first embodiment assumes, for example, that the first write is input A, the second write is input B, and the read value after the second write is output. Under this assumption, the arithmetic unit 1 of the first embodiment configures a two-input AND gate as shown in Figure 3(A) by writing to and reading from the memory cells of the flash memory 20. Figure 3(B) is the truth table of the two-input AND gate. The value of "A AND B" shown in Figure 3(B) matches the "read value" shown in Figure 2(B).

[0022] Thus, the arithmetic unit 1 of the first embodiment can perform AND operations on written data by utilizing the properties of the memory cells of the flash memory 20. The arithmetic unit 1 of the first embodiment is not limited to the two-input AND gate described above, but can also be configured as an N-input AND gate (where N is a natural number greater than or equal to 2).

[0023] Furthermore, the arithmetic unit 1 of the first embodiment can configure a two-input NAND gate as shown in Figure 4(A) by inverting the read value from the memory cell of the flash memory 20 in some way. Figure 4(B) is the truth table of the two-input NAND gate. Figure 4(C) is the table in Figure 2(B) with the addition of a column for read value negation, which is the value obtained by inverting the read value from the memory cell of the flash memory 20. The value of "A NAND B" shown in Figure 4(B) matches the "read value negation" which is the inverted "read value" shown in Figure 4(C).

[0024] Three methods can be considered for inverting the values ​​read from the memory cells of the flash memory 20.

[0025] (1) The program, referred to as firmware or the like, which operates within the memory controller 10 (a program that constitutes the arithmetic area readout circuit 14, which will be described later), is used to invert the image. (2) A NOT gate is provided on the line in the bus between the memory controller 10 and the flash memory 20 through which the read value is transferred from the flash memory 20 to the memory controller 10. (3) When reading data, the flash memory 20, instead of normally determining the value as "1" if the threshold voltage of the memory cell is low, determines the value as "0". The threshold voltage is the voltage at which current begins to flow between the source and drain of the memory cell. Current flows easily through the memory cell in its initial state (erasure state, unwritten state) when no electrons are stored in the floating gate, while current flows less easily in the write state when electrons are stored in the floating gate. In other words, the flash memory 20 reverses the read value based on its determination when reading from the memory cell.

[0026] Thus, the arithmetic unit 1 of the first embodiment can perform NAND operations on written data by utilizing the properties of the memory cells of the flash memory 20. In other words, the arithmetic unit 1 of the first embodiment can logically construct NAND gates using the flash memory 20.

[0027] NAND gates are known to possess "functional completeness" (also called functional suitability) on their own. Therefore, in the arithmetic unit 1 of the first embodiment, any logic circuit can be constructed depending on the combination of NAND gates.

[0028] Thus, the arithmetic unit 1 of the first embodiment can configure any logic circuit by writing to and reading from the flash memory 20.

[0029] Next, with reference to Figures 5 to 7, another example of a method for configuring a logic circuit by writing to and reading from the flash memory 20 will be described.

[0030] In this alternative method, the arithmetic unit 1 of the first embodiment defines the initial state of the memory cell of the flash memory 20, in which no electrons are stored in the floating gate, as "0," which is the opposite of the usual state. In this case, once a "1" is written by applying a voltage to the control gate and causing electrons to flow into the floating gate, the value will not change even if it is subsequently overwritten with "0".

[0031] Figure 5(A) shows the state transitions of the memory cells of the flash memory 20 when a "0" or a "1" is written to the memory cells of the flash memory 20, with the definitions of "0" and "1" reversed.

[0032] Figure 5(B) shows the read values ​​from the memory cells of the flash memory 20 after two write operations have been performed on the memory cells of the flash memory 20.

[0033] As shown in Figure 5(B), when "0" is written to the memory cell of flash memory 20 the first time, and then "0" is written to it the second time, the value read from the memory cell of flash memory 20 will be "0". Also, when "0" is written the first time and "1" is written the second time, the value read will be "1". Similarly, when "1" is written the first time and "0" is written the second time, the value read will be "1", and when "1" is written the first time and "1" is written the second time, the value read will be "1".

[0034] As described above, the arithmetic unit 1 of the first embodiment assumes that the first write is input A, the second write is input B, and the read value after the second write is output, and by writing to and reading from the memory cells of the flash memory 20, it configures a two-input OR gate as shown in Figure 6(A). Figure 6(B) is the truth table of the two-input OR gate. The value of "A OR B" shown in Figure 6(B) matches the "read value" shown in Figure 5(B).

[0035] Furthermore, Figure 7(A) shows the read value from the memory cell of the flash memory 20 and the negation of the read value when the definitions of "0" and "1" are reversed and two write operations are performed on the memory cell of the flash memory 20.

[0036] As shown in Figure 7(A), when "0" is written to the memory cell of flash memory 20 the first time and then "0" is written to it the second time, the read value from the memory cell of flash memory 20 is "0", and the read value negation is "1". Also, when "0" is written the first time and "1" the second time, the read value is "1" and the read value negation is "0". Similarly, when "1" is written the first time and "0" the second time, the read value is "1" and the read value negation is "0", and when "1" is written the first time and "1" the second time, the read value is "1" and the read value negation is "0".

[0037] Furthermore, Figure 7(B) shows the truth tables for a two-input OR gate and a two-input NOR gate. The values ​​for "A OR B" shown in Figure 7(B) match the "readout values" shown in Figure 7(A), and the values ​​for "A NOR B" shown in Figure 7(B) match the "negation of the readout values" shown in Figure 7(A).

[0038] Thus, the arithmetic unit 1 of the first embodiment can perform OR operations on written data by utilizing the properties of the memory cells of the flash memory 20, and can also perform NOR operations on written data by inverting the values ​​read from the memory cells of the flash memory 20.

[0039] In other words, the arithmetic unit 1 of the first embodiment can logically construct a NOR gate using the flash memory 20.

[0040] NOR gates are known to possess "functional completeness" (also called functional suitability) on their own. Therefore, in the arithmetic unit 1 of the first embodiment, any logic circuit can be constructed depending on the combination of NOR gates.

[0041] Thus, the arithmetic unit 1 of the first embodiment can configure any logic circuit by writing to and reading from the flash memory 20.

[0042] In the above, we have described an example that utilizes the property of flash memory 20 in which, once a write operation is performed by applying a voltage to the control gate and causing electrons to flow into the floating gate, the state does not change until an erase operation is performed by applying a voltage to the silicon substrate and causing the electrons stored in the floating gate to flow out to the silicon substrate. Alternatively, the arithmetic unit 1 of the first embodiment can also use a non-volatile memory other than flash memory 20 by having the memory controller 10 control the non-volatile memory to simulate the properties of flash memory 20.

[0043] Specifically, for example, if the initial state of each storage area of ​​the non-volatile memory to be applied is defined as "1", the memory controller 10 only needs to control the write operation to the target storage area if the data to be written is "0". In other words, if the data to be written is "1", the write operation to the target storage area is omitted. This makes it possible to construct a multi-input AND gate (N (where N is a natural number greater than or equal to 2) input AND gate) where the read value is "1" if no "0" is written, and the read value is "1" if "0" is written at least once.

[0044] Figure 8 shows an example in the first embodiment of the arithmetic unit 1, where the memory cells of the flash memory 20 are treated as NAND gates to configure an adder.

[0045] In Figure 8, inputs A and B are two values ​​for a certain digit to be added. Input C' is the carry value from the lower digit. Output S is the value of that digit obtained as a result of the addition, and output C is the carry value to the upper digit.

[0046] Thus, the arithmetic unit 1 of the first embodiment can be configured as a one-digit adder by combining six stages of NAND gates, each of which is constructed using the memory cells of the flash memory 20.

[0047] Figure 9 also shows an example of connecting several stages of adders configured as described above.

[0048] In Figure 9, the area above the dashed line shows an example where multiple adders are connected in series. In contrast, the area above the dashed line shows an example where multiple adders are connected in parallel using a carry-lookahead adder.

[0049] The arithmetic unit 1 of the first embodiment requires, for example, multiple writes to flash memory 20 and one read from flash memory 20 for a single NAND operation, but the critical path can be reduced by applying prior art such as a carry lookahead adder.

[0050] Returning to Figure 1, we will now proceed with the explanation of one example configuration of the arithmetic unit 1 of the first embodiment.

[0051] The memory controller 10 includes a ROM area read circuit 11, an instruction decoder 12, an interface (I / F) circuit 13, an arithmetic area read circuit 14, an arithmetic area write circuit 15, and an erase circuit 16.

[0052] The ROM area read circuit 11 is a module that reads a program for logical calculations from the ROM area 21 reserved in the flash memory 20. The memory controller 10 reserves, for example, the ROM area 21 for storing the program and the arithmetic area 22 used for logical calculations in the flash memory 20.

[0053] The ROM area read circuit 11 reads one step of program from the ROM area 21 of the flash memory 20 based on the address transmitted from the program counter 30. The ROM area read circuit 11 then transfers the read one step of program to the instruction decoder 12.

[0054] The instruction decoder 12 is a module that interprets a one-step program received from the ROM area read circuit 11. As a result of the interpretation, the instruction decoder 12 outputs, for example, a command to read data from the arithmetic area 22 of the flash memory 20, or a command to write data to the arithmetic area 22 of the flash memory 20, to the interface circuit 13. When outputting these commands, the instruction decoder 12 also outputs the address of the target to be read or written in the arithmetic area 22 to the interface circuit 13.

[0055] Furthermore, when the instruction decoder 12 outputs a data read command to the interface circuit 13, it outputs a control signal to the interface circuit 13 to cause that command to be output to the arithmetic area read circuit 14. On the other hand, when the instruction decoder 12 outputs a data write command to the interface circuit 13, it outputs a control signal to the interface circuit 13 to cause that command to be output to the arithmetic area write circuit 15. In addition, the instruction decoder 12 outputs a logic inversion signal to the interface circuit 13 to invert the read value to the negation of the read value, as needed.

[0056] The interface circuit 13 is a module that operates as a demultiplexer. Based on the control signals input from the instruction decoder 12, the interface circuit 13 selectively outputs the commands received from the instruction decoder 12 to either the arithmetic area read circuit 14 or the arithmetic area write circuit 15.

[0057] The arithmetic area read circuit 14 issues a read command to the flash memory 20 for data received from the interface circuit 13. At this time, the arithmetic area read circuit 14 appends the address received from the interface circuit 13 to the data read command. This address indicates the arithmetic area 22 of the flash memory 20. The arithmetic area read circuit 14 transfers the read value from the arithmetic area 22 of the flash memory 20 to the interface circuit 13. This read value is stored, for example, in a register in the memory controller 10 via the interface circuit 13.

[0058] The arithmetic area writing circuit 15 issues a write command to the flash memory 20 based on the data it received from the interface circuit 13. At this time, the arithmetic area writing circuit 15 appends the address received from the interface circuit 13 to the data write command. This address points to the arithmetic area 22 of the flash memory 20.

[0059] The erase circuit 16 is a module that controls the erasure process to restore used memory cells in the arithmetic area 22 of the flash memory 20 to their initial state. Specifically, the erase circuit 16 issues an erase command to the flash memory 20, targeting a portion of the arithmetic area 22. As memory cells in the arithmetic area 22 are consumed for logical operations, the initial state of memory cells is depleted. The memory controller 10, as needed, uses the erase circuit 16 to perform erasure to restore used memory cells to their initial state.

[0060] Figure 10 shows an example of instruction codes used to create a program for performing arbitrary logical operations using the flash memory 20 in the arithmetic unit 1 of the first embodiment. Figure 10 shows 16 instruction codes, each identified by 4 bits. A program for performing arbitrary logical operations is created using these instruction codes and stored in the ROM area 21 of the flash memory 20.

[0061] Figure 11 also shows an example of a program created using the instruction code shown in Figure 10 to perform the same logical operations as the adder shown in Figure 8. The ROM area read circuit 11 reads one step of the program from the ROM area 21, for example, the program shown in Figure 11, based on the address it receives from the program counter 30. The instruction decoder 12 converts the one step of program received from the ROM area read circuit 11 into one of the commands shown in Figure 10. The instruction decoder 12 then transfers the converted command to the arithmetic area read circuit 14 or the arithmetic area write circuit 15 via the interface circuit 13.

[0062] As a result, the arithmetic unit 1 of the first embodiment realizes logical operations by reading and writing to the memory cells of the flash memory 20.

[0063] Figure 12 is a flowchart showing the procedure by which the arithmetic unit 1 of the first embodiment performs logical operations using the memory cells of the flash memory 20. Here, an example of performing an N-input AND operation or an N-input NAND operation is described. In other words, it is assumed here that the initial state of the memory cell is defined as "1" and the written state in which electrons are accumulated in the floating gate is defined as "0".

[0064] First, the memory controller 10 initializes the memory cells of the arithmetic area 22 of the flash memory 20 using the erase circuit 16 (S101). It is preferable that this initialization is performed in advance.

[0065] The memory controller 10 obtains the write command described in the program stored in the ROM area 21 using the ROM area read circuit 11 (S102). The memory controller 10 then determines whether the write data is "0" or "1" (S103).

[0066] If the data to be written is "1" (S103:YES), the memory controller 10 writes "0" to the memory cell using the arithmetic area writing circuit 15 (S104). If the data to be written is "0" (S103:NO), the memory controller 10 omits the writing process to the memory cell. Note that, since flash memory 20 is assumed as the non-volatile memory here, the memory controller 10 may also write "1" to the memory cell using the arithmetic area writing circuit 15.

[0067] The memory controller 10 determines whether the number of acquired write commands has reached N (S105). If it is less than N (S105: NO), the memory controller 10 returns to S102 and acquires the next write command.

[0068] If the number of write commands reaches N (S105: YES), the memory controller 10 then obtains a read command using the ROM area read circuit 11 (S106). The memory controller 10 then reads information from the memory cell using the arithmetic area read circuit 14 (S107).

[0069] This information corresponds to the result of an N-input NAND operation. Furthermore, when reading information from a memory cell, the memory controller 10 may perform a process to invert the information. The inverted information corresponds to the result of an N-input NAND operation.

[0070] As described above, the arithmetic unit 1 of the first embodiment can logically configure at least an AND gate or a NAND gate by reading from and writing to the memory cells of the flash memory 20.

[0071] Furthermore, the arithmetic unit 1 of the first embodiment can logically construct at least an OR gate or a NOR gate by reversing the definitions of "0" and "1" which correspond to the state of the memory cells of the flash memory 20.

[0072] As mentioned above, NAND gates and NOR gates are known to possess "functional completeness" (also called functional suitability) on their own. Therefore, in the arithmetic unit 1 of the first embodiment, any logic circuit can be constructed depending on the combination of NAND gates or NOR gates.

[0073] Thus, the arithmetic unit 1 of the first embodiment realizes large-scale and rewritable hardware at a low cost compared to, for example, an FPGA.

[0074] Furthermore, although not shown in Figure 1, the arithmetic unit 1 of the first embodiment can also be configured as a basic element of a computer by further allocating a main memory area used as a working area for a program that performs logical operations, and an auxiliary memory area where information used by the program is stored, within the flash memory 20.

[0075] In the first embodiment, the computer configured by the arithmetic unit 1 retains all information in the flash memory 20, including the main memory area, even when the power is cut off. Therefore, calculations that were in progress before the power cut can be immediately resumed when the power is restored after a power cut. In addition, it is possible to easily debug the program in the event of a malfunction, such as by tracing the logical operation process.

[0076] (Second Embodiment) Next, a second embodiment will be described.

[0077] The arithmetic unit 1 of the first embodiment is based on SLC (single-level cell) flash memory 20. In contrast, the arithmetic unit 1 of the second embodiment uses multi-level cell flash memory 20 such as MLC (multi-level cell), TLC (triple-level cell), or QLC (quad-level cell).

[0078] For example, in the case of MLC, the memory cells of the flash memory 20 store binary values ​​such as "0,0", "0,1", "1,0", or "1,1". Figure 13(A) schematically shows the write state in which electrons are stored in the floating gate of the memory cell of the flash memory 20. The MLC flash memory 20 focuses on the fact that the threshold voltage changes depending on the number of electrons stored in the floating gate, and as shown in Figure 13(B), it is possible to record binary values ​​by setting four distributions.

[0079] If the binary correspondence for each distribution is as shown in Figure 13(B), then if current flows at a determination voltage of 1, then "1, 1" is recorded. In other words, the read value is "1, 1". Note that the state where current flows at the smallest determination voltage of 1 and the read value is "1, 1" is the initial state (erasure state) of the memory cell.

[0080] If no current flows at detection voltage 1, but current flows at detection voltage 2, the read value is "1, 0". Also, if no current flows at detection voltages 1 and 2, but current flows at detection voltage 3, the read value is "0, 0". And if no current flows even at detection voltage 3, the read value is "0, 1".

[0081] In contrast, the arithmetic unit 1 of the second embodiment, as shown in Figure 13(B), determines that if current flows at the determination voltage 1, the read value is "1", while if no current flows at the determination voltage 1, the read value is "0". Specifically, "1, 1" is treated as "1", and "1, 0", "0, 0", and "0, 1" are treated as "0". In other words, the four values ​​are combined into two values.

[0082] Figure 13(C) shows the state transitions of the read values ​​of the memory cells of the MLC flash memory 20 when "0,0", "0,1", "1,0", or "1,1" is written to the memory cells of the MLC flash memory 20 in the arithmetic unit 1 of the second embodiment.

[0083] As can be seen from Figure 13(C), when a write operation is performed that includes "1", such as "0, 1", "1, 0", or "1, 1", the read value of the memory cell in the arithmetic unit 1 of the second embodiment becomes "0".

[0084] In the first embodiment of the arithmetic unit 1, two write operations to the memory cell are required to perform a two-input AND operation. In contrast, in the second embodiment of the arithmetic unit 1, a two-input AND operation can be performed with a single write operation to the memory cell. The same applies to a two-input NAND operation that inverts the read value of the memory cell. Furthermore, by changing the binary mapping for each distribution, two-input OR and two-input NOR operations can also be performed with a single write operation to the memory cell.

[0085] Figure 13(D) shows the number of write operations for each combination of memory cell type and N-input NAND operation.

[0086] For example, with TLC memory cells, a 3-input NAND operation can be performed in a single write operation to the memory cell, while with QLC memory cells, a 4-input NAND operation can be performed in a single write operation to the memory cell.

[0087] For example, in the case of TLC and QLC memory cells, a 2-input NAND operation can be performed in a single write operation to the memory cell, but TLC lacks one input and QLC lacks two inputs. Therefore, the arithmetic unit 1 of the second embodiment supplements the inputs that are not used for the operation with 1.

[0088] As described above, the arithmetic unit 1 of the second embodiment can logically configure a multi-input, for example, NAND gate, with fewer write operations to the memory cells of the flash memory 20.

[0089] As a result, the arithmetic unit 1 of the second embodiment can achieve a higher calculation speed compared to the arithmetic unit 1 of the first embodiment.

[0090] (Third embodiment) Next, a third embodiment will be described.

[0091] For example, the arithmetic unit 1 of the first embodiment logically constructs a NAND gate or NOR gate known to possess "functional completeness" (also called functional suitability) by performing N write operations and one read operation on a memory cell, and then inverting the read value from the memory cell. The arithmetic unit 1 of the first embodiment, which can logically construct a NAND gate or NOR gate, can construct any logic circuit depending on the combination of NAND gates or NOR gates.

[0092] As mentioned earlier, there are three possible methods for inverting the values ​​read from memory cells.

[0093] (1) The program, which is called firmware or the like, that runs within the memory controller 10 (the program that constitutes the arithmetic area read circuit 14) is used to invert the data. (2) A NOT gate is provided on the line in the bus between the memory controller 10 and the flash memory 20 through which the read value is transferred from the flash memory 20 to the memory controller 10. (3) When reading, the flash memory 20, instead of normally determining "1" if the threshold voltage of the memory cell is low, determines "0".

[0094] The arithmetic unit 1 of the third embodiment has a function to turn on / off the function of inverting this read value, for example, by issuing a command to the memory controller 10 or by inputting a control signal to the flash memory 20 via the memory controller 10. In the case of the method of providing a NOT gate as in (2), the NOT gate is configured to be disabled by the control of the memory controller 10.

[0095] In other words, the arithmetic unit 1 of the third embodiment can operate as a device capable of configuring any logic circuit, such as an FPGA, and can also operate as a storage device for storing data by turning off the inversion function of the read value from the memory cell.

[0096] Furthermore, in the third embodiment, the arithmetic unit 1 may allow the on / off function of the inversion function of the read value from the memory cell to be switched not for the entire flash memory 20, but for example, for each predetermined area unit. In this case, the allocation of auxiliary storage area when constituting the basic elements of a computer, as described in the first embodiment, may be performed by turning off the inversion function of the read value from the memory cell.

[0097] As described above, the arithmetic unit 1 of the third embodiment has a function to turn on / off the function of inverting the value read from the memory cell, so it can operate as either (1) a device that can configure any logic circuit like an FPGA, or (2) a storage device for storing data.

[0098] (Fourth Embodiment) Next, a fourth embodiment will be described.

[0099] For example, the arithmetic unit 1 of the first embodiment performs logical operations by reading from and writing to memory cells. Therefore, when configuring a large-scale logic circuit, the throughput from the time an input is given until an output is obtained decreases.

[0100] On the other hand, flash memory 20 typically has multiple memory dies, each containing multiple memory cells. These memory dies are also called memory chips. Each memory die can operate independently; that is, the memory dies function as parallel operating units for the flash memory 20.

[0101] Therefore, the arithmetic unit 1 of the fourth embodiment aims to improve throughput by performing logical operations in parallel using multiple memory dies.

[0102] Figure 14 is a diagram illustrating the parallel processing of logical operations in the arithmetic unit 1 of the fourth embodiment.

[0103] In Figure 14, "FLASH" refers to the memory dies of the flash memory 20. An equal number of memory dies are connected to each channel. In Figure 14, four memory dies are connected to each of the two channels. Additionally, the two memory dies connected in parallel to channels 1 and 2 are organized as banks. A bank functions as a unit for parallel operation of multiple memory dies through bank interleaving. In the example shown in Figure 14, eight memory dies can be operated in parallel through bank interleaving using four banks across two channels.

[0104] The arithmetic unit 1 of the fourth embodiment processes logical operations in parallel using eight memory dies, as shown in Figure 14, for example. More specifically, data transfer is performed on each channel in a time-division multiplexer manner toward each memory die, and data writing is performed independently on each memory die.

[0105] As a result, the arithmetic unit 1 of the fourth embodiment can improve the throughput of the logic circuits configured using the flash memory 20.

[0106] (Fifth embodiment) Next, a fifth embodiment will be described.

[0107] As described in the first embodiment, for example, as memory cells of the flash memory 20 are consumed for logical operations, the initial state of memory cells is depleted. Therefore, the memory controller 10 performs an erase operation using the erase circuit 16 as needed to return the used memory cells to their initial state.

[0108] If the initial memory cells are depleted during a logical operation, the system will have to wait for the erasure process on the used memory cells to complete, significantly reducing the throughput of the logical operation.

[0109] Therefore, the arithmetic unit 1 of the fifth embodiment prevents the depletion of initial memory cells during logical operations by controlling, for example, the selection of memory dies that function as parallel operation units of the flash memory 20 as described in the fourth embodiment.

[0110] Specifically, for example, the memory controller 10 rotates the erasure of memory cells by the erase circuit 16 for each memory die, and performs logical operations using memory dies from banks other than the bank containing the memory die being erased.

[0111] As a result, the arithmetic unit 1 of the fifth embodiment prevents the throughput of the logic circuit configured using the flash memory 20 from decreasing due to the depletion of memory cells.

[0112] (Sixth Embodiment) Flash memory 20 degrades with each write and erase operation. Therefore, flash memory 20 undergoes periodic fault diagnosis. The memory die contains multiple blocks, and fault diagnosis is usually performed on a block-by-block basis. Blocks identified as faulty during fault diagnosis are then managed as faulty blocks and are not used thereafter.

[0113] Logical operations cannot be performed on a memory die containing a block undergoing fault diagnosis. Therefore, the arithmetic unit 1 of the sixth embodiment performs fault diagnosis on each memory die in rotation, similar to the memory cell erasure described in the arithmetic unit 1 of the fifth embodiment. The arithmetic unit 1 of the sixth embodiment then performs logical operations using memory dies from banks other than the bank containing the memory die undergoing fault diagnosis.

[0114] As a result, the arithmetic unit 1 of the sixth embodiment prevents the throughput of the logic circuit configured using the flash memory 20 from decreasing due to fault diagnosis.

[0115] (Seventh Embodiment) Next, a seventh embodiment will be described.

[0116] As explained in the sixth embodiment, the flash memory 20 degrades each time it is written to or erased. As the degradation progresses, the likelihood of errors occurring during reading and writing to the flash memory 20 increases. Therefore, errors occur with a certain probability in logical operations using the flash memory 20.

[0117] Therefore, the arithmetic unit 1 of the seventh embodiment is equipped with a mechanism to deal with errors in logical operations caused by the quality of the flash memory 20.

[0118] In the seventh embodiment, the arithmetic unit 1, for example, when performing a single NAND operation, duplicates the reading and writing operations to the memory cells for that NAND operation using multiple memory cells. This is equivalent to performing a single NAND operation multiple times. These operations are preferably performed in parallel.

[0119] For example, the memory controller 10 uses three memory cells to perform redundant and parallel read / write operations for a single NAND operation. The memory controller 10 then takes a majority vote on the read values ​​of the three memory cells. Considering the probability of the flash memory 20 generating errors, it can be said that it is highly unlikely that the incorrect read values ​​will constitute the majority.

[0120] As described in the fifth and sixth embodiments, the flash memory 20 has multiple memory dies, and each of the multiple memory dies contains multiple blocks. Each of the multiple blocks also contains multiple pages. Reading and writing to the flash memory 20 is usually performed in page units.

[0121] Therefore, when the memory controller 10 performs duplicate and parallel read / write operations for a single NAND operation, it performs them collectively using memory cells within the same page. This prevents a decrease in throughput caused by duplicate read / write operations for a single NAND operation in the arithmetic unit 1 of the seventh embodiment.

[0122] As described above, the arithmetic unit 1 of the seventh embodiment can deal with errors in logical operations caused by the quality of the flash memory 20.

[0123] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.

[0124] This embodiment includes the following features. [Note 1] A non-volatile memory containing multiple memory cells, each capable of being in any of the states from the first state to the Mth state (where M is 2 to the power of L (where L is a natural number greater than or equal to 2)), A memory controller that controls the non-volatile memory, A computing device comprising, The aforementioned memory controller The first state is defined as the state in which a first value is stored, and any state other than the first state is defined as the state in which a second value is stored, and the memory cell is initialized to the first state. In response to a request to write an L-digit value consisting only of the first values ​​to the memory cell, the current state of the memory cell is maintained. In response to a request to write an L-digit value consisting of a combination of the first value and the second value, or an L-digit value consisting of a combination of only the second value, to the memory cell, the memory cell is transitioned to one of the states from the second state to the M state, depending on the L-digit value. In response to a request to read a value stored in the memory cell, if the memory cell is in the first state, the first value or the second value obtained by reversing the first value between the first and second values ​​is obtained as the value stored in the memory cell; if the memory cell is in a state other than the first state, the second value or the first value obtained by reversing the second value between the first and second values ​​is obtained as the value stored in the memory cell. The arithmetic unit can perform logical operations including L×N input AND operations, L×N input NAND operations, L×N input OR operations, or N input NOR operations by writing the L-digit value to the memory cell N times (where N is a natural number greater than or equal to 1) and then reading the value stored in the memory cell. Computing device. [Explanation of symbols]

[0125] 1...Arithmetic unit, 10...Memory controller, 11...ROM area read circuit, 12...Instruction decoder, 13...Interface circuit, 14...Arithmetic area read circuit, 15...Arithmetic area write circuit, 16...Erase circuit, 20...Flash memory, 21...ROM area, 22...Arithmetic area, 30...Program counter.

Claims

1. A non-volatile memory comprising multiple memory cells, each of which can be in either the first or second state, A memory controller that controls the non-volatile memory, A computing device comprising, The aforementioned memory controller The first state is defined as the state in which a first value is stored, and the second state is defined as the state in which a second value is stored, and the memory cell is initialized to the first state. In response to a request to write the first value to the memory cell, the current state of the memory cell is maintained. In response to a request to write the second value to the memory cell, the memory cell is transitioned to the second state. In response to a request to read a value stored in the memory cell, the first value or the second value stored in the memory cell, or the second value or the first value obtained by reversing the first value or the second value stored in the memory cell, is acquired as the value stored in the memory cell. The arithmetic unit can perform logical operations including N-input AND operations, N-input NAND operations, N-input OR operations, or N-input NOR operations by writing the first or second value to the memory cell N times (where N is a natural number of 2 or more), and then reading the value stored in the memory cell. Computing device.

2. A computer can be configured by allocating four areas within the non-volatile memory area: (1) a first area where a program for performing the logical operations is stored, (2) a second area used for the logical operations, (3) a third area used as a working area for the program, and (4) a fourth area where information used by the program is stored. The computing device according to claim 1.

3. A program running within the memory controller reverses the first value or the second value read from the memory cell between the first value and the second value. The computing device according to claim 1.

4. A NOT gate is provided between the memory controller and the non-volatile memory to reverse the first value or the second value output from the non-volatile memory between the first value and the second value. The computing device according to claim 1.

5. The non-volatile memory reverses the correspondence between the first state and the second state and the first value and the second value. The computing device according to claim 1.

6. Each of the aforementioned plurality of memory cells is further capable of being in a state other than the first or second state. The memory controller defines any state other than the first state as a state in which the second value is stored. The computing device according to claim 1.

7. The aforementioned memory controller A first mode for controlling the non-volatile memory to perform the aforementioned logical operations, and a second mode for controlling the non-volatile memory to function as storage for holding data, are switchable. The computing device according to claim 1.

8. The aforementioned non-volatile memory has multiple memory dies, each of which can operate independently. The memory controller uses the multiple memory dies to execute in parallel multiple N-input AND operations, N-input NAND operations, N-input OR operations, or N-input NOR operations included in the logical operations. The computing device according to claim 1.

9. The aforementioned non-volatile memory has multiple memory dies, each of which can operate independently. The memory controller initializes the memory cells to the first state in a cyclical manner, one by one, from among the plurality of memory dies. The computing device according to claim 1.

10. The aforementioned non-volatile memory has multiple memory dies, each of which can operate independently. The memory controller performs fault diagnosis of the non-volatile memory one by one from among the plurality of memory dies in a cyclical manner. The computing device according to claim 1.

11. The memory controller performs the N-input AND operation, N-input NAND operation, N-input OR operation, or N-input NOR operation included in the logical operation multiple times for each operation and takes a majority vote. The computing device according to claim 1.

12. A memory controller for controlling a non-volatile memory comprising a plurality of memory cells, each of which can be in either a first state or a second state, The first state is defined as the state in which a first value is stored, and the second state is defined as the state in which a second value is stored, and the memory cell is initialized to the first state. In response to a request to write the first value to the memory cell, the current state of the memory cell is maintained. In response to a request to write the second value to the memory cell, the memory cell is transitioned to the second state. In response to a request to read a value stored in the memory cell, the first value or the second value stored in the memory cell, or the second value or the first value obtained by reversing the first value or the second value stored in the memory cell, is obtained as the value stored in the memory cell. After making N requests (where N is a natural number greater than or equal to 2) to write the first or second value to the memory cell, the value stored in the memory cell is read out, thereby enabling the execution of logical operations including N-input AND operations, N-input NAND operations, N-input OR operations, or N-input NOR operations. Memory controller.

13. A calculation method for an arithmetic device comprising: a non-volatile memory including a plurality of memory cells, each of which can be in either a first state or a second state; and a memory controller for controlling the non-volatile memory; The aforementioned memory controller The first state is defined as the state in which a first value is stored, and the second state is defined as the state in which a second value is stored, and the memory cell is initialized to the first state. When a request is received to write the first value to the memory cell, the current state of the memory cell is maintained and the processing in response to the request is terminated. When a request is received to write the second value to the memory cell, the memory cell is moved to the second state and the processing in response to the request is terminated. In response to a request to read a value stored in the memory cell, the first value or the second value stored in the memory cell, or the second value or the first value obtained by reversing the first value or the second value stored in the memory cell, is obtained as the value stored in the memory cell. After making N requests (where N is a natural number greater than or equal to 2) to write the first or second value to the memory cell, the value stored in the memory cell is read out, thereby enabling the execution of logical operations including N-input AND operations, N-input NAND operations, N-input OR operations, or N-input NOR operations. Calculation method.

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