Power converter control device using pulse pattern recognition

Abstract

A power converter control device using commands based on pulse pattern recognition is described. [Solution] The control system for the power converter includes a first switching circuit including a first control device and a second switching circuit including a second control device. The second control device receives the transmission signal U TX It is configured to generate a pulse pattern in the transmitted signal U TX The pulse pattern in corresponds to a predetermined command. The first control unit receives the signal U RX The first control device is configured to receive the pulse pattern in U. RX This involves comparing the pulse pattern in the signal U with the expected pattern, and the received signal U RX The system is configured to assert a predetermined command when the pulse pattern corresponds to a pre-defined pattern.

Description

[Technical Field] 【0001】 Cross-reference of related applications

[0001] This application is a continuation-in-part application of International Patent Application PCT / US / 2024 / 058266, filed on 3 December 2024, which is incorporated herein by reference in its entirety. 【0002】

[0002] This disclosure generally relates to power converters, and more particularly to control devices for power converters. [Background technology] 【0003】

[0003] Electronic devices use power to operate. Switching power converters, also called switching power converters, are commonly used to power many modern electronic devices due to their high efficiency, small size, and light weight. In a switching power converter, a high-voltage alternating current (AC) or direct current (DC) input is converted to provide an output through an energy transfer element. The output is typically a well-regulated direct current (DC) voltage or DC current of a power source that may be included in the power conversion system. Switching power conversion systems typically provide output regulation by detecting one or more signals representing one or more output quantities and controlling the output in a closed loop. During operation, switches are used to provide the desired output by changing the duty cycle (typically the ratio of the on-time of the switch to the total switching period), changing the switching frequency, or changing the number of pulses per unit time of the switch in a switching power converter. 【0004】

[0004] Power conversion systems generally include one or more control devices that detect the output of a power supply and control the operation of one or more switches to adjust the output. Communication between control device circuits is usually achieved by transmitting signals across an isolation barrier through magnetic coupling, dielectric coupling, or optical coupling. The isolation barrier provides separation between circuits that electrically reference different potentials, such as a circuit referenced to an input return path and a circuit referenced to an output return path. In other words, a DC voltage source located between any node of an input circuit and any node of an output circuit does not conduct current. When a power supply operates in an environment with considerable electrical noise, for example, in electric vehicles or near industrial equipment, the noise can disrupt the communication signals between control circuits to such an extent that the power supply no longer operates as intended. Communication signals between control circuits in applications that do not require an isolation barrier are further susceptible to disturbances by noise that can interfere with the operation of the power supply. Therefore, systems and methods for operating power converters in noisy environments are still needed. [Overview of the Initiative] 【0005】

[0005] This summary is provided in a simplified form to present the options of concepts that will be described in more detail below in embodiments for carrying out the invention. This summary is not intended to identify any important features of the subject matter described in the claims, nor is it intended to be used to help to define the scope of the subject matter described in the claims. 【0006】

[0006] In some embodiments of the power supply, the power control device includes two control circuits, such as a lower control device and an upper control device, or a first control device and a second control device, depending on the different embodiments of the power supply. An embodiment of the technology of the present invention relates to removing a communication signal that is disturbed by noise between two control devices of the power control device. For example, upper / first control device (U RX The signal received by ) has a loss that can reduce the amplitude of the signal, and the signal U RXDue to the addition of electrical noise (also referred to as "signal noise" or simply "noise") to, the lower / second control device (U TX ) may be different from the signal initially transmitted by it. The presence of noise in the communication signal can result in errors in the operation of the control device. For example, the noise may trigger such a charging cycle when a charging cycle is not required, or may start a charging cycle when a charging cycle is not permitted, such as when switch S2 is closed. Improper operation of the switch can affect the regulation of the output or damage components in the power supply. 【0007】 【0007】 In some embodiments, the power control device is configured to reject those communication signals disrupted by noise. For example, the U TX signal from the lower / second control device may include a pattern of timing-controlled pulses that have been passed through and filtered by the pattern filter of the upper control device. Thus, when the U TX signal contains an acceptable amount of noise, the timing of the pulses in the pattern is recognized as a valid pattern by the pattern filter of the upper / first control device, and the power control device continues its normal operation by transmitting a charge signal. However, when the U TX signal contains an unacceptably high amount of noise, the timing of the pulses in the pattern is not recognized as a valid pattern by the pattern filter, and the power control device stops its operation by transmitting an inhibit signal over a predetermined blanking period, and a waiting state is started to wait for the next set of U TX signals. Generally, the pattern of timing-controlled U TX pulses can be selected to reduce the likelihood of accidentally coinciding with the periodicity of common radio communication frequencies that can be predicted to come from an external source, in order to avoid misdetecting noise in the system as being correct. 【0008】 【0008】 In some embodiments, U RXMultiple pulse patterns of a signal can be received by one or more timers of the first control device. Such patterns may overlap in time, thus enabling higher frequencies of commands issued by the pattern filters. In different embodiments, such multiple patterns may be received by a single pattern filter, or each of the overlapping patterns may be received by one of the multiple pattern filters. RX Different pulse patterns of the signal may correspond to different commands asserted by the pattern filter. In different embodiments, the pattern filter may receive a window signal from a timer, or it may generate a window signal based on a time offset received from a timer. 【0009】

[0009] Non-limiting and non-exclusive embodiments of the present invention will be described with reference to the following figures, and similar reference numerals will indicate the same parts throughout the various drawings unless otherwise specified. Corresponding reference numerals will indicate corresponding components across multiple drawings. [Brief explanation of the drawing] 【0010】 [Figure 1A]

[0010] Figure 1A is a schematic diagram of a power supply including a control device according to an embodiment of the present technology. [Figure 1B] 【0011】 Figure 1B is a schematic diagram of a power supply including a control device according to an embodiment of this technology. [Figure 2A] 【0012】 Figure 2A is a functional block diagram of the upper and lower control devices shown in Figure 1A. [Figure 2B] 【0013】 Figure 2B is a functional block diagram of the first control device and the second control device shown in Figure 1B. [Figure 3] 【0014】Figure 3 is a timing diagram for the transmitted signal (UTX), received signal (URX), and window signal (UW) when noise is absent, according to an embodiment of this technology. [Figure 4] 【0015】 Figures 4 to 8 show the timing diagrams of the window signal UW and the received signal URX in an example where noise is present according to an embodiment of this technology. [Figure 5]

[0015] Figures 4 to 8 are timing diagrams of the window signal UW and the received signal URX in an example where noise is present according to an embodiment of the present technology. [Figure 6]

[0015] Figures 4 to 8 are timing diagrams of the window signal UW and the received signal URX in an example where noise is present according to an embodiment of the present technology. [Figure 7]

[0015] Figures 4 to 8 are timing diagrams of the window signal UW and the received signal URX in an example where noise is present according to an embodiment of the present technology. [Figure 8]

[0015] Figures 4 to 8 are timing diagrams of the window signal UW and the received signal URX in an example where noise is present according to an embodiment of the present technology. [Figure 9] 【0016】 Figure 9 is a timing diagram showing an example of a block signal UINH, a charge signal UCH, and a receive signal URX for valid and invalid requests to initiate a charge cycle according to an embodiment of this technology. [Figure 10] 【0017】 Figure 10 is a flowchart illustrating the operation of the upper control device or the first control device according to an embodiment of this technology. [Figure 11] 【0018】 Figure 11 is a schematic diagram of an exemplary power supply including a power control device configured to reject noise according to an embodiment of the present technology. [Figure 12A] 【0019】 Figures 12A and 12B are timing diagrams of the window signal UW and the received signal URX when noise is absent, according to an embodiment of this technology. [Figure 12B]

[0019] Figures 12A and 12B are timing diagrams of the window signal UW and the received signal URX when there is no noise according to an embodiment of the present technology. [Figure 13] 【0020】 Figure 13 is a graph showing the noise immunity of the system as a function of periods TD1 and TD2, and as a function of detection of undesirable pulses, according to an embodiment of this technology. [Figure 14A] 【0021】 Figure 14A is a functional block diagram of the upper control device or the first control device according to an embodiment of the present technology. [Figure 14B] 【0022】 Figure 14B shows the timing diagrams for the window signal and threshold signal according to an embodiment of this technology. [Figure 15A] 【0023】 Figure 15A is a schematic diagram showing an exemplary timer and pattern filter according to an embodiment of the present technology. [Figure 15B] 【0024】 Figures 15B and 15C are timing diagrams showing exemplary waveforms for different signals according to embodiments of this technology. [Figure 15C]

[0024] Figures 15B and 15C are timing diagrams showing exemplary waveforms for different signals according to embodiments of the present technology. [Figure 16A] 【0025】 Figures 16A and 16B are functional block diagrams of the upper control device or the first control device according to an embodiment of the present technology. [Figure 16B]

[0025] Figures 16A and 16B are functional block diagrams of the upper control device or the first control device according to an embodiment of the present technology. [Figure 17A] 【0026】 Figures 17A and 17B show timing diagrams for an embodiment of a control device that generates multiple commands according to an embodiment of this technology. [Figure 17B]

[0026] Figures 17A and 17B show timing diagrams for an embodiment of a control device that generates multiple commands according to an embodiment of the present technology. [Figure 18] 【0027】 Figure 18 is a flowchart illustrating the operation of the upper control unit or the first control unit that generates multiple commands according to an embodiment of this technology. [Figure 19] 【0028】 Figure 19 shows a power converter according to an embodiment of the present disclosure. [Modes for carrying out the invention]

[0011] 【0029】 In some embodiments of a power supply, the power control unit includes two control circuits. Communication between the two control circuits is typically achieved by transmitting signals across an isolation barrier through magnetic coupling, dielectric coupling, or optical coupling. When the power supply operates in an environment with considerable electrical noise, for example, in electric vehicles or near industrial equipment, the noise can disrupt the communication signals between the control circuits to such an extent that the power supply no longer operates as intended.

[0012] 【0030】 In some embodiments, U from the lower / second control unit TX The signal includes a pattern of timing-controlled pulses filtered by a pattern filter in the upper / first control unit. The timing of the pulses in the pattern may be selected to reduce the likelihood of matching the periodicity of a typical radio communication frequency expected to come from an external source.

[0013] 【0031】 During operation, the pattern filter receives the signal U RX to a valid U TXThe signal is compared to a timing window that matches a known pattern. If the pattern filter identifies the received signal as valid, the charge signal may be asserted so that the driver circuit initiates a charge cycle. A charge cycle in a power supply can represent any operation that allows energy to be stored in electrical components, such as an inductor or capacitor. In some embodiments, for example, in other power converter topologies, a valid received signal may assert a different command, which is a prescribed operation of the power supply and is not necessarily a charge command. For example, to control the operation of a half-bridge power converter, the asserted signal may be a rectifier command. Generally, such charge commands, rectifier commands, and similar commands may be called the first command that initiates a charge cycle of the power supply. If the pattern filter rejects the received signal as invalid (i.e., the received pattern does not correspond to an expected pattern), a block signal may block the processing of the received signal for a predetermined blanking period. The blanking period is typically a valid U TX The blanking period can be significantly longer than the duration of the signal (e.g., twice as long, several times longer, or an order of magnitude larger (ten times)), and may be chosen to be long enough to allow the expected noise event to subside, but short enough to allow the output capacitor to maintain its output voltage within the desired range in the absence of a new charging cycle. Generally, such an INHIBIT command or similar command may be called a second command that functions to delay the start of a power supply charging cycle over the duration of the blanking period.

[0014] 【0032】Figure 1A is a schematic diagram of a power supply 10 including a control device 100 according to an embodiment of the present technology. Figure 1A shows exemplary elements of a power supply 10 configured to reject noise in a signal transmitted from a lower control device 114 to an upper control device 112. The circuit topology of the power supply shown is referred to in the art as a two-switch buck converter and is also described as a synchronous buck converter. The upper switching circuit 120 and the lower switching circuit 140 shown are coupled to an input DC voltage source V IN In some embodiments, the switch S1 in the upper switching circuit 120 is coupled to the positive terminal of the input voltage source, and the switch S2 in the lower switching circuit 140 is coupled to the negative terminal of the input voltage source. 【0015】 【0033】 The switch S1 in the upper switching circuit and the switch S2 in the lower switching circuit can be controlled by circuits in the upper control device 112 and circuits in the lower control device 114, respectively, to adjust the output voltage V O across the load 150. In the embodiment shown in FIG. 1, the output to be controlled is the voltage V O However, those skilled in the art will understand that in other embodiments, the output to be controlled can be the current to the load 150, or a combination of voltage and current at the load. 【0016】 【0034】 During operation, switches S1 and S2 close and open at appropriate times to allow the output inductor L O to conduct current from the input voltage source V IN A closed (on-position) switch can conduct current, while an open (off-position) switch does not conduct current. The currents I S1 and I S2 through each of the switches S1 and S2 pulse-operate as illustrated by the switch drive waveforms UD and LD in the figure. The upper graph showing the current I S1 through switch S1 indicates that it reaches a maximum value I LIMIT and the current I through switch S1S1 (Dashed line) and the current I passing through switch S2 S2 The following graph showing both (solid line) has a maximum value I for both currents LIMIT has. 【0017】 【0035】 Inductor L O The current I to O is the current I S1 and I S2 The sum of. During operation, the current from the output inductor L O Can be selected to be large enough to filter the pulse operating current to charge the output capacitor C O Thus, the voltage V O Is maintained at a substantially constant regulated value over the period T defining the charging cycle S 【0018】 【0036】 The upper control device 112 receives a signal IS representing the current I passing through switch S1 at the current detection terminal. At the start of the charging cycle, switch S2 is open, and the upper control device 112 asserts (enables) the upper drive signal to close switch S1. When switch S1 is closed, the current I increases until the upper control device detects that I has reached a value I that is predefined and can be set in advance by the circuit of the upper control device 112 according to the control algorithm. Those skilled in the art will understand how to set a predetermined threshold value to function as a current limit value in the control device. When the current I reaches the I S1 Value, the upper control device 112 deasserts (disables) the upper drive signal and opens switch S1 (i.e., sets switch S1 to the off position). LIMIT To S1 When reached, the upper control device S1 Increases. S1 Is LIMIT When the value is reached, the upper control device 112 deasserts the upper drive signal (invalidates) and opens switch S1 (i.e., sets switch S1 to the off position). 【0019】 【0037】 Next, when switch S1 is opened in response to the upper drive signal, the lower control device 114 asserts the lower drive signal to close switch S2 (i.e., sets switch S2 to the on position), and S2 is the current I S2 ​The diode D2 coupled across switch S2 allows current I to be conducted before switch S2 closes. S2 It provides a path for that. Therefore, in the actual circuit, closing switch S2 means I S2 The voltage in the path is reduced to improve the efficiency of the power supply. The control device 114 monitors the voltage VS applied to switch S2 at the voltage detection terminal and checks when the current I S2 The system detects when the voltage drops to zero, and as a result, switch S2 may be opened (i.e., set to off) in preparation for the next charging cycle. How to set a predetermined threshold to function as a voltage limit in the control unit will be understood by those skilled in the art.

[0020] 【0038】 In the example shown in Figure 1A, the lower control device 114 further detects the output voltage V at its output detection terminal. O The signal OS is received. During operation, the lower control device 114 receives the received signal U RX The communication signal U received by the control device 112 is used as the above communication signal U TX The transmission signal U from the lower control device 114 is transmitted. TX The purpose is to configure the upper control unit 112 to start the next charging cycle by closing switch S1.

[0021] 【0039】 Received signal U RX The reason for adding noise to the communication signal is that the transmitted signal U TX This can differ from the above. For example, the presence of noise in the communication signal may cause the upper control unit 112 to start a charging cycle when it is not needed, or to start a charging cycle when it is not permitted, for example, when switch S2 is closed. Improper operation of the switch may result in a lack of output regulation or damage to components in the power supply. Therefore, it is desirable to configure a control unit that rejects communication signals disturbed by noise.

[0022] 【0040】In one example, switches S1 and S2 may be transistors such as metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), insulated-gate bipolar transistors (IGBTs), gallium nitride (GaN)-based transistors, or silicon carbide (SiC)-based transistors. The upper control unit 112 and the lower control unit 114 may be included in an integrated circuit manufactured as either a hybrid integrated circuit or a monolithic integrated circuit. In one example, the upper control unit 112 is included in a first integrated circuit die, and the lower control unit 114 is included in a second integrated circuit die, both located within the same integrated circuit package. Switches S1 and S2 may be included in a monolithic or hybrid structure in an integrated circuit package further including the upper control unit 112 and the lower control unit 114. In one example, switch S1 is located in a first integrated circuit die further including the upper control unit 112, and the lower control unit 114 is included in a second integrated circuit die. Furthermore, it should be understood that the upper control unit 112, the lower control unit 114, and both switches S1 and S2 do not need to be included in a single package, but may be implemented as separate packages or as a combined / separate package combination.

[0023] 【0041】 Figure 1B is a schematic diagram of a power supply 20 including a control device 200 according to an embodiment of the present technology. In the example shown, the power supply 20 is shown as including a flyback topology. In the case of a flyback power converter, a power switch S1 is switched on and off to control the amount of energy transferred to the output of the power supply 20. When the power switch S1 is switched on, current is conducted through the input winding 202 and energy is stored by the energy transfer element T1. When the power switch S1 is switched off, current is conducted through the output winding 204 and energy is stored in the output capacitor C O It is stored there.

[0024] 【0042】Furthermore, the input 200 of the power converter is galvanically isolated from the output 200 of the power converter, and as a result, the input return path 206 is galvanically isolated from the output return path 216. Since the input and output of the power converter 200 are galvanically isolated, there are no DC (DC) paths that span the isolation barrier of the energy transfer element T1 or between the input winding 202 and the output winding 204. It is understood that other known topologies and configurations of power converters, including configurations that do not require galvanic isolation, may further benefit from the teachings of this disclosure.

[0025] 【0043】 Power supply 20 has an unadjusted input voltage V IN It provides output power to a load (LOAD) 150. In one example, the input voltage V IN This is the rectified and filtered AC line voltage. In another example, the input voltage V IN This is the DC input voltage. Input voltage V IN This is coupled to an energy transfer element T1. In the example in Figure 1B, the energy transfer element T1 is a coupled inductor. The energy transfer element T1 is shown to include two windings: an input winding 202 (also called the primary winding) and an output winding 204 (also called the secondary winding). However, in different embodiments, the energy transfer element T1 may include three or more windings. The input winding 202 of the energy transfer element is further coupled to a power switch S1, and the power switch S1 is further coupled to an input return path 206. A clamp circuit 208 is coupled across the input winding 202. The clamp circuit 208 limits the maximum voltage in the power switch S1.

[0026] 【0044】 Figure 1B shows the first switching circuit 220 and the second switching circuit 240. The power supply 20 consists of a clamp circuit 208, an energy transfer element T1, an input winding 202 of the energy transfer element T1, an output winding 204 of the energy transfer element T1, a power switch S1, an input return path 206, an output switch S2 (also called an output switch / rectifier combination DO), and an output capacitor C. O, an output return path 216, and an output detection circuit 210 are included. The control device 200 includes a first control device 212 and a second control device 214. The first control device 212 may also be called a primary control device, while the second control device 214 may also be called a secondary control device. A communication link U between the second control device 214 and the first control device 212 TX / U RX However, this is further shown in Figure 1B. In the context of this application, the first control device 212 and the second control device 214 may be collectively referred to as the power control device 200. Input voltage V IN Switch current I SW Output voltage V O , output current I O , output amount U O The feedback signal FB, primary drive signal DR, current detection signal ISNS, and voltage detection signal VSNS are further shown in Figure 1B.

[0027] 【0045】 In one example, the power switch S1 may be a transistor such as a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated-gate bipolar transistor (IGBT), a gallium nitride (GaN)-based transistor, or a silicon carbide (SiC)-based transistor. In another example, the power switch may be a cascode switch comprising a normally-on first switch and a normally-off second switch coupled together in a cascode configuration. The first switch may generally be a GaN or SiC-based transistor, while the second switch may be a MOSFET, BJT, or IGBT.

[0028] 【0046】 The output winding 204 is coupled to a second switch S2 (also called the output switch / rectifier DO). The second switch S2 is exemplified as a transistor containing an integrated diode used as a synchronous rectifier. However, the second switch may also be exemplified as a separate diode and a separate transistor. Output capacitor C OThis is shown as coupled to the second switch S2 and the output return path 216. Power supply 20 has an output voltage U O The circuit further includes a circuit to adjust the output quantity U O For example, the output voltage V O , output current I O , or a combination of the two. The output detection circuit 210 detects the output amount U O It is configured to detect the output. The output detection circuit 210 provides a feedback signal FB representing the power supply output to the second control device 214.

[0029] 【0047】 The second control device 214 is configured to output a signal SR that controls the on and off switching of the second switch S2. Furthermore, the second control device 214 transmits a signal U to the first control device 212. TX It is configured to transmit. However, similar to the noise contamination shown in Figure 1A above, the received signal U RX (i.e., the signal received by the first control device 212) is affected by the addition of noise 125 to the communication signal, resulting in the transmission signal U TX This can differ from the above. For example, the presence of noise in the communication signal may cause the first control device 212 to initiate a charging cycle when it is not needed or when it is not permitted. Improper operation of the switch may result in a lack of output regulation or damage to components in the power supply. Therefore, it is desirable to configure a control device that rejects communication signals disturbed by noise.

[0030] 【0048】The first control device 212 and the second control device 214 may be included in an integrated circuit manufactured as a hybrid integrated circuit or a monolithic integrated circuit. In one example, the first control device 212 is included in a first integrated circuit die, and the second control device 214 is included in a second integrated circuit die, both located within the same integrated circuit package. The power switch S1 may be included in a monolithic or hybrid structure in an integrated circuit package further including the first control device 212 and the second control device 214. In one example, the power switch S1 is located in a first integrated circuit die further including the first control device 212, and the second control device 214 is included in the second integrated circuit die. In another example, the power switch S1 is located in a first integrated circuit die, the first control device 212 is included in a second integrated circuit die, and the second control device 214 is included in a third integrated circuit die. Furthermore, it should be understood that the first control device 212, the second control device 214, and the power switch S1 do not necessarily need to be contained in a single package, but can be realized in separate packages or in a combined / separate package combination. The power switch S1 may be a cascode switch containing a first switch and a second switch. The first switch may be located on the same integrated circuit die as the second switch. Alternatively, the first and second switches may be located on different integrated circuit dies. The first and second switches may be contained in a single package, or they may be realized in separate packages.

[0031] 【0049】 The first control device 212 is configured to control the on and off switching of the power switch S1. The first control device 212 controls the switch current I conducted by the power switch S1. SW It is coupled to receive a current detection signal ISNS that represents the switch current I of the power switch S1. In one example, the current detection signal ISNS represents the switch current I of the power switch S1. SW The current detection signal ISNS can be a voltage signal or a current signal. The first control device 212 controls the input voltage V of the power supply. INIt is configured to receive a voltage detection signal VSNS that represents [a certain value]. The input voltage detection signal VSNS can be a voltage signal or a current signal.

[0032] 【0050】 The first control device 212 outputs a first drive signal DR to the power switch S1 to control various switching parameters of the power switch S1, thereby controlling the transfer of energy from the input to the output of the power converter 200 through the energy transfer element T1. An example of such a parameter is the switching frequency f SW (Alternatively, switching period T) SW ), including duty cycle, on period and off period, or including changing the number of pulses per unit time of the power switch S1.

[0033] 【0051】 Figures 2A and 2B are functional block diagrams of the upper control unit 112 and lower control unit 114 shown in Figure 1A, and the first control unit and second control unit shown in Figure 1B, respectively. Furthermore, embodiments shown in Figures 3 to 10 are presented in the context of both the architecture of the lower control unit and the architecture of the upper control unit (Figures 1A and 2A), and the architecture of the first control unit and the architecture of the second control unit (Figures 1B and 2B).

[0034] 【0052】 Referring to Figure 2A, each control device 112, 114 may include separate clock circuits 308, 408 that provide a reference for synchronization and event timing. Each control device includes driver circuits 302, 402 that open and close switches S1 and S2, respectively, in response to internal and / or external signals.

[0035] 【0053】In some embodiments, the lower control unit 114 may include a comparator and logic circuit 404 that receives an output detection signal OS and timing signals from the clock circuit 408 to determine when the driver circuit 402 asserts and deasserts the lower drive signal LD ​​to close and open the switch S2. The transmitter circuit 410 may interpret the signals from the comparator and logic circuit 404 to initiate communication with the upper control unit 112, for example, and thus initiate a charging cycle. The transmitter circuit 410 may also initiate a U for communication with the upper control unit 112. TX It can generate a signal. However, in some situations, the transmitted U TX The signal is U TX The signal U is input to the receiver circuit in the upper control unit. RX It can be disturbed by noise before it appears as such. Noise contamination is U TX It receives the signal and noise 125 as input, U TX A combination of signal and noise (for example, U TX U (the sum of noise and U) RX This is symbolically represented by the adder 130 that outputs a signal.

[0036] 【0054】 In some embodiments, U from the lower control unit 114 TX The signal may be a pattern of timing-controlled pulses that will later be filtered by the pattern filter 304 of the upper control unit 112. TX The pattern can be configured to differ from the periodic characteristics of the expected noise source, thus reducing the likelihood that the noise will be interpreted as a valid signal. For example, the timing of pulses in the pattern can be chosen to reduce the likelihood of matching the periodicity of a common radio communication frequency that might be expected to come from an external source.

[0037] 【0055】 During operation, the pattern filter 304 receives the signal U RX to a valid U TXCompare it with a timing window that matches a known pattern of the signal. If the pattern filter identifies that the received signal is valid, a charging signal for the driver circuit 302 can be asserted to start the next charging cycle through the switch S1. On the other hand, when the pattern filter 304 rejects the received U RX signal as invalid, the pattern filter 304 can transmit a blocking signal to block the processing of the received U RX signal over a predetermined blanking period (a period during which the operation of the receiver 310 is blocked). The blanking period is typically longer than the duration of a valid U TX signal, and long enough for the predicted noise event to end, and short enough for the output capacitor C O to maintain the output within the desired range in the absence of a charging cycle. 【0038】 【0056】 FIG. 2B is a functional block diagram of the first control device 212 and the second control device 214 shown in FIG. 1B. For the purpose of being short and concise, the operations of the first control device 212 and the second control device 214 are not described in detail, because the operations of these components generally correspond to those of the upper control device 112 and the lower control device 114 respectively. That is, the operations of the first control device 212 and the second control device 214 depend on different inputs (e.g., output detection FB, current detection I SNS , voltage detection V SNS ), and provide different outputs (e.g., primary drive DR, secondary drive SR). Also, the communication between the first control device 212 and the second control device 214 still remains vulnerable to noise 125 in the same sense as described in relation to that of the lower control device 112 / upper control device 114. That is, the received signal U RX (i.e., the signal received by the first control device 212) can be different from the transmitted signal U TX due to the addition of noise 125 to the communication signal. Therefore, the pattern filter 304 determines whether the received signal U RX is a valid UTX Compare it with a timing window that matches a known pattern of the signal. If the pattern filter determines that the received signal is valid, a charging signal can be asserted to the driver circuit 302 to start the next charging cycle through the switch S1. On the other hand, when the pattern filter 304 rejects the received U RX signal as invalid, the pattern filter 304 blocks the processing of the received U RX signal for a predetermined blanking period during which the operation of the receiver 310 is blocked. U TX / U RX Some examples of processing the signal are described below in connection with FIGS. 3-9. 【0039】 【0057】 FIG. 3 is a timing diagram for a transmission signal U TX , a received signal U RX , and a window signal U W according to an embodiment of the present technology. The time axes of the window signal U W and the received signal U RX in the exemplary diagram of FIG. 3 are shown as being synchronized because they are derived from the same clock 308 in the upper control device circuit 112 / the first control device circuit 212. However, the time axis of the transmission signal U TX is generally not synchronized with the other two horizontal axes because the timing of the U TX signal may not be synchronized with the clock 308 in the upper control device circuit and is derived from another clock 408 of the lower control device circuit 1-14 / the second control device circuit 214. 【0040】 【0058】 FIG. 3 shows the transmission signal U T0 as a pattern of n + 1 pulses with pre-edges occurring at time points t T1 , ~, t Tn . The time point t TX is after the time point t T1 by an interval T X1 , and the time point t T0 is after the time point t T2 by an interval TX2 Bun time t T1 It is later than, and at point t Tn Interval T Xn Bun time t T2 It is later. In practical applications, n is 2 or greater (n≧2). In the example where n=2, T X1 This can be 200ns, T X2 This can be 500ns. These interval values ​​are, respectively, 5MHz(T X1 (This is 200 ns) and 2 MHz (T X1 This effectively blocks periodic noise at frequencies of 500 ns. In some embodiments, 2 MHz and 5 MHz may be assumed values ​​for electrical noise in the environment. The pulse width is typically significantly smaller than the interval between pulses. In some embodiments, the pulse width in the transmitted signal may be about 5 ns.

[0041] 【0059】 Received signal U RX is, at point t R0 t R1 ,~,t Rn The previous edge that occurs at time t F0 t F1 ,~,t Fn It is represented as a pattern of n+1 pulses with a post-edge that occur at U. In some embodiments, U TX The leading edge of the pulse is U RX Corresponds to the leading edge of the pulse. Received signal U RX The pulse width in the transmitted signal U is a result of variations and distortion due to the natural bandwidth limitations along the path from transmitter to receiver. TX The width of each pulse may not be the same as the width of each pulse in the signal.

[0042] 【0060】 In some embodiments, the receiver 310 in the upper control unit 112 / first control unit 212 is configured such that the magnitude of the received signal is a threshold U TH Only when the above conditions are met, the received signal U RX It responds to the threshold U. In the example in Figure 3, all received pulses are at the threshold U. TH To indicate something is larger.

[0043] 【0061】 Window signal U in Figure 3 W is width T W1 , T W2 ,~,T Wn This shows a pulse, and its preceding edge is at time t R0 t R1 and t R2 Received signal U RX From the preceding edge of each pulse, for each period T D1 , T D2 ,~,T Dn It can be delayed by several minutes. Generally, the window signal U W The pre-edge of the pulse at time t R(n-1) Time offset T from the front edge of the received pulse Dn It can be delayed by a few minutes. In some embodiments, the time offset T D1 , T D2 ,~,T Dn The time window U is set when it is assumed that a pulse from a valid signal will arrive. W Open (for example U W Based on the goal that the value of is higher than a specific voltage value, the transmitted signal U TH It is calculated from the expected natural variation in the timing parameters. Therefore, the time offset T D1 , T D2 ,~,T Dn It does not generally have a uniform duration.

[0044] 【0062】 In another example (not shown in Figure 3), the window signal U W The delay period for the pulse is time t F0 t F1 , and, t F2 Received signal U RX It can be measured relative to the falling edge of the pulse. In other words, the window signal U W The pre-edge of the pulse at time t F(n-1) In this case, from the falling edge of the received pulse to the period T Dn It can be delayed by several minutes.

[0045] 【0063】 Receiver 310 receives signal U RX After recognizing the first pulse in the received signal U, the pattern filter 304 processes the received signal U. RX For comparison with the subsequent pulse in the window signal U W A sequence of window pulses can be generated in the window signal U. W The pulse in this case is a valid transmit signal U TX The timing is controlled to match the expected pulse from the source.

[0046] 【0064】 Received signal U RX If the pattern filter 304 identifies the charging signal as a valid request from the lower control unit 114 / second control unit 214 to initiate a charging cycle, the charging signal is asserted to cause the driver 302 to close switch S1. On the other hand, if the pattern filter 304 receives the signal U RX If no valid request is recognized, the charge signal is not asserted, and the pattern filter 304 may instead assert a block signal to prevent any further processing of the received signal over the blanking duration. n=2, T X1 =200ns, and, T X2 In the example where = 500 ns, the blanking duration is set to 4 μs, because such a duration for the blanking period still does not affect the output voltage V O This is because it is sufficient to suppress noise interference while keeping the output voltage within the adjustment limits. Generally, the selection of the blanking period depends on the effectiveness of noise rejection on the one hand, and on the other hand, on the output voltage V O This includes engineering trade-offs based on product requirements to keep the adjustment limits in place.

[0047] 【0065】 Figure 4 shows the window signal U for an example where electrical noise is present, according to an embodiment of this technology. W and received signal U RX This is a timing diagram. In the shown case, the transmitter 410 sends a pulse train U requesting the start of the charging cycle. TX Just before sending, at time t NOISEA noise event occurs at this point. The magnitude of the noise event is the threshold U. TH Because it is larger, receiver 310 transmits the noise event as the first signal U in the pulse train. RX It was misinterpreted as, at pointt NOISE Delay period T D1 Later, window signal U W The receiver responds by initiating a pulse pattern at U. In other words, receiver 310 responds at U TH The first U of the valid pulse pattern TH It "concludes" that a pulse was received. However, the window signal U W The pulse pattern at time t R0 The first pulse from the transmitter in U TX Since it did not start from the previous edge, none of the subsequent pulses received from receiver 310 are window signals U W It does not enter the pulse. As a result, the pattern filter 304 does not have an effective U for initiating the charge cycle. RX The pattern is not recognized. Therefore, the pattern filter 304 does not issue a charge command. Alternatively, the pattern filter issues a block command. As described above, in some embodiments, the window signal U W and pulse U TX Even a slight misalignment between one of them can lead to the issuance of a block command, and the reason for this is that in many situations, U TX This is because it is preferable to reject a noisy received signal rather than risk initiating a charging cycle with a charging command when there is any doubt as to whether the pulse is sufficiently free of noise.

[0048] 【0066】 Figure 5 shows the window signal U for an example where noise is present, according to an embodiment of this technology. W and received signal U RX This is a timing diagram. NOISE The noise events shown in the threshold U TH It exceeds [value]. Therefore, receiver 310 receives the first pulse U TXBefore the window signal U is received from transmitter 410, W It begins generating pulses. However, the first actual pulse U is received from transmitter 410. RX However, the first window signal U W It occurs within. However, the subsequent pulse U received from transmitter 410 RX This is the window signal U W The pulse does not fully enter the window pulse, and therefore the pattern filter 304 does not recognize a valid request to initiate a charge cycle. As mentioned above, one mismatch may be sufficient to determine that the request to initiate a charge cycle is not valid, so the received pulse U does not occur within the duration of the corresponding window pulse. RX When the window signal U first occurs, W Analysis of the pulses within may be stopped.

[0049] 【0067】 Figure 6 shows the window signal U for an example where noise is present, according to an embodiment of this technology. W and received signal U RX This is another timing diagram. In the example shown, time t NOISE The noise event in is a series of U RX At time t of the second pulse F1 and the time t of the third pulse R2 It occurs between [time t] and [time t]. R1 and time t F1 The second received pulse that occurs between the first and second pulses is the pattern filter interval T. W1 Enter inside, at point t R2 and time t F2 The third received pulse between these two points corresponds to the pattern filter interval T. W2 It enters the window, but the recognized noise event occurs outside the pattern filter window, and window T Wn Delay period T related to Dn It was started too early, and therefore, window T Wn at point t Rn and time t FnThis does not occur during the transmission pulse period between the two. Therefore, the upper control unit 112 / first control unit 212 does not recognize a valid request to start a charging cycle.

[0050] 【0068】 As described above, in some embodiments of the technology of the present invention, the pattern filter 304 of the upper control device 112 / first control device 212 is pulse U RX Only one of them corresponds to window T W Even if outside of the pulse train U RX It is set to reject. Therefore, at point t NOISE Window pulse T of the pattern filter in W External received pulse U RX The occurrence of this may be sufficient to determine that the request to start the charging cycle is not valid, and the window signal U W The generation of subsequent pulses in this case may be stopped. Such a scenario results in the pattern filter 304 asserting a block command to the receiver 310.

[0051] 【0069】 Figure 7 shows the window signal U for an example where noise is present, according to an embodiment of this technology. W and received signal U RX This is another timing diagram. The timing diagram shown is at point t R2 and time t F2 U received between RX It shows a pulse. However, the received U RX The pulse is at threshold U TH It has a magnitude (amplitude) of less than this. Received U with such a small magnitude (amplitude) RX A pulse can be the result of noise disrupting a pulse that was sent at the correct time in the pattern, and therefore an undisturbed pulse U RX In that case, the window signal U W Interval T W2 Enter inside. However, the received distorted U RX Since the pulse is too small for receiver 310 to respond, such a pulse is treated as a missing pulse by pattern filter 304, URX The pattern is rejected as a valid request to initiate a charging cycle. Therefore, the upper control unit 112 / first control unit 212 also asserts a block signal over a predetermined blanking period, and during the predetermined blanking period, the control unit U TX Wait for the next set of signals to begin.

[0052] 【0070】 Furthermore, window signal U W Even if pulse generation continues in the window signal U W Failure of the received pulse to initiate the delay period until the next pulse results in the subsequent transmitted pulse in the pattern failing to occur within the subsequent window interval, and the control unit does not recognize a valid request to initiate the charging cycle.

[0053] 【0071】 Figure 8 shows the window signal U for an example where noise is present, according to an embodiment of this technology. W and received signal U RX This is another timing diagram. The timing diagram shown is for period T N1 t at a point in time that is several minutes apart NOISE1 t NOISE2 ,~,t NOISEn This shows periodic noise events that occur in [location]. These noise events are below threshold U TH Having a larger amplitude, therefore, receiver 310 receives the window signal U W It generates a pulse pattern. However, the window signal U W To prevent it from corresponding to subsequent noise signals, that is, a delay period T D1 , T D2 ,~,T Dn is the period T N1 The delay period T is not an integer multiple of the specified value. D1 , T D2 ,~,T Dn If the noise is dispersed, the pattern filter 304 does not recognize the periodic noise event as a valid request to start a charging cycle. Therefore, the pattern filter 304 asserts a block command.

[0054] 【0072】 Figure 9 shows the block signals U for valid and invalid requests to initiate a charging cycle according to an embodiment of this technology. INH , charging signal U CH , and received signal U RX This is a timing diagram showing an example. In the embodiment shown, the time between time point t1 and time point t2, between time point t3 and time point t4, and between time point t9 and time point t 10 A valid U received between RX The pattern is as follows: time point t2, time point t4, and time point t 10 The charging signal pulse U CH This generates the above U. RX The pattern is considered valid by the pattern filter 304, which causes the pattern filter to assert a charge command to the driver 202, initiating a pulse UD to the first cascode switch S1, which closes the first cascode switch S1. Different scenarios occur where the transmission pattern starts at time t5 and ends at time t6, and the reason for this is this U RX This is because the pattern is declared invalid at time t6. Therefore, the pattern filter 304 has a blanking period T at time t6. INH Block signal U over the duration of INH Assert signal U. INH While asserted, the pattern filter 304 has a valid U starting from time t7. RX The pattern also contains invalid U starting from time t8. RX It does not respond to patterns. The duration of the block signal is T. INH After the (blanking period), the pattern filter 304 is a new U RX Ready to receive the pattern. In the timing diagram shown, a new U RX The pattern starts at time t9, and at time t 10 It continues until this new U RX Since the pattern is observed to be valid by pattern filter 304, the pattern filter initiates a new U CHAssert the signal (charging signal CHARGE). As mentioned above, U RX The determination of the pattern's effectiveness may be completed at the first occurrence of the missing window or at the end of the entire pattern. In some embodiments, the duration T of the block signal is used. INH (Blanking period) is for individual U RX Signal duration or valid U RX This can be more than 10 times longer than the overall duration of the pattern.

[0055] 【0073】 Figure 10 is a flowchart 1000 of the operation of the upper control unit or the first control unit according to an embodiment of the present technology. Those skilled in the art will understand that in different embodiments, the method shown may be performed including further steps, or some of the steps shown in Figure 10 may be omitted. For example, in some practical scenarios, blocks 1004 and 1006 may be skipped during the normal operation of the upper control unit, and the method shown may operate within the loop described by blocks 1008-1018.

[0056] 【0074】 The method begins in block 1002. In block 1004, receiver 310 is set to idle mode, and while in idle mode, pattern filter 304 receives incoming U RX The pattern cannot be processed. In block 1006, timer 306 receives U from receiver 310. RX Initialize the pattern filter 304 to begin receiving patterns. In block 1008, if the receiver 310 receives any U RX A determination is made as to whether or not a pulse has been detected. As mentioned above, U RX Pulse amplitude is threshold U TH Only if it exceeds U RX A pulse is detected. Furthermore, as already explained, U RX The pulse pattern is the window signal U W Time offset T used to set the start time of the pulse. D1 , T D2 ,~,T DnSet it. Receiver 310 is U RX If no pulse is detected, the method is U RX Continue checking for pulses. Receiver 310 is U RX If a pulse is detected, the method proceeds to block 1010, where timer 306 is set to the corresponding U RX Pulse (window) U with an appropriate delay period for the pulse W The time offset T for positioning D1 , T D2 ,~,T Dn Generates.

[0057] 【0075】 In block 1012, the pattern filter 304 receives U RX The signal is processed, U RX The pattern is window signal U W Verify that the pulses are properly aligned. In some embodiments, U RX Each pulse in the pattern corresponds to the window signal U W If they are properly aligned within the duration of U RX The pattern is window signal U W It is thought that the pulses are properly aligned.

[0058] 【0076】 In block 1014, based on the filtering performed in block 1012, U RX A determination is made as to whether the pattern is valid or not. RX If the pattern is observed to be valid, the method proceeds to block 1018, where the charging signal is asserted by the pattern filter 304, and a new charging cycle is initiated, for example, by the driver 302 asserting the UD signal to switch S1, and thus the switch S1 is started to close. Next, the method returns to block 1008, where a new U RX Verification will be performed to determine whether or not a pulse was detected.

[0059] 【0077】 However, in block 1014 U RXIf the pattern is observed to be invalid, the method proceeds to block 1016, in which the pattern filter 304 asserts a block signal to the receiver 310 and blanking period T INH Processing is suspended for the duration of the process. Next, the method returns to block 1008, and in block 1008, a new U RX Verification will be performed to determine whether or not a pulse was detected.

[0060] 【0078】 Figure 11 is a schematic diagram of an exemplary power supply 10, including a control device 100 configured to reject noise, according to an embodiment of the present technology. Figure 11 generally corresponds to the power supply shown in Figure 1A and further shows an embodiment that includes transistors and diodes and implements switches S1, S2 and diode D2 of Figure 1A. Those skilled in the art will understand that a similar schematic diagram applies to the power supply shown in Figure 1B, but such similar schematic diagrams are not repeated in this example for brevity and conciseness.

[0061] 【0079】 Switch S1 is transistor Q UHV and Q ULV Shown as a cascode connection, Q UHV This could be a normally-on gallium nitride (GaN) high electron mobility transistor (HEMT), and Q ULV This can be a normally-off silicon (Si) metal-oxide-semiconductor field-effect transistor (MOSFET). In some embodiments, transistor Q UHV and Q LHV While a transistor Q can be a relatively high-voltage device with a dielectric breakdown voltage of several hundred volts, ULV and Q LLV This can be a relatively low-voltage device with a dielectric breakdown voltage of less than 100 volts. Transistor Q ULV and Q LLV The structure is such that when switch S2 is open, these transistors generate current I S2 Conducting in the positive direction (current I in the negative direction) S2This makes it possible to prevent conduction and effectively incorporate diode D2 into the operation of the transistor. During operation, the upper control unit 112 and the lower control unit 114 determine the voltage and current at switches S1 and S2 by, for example, detecting the current IS at switch S1 and the voltage VS at switch S2. In other embodiments, the upper control unit 112 and the lower control unit 114 may detect the voltage at switches S1 and S2, or detect the current at switches S1 and S2. It is understood that the present invention may be applied when a communication signal does not necessarily operate the switch, for example, when only confirmation of the occurrence of an event is required as information.

[0062] 【0080】 Figure 12A shows the window signal U in one embodiment of the present technology. W and received signal U RX This is a timing diagram. Similar to Figure 3, the timing diagram shown represents the received signal U when noise is absent, according to an embodiment of this technology. RX and window signal U W This is shown. In particular, Figure 12A shows that the previous edge is at point t. R0 t R1 , and t R2 It occurs at time t, and the subsequent edge is at time t F0 t F1 , and t F2 The received signal U is a pattern of three pulses that occur in the same location. RX This is shown. In some embodiments, as described above, U TX The leading edge of the pulse is U RX Corresponds to the preceding edge of the pulse. In the example shown, period T D1 is period T D2 Shorter, that is, the first two U pulses of the three pulse pattern RX The time difference between pulses is shorter than the time difference between the last two pulses.

[0063] 【0081】 During operation, the receiver receives the signal U, as already described with reference to Figures 3 and 4. RX The size of the threshold U THWhen the above conditions are met, the received signal U RX It responds to the following. The receiver output is, for the sake of brevity, the output of the received signal U RX ', processed received signal U RX It must be understood that this can be rephrased as ', or simply the output of the receiver. Received signal U RX Threshold U in TH For each larger pulse, the receiver outputs U RX Generates output pulses at '. In the example shown in Figure 12A, three pulses are at threshold U TH Larger, and therefore the output of the receiver, U RX ' is the received signal U RX It is similar to that.

[0064] 【0082】 The graph above shows the pulse width T. W1 and T W2 The window signal U is shown as containing two pulses having W This shows that the leading edge of the two pulses is at time t. R0 and time t R1 Received signal U RX From each of the preceding edges of the pulses in each period T D1 and T D2 It is being delayed by several minutes. In particular, the window signal U W The first pulse 1280 in is the received signal U RX From the pre-edge of the first pulse in period T D1 The pulse width T is delayed by several tens of milliseconds. W1 It has a window signal U. W The second pulse 1282 in the received signal U RX From the second pulse in period T D2 It is delayed by 1000, pulse width T W2 In other embodiments (not shown in Figure 12A), the preceding edges of two pulses 1280, 1282 are at time t. F0 and time t F1 Received signal U RX A predetermined period T measured from each falling edge of the pulse in the pulse.D1 and T D2 It can be delayed by a few minutes. The first pulse 1280 and the second pulse 1282 can also be called the timing window.

[0065] 【0083】 As shown, period T D1 is period T D2 Shorter. Window signal U W The pulse in the received signal U RX Received signal U for a valid sequence of pulses RX To correspond to the subsequent received pulse in period T D1 and T D2 It can be selected. For example, period T D1 While the interval is approximately 50 ns, the interval T D2 It is approximately 300 ns.

[0066] 【0084】 Figure 12B shows a window signal U in one embodiment of the present technology. W and received signal U RX This is a timing diagram. Figure 12B has many similarities to the timing diagram in Figure 12A. However, in Figure 12B, period T D1 is period T D2 Longer. For example, period T D1 While the duration is approximately 300 ns, the duration T D2 The duration is approximately 50 ns. In some practical applications, the duration T is used. D2 longer period T D1 It may be preferable to have such a configuration of the delay period, because it provides a longer period for the system noise to dissipate, for example, after the power switch S1 is opened or closed.

[0067] 【0085】 Figure 13 shows the period T according to an embodiment of this technology. D1 and T D2 This graph shows the system's noise immunity as a function of the detection of undesirable pulses. The x-axis is in nanoseconds (ns). D1 or T D2This is the duration. The y-axis represents the distance from the noise generator in millimeters (mm). In particular, the graph shows the distance from the noise generator at which a device carrying out an embodiment of the present disclosure detects an undesirable noise pulse. D1 or T D2 Observations are obtained for carefully selected values, and these selected values ​​are important for optimizing the actual system operation. For example, one goal of the technology of the present invention is to minimize the length between pulses, which in turn enables a higher operating speed of the system. On the other hand, the system must be robust in noisy environments, and longer T intervals are required so that there is sufficient time for system noise to dissipate after a particular event, such as opening or closing a power switch S1. D1 and T D2 (or at least longer T D1 By enabling this, the robustness of the system can be improved. Therefore, there is a trade-off between the duration of the delay period between pulses and the robustness of the system.

[0068] 【0086】 In the experimental data shown, the shorter duration between pulses is set to approximately 50 ns, while the longer duration between pulses can be varied from 0 ns to 500 ns. The data at 0 ns is from the received signal of two pulses U RX This corresponds to the period T set to 50 ns when viewed in conjunction with Figure 12A. D1 , and a period T that varies from 0 ns to 500 ns. D2 Related to this, for Figure 12B, the results shown are for a period T set to 50 ns. D2 , and a period T that varies from 0 ns to 500 ns. D1 Related to.

[0069] 【0087】 In particular, at 0ns, an undesirable pulse is received in the signal U RX When observed, the distance between the noise generator and the device was slightly over 12 mm. At 100 ns, an undesirable pulse was detected in the received signal URX When observed, the noise generator was approximately 8 mm from the device. At 150 ns, an undesirable pulse was detected in the received signal U RX When observed, the noise generator was located slightly more than 6 mm away from the device. At 300 ns, three devices were tested, and an undesirable pulse was detected in the received signal U RX When observed, the noise generator was approximately 4-6 mm from the device. The set of measurement results aligned vertically at 300 ns is the same T D1 or T D2 This corresponds to several iterative measurement results and therefore provides some indication of the associated measurement error. At 400 ns, an undesirable pulse is received in the signal U RX When observed, the noise generator was slightly less than 4 mm from the device. At 500 ns, an undesirable pulse was detected in the received signal U RX When observed, the noise generator was slightly less than 4 mm from the device. Overall, longer delay periods make the system more resistant to noise, and the distance of the noise generator to the system represents the intensity of the noise recorded by the system.

[0070] 【0088】 As shown, after about 300 ns, T D1 or T D2 While the benefits of longer durations are limited, the benefits were significant between 100 ns and 300 ns. Therefore, some embodiments of this disclosure set the duration of TD1 or TD2 substantially within the range of 100 ns to 300 ns.

[0071] 【0089】Figure 14A is a functional block diagram of the upper control unit or first control unit 1412 according to an embodiment of the present technology. Those skilled in the art will understand that the first control unit 1412 shown in Figure 14A is an example of the upper control unit 112 in Figure 1A or the first control unit 212 in Figure 1B. The shown control unit 1412 includes a receiver 1410, a timer 1406, a pattern filter 1404, and a driver 1402. The clock is indicated by a dashed line to indicate that this component is optional; that is, the clock outputs a clock signal CLK which can be optionally received by the timer 1406.

[0072] 【0090】 The embodiment of the control device 1412 shown in Figure 14A is similar to the upper control device 112 in Figure 2A and the first control device 212 in Figure 2B. However, one difference is that the timer 1406 uses the full window signal U WH , the first window signal U W1 , and the second window signal U W2 This is indicated as outputting multiple window signals. During operation, the receiver 1410 receives the received signal U RX The received signal U is to be received and processed. RX It is configured to output '(receiver output). In some embodiments, receiver 1410 receives the received signal U RX The size of the threshold U TH When the above conditions are met, the received signal U RX Responds to the threshold U. TH Larger received signal U RX For each pulse in the signal, the receiver 1410 processes the received signal U RX It generates an output that is a pulse in '.

[0073] 【0091】 Timer 1406 processes the received signal U RX ' to receive, and the full window signal U WH , the first window signal U W1 , and the second window signal U W2It is configured to output the following. Examples of these signals are shown below in Figure 14B. The window signal U provided by timer 1406 WH , U W1 , and U W2 This is received by pattern filter 1404, and the received signal U RX It is used to determine whether it corresponds to the expected pattern. For example, the window signal may represent a duration, during which one or more pulses receive the received signal U RX It is assumed to exist in [location].

[0074] 【0092】 Figure 14B shows the timing diagram of the window signal and threshold signal according to an embodiment of the present technology. In the embodiment shown, the entire window signal U WH is the pulse width T WHOLE It is a square pulse waveform with the full window signal U WH This represents a timing window that substantially corresponds to the entire duration of a multi-pulse command. In one example, the entire window signal U WH The threshold U TH Larger received signal U RX It transitions to a logic high value in response to the first pulse in . Subsequently, the full window signal U WH pulse width T WHOLE It maintains its logical high value over the duration of the pulse width T. WHOLE In effect, the received signal U RX This is the expected duration for receiving the expected pulse pattern in [location].

[0075] 【0093】 First window signal U W1 is the pulse width T W1 This is a square pulse waveform with the first window signal U. W1 The received signal U RX The second pulse in (i.e., t in the graph below Figure 14B) R1 and t F1This represents the expected time window for receiving pulses that occur between the first and second signals. That is, the first window signal U W1 The received signal U RX The first (first) received pulse in (i.e., t in the graph below Figure 14B) R0 and t F0 This represents the expected period for receiving the second pulse after the first pulse that occurs between the first and second pulses. As a result, the first window signal U W1 This provides a timing window encompassing the duration during which a second pulse is expected to occur. In some embodiments, the pulse width T W1 This can be between 100ns and 200ns. In one example, the pulse width T W1 This is effectively 100 ns.

[0076] 【0094】 Similarly, the second window signal U W2 Furthermore, the pulse width T W2 It may be a square pulse waveform having the second window signal U W2 This represents the expected time window, and within this expected time window, the pattern filter 1404 receives the signal U RX The third pulse in (i.e., t in the graph below Figure 14B) R2 and t F2 It is assumed that a pulse (generating between) is received. Therefore, the second window signal U W2 The received signal U RX This represents the period in which a third pulse is expected to be received after the second (second) received pulse. Alternatively, the second window signal U W2 This may be understood in reference to the first pulse, i.e., the second window signal U W2 The received signal U RX This represents the period in which a third pulse is expected to be received after the first received pulse. In other words, the second window signal U W2 This provides an approximate timing window when a third pulse is assumed to be present. Pulse width T W2This can be between 100ns and 200ns. In one example, the pulse width T W2 This is effectively 150 ns. Pulse width T W1 and T W2 It must be understood that they do not need to be the same. For example, delay period T D2 The delay period is T D1 Longer pulse width T W2 The pulse width T W1 Wider range. Delay period T D1 and T D2 is the pulse width T W1 and T W2 This can be considered when making a selection. For example, the pulse width may be chosen to account for the inaccuracy of the transmitter's assumed clock. In practice, the pulse width T W1 , T W2 The duration T between pulses D1 , T D2 They are selected to be significantly shorter. For example, the pulse width can be on the scale of nanoseconds, while the length between pulses can be on the scale of tens or hundreds of nanoseconds.

[0077] 【0095】 In some embodiments, the pattern filter 1404 processes the received signal U RX ', and window signal U WH , U W1 , and U W2 It is configured to receive and output the CHARGE charging signal.

[0078] 【0096】 Returning to Figure 14A, the pattern filter 1404 processes the received signal U RX ' to window signal U WH , U W1 , and U W2 It is configured to compare with and output the CHARGE signal. For example, the full window signal U WH Before the timing window provided by (e.g., window 1486) closes, the window signal U W1 and U W2A pulse is received within a timing window provided by (shown as windows 1482 and 1484 in Figure 14B), and the window signal U W1 and U W2 If no pulse is received outside the timing window provided by the pattern filter 1404, the pattern filter 1404 asserts the charge signal to initiate the charge cycle of the power switch S1. Full window signal U WH If no pulse is received within timing windows 1482, 1484 before the timing window 1486 provided by closes, or if the window signal U W1 and U W2 If a pulse is received outside of the timing windows 1482, 1484 provided by the pattern filter 1404, the pattern filter 1404 does not assert the charge signal. In the context of Figure 14A, the pattern filter 1404 is shown as asserting the charge signal. However, in different embodiments, the pattern filter does not assert the received signal U that has been processed as described above. RX Depending on the appropriate detection of the pulse, different control signals may be asserted.

[0079] 【0097】 In some embodiments, the driver and control circuit 1402 are configured to receive a charge signal CHARGE and to output a drive signal UD that controls the on and off switching of switch S1. When the driver receives an asserted charge signal CHARGE, the driver 1402 outputs a drive signal UD to switch switch S1 on. In one example, the driver and control circuit 1402 are further configured to receive a current sensing signal CURRENT SENSE representing the current conducted through switch S1. When the current conducted through switch S1 reaches a current limit, the driver and control circuit 1402 outputs a drive signal UD to switch switch S1 off. However, it should be understood that other control techniques may be used to regulate the output of the power converter.

[0080] 【0098】Returning to Figure 14B, the timing diagram shown in Figure 14B is the same as the timing diagram shown in Figure 12A. In Figure 12A, there is one window signal U W This includes multiple timing windows 1280, 1282. In the example shown in Figure 14B, each window signal U W1 , U W2 This includes one timing window 1482, 1484. As with the above, the received signal U RX Each of these has a front edge that is t R0 t R1 , and t R2 It occurs at the point in time when it occurs, and the post edge is t F0 t F1 , and t F2 This is shown as a pattern of three pulses that occur. In the example shown, the received signal U RX The amplitude of each pulse in is the threshold U TH Larger, and therefore, the processed received signal U output by receiver 1410 RX ' is the received signal U RX It is similar to that.

[0081] 【0099】 First window signal U W1 is the pulse width T W1 It is shown as containing one pulse 1482, the preceding edge of pulse 1482 is at time t R0 Received signal U RX From the pre-edge of the first pulse to the period T D1 It can be delayed by 10 seconds. Pulse 1482 can also be called timing window 1482. When in operation, pattern filter 1404 receives the signal U RX (and the corresponding processed received signal U RX It is configured to determine whether or not a pulse was received within the timing window 1482 generated to detect ').

[0082] 【0100】 Second window signal U W2 is the pulse width T W2It is shown as containing one pulse 1484, and the preceding edge of pulse 1484 is at time t R1 Received signal U RX From the pre-edge of the second pulse in period T D2 It can be delayed by 1 minute. However, in a different embodiment, the preceding edge of pulse 1484 is at time t R0 Received signal U RX From the pre-edge of the first pulse in period T D2 It may be delayed by a few minutes. Pulse 1484 may also be called timing window 1484. Pattern filter 1404 receives the signal U RX (and the correspondingly processed received signal U RX It is configured to determine whether or not this third pulse was received within the timing window 1484 generated to detect ').

[0083] 【0101】 Full window signal U WH is the pulse width T WHOLE It is shown as containing one pulse 1486 with a preceding edge at time t R0 It is triggered by the first pulse in the received signal URX. Pulse 1486 may also be called timing window 1486. ​​Pulse width T WHOLE The duration of the received signal U RX Selected to encompass the entire (valid) pattern. In other words, pulse width T WHOLE During that duration, the control device 1412 receives the signal U RX This is the expected duration for detecting the entire pulse (i.e., the entire pulse train). The pattern filter 1404 is configured to determine whether all expected pulses were received within the timing window 1486.

[0084] 【0102】Figure 15A is a schematic diagram showing an exemplary timer 1506 and pattern filter 1504 according to an embodiment of the present technology. The timer 1506 and pattern filter 1504 shown are examples of the timer 1406 and pattern filter 1404 shown in relation to Figure 14A, and different embodiments are possible in different embodiments. The timer 1506 is shown to include a flip-flop 1552, a pulse generator 1554, a delay 1556, a pulse generator 1558, and a delay 1560. The pattern filter 1504 is shown to include flip-flips 1562, 1564, and 1566, an OR gate 1567, an AND gate 1568, a comparator 1570, and a pulse generator 1572.

[0085] 【0103】 Figure 15A shows the processed received signal U RX (Output of receiver 1410), full window signal U WH , the first window signal U W1 , and the second window signal U W2 Further details include a first acknowledgment signal U1, a second acknowledgment signal U2, a further pulse signal UEP, a slope signal RAMP, a reference signal REF, and a reset signal RST.

[0086] 【0104】 In particular, timer 1506 processes the received signal U RX ' to receive, and the full window signal U WH , the first window signal U W1 , and the second window signal U W2 It is configured to output U.Flip-flop 1552 is shown as a D-type flip-flop, and the received signal U processed at its clock input is RX It is configured to receive a '' and a voltage VCC at its D input. In some embodiments, the voltage VCC may be a voltage for the "logic high" value of the control unit. The flip-flop 1552 is further configured to receive a reset signal RST at its reset input and a full window signal U WH Outputs.

[0087] 【0105】 During operation, when the reset signal RST is asserted, the full window signal U WH This is logically low. All window signals U WH The processed received signal U RX The flip-flop 1552 transitions to a logic high (e.g., VCC) on the first received pulse in '. In other words, the flip-flop 1552 outputs a logic high (e.g., VCC) for the full window signal UWH in response to the preceding edge in the processed received signal URX'. The flip-flop 1552 resets in response to the asserted reset signal RST.

[0088] 【0106】 Both pulse generators 1554 and 1558 are coupled to flip-flop 1552, and the entire window signal U WH The pulse generators 1554 and 1558 are triggered by the preceding edge, as shown. Pulse generator 1554 receives the full window signal U. WH In response to the front edge in, width T W1 It outputs a pulse with the full window signal U. Similarly, the pulse generator 1558 outputs a pulse with the full window signal U. WH In response to the front edge in, width T W2 It outputs a pulse with the following properties.

[0089] 【0107】 Next, delay 1556 is delay period T D1 Furthermore, it is configured to delay the pulse output by the pulse generator 1554. The output of the delay 1556 is the first window signal U W1 Therefore, the pulse generator 1554 and delay 1556 process the received signal U RX From the first pulse received in ', a delay period T D1 A first window signal U with a pulse / timing window that is delayed by 1000m W1 This generates the delay 1560, which corresponds to the delay period T. D2 The pulse generator 1558 is configured to delay the pulse output by the delay 1560, and the output of the delay 1560 is the second window signal U W2Therefore, the pulse generator 1558 and delay 1560 process the received signal U RX From the first pulse received in ', a delay period T D2 'Second window signal U with a pulse / timing window delayed by 1 / minute W2 The timing for pulse generator 1558 and delay 1560 is set to the full window T. WH Triggered by the preceding edge, the received signal U is processed in the example shown. RX It must be understood that it is triggered by the first pulse in '.

[0090] 【0108】 Pattern filter 1504 uses the full window signal U WH , the first window signal U W1 , and the second window signal U W2 It is configured to receive and output a charging signal CHARGE.

[0091] 【0109】 Flip-flops 1562, 1564, and 1566 are shown as D-type flip-flops. Flip-flop 1562 has a first window signal U at its D input. W1 The received signal U is received and processed at its clock input. RX It is shown to receive a reset signal RST at its reset input. The output of the flip-flop 1564 is a first acknowledgment signal U1. In the shown embodiment, the first acknowledgment signal U1 is logic high when asserted and logic low when not asserted. When the first acknowledgment signal U1 is asserted (e.g., logic high), the first window signal U W1 This represents the reception of a pulse within the timing window. When the reset signal RST is asserted, the flip-flip 1562 is reset and the first acknowledgment signal U1 is set to logic low. The first window signal U W1 Within the timing window provided by, the processed received signal U RXIf a pulse is received in ', the first acknowledgment signal U1 is asserted (e.g., to a logic high). W1 If no pulse is received within the timing window provided by the first acknowledgment signal U1 remains in a logic low state.

[0092] 【0110】 The flip-flop 1564 receives the second window signal U at its D input. W2 The received signal U is received and processed at its clock input. RX It is indicated that it receives ' and receives the reset signal RST at its reset input. The second acknowledgment signal U2 is logic high when asserted and logic low when not asserted. The asserted second acknowledgment signal U2 (e.g., logic high) is indicated by the pulse of the second window signal U W2 This indicates that the signal was received within the timing window. When the reset signal RST is asserted, flip-flop 1564 is reset and the second acknowledgment signal U2 is set to a logic low. The second window signal U W2 Within the timing window provided by, the processed received signal U RX When a pulse is received in ', the second acknowledgment signal U2 is set to logical high. Conversely, the second window signal U W2 If no pulse is received within the timing window provided by the second acknowledgment signal U2 remains in a logic low state.

[0093] 【0111】 OR gate 1567 is the first window signal U W1 and the second window signal U W2 The flip-flop 1566 is coupled to receive the received signal U, which has been processed at its clock input, so that it receives the output of the OR gate 1567 at its D input. RXIt is configured to receive ' and to receive a reset signal RST at its set input. A further pulse signal UEP is set to logic low when asserted and to logic high when not asserted. An asserted further pulse signal UEP (e.g., logic low) consists of one or more pulses that meet the first window signal U W1 and the second window signal U W2 This indicates that the signal was received outside the timing window provided by [the system]. When the reset signal RST is asserted, flip-flop 1566 outputs a further pulse signal UEP that is logically high.

[0094] 【0112】 Processed received signal U RX The pulse of ' is the first window signal U W1 and the second window signal U W2 If received outside the timing window provided by the first window signal U, an additional pulse signal UEP is set to logical low. W1 and the second window signal U W2 If no pulse is received outside the timing window provided by the system, the further pulse signal UEP remains logically high.

[0095] 【0113】 AND gate 1568 controls the full window signal U WH It is configured to receive a first acknowledgment signal U1, a second acknowledgment signal U2, and a further pulse signal UEP. The AND gate 1568 outputs a charge signal CHARGE. The full window signal U WH Within the timing window, for example, the entire window signal U WH The charge signal CHARGE is asserted (e.g., logical high) to switch switch S1 ON if the following occurs before the transition to a logic low value:

[0096] 【0114】 First window signal U W1 Within the timing window, the processed received signal URX The pulse in ' is received, for example, the first acknowledgment signal U1 is logically high;

[0097] 【0115】 Second window signal U W2 Within the timing window, the processed received signal U RX The pulse in ' is received, for example, the second acknowledgment signal U2 is logically high; and,

[0098] 【0116】 First window signal U W1 and the second window signal U W2 Outside the timing window, the processed received signal U RX This means that no pulse is received in ', for example, that a further pulse signal UEP is logically high;

[0099] 【0117】 Comparator 1570 and pulse generator 1572 are used to generate the reset signal RST. In particular, comparator 1570 is configured to receive a slope signal RAMP at its inverting input and a reference at its non-inverting input. The slope signal RAMP is a triangular waveform. The time it takes for the slope signal RAMP to reach the reference REF is substantially the entire window signal U WH Duration T WHOLE That is the case.

[0100] 【0118】 In the embodiment shown, the pulse generator 1572 is triggered by the previous edge and generates a pulse when the slope signal RAMP reaches or exceeds the reference REF. The pulse generated by the pulse generator 1572 is an asserted reset signal RST.

[0101] 【0119】 Figure 15B shows the processed received signal U, generated, for example, by the circuit in Figure 15A. RX ', all window signals U WH , the first window signal U W1 , second window signal U W2This timing diagram shows exemplary waveforms for the first acknowledgment signal U1, the second acknowledgment signal U2, the further pulse signal UEP, the slope signal RAMP, the reset signal RST, and the charge signal CHARGE. The timing diagram shows the waveform when no further pulses are received.

[0102] 【0120】 When timer 1506 and pattern filter 1504 are reset, all signals are logic low except for the additional pulse signal UEP. That is, the additional pulse signal UEP is logic high at the time of reset. At time t1, the processed received signal U RX The first pulse in ' becomes the clock for flip-flop 1552, and the entire window signal U WH The signal transitions to a logical high, which opens a timing window 1586. As the slope signal RAMP begins to increase from t1, all other signals remain logical low, except for another pulse signal UEP which remains logical high.

[0103] 【0121】 The length from time point t1 to time point t2 is the delay period T. D1 This represents a delay period T. D1 Furthermore, the full window signal U WH This can be referred to as starting after the previous edge in . This is because delay 1556 is the first window signal U W1 This can also be described as outputting a timing window 1582, where the timing window 1482 has a pulse width T W1 It has.

[0104] 【0122】 At time t3, the processed received signal U RX The second pulse in ' is still within the timing window 1582. Furthermore, the flip-flop 1562 receives the clock input and the first acknowledgment signal U1 transitions to a logic high value.

[0105] 【0123】 At time t4, the entire window signal U WH Delay period T after the previous edge in D2'They are separated. Therefore, delay 1560 is the second window signal U W2 The timing window 1584 is output, and the timing window 1584 has a pulse width T W2 It has.

[0106] 【0124】 At time t5, the processed received signal U RX The third pulse in ' is within the timing window 1584. The flip-flop 1564 receives the clock input and the second acknowledgment signal U2 transitions to a logic high value. Furthermore, outside the timing windows 1582 and 1584, the processed received signal U RX Since no further pulses were present, the further pulse signal UEP remains logically high.

[0107] 【0125】 In addition, while the timing window 1586 is open, the processed received signal U RX The pulse was received within timing windows 1582 and 1588. Therefore, the charge signal CHARGE transitions to a logic high value (for example, CHARGE is asserted).

[0108] 【0126】 At time t6, the slope signal RAMP reaches the reference REF, and pulse generator 1572 asserts the reset signal RST. In other words, a pulse in the reset signal RST is observed at time t6. In response to the asserted reset signal, flip-flops 1552, 1562, and 1564 are reset, while flip-flop 1566 is set. The full window signal U WH , the first window signal U W1 , second window signal U W2 The first acknowledgment signal U1 and the second acknowledgment signal U2 are logically low. The charge signal CHARGE is set to logically low, and the further pulse signal UEP remains logically high.

[0109] 【0127】 Figure 15C shows the processed received signal U from Figure 15A. RX', all window signals U WH , the first window signal U W1 , second window signal U W2 This timing diagram shows exemplary waveforms for the first acknowledgment signal U1, the second acknowledgment signal U2, a further pulse signal UEP, a slope signal URAMP, a reset signal RST, and a charge signal CHARGE. In particular, this timing diagram shows the processed received signal U RX This shows the waveform when a further pulse is received in ', and as a result prevents the CHARGE charge signal from being asserted.

[0110] 【0128】 When timer 1506 and pattern filter 1504 are reset, all signals are logic low except for an additional pulse signal UEP. The additional pulse signal UEP is logic high at the time of reset. Times t7, t8, and t9 are substantially the same as times t1, t2, and t3, respectively, as described in relation to Figure 15B.

[0111] 【0129】 At time t10, additional pulses are received that are not part of the expected multi-pulse charging command. The timing window closes at time t2, so the window signal U W1 and U W2 This is a logic low. Therefore, when the flip-flop 1566 receives the clock input while it has a logic low value, the further pulse signal UEP transitions to a logic low value.

[0112] 【0130】 At time t11, the entire window signal U WH Delay period T after the previous edge in D2 Corresponds to '. Therefore, delay 1560 corresponds to pulse width T W2 The second window signal U has W2 Outputs the timing window 1584 in this case.

[0113] 【0131】 At time t12, the processed received signal U RXThe received pulse in ' falls within the timing window 1584. The flip-flop 1564 receives the clock input, and the second acknowledgment signal U2 transitions to a logic high. However, a further pulse signal UEP is logic low, and therefore the charge command CHARGE does not transition to a logic high.

[0114] 【0132】 At time t13, the gradient signal RAMP reaches the reference REF, the pulse generator 1572 asserts the reset signal RST, and therefore U becomes available for cycle completion. WH Window 1586 is terminated. In other words, a pulse in the reset signal RST is observed at time t13. In response to the asserted reset signal, flip-flops 1552, 1562, and 1564 are reset, while flip-flop 1566 is set. All window signals U WH The first window signal UW1, the second window signal UW2, the first acknowledgment signal U1, and the second acknowledgment signal U1 are logically low. The further pulse signal UEP is logically high. As a result, the entire cycle is completed without asserting the charge command CHARGE to a logical high value.

[0115] 【0133】 Figure 16A is a functional block diagram of an upper control unit or first control unit 1612 according to an embodiment of the present technology. The upper control unit or first control unit 1612 shown in Figure 16A is similar to the upper control unit 112 shown in Figure 2A, the first control unit 212 in Figure 2B, and the control unit 1412 in Figure 14A. However, at least one difference is that the control units already shown include only one pattern filter and one timer, whereas Figure 16A shows three pattern filters 1604A, 1604B, and 1604C, and three corresponding timers 1606A, 1606B, and 1606C. Those skilled in the art will understand that in different embodiments, two or more pattern filters and corresponding timers may also be used.

[0116] 【0134】As shown in the diagram, pattern filters 1604A, 1604B, and 1604C receive their window signals U from their corresponding timers 1606A, 1606B, and 1606C. WX Receives window signal U. WX This is the signal U at different points in time. W1 , U W2 , U WH Corresponding to, and in a typical example, for different timers 1606A, 1606B, and 1606C, the window signal U W1 , U W2 , U WH However, the window signal U is different. WX It should be understood that this may be a single window signal containing multiple windows, for example, as shown in Figures 12A and 12B. Pattern filters 1604A, 1604B, and 1604C further process the received signal U from receiver 1610. RX ' is received. The operation of each pattern filter is similar to the operation of pattern filter 1404 shown in Figure 14A. In particular, the inputs to each pattern filter 1604A, 1604B, and 1604C are U WX The value (i.e., U W1 , U W2 , U WH Since it is defined as ), each pattern filter determines the output CMD1 for pattern filter 1604A, the output CMD2 for pattern filter 1604B, and the output CMD3 for pattern filter 1604C by processing the received signal U RX Determine whether the pulse train in ' is properly positioned within the window.

[0117] 【0135】Furthermore, the first pattern filter 1604A is shown as generating commands CMD1.1, CMD1.2, and / or CMD1.3. This is intended to show that even though the art of the present invention is generally described considering that the pattern filters output (or do not output) the charge signal CHARGE, different embodiments of the art of the present invention may generate other commands provided to the driver and control circuit 1602. Based on commands CMD1.1, CMD1.2, and / or CMD1.3, the driver and control circuit 1602 may generate other control inputs for controlling different functions of the power control device. In the shown embodiments, one pattern filter (1604A) provides multiple command outputs, while the other pattern filters (1604B, 1604C) provide one command output (e.g., CMD2 and CMDN). However, it will be understood by those skilled in the art that in different embodiments, each pattern filter may provide one or more commands.

[0118] 【0136】 Figure 16B is a functional block diagram of the upper control unit or the first control unit 1612 according to an embodiment of the present technology. Figure 16B shows that timers 1606A, 1606B, and 1606C control the delay period T of their corresponding pattern filters 1604A, 1604B, and 1604C. DX This is the same as Figure 16A, except that it generates the following delay period T. DX Based on this, each pattern filter uses the corresponding full window signal U WH , the first window signal U W1 , and the second window signal U W2 (All together U WX It can generate a (called) pattern filter. Alternatively, each pattern filter can generate a single combined window signal U similar to that shown in Figure 12A or Figure 12B. W It can generate a delay period T. DX (For example T D1 , T D2One embodiment of generating such a window signal based on ) is described with reference to Figure 14B, and for brevity and conciseness, the description will not be repeated in this example. During operation, the generated window signal U WX (that is, U W1 , U W2 , U WH Based on this, each pattern filter determines the output CMD1 for pattern filter 1604A, the output CMD2 for pattern filter 1604B, and the output CMD3 for pattern filter 1604C by processing the received signal U RX Determine whether the pulse train in ' is properly positioned within the window. As described above, in different embodiments, one or more pattern filters may be configured to generate multiple commands.

[0119] 【0137】 Figures 17A and 17B show timing diagrams for a control device that generates multiple commands according to an embodiment of this technology. In particular, Figures 17A and 17B show the received signal U when no noise is present. RX and window signal U W This indicates that, as a result, the pattern filter asserts a predetermined command.

[0120] 【0138】 Figure 17A shows the previous edge at point t. R0 t R1 t R2 and t R3 It occurs at time t, and the subsequent edge is at time t F0 t F1 t F2 and t F3 The received signal U is a combination pattern of four pulses that occur in that location. RX This is shown. In some embodiments, as described above, U TX The leading edge of the pulse is U RX It corresponds to the leading edge of the pulse. However, in the embodiment shown, the output U of the received signal RX The four pulses correspond to two predetermined commands, namely command 1 and command 2.

[0121] 【0139】 The graph above shows the pulse width T. W1 , T W2 , and T W3 Window signal U containing three pulses W This shows that the front edge of the three pulses is at time t. R0 t R1 , and t R2 Received signal U RX From the preceding edge of each of those pulses within, for each period T D1 , T D2 and T D3 It can be delayed by 10 seconds. In other embodiments (not shown in Figure 17A), U W The preceding edges of the three pulses are at point t. F0 t F1 , and t F2 Received signal U RX Measured from the falling edge of each pulse within, over a predetermined period T D1 , T D2 , and T D3 It can be delayed by 10 seconds. In another example, U W The preceding edges of the three pulses are at point t. R0 or t F0 Received signal U RX The first pulse in the signal may be delayed by a predetermined period from the preceding edge or falling edge. During operation, the output U of the received signal RX Each of the second, third, and fourth pulses of ' is a given pulse U, as in the embodiments described with reference to Figures 12A and 12B. W It is evaluated whether or not it occurred within the system. However, in the embodiment of Figure 17A, the output U of the received signal RX The first three pulses of ' are interpreted as a pattern for command 1, and the last three pulses (i.e., the output of the received signal U) RX The second, third, and fourth pulses of ' are interpreted as a pattern for command 2. Therefore, the output of the received signal U RXThe combination of the four pulses ' results in two commands, which, for example, pattern filter 1604A may provide to the driver and control circuit 1602. In another embodiment, the output U of the received signal RX The pulses of ' can be processed by pattern filters 1604B and 1604C, each configured to issue, for example, command 1 or command 2. In the shown embodiment, more commands can be issued in a shorter period of time than if each command were determined separately, i.e., sequentially. In the shown example, the delay period T D2 The delay period T D1 and T D3 Longer. That is, the combination of delay periods is short-long for command 1 and long-short for command 2. In one example, delay period T D1 and T D3 While the interval can be approximately 50 ns, the interval T D2 The duration is approximately 300 ns. In another embodiment, the output U of the received signal RX More than four pulses may be used, resulting in the pattern filter issuing more than two commands for such a pulse train.

[0122] 【0140】 Figure 17B shows the delay period T. D1 , T D2 , and T D3 and associated pulse U W Figure 17B is the same as Figure 17A, except that it shows a different configuration. Figure 17B shows the delay period T D2 The delay period is T D1 and T D3 This shows the shorter case. That is, the combination of delay periods is long-short for command 1 and short-long for command 2.

[0123] 【0141】Figure 18 is a flowchart 1800 of the operation of the upper control unit or the first control unit according to the embodiments shown in Figures 16A and 16B. Those skilled in the art will understand that in different embodiments, the method shown may be performed including further steps, or some of the steps shown in Figure 18 may be omitted. For example, in some practical scenarios, blocks 1804 and 1806 may be skipped in the normal operation of the upper control unit, and the method shown operates primarily within the loop described by blocks 1808-1816.

[0124] 【0142】 The method begins in block 1802. In block 1804, the receiver is set to idle mode, and in idle mode, the pattern filter receives the incoming U RX The pattern cannot be processed. In block 1806, the timer initializes the pattern filter and receives U from the receiver. RX The pattern begins to be received. In block 1808, receiver 1610 receives some U RX A determination is made as to whether or not a pulse has been detected. As mentioned above, their amplitudes are below the threshold U TH Only if U RX A pulse is detected. Furthermore, as already explained, U RX The pulse pattern is the window signal U W Time offset T used to set the start time of the pulse. D1 , T D2 ,~,T DN Set it. The receiver is U RX If no pulse is detected, the method is U RX Continue to check for pulses. Receiver 1610 is U RX If a pulse is detected, the method proceeds to block 1810, where timers 1606A, 1606B, and 1606C are controlled by the corresponding U (as shown in Figure 16B). RX A pulse (window) U with an appropriate delay period based on the pulse. W The time offset T for positioning D1 , T D2 ,~,T DNGenerate or (as shown in Figure 16A) pulse (window) U with an appropriate delay period. W It generates it directly.

[0125] 【0143】 In block 1812, each pattern filter receives U RX The signal is processed, U RX The pattern is window signal U W Verify whether the pulses are properly aligned. In some embodiments, U RX Each pulse in the pattern corresponds to the window signal U W If they are properly aligned within the duration of U RX The pattern is window signal U W It is thought that the pulses are properly aligned.

[0126] 【0144】 In block 1814, each pattern filter performs a specific U based on the filtering performed in block 1812. RX Determine whether the pattern is valid or not. RX If a pattern is observed to be valid, the method proceeds to block 1816, where commands associated with the valid pattern (e.g., charging signals) are asserted by each pattern filter. RX If the pattern is observed to be invalid, the method returns to block 1804, in which the receiver is set to idle mode, for example, during a blanking period T. INH Processing is suspended for the duration of the command. Other exemplary commands include configuring the control unit for a power converter to operate in continuous conduction mode (CCM) or discontinuous conduction mode (DCM), to enter a low-power mode, or to lower the current limit threshold for the power converter's switch current, or to enable or disable the control unit.

[0127] 【0145】Figure 19 shows a power converter 1900 using an embodiment of the present technology. A two-stage power converter 1900 is shown, including a power factor correction (PFC) stage 1904 and a subsequent DC-DC conversion stage 1908. An AC input rectifier is shown as 1902. In one example, several commands may be transmitted from a second control unit 1912 to a first control unit 1910 via a communication link 1916. One or more of these commands may then be transmitted to a PFC control unit 1906 via a communication link 1918. Non-limiting exemplary commands include requests from the second control unit 1912 to switch the first control unit 1910 on, and enable / deactivate commands to enable or disable the PFC control unit 1906.

[0128] 【0146】 Many specific details have been described so far so that the present invention may be fully understood. However, it will be apparent to those skilled in the art that not all specific details will necessarily be used to carry out the present invention. For example, well-known materials or methods are not described in detail so as not to make the present invention difficult to understand. For example, those skilled in the art will understand that the elements in the aforementioned figures are drawn in a concise and clear manner and are not necessarily drawn to a constant scale. For example, the dimensions of some elements in the figures may be exaggerated compared to others in order to make the various embodiments of the present invention easier to understand. Furthermore, common but well-understood elements that are useful or necessary in commercially suitable embodiments are often not shown in the figures so as not to make the figures of these various embodiments of the present invention difficult to read.

[0129] 【0147】In this specification, any reference to “one embodiment,” “embodiment,” “example,” or “example” means that a particular feature, structure, or characteristic described in relation to an embodiment or example is included in at least one embodiment of the present invention. Therefore, the use of expressions such as “one embodiment,” “embodiment,” “example,” or “example” in various places in this specification does not necessarily relate to the same embodiment or example. Furthermore, a particular feature, structure, or characteristic may be combined in any suitable combination and / or partial combination in one or more embodiments or examples. A particular feature, structure, or characteristic may be included in an integrated circuit, electronic circuit, combinational logic circuit, or other suitable component that provides the function described. In the context of this disclosure, terms such as “generally,” “substantially,” “essentially,” and “about” correspond to up to 5% of the stated value or term.

[0130] 【0148】 The description of the examples presented in this invention, including matters described in the abstract, is not intended to be exhaustive or to limit itself to the forms disclosed. While specific embodiments and examples of the invention are described herein for illustrative purposes only, various equivalent modifications are possible without departing from the broader spirit and scope of the invention. Indeed, it is understood that any specific and exemplary voltages, currents, frequencies, output range values, times, etc., are presented for illustrative purposes, and that other values ​​may be used in other embodiments and examples taught in this invention.

[0131] 【0149】 While the present invention is defined in the claims, it should be understood that the present invention may also be defined by the following examples.

[0132] Example 1. A power control device for a power supply, the power control device comprising: a first switching circuit comprising a first control device; and a second switching circuit comprising a second control device, wherein the second control device is configured to generate a pattern of a transmit signal UTX; the first control device is configured to receive a pattern of a receive signal URX, which includes a pattern of a transmit signal UTX combined with noise; and the first control device comprises a pattern filter, the pattern filter is configured to compare a pattern of a receive signal URX with a pattern of an assumed receive signal URX, and to assert a first command to start a charging cycle of the power supply when the pattern of a receive signal URX corresponds to a pattern of an assumed receive signal URX.

[0133] Example 2. The power control device according to Example 1, further configured to assert a second command to delay the start of the power supply's charging cycle for the duration of the blanking period when the pattern of the received signal URX does not correspond to the expected pattern of the received signal URX.

[0134] Example 3. The power control device described in Example 1, wherein the first command is a charging command asserted by a pattern filter to the driver of the first control device.

[0135] Example 4. The power control device described in Example 2, wherein the second command is a block command asserted by a pattern filter toward the receiver of the first control device.

[0136] Example 5. The power control device according to Example 1, wherein the first control device is configured to open and close the first switch.

[0137] Example 6. The power control device according to Example 5, wherein a second control device is configured to open and close a second switch.

[0138] Example 7. The first switch is a cascode switch comprising a normally-on gallium nitride (GaN) high electron mobility transistor (HEMT) and a normally-off silicon (Si) metal-oxide-semiconductor field-effect transistor (MOSFET), The second switch is a cascode switch with two transistors. The power control device described in Example 6.

[0139] Example 8. The power control device according to Example 1, wherein a pattern filter is configured to generate a sequence of window pulses of a window signal UW, and a first command to initiate a power supply charging cycle is asserted when each of the received pulses of the pattern of the received signal URX occurs within the corresponding window pulse of the window signal UW.

[0140] Example 9. The power control device according to Example 2, wherein a pattern filter is configured to generate a sequence of window pulses of a window signal UW, and a second command to block a power supply charge cycle is asserted when at least one pulse of the pattern of the received signal URX occurs outside of the corresponding window pulse of the window signal UW.

[0141] Example 10. The power control device described in Example 9, wherein a second command for preventing the start of a power supply charging cycle has a length at least one order of magnitude greater than the duration of the pulse of the received signal URX.

[0142] Example 11. The power control device according to Example 1, wherein the timer is configured to generate a time offset for a window signal UW in response to the magnitude of a pulse in the received signal URX being greater than a threshold voltage value.

[0143] Example 12. The power control device according to Example 11, wherein the timer is configured not to generate a time offset in response to the magnitude of the pulse of the received signal URX being less than a threshold voltage.

[0144] Example 13. The power control device described in Example 12, wherein a time offset is applied from the rising edge of each pulse of the received signal URX.

[0145] Example 14. The power control device described in Example 11, wherein the time offset is not uniform for each window pulse in the sequence of window pulses of the window signal UW.

[0146] Example 15. The first control device comprises a first clock configured to generate a time offset based on the pattern of the received signal URX, The second control unit includes a second clock configured to initiate the transmission of a pattern of the transmit signal UTX, The first clock and the second clock are not synchronized. The power control device described in Example 1.

[0147] Example 16. The first control device is configured to detect the current flowing into the first switch. The second control device is configured to detect the voltage in the second switch. The power control device described in Example 1.

[0148] Example 17. A power supply equipped with the power control device described in Example 1.

[0149] Example 18. A method for controlling a power supply, the method comprising: detecting a current in a first switching circuit with a first control device; detecting a voltage in a second switching circuit with a second control device; generating a pattern of a transmit signal UTX with the second control device; receiving a pattern of a receive signal URX including a pattern of a transmit signal UTX combined with noise with the first control device; comparing the pattern of the receive signal URX with a hypothetical pattern of a receive signal URX with the first control device; and asserting a first command to start a charging cycle of the power supply with the first control device when the pattern of the receive signal URX corresponds to a hypothetical pattern of a receive signal URX. 【0150】 Example 19. The method according to Example 18, further comprising the first control unit asserting a second command to delay the start of the power supply charging cycle for the duration of the blanking period when the pattern of the received signal URX does not correspond to the expected pattern of the received signal URX. 【0151】 Example 20. The method according to Example 18, wherein the first command is a charge command asserted by a pattern filter to the driver of the first control unit. 【0152】 Example 21. The method according to Example 19, wherein the second command is a block command asserted by a pattern filter toward the receiver of the first control device. 【0153】 Example 22. The method according to Example 18, wherein a first control device is configured to open and close a first switch, and a second control device is configured to open and close a second switch. 【0154】 Example 23. The first control device is configured to detect the current in the first switch. The second control device is configured to detect the voltage in the second switch. The method described in Example 18. 【0155】 Example 24. Generating a sequence of window pulses for the window signal UW using a pattern filter, When each received pulse in the pattern of the received signal URX occurs within the corresponding window pulse of the window signal UW, a first command is asserted to initiate a power supply charging cycle, The method described in Example 18, further including the following. 【0156】 Example 25. Generating a sequence of window pulses in the window signal UW using a pattern filter, When at least one received pulse in the pattern of the received signal URX occurs outside the corresponding window pulse of the window signal UW, a second command is asserted to block the power supply charging cycle, The method described in Example 19, further including the method described in Example 19. 【0157】 Example 26. The method according to Example 25, wherein the second command for preventing the start of the power supply charging cycle has a length at least one order of magnitude greater than the duration of the received signal URX. 【0158】 Example 27. The method according to Example 18, wherein the timer is configured to generate a time offset for a window signal UW in response to a received pulse of signal URX that is greater than a threshold voltage, and the timer is configured not to generate a time offset in response to a received pulse of signal URX that is less than a threshold voltage. 【0159】 Example 28. The method of Example 27, wherein the time offset is applied from the rising edge of each received signal URX, and the time offset is not uniform for each window pulse in the sequence of window pulses of the window signal UW.

Claims

[Claim 1] A control system for a power converter, wherein the control system is A first switching circuit comprising a first control device, A second switching circuit comprising a second control device, Equipped with, The second control device transmits the signal U ＴＸ It is configured to generate pulse patterns in The aforementioned transmission signal U ＴＸ The pulse pattern in corresponds to a predetermined command, The first control device receives the received signal U ＲＸ It is configured to receive pulse patterns in The first control device includes a pattern filter, and the pattern filter is The received signal U ＲＸ Comparing the pulse pattern in the above with the expected pattern, The received signal U ＲＸ When the pulse pattern in corresponds to the assumed pattern, the predetermined command is asserted, It is configured to do so Control system. [Claim 2] The pattern filter receives the received signal U ＲＸ Based on the time offset between individual pulses of a given pulse pattern in the received signal U ＲＸ The pulse pattern in is configured to be compared with the assumed pattern. The power control device according to claim 1. [Claim 3] The predetermined command is a charging command asserted by the pattern filter to the driver and control circuit of the first control device. The power control device according to claim 1. [Claim 4] The first control device receives the received signal U ＲＸ A timer configured to generate a time offset based on the pulse pattern in the above, The power control device according to claim 1. [Claim 5] The aforementioned pattern filter, Receiving the aforementioned time offset, Based on the aforementioned time offset, a plurality of window signals are generated, the received signal U ＲＸ determining whether at least two pulses of the pulse pattern in the received signal U are present in at least two of the plurality of window signals It is configured to do so The power control device according to claim 4. [Claim 6] The first control device receives the received signal U ＲＸ A timer configured to generate a window signal based on the pulse pattern in the above, The aforementioned pattern filter, Receiving the aforementioned window signal, The received signal U ＲＸ To determine whether at least two pulses of the pulse pattern in the above are present within at least two of the window signals of the plurality of window signals, Configured to do so, The power control device according to claim 1. [Claim 7] The pattern filter receives the received signal U ＲＸ The pulse pattern in the full window signal U ＷＨ To determine whether or not it exists within, The received signal U ＲＸ The pulse pattern in the full window signal U ＷＨ If it does not exist within, the predetermined command will not be asserted. It is further structured to do the following: The power control device according to claim 6. [Claim 8] The aforementioned pattern filter, A comparator configured to receive a slope signal RAMP and a reference signal REF as inputs, wherein the period for the slope signal RAMP to reach the reference signal REF is the full window signal U ＷＨ The comparator, which substantially corresponds to the duration of, A pulse generator configured to receive the output of the comparator and to generate a reset signal RST, Equipped with, The power control device according to claim 6. [Claim 9] The aforementioned pattern filter, The first flip-flop, First window signal U Ｗ１ The received signal U processed as ＲＸ 'and receiving the reset signal RST, Outputting a first confirmation signal U1, The first flip-flop is configured to do the following, The second flip-flop, Second window signal U Ｗ２ and the processed received signal U ＲＸ 'and receiving the reset signal RST, Outputting a second confirmation signal U2, The preceding second flip-flop is configured to do the following, The first window signal U Ｗ１ and the second window signal U Ｗ２ An OR gate configured to receive and The third flip-flop, The output of the OR gate and the processed received signal U ＲＸ 'and receiving the reset signal RST, To output an additional pulse signal UEP, A flip-flop configured to do the following, It also has, The power control device according to claim 8. [Claim 10] The pattern filter further comprises an AND gate, and the AND gate is The first confirmation signal U1, the second confirmation signal U2, the further pulse signal UEP, and the full window signal U ＷＨ Receiving and Asserting a charge command to the driver and control circuit of the first control device, Configured to do so, The power control device according to claim 9. [Claim 11] The aforementioned timer, Full window signal U ＷＨ A flip-flop configured to output, The aforementioned full window signal U ＷＨ In response to the front edge in, width T Ｗ１ A first pulse generator configured to generate a first pulse having, The aforementioned full window signal U ＷＨ In response to the front edge in, width T Ｗ２ A second pulse generator configured to generate a second pulse having, Equipped with, The power control device according to claim 6. [Claim 12] The aforementioned timer, The first delay circuit is, Said width T Ｗ１ Receiving the first pulse having, First window signal U Ｗ１ To output, The first delay circuit is configured to do the following, A second delay circuit, Said width T Ｗ２ Receiving the aforementioned second pulse having, Second window signal U Ｗ１ To output, The second delay circuit is configured to do the following: It also has, The power control device according to claim 11. [Claim 13] The received signal U ＲＸ The time offset between individual pulses in the pulse pattern is not uniform. The power control device according to claim 1. [Claim 14] The received signal U ＲＸ The first time offset between the first pulse and the second pulse of the pulse pattern in the received signal U ＲＸ The second time offset between the second pulse and the third pulse in the pulse pattern is longer than the second time offset in the pulse pattern. The power control device according to claim 13. [Claim 15] The received signal U ＲＸ The first time offset between the first pulse and the second pulse of the pulse pattern in the received signal U ＲＸ Shorter than the second time offset between the second pulse and the third pulse of the pulse pattern in the said pulse pattern, The power control device according to claim 13. [Claim 16] The received signal U ＲＸ The pulse pattern in consists of three pulses. The pattern filter receives the received signal U ＲＸ The system is further configured to determine whether the last two pulses of the pulse pattern in the system are located within two of the corresponding window signals among a plurality of window signals. The power control device according to claim 1. [Claim 17] The aforementioned transmission signal U ＴＸ The pulse pattern in the transmission signal U ＴＸ This is the first pulse pattern in The received signal U ＲＸ The pulse pattern in the received signal U ＲＸ This is the first pulse pattern in The aforementioned pattern filter is a first pattern filter, The aforementioned assumed pattern is the first assumed pattern, The second control device transmits the transmission signal U corresponding to the second predetermined command. ＴＸ It is configured to generate a second pulse pattern in The first control device receives the received signal U ＲＸ It is configured to receive a second pulse pattern in The first control device comprises a second pattern filter, and the second pattern filter is The received signal U ＲＸ Comparing the second pulse pattern in with a second assumed pattern, The received signal U ＲＸ When the second pulse pattern in corresponds to the second assumed pattern, the second predetermined command is asserted, It is configured to do so The power control device according to claim 1. [Claim 18] The second control device transmits the transmission signal U corresponding to the third predetermined command. ＴＸ It is configured to generate a third pulse pattern in The first control device receives the received signal U ＲＸ It is configured to receive a third pulse pattern in The first pattern filter described above, The received signal U ＲＸ Comparing the third pulse pattern in with a third assumed pattern, The received signal U ＲＸ When the third pulse pattern in corresponds to the third assumed pattern, the third predetermined command is asserted, It is further structured to do the following: The power control device according to claim 17. [Claim 19] The received signal U ＲＸ The first pulse pattern in and the received signal U ＲＸ The second pulse pattern in the above is transmitted at least partially during the same period. The power control device according to claim 17. [Claim 20] The received signal U ＲＸ The pulse pattern in the above includes noise, The pattern filter is configured such that it does not assert the predetermined command when the noise is greater than a predetermined noise threshold. The power control device according to claim 1. [Claim 21] The received signal U ＲＸ The pattern filter is configured such that it does not assert the predetermined command when the amplitude of at least one pulse in the pulse pattern is less than a predetermined threshold. The power control device according to claim 1. [Claim 22] A method for controlling a power converter, wherein the method is The second control device of the second switching circuit transmits the signal U ＴＸ The process involves generating a pulse pattern in the transmission signal U ＴＸ The pulse pattern in the above corresponds to a predetermined command, and is generated. The first control device of the first switching circuit receives the received signal U ＲＸ Receiving the pulse pattern in and The pattern filter of the first control device filters the received signal U ＲＸ Comparing the pulse pattern in the above with the expected pattern, The received signal U ＲＸ When the pulse pattern in corresponds to the assumed pattern, the predetermined command is asserted, Methods that include... [Claim 23] The received signal U ＲＸ The pulse pattern in the full window signal U ＷＨ To determine whether or not it exists within, The received signal U ＲＸ The pulse pattern in the full window signal U ＷＨ If it does not exist within, the predetermined command will not be asserted. The method according to claim 22, further comprising: [Claim 24] The received signal U ＲＸ Comparing the pulse pattern in the received signal U with the assumed pattern is performed. ＲＸ Based on the time offset between individual pulses of a given pulse pattern in The method according to claim 22. [Claim 25] The aforementioned predetermined command is a charging command, The method further includes receiving the charging command by the driver and control circuit of the first control device, The method according to claim 22. [Claim 26] The timer of the first control device transmits the transmission signal U ＴＸ Receiving the pulse pattern in the above, The timer receives the received signal U ＲＸ Based on the pulse pattern in, a time offset is generated, The pattern filter receives the time offset, Based on the aforementioned time offset, the pattern filter generates a plurality of window signals, The pattern filter allows the received signal U ＲＸ To determine whether at least two pulses of the pulse pattern in the above are present within at least two of the window signals of the plurality of window signals, The method according to claim 22, further comprising: [Claim 27] The timer of the first control device controls the transmission signal U ＴＸ Receiving the pulse pattern in the above, The timer generates multiple window signals, The pattern filter receives the plurality of window signals, The pattern filter allows the received signal U ＲＸ To determine whether at least two pulses of the pulse pattern in the above are present within at least two of the window signals of the plurality of window signals, The method according to claim 22, further comprising: [Claim 28] The received signal U ＲＸ The time offset between individual pulses in the pulse pattern is not uniform. The method according to claim 22. [Claim 29] The received signal U ＲＸ The first time offset between the first pulse and the second pulse of the pulse pattern in the received signal U ＲＸ The second time offset between the second pulse and the third pulse in the pulse pattern is longer than the second time offset in the pulse pattern. The method according to claim 28. [Claim 30] The received signal U ＲＸ The first time offset between the first pulse and the second pulse of the pulse pattern in the received signal U ＲＸ Shorter than the second time offset between the second pulse and the third pulse of the pulse pattern in the said pulse pattern, The method according to claim 28. [Claim 31] The aforementioned transmission signal U ＴＸ The pulse pattern in the transmission signal U ＴＸ This is the first pulse pattern in The received signal U ＲＸ The pulse pattern in the received signal U ＲＸ This is the first pulse pattern in The aforementioned pattern filter is a first pattern filter, The aforementioned assumed pattern is the first assumed pattern, The method described above is The second control device transmits the transmission signal U ＴＸ To generate a second pulse pattern in which the second pulse pattern corresponds to a second predetermined command, The second pattern filter of the first control device processes the received signal U ＲＸ Receiving the second pulse pattern in the above, The second pattern filter allows the received signal U to be filtered. ＲＸ Comparing the second pulse pattern in with a second assumed pattern, The received signal U ＲＸ When the second pulse pattern corresponds to the second assumed pattern, the second pattern filter asserts the second predetermined command, This also includes, The method according to claim 22. [Claim 32] The second control device controls the transmission signal U ＴＸ To generate a third pulse pattern in which the third pulse pattern corresponds to a third predetermined command, The first pattern filter allows the received signal U ＲＸ Receiving the third pulse pattern in the above, The first pattern filter allows the received signal U ＲＸ The third pulse pattern in the received signal U ＲＸ This involves comparing it with a third hypothetical pulse pattern, the received signal U ＲＸ when the third pulse pattern in the received signal U corresponds to the assumed pattern, asserting the third predetermined command by the first pattern filter; The method according to claim 31, further comprising: [Claim 33] The received signal U ＲＸ The first pulse pattern and the received signal U ＲＸ The second pulse pattern in the above is transmitted at least partially during the same period. The method according to claim 31. [Claim 34] The received signal U ＲＸ The pulse pattern in the above includes noise, The pattern filter is configured such that it does not assert the predetermined command when the noise is greater than a predetermined noise threshold. The method according to claim 22. [Claim 35] The received signal U ＲＸ The pattern filter is configured such that it does not assert the predetermined command when the amplitude of at least one pulse in the pulse pattern is less than a predetermined threshold. The method according to claim 22.

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