A method and program for correcting the conversion value of a semiconductor device and an analog / digital converter.

Abstract

This invention provides a semiconductor device that automatically corrects the conversion value of an analog-to-digital converter, a method for correcting the conversion value of an analog-to-digital converter, and a program for doing so. [Solution] The analog / digital converter 1 outputs a converted value DS obtained by converting the input signal IN from analog to digital. The non-volatile memory 11 stores multiple correction values. The correction circuit 21 selects a correction value from the multiple correction values ​​according to the situation, depending on the situation affecting the offset on the converted value DS of the analog / digital converter 1, and outputs an output value OUT with the offset on the converted value DS corrected based on the selected correction value.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device, a method for correcting the conversion value of an analog-to-digital converter, and a program, and is suitably applicable, for example, to a semiconductor device equipped with non-volatile memory. [Background technology]

[0002] Microcomputers incorporated into semiconductor devices are equipped with analog-to-digital converters (hereinafter referred to as A / D converters). It is known that A / D converters are affected by factors such as operating frequency and ambient temperature, resulting in an offset in the conversion result. While it is conceivable to define the specifications of the semiconductor device for each usage condition, this is not practical considering the complexity. As a result, there are cases where the use of a semiconductor device must be decided based on the worst-case scenario affected by the usage conditions. In this case, the performance of the semiconductor device may be limited.

[0003] In contrast, a common method involves measuring the offset amount of the A / D converter mounted on the semiconductor device, and then correcting the output of the A / D converter by adding or subtracting the measured offset amount from the output of the A / D converter. In this method, the measured offset amount of the A / D converter is stored in a register mounted on the semiconductor device. Then, the offset amount read from the register according to the operating conditions of the semiconductor device is added or subtracted from the output of the A / D converter to correct the output of the A / D converter.

[0004] Furthermore, a method has been proposed to switch the settings of the processing unit according to the non-volatile memory installed in the semiconductor device (Patent Document 1). [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2014-209390 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] However, in general methods, the output offset of the A / D converter caused by the connection between the semiconductor device and other devices is corrected. Therefore, the measurement of the offset amount and the determination of the correction value are performed by the user of the semiconductor device. Consequently, general methods cannot be applied to determining the specifications of the semiconductor device before it is provided to the user.

[0007] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0008] According to one embodiment, the semiconductor device includes an analog-to-digital converter that outputs a converted value obtained by converting an input signal from analog to digital, a non-volatile memory that stores a plurality of correction values, and the analog-to-digital converter that selects a correction value corresponding to a given situation from the plurality of correction values ​​as a selected correction value according to a situation that affects the offset on the converted value, and outputs an output value in which the offset on the converted value has been corrected based on the selected correction value.

[0009] According to one embodiment, the method for correcting the conversion value of an analog / digital converter involves outputting a converted value obtained by converting an input signal from analog to digital, selecting a correction value corresponding to the situation from a plurality of correction values ​​stored in a non-volatile memory according to the situation affecting the offset on the converted value, and outputting an output value in which the offset on the converted value has been corrected based on the selected correction value.

[0010] According to one embodiment, the program causes the computer to perform the following processes depending on the circumstances affecting the offset on the converted value obtained by converting the input signal from analog to digital using an analog-to-digital converter: selecting a correction value corresponding to the circumstances from a plurality of correction values ​​stored in non-volatile memory; and outputting an output value in which the offset on the converted value has been corrected based on the selected correction value. [Effect of the Invention]

[0011] According to one embodiment, a semiconductor device that automatically corrects the conversion value of an analog / digital converter, a method for correcting the conversion value of an analog / digital converter, and a program can be provided. [Brief Description of the Drawings]

[0012] [Figure 1] It is a block diagram schematically showing the configuration of a semiconductor device according to Embodiment 1. [Figure 2] It is a sequence diagram showing the operation of a semiconductor device according to Embodiment 1. [Figure 3] It is a block diagram showing the configuration of a semiconductor device according to Embodiment 1 in more detail. [Figure 4] It is a block diagram schematically showing the configuration of a semiconductor device according to Embodiment 2. [Figure 5] It is a block diagram schematically showing the configuration of a semiconductor device according to Embodiment 3. [Figure 6] It is a block diagram schematically showing a configuration example of a main part of an A / D converter. [Figure 7] It is a block diagram schematically showing the configuration of a semiconductor device according to Embodiment 4. [Figure 8] It is a block diagram schematically showing the configuration of a semiconductor device according to Embodiment 5. [Figure 9] It is a block diagram schematically showing the configuration of a semiconductor device according to Embodiment 6. [Figure 10] It is a block diagram schematically showing the configuration of a semiconductor device according to Embodiment 7. [Figure 11] It is a diagram showing a configuration example of a computer for realizing a semiconductor device. [Modes for Carrying Out the Invention]

[0013] Embodiments of the present invention will be described below with reference to the drawings. In each drawing, the same elements are denoted by the same reference numerals, and redundant explanations are omitted where necessary.

[0014] Embodiment 1 Figure 1 is a schematic block diagram showing the configuration of a semiconductor device according to Embodiment 1. The semiconductor device 100 includes an analog / digital converter 1, a non-volatile memory 11, and a correction circuit 21. Hereinafter, for simplicity, the analog / digital converter will also be referred to as an A / D converter.

[0015] The configuration of the semiconductor device 100 will be described below with reference to the operation flow. Figure 2 is a sequence diagram showing the operation of the semiconductor device according to Embodiment 1.

[0016] Step S1 The A / D converter 1 converts the input analog signal, data signal IN, into a digital value, conversion value DS. The A / D converter 1 outputs the conversion value DS to the correction circuit 21.

[0017] The non-volatile memory 11 stores multiple correction values ​​used to correct the offset on the conversion value DS of the A / D converter 1. The multiple correction values ​​stored in the non-volatile memory 11 are preset correction values ​​corresponding to the usage status of the semiconductor device 100.

[0018] Step S2 The correction circuit 21 receives multiple correction values ​​from the non-volatile memory 11. The correction circuit 21 also receives status information INF indicating the usage status of the semiconductor device 100. In Figure 1, for simplification, multiple correction values ​​are represented by the code CV. The correction circuit 21 selects a correction value CVS from the multiple correction values ​​CV that corresponds to the usage status of the semiconductor device 100 indicated by status INF. Then, the correction circuit 21 corrects the conversion value DS of the A / D converter 1 using the selected correction value CVS and outputs the corrected output value OUT. Hereafter, the correction value selected by the correction circuit will be referred to as the selected correction value.

[0019] The configuration and operation of the semiconductor device 100 will be described below based on specific examples. In this embodiment, an example will be described in which the offset on the conversion value DS of the A / D converter 1 is corrected depending on the circuit mounted on the semiconductor device 100 and the operating frequency of the A / D converter 1.

[0020] Figure 3 is a block diagram showing the configuration of the semiconductor device according to Embodiment 1 in more detail. The semiconductor device 100 is provided with a clock generation circuit 110. The clock generation circuit 110 outputs a clock signal ADCLK to the A / D converter 1, which specifies the A / D conversion operating frequency of the A / D converter 1. The clock generation circuit 110 also outputs a reference clock signal PCLK. At least the circuits mounted on the semiconductor device 100, excluding the A / D converter 1, operate in accordance with the reference clock signal PCLK output by the clock generation circuit 110. In Figure 3, the clock generation circuit 110 generates the clock signal ADCLK and the reference clock signal PCLK, but this is merely an example. For example, the clock signal ADCLK and the reference clock signal PCLK may be generated by different clock signal generation means provided on the semiconductor device 100.

[0021] In the semiconductor device 100, the A / D converter 1 performs A / D conversion according to a clock signal ADCLK that is different from the reference clock signal PCLK. The conversion value DS of the A / D converter 1 has an offset that arises from various factors. It is known that the amount of offset on the conversion value DS can also be caused by, for example, the combination of the reference clock and the A / D conversion frequency. In this case, the amount of offset on the conversion value DS changes according to the change in the combination of the reference clock and the A / D conversion frequency. Although the combination of the reference clock and the A / D conversion frequency was used as an example of a factor in the offset on the conversion value DS, The factors causing the offset are not limited to these.

[0022] Therefore, the semiconductor device 100 according to this embodiment has a frequency f of the clock signal ADCLK, which is the A / D conversion operating frequency. AD and the frequency f of the reference clock signal PCLKP Based on both of them, correct the offset of the conversion value DS.

[0023] The non-volatile memory 11 stores a plurality of correction values CV associated with the frequency f of the clock signal ADCLK AD and the frequency f of the reference clock signal PCLK. P For the sake of simplicity in the following description, the frequency f of the clock signal ADCLK AD and the frequency f of the reference clock signal PCLK P are also referred to as the operating frequency of the semiconductor device 100. Also, the frequency f of the clock signal ADCLK AD is also referred to as the conversion operation frequency of the A / D converter 1.

[0024] The correction circuit 21 includes an arithmetic circuit 20, a select signal generation circuit 21A, and a selector 21B.

[0025] The select signal generation circuit 21A receives the clock signal ADCLK and the reference clock signal PCLK. Note that the clock signal ADCLK and the reference clock signal PCLK correspond to the above-described situation information INF. Then, the select signal generation circuit 21A generates a select signal SEL for controlling the operation of the selector 21B based on the frequencies of the clock signal ADCLK and the reference clock signal PCLK. The select signal generation circuit 21A identifies the frequency f of the clock signal ADCLK AD and the frequency f of the reference clock signal PCLK P based on the multiplication setting and division setting of the clock generation circuit 110. However, the method for identifying the frequency f of the clock signal ADCLK in the select signal generation circuit 21A AD and the frequency f of the reference clock signal PCLK P is merely an example. The select signal generation circuit 21A may identify the frequency f of the clock signal ADCLK AD and the frequency f of the reference clock signal PCLK P using various frequency identification methods. The select signal generation circuit 21A outputs the generated select signal SEL to the selector 21B.

[0026] The selector 21B selects a correction value from a plurality of correction values ​​stored in the non-volatile memory 11 that corresponds to the combination of frequencies of the clock signal ADCLK and the reference clock signal PCLK indicated by the select signal SEL. For example, if the frequency of the clock signal ADCLK is 8MHz and the frequency of the reference clock signal PCLK is 24MHz, the selector 21B selects a correction value CV(8MHz,24MHz) that corresponds to the combination of frequencies of the clock signal ADCLK and the reference clock signal PCLK, and outputs it to the arithmetic circuit 20 as the selected correction value CVS.

[0027] The arithmetic circuit 20 corrects the converted value DS based on the selection correction value CVS received from the selector 21B. The arithmetic circuit 20 may be configured as, for example, an addition / subtraction circuit. In this case, the selector 21B corrects the converted value DS by adding or subtracting the selection correction value CVS to the converted value DS. The arithmetic circuit 20 then outputs the value obtained by the correction as the output value OUT.

[0028] As a result, the semiconductor device 100 can automatically correct the offset amount on the conversion value of the A / D converter by using an appropriate correction value corresponding to the conversion operating frequency of the A / D converter and the frequency of the reference clock signal of the semiconductor device 100. This allows the semiconductor device 100 to obtain the desired output value as the A / D conversion result of the A / D converter to the input signal, regardless of the conversion operating frequency of the A / D converter and the frequency of the reference clock signal of the semiconductor device 100.

[0029] The above correction value may be selected, for example, when the semiconductor device 100 is started up. By selecting the correction value prior to the start of operation of the A / D converter after startup, the amount of offset that is added to the output value from the time the A / D converter starts operating can be suitably corrected.

[0030] Furthermore, the selection of the above correction value may be performed during the operation of the semiconductor device 100. For example, it is expected that the combination of frequencies of the clock signal ADCLK and the reference clock signal PCLK may fluctuate after the start of operation of the semiconductor device 100, such as when the user changes the frequency setting. In this case, the select signal generation circuit 21A detects the fluctuation in the combination of frequencies of the clock signal ADCLK and the reference clock signal PCLK and reflects the detection result in the select signal SEL. As a result, the selector 21B can select a correction value corresponding to the combination of frequencies of the clock signal ADCLK and the reference clock signal PCLK after the fluctuation, according to the select signal SEL. In this way, the semiconductor device 100 can suitably correct the offset of the conversion value to the A / D converter according to the latest usage conditions.

[0031] The correction of the offset of the conversion value of the A / D converter in the semiconductor device 100 is performed automatically as described above, without requiring any special awareness from the user of the semiconductor device 100. Therefore, the user of the semiconductor device can avoid the task of determining the correction value of the offset amount, as in the general method described above. Consequently, the semiconductor device 100 can be installed more easily by the user, and the amount of work required for installation can be reduced.

[0032] This makes it possible to present the maximum performance of the semiconductor device 100 according to its usage conditions as the specifications of the semiconductor device 100 presented to the user. As a result, the specifications can be determined based on the performance that the semiconductor device 100 can inherently deliver, without restricting the specifications of the semiconductor device 100 presented to the user, as is the case with general methods.

[0033] Furthermore, the non-volatile memory 11 of the semiconductor device 100 can utilize optional memory, which is generally provided in semiconductor devices and can additionally store various types of data. Therefore, the semiconductor device 100 according to Embodiment 1 can be realized without adding any special hardware configuration to a general semiconductor device. As a result, the semiconductor device according to the embodiment can be easily realized at low cost using existing semiconductor devices.

[0034] Embodiment 2 Embodiment 1 described a semiconductor device that corrects the offset on the conversion value DS depending on the operating frequency of the semiconductor device. However, the factors causing the offset on the conversion value DS are not limited to the operating frequency of the semiconductor device. For example, the offset on the conversion value DS may fluctuate with changes in the temperature of the semiconductor device. Therefore, Embodiment 2 describes a semiconductor device that corrects the offset on the conversion value of an A / D converter according to the ambient temperature.

[0035] Figure 4 is a schematic block diagram showing the configuration of the semiconductor device according to Embodiment 2. The semiconductor device 200 according to Embodiment 2 has a configuration in which the non-volatile memory 11 and correction circuit 21 of the semiconductor device 100 are replaced with a non-volatile memory 12 and a correction circuit 22, respectively.

[0036] Furthermore, in semiconductor device 200, compared to semiconductor device 100, the input to the select signal generation circuit 22A is replaced from the clock generation circuit 110 to the temperature sensor 210 and the reference voltage source 220. Note that in Figure 4, the clock generation circuit 110 is omitted from the diagram for simplification.

[0037] The temperature sensor 210 measures the temperature at a predetermined location on the semiconductor device 200. The temperature sensor 210 then outputs a temperature signal ST, which indicates the measured ambient temperature TMP, to the correction circuit 22. The temperature signal ST is, for example, a voltage signal that represents temperature using voltage.

[0038] The reference voltage source 220 outputs a reference voltage REF, which indicates the reference temperature to be compared with the temperature signal ST, to the correction circuit 22.

[0039] The non-volatile memory 12 stores multiple correction values ​​corresponding to the temperature TMP. In Figure 4, as an example, a correction value CV (from TL to TH) is set for each temperature range in 10-degree increments that is above the lower limit temperature and below the upper limit temperature TH.

[0040] The correction circuit 22 has select signal generation circuits 22A and selector 22B, which correspond to the select signal generation circuits 21A and selector 21B of the correction circuit 21, respectively. The calculation circuit 20 in the correction circuit 22 is the same as the calculation circuit 20 in the correction circuit 21.

[0041] The select signal generation circuit 22A compares the temperature signal ST with the reference voltage REF to detect the temperature TMP indicated by the temperature signal ST. The temperature signal ST and the reference voltage REF correspond to the status information INF mentioned above. Based on the detected temperature TMP, the select signal generation circuit 22A outputs a select signal SEL to the selector 22B, indicating the correction value to be selected from a plurality of correction values ​​output by the non-volatile memory 12.

[0042] The selector 22B selects a correction value from among several correction values ​​stored in the non-volatile memory 12 that corresponds to the temperature TMP indicated by the select signal SEL. For example, if the temperature TMP is 28°C, the correction value CV (20 to 30 degrees) corresponding to 20 degrees Celsius ≤ T < 30 degrees Celsius is output to the calculation circuit 20 as the selected correction value CVS.

[0043] The operation of the calculation circuit 20 in the correction circuit 22 is the same as that in the correction circuit 21, so the explanation will be omitted.

[0044] As a result, the semiconductor device 200 can automatically correct the offset in the conversion value of the A / D converter using an appropriate correction value according to the ambient temperature. This allows the semiconductor device 200 to obtain the corrected desired output value OUT as the A / D conversion result of the A / D converter for the input signal, regardless of the ambient temperature.

[0045] The other advantages of semiconductor device 200 are the same as those of semiconductor device 100, so redundant explanations will be omitted.

[0046] Embodiment 3 In the embodiments described above, a semiconductor device was described that corrects the offset on the converted value DS depending on the operating frequency or ambient temperature of the semiconductor device. However, the factors causing the offset on the converted value DS are not limited to the operating frequency and ambient temperature of the semiconductor device. For example, the offset on the converted value DS may fluctuate depending on the input signal IN. Therefore, Embodiment 3 describes a semiconductor device that corrects the offset that changes depending on the input signal IN. Note that the converted value DS changes depending on the input signal IN and the reference voltage of the A / D converter 1, but for the sake of simplicity, the case in which the reference voltage of the A / D converter 1 is a predetermined constant voltage will be described.

[0047] Figure 5 is a schematic block diagram showing the configuration of the semiconductor device according to Embodiment 3. The semiconductor device 300 according to Embodiment 3 has a configuration in which the non-volatile memory 11 and correction circuit 21 of the semiconductor device 100 are replaced with a non-volatile memory 13 and a correction circuit 23, respectively. In addition, compared to the semiconductor device 100, the input from the clock generation circuit 110 to the select signal generation circuit 23A is removed in the semiconductor device 300. Note that in Figure 5, the clock generation circuit 110 is omitted from the diagram for simplification.

[0048] The A / D converter 1 outputs the converted value DS, which consists of the conversion code after A / D conversion, not only to the arithmetic circuit 20 but also to the correction circuit 23. Here, for distinction, the converted value output from the A / D converter 1 to the arithmetic circuit 20 is referred to as the converted value DS_REF. Note that the converted value DS_REF corresponds to the status information INF mentioned above.

[0049] In this case, the A / D converter 1 may output a conversion code to the correction circuit 23 prior to outputting the conversion value DS to the arithmetic circuit 20. Figure 6 is a schematic block diagram showing an example of the configuration of the main parts of the A / D converter. Figure 6 shows an example in which the A / D converter 1 is configured as a successive approximation type A / D converter and converts the input signal IN into an N-bit conversion code. In this case, the A / D conversion of the input signal IN is performed bit by bit sequentially from the most significant bit (MSB) BIT[N-1] to the least significant bit (LSB) BIT[0]. At this time, the conversion result of each bit is held in the latch circuits L_N-1 to L_0. After the conversion of all bits is completed, the A / D converter 1 outputs the results of the changes of all bits from the output circuits OC_N-1 to OC_0 as a conversion value DS to the arithmetic circuit 20 in accordance with the transition of the output enable signal EN given from the output circuits OC_N-1 to OC_0.

[0050] In contrast, the A / D converter 1 shown in Figure 6 sequentially outputs the conversion result of each bit held in latch circuits L_N-1 to L_0 to the correction circuit 23, regardless of the output enable signal EN. In this case, the arithmetic circuit 20 can notify the correction circuit 23 of the converted value DS_REF before it receives the converted value DS from the A / D converter 1. As a result, the correction circuit 23 can provide the arithmetic circuit 20 with a selected correction value CVS corresponding to the converted value DS_REF prior to the correction of the converted value DS in the arithmetic circuit 20.

[0051] The non-volatile memory 13 stores multiple correction values ​​corresponding to the conversion value DS_REF. In Figure 5, as an example, correction values ​​CV (from MIN to MAX) are set for each range of 1000 increments where the conversion value DS_REF is greater than or equal to the lower limit MIN and less than the upper limit MAX.

[0052] The correction circuit 23 has a select signal generation circuit 23A and a selector 23B, which correspond to the select signal generation circuit 21A and selector 21B of the correction circuit 21, respectively. The calculation circuit 20 in the correction circuit 23 is the same as the calculation circuit 20 in the correction circuit 21.

[0053] The select signal generation circuit 23A outputs a select signal SEL to the selector 23B, which indicates the correction value to be selected from among multiple correction values ​​output by the non-volatile memory 13 based on the conversion value DS_REF.

[0054] The selector 23B selects a correction value from among multiple correction values ​​stored in the non-volatile memory 13 that corresponds to the conversion value DS_REF indicated by the select signal SEL. For example, if the conversion code is 5265, the correction value CV (5000 to 5999) is output to the arithmetic circuit 20 as the selected correction value CVS.

[0055] The operation of the calculation circuit 20 in the correction circuit 23 is the same as the operation of the calculation circuit 20 in the correction circuit 21, so the explanation will be omitted.

[0056] In this embodiment, for the sake of simplicity, the case where the reference voltage of the A / D converter 1 is a predetermined constant voltage has been described, but this is merely an example. In general, the reference voltage of the A / D converter is changeable, and the value of the reference voltage varies depending on the user. That is, even if the input signal IN is constant, the conversion code that corrects the offset may differ depending on the reference voltage. Therefore, instead of the conversion value DS_REF, the reference voltage of the A / D converter 1 may be input to the select signal generation circuit 23A, so that the select signal generation circuit 23A can identify the reference voltage. As a result, the select signal generation circuit 23A may output a select signal SEL corresponding to the A / D converter 1. Then, by storing a correction value CV corresponding to the reference voltage in the non-volatile memory 13, the selector 21B may select the correction value CV corresponding to the reference voltage. Regarding the identification of the reference voltage of the A / D converter 1, if there is a holding means such as a register that holds information indicating the reference voltage of the A / D converter 1 in the semiconductor device 300, the information indicating the reference voltage of the A / D converter 1 may be input from the holding means to the select signal generation circuit 23A.

[0057] By combining these, the semiconductor device 300 can automatically correct the offset on the conversion value of the A / D converter using an appropriate correction value corresponding to the offset that fluctuates in accordance with the input signal IN. As a result, the semiconductor device 300 can suitably correct the offset that fluctuates depending on the input signal IN and obtain the desired output value OUT.

[0058] Other advantages of the semiconductor device 300 are the same as those of the semiconductor device according to the above-described embodiment, so redundant explanations will be omitted.

[0059] Embodiment 4 In the above-described embodiment, the operating frequency of the semiconductor device, ambient temperature, and the conversion value output by the A / D converter were referenced as the usage status of the semiconductor device to select the correction value. However, depending on the application of the semiconductor device, there may be cases where it is necessary to select a correction value by referencing multiple parameters simultaneously to correct the conversion value with greater accuracy. Therefore, Embodiment 4 describes a semiconductor device that selects a correction value by referencing two types of mutually independent usage status information.

[0060] Figure 7 is a schematic block diagram showing the configuration of the semiconductor device according to Embodiment 4. The semiconductor device 400 refers to two independent types of information indicating usage conditions and corrects the conversion value DS using two types of correction values ​​corresponding to the two conditions.

[0061] The semiconductor device 400 has a configuration in which the non-volatile memory 11 and correction circuit 21 of the semiconductor device 100 are replaced with a non-volatile memory 14 and a correction circuit 24, respectively.

[0062] Furthermore, the semiconductor device 400 is provided with a temperature sensor 210 and a reference voltage source 220, similar to those in the semiconductor device 200, compared to the semiconductor device 100.

[0063] The non-volatile memory 14 includes at least a memory area 14A for storing correction values ​​set in accordance with the operating frequency, similar to Embodiment 1, and a memory area 14B for storing correction values ​​set in accordance with the temperature, similar to Embodiment 2.

[0064] The correction circuit 24 includes a select signal generation circuit 24A, a selector 24B, a select signal generation circuit 24C, and a selector 24D. The calculation circuit 20 in the correction circuit 24 is the same as the calculation circuit 20 in the correction circuit 21.

[0065] The select signal generation circuit 24A and the selector 24B are the same as the select signal generation circuit 21A and the selector 21B according to Embodiment 1, respectively, so redundant explanations are omitted. In Figure 7, for distinction, the select signal output by the select signal generation circuit 24A to the selector 24B is indicated as SEL1. Also, the select correction value selected by the selector 24B is indicated as CVS1.

[0066] The select signal generation circuit 24C and the selector 24D are the same as the select signal generation circuit 22A and the selector 22B in Embodiment 2, respectively, so redundant explanations are omitted. In Figure 7, for distinction, the select signal output by the select signal generation circuit 24C to the selector 24D is indicated as SEL2. Also, the select correction value selected by the selector 24D is indicated as CVS2.

[0067] In this embodiment, the clock signal ADCLK, the reference clock signal PCLK, the temperature signal ST, and the reference voltage REF correspond to the status information INF described above.

[0068] Therefore, according to the semiconductor device 400, a selective correction value CVS1 corresponding to the operating frequency of the semiconductor device 400 and a selective correction value CVS2 corresponding to the ambient temperature can be selected from a plurality of correction values ​​stored in the non-volatile memory 14. The arithmetic circuit 20 then uses the selective correction value CVS1 corresponding to the operating frequency of the semiconductor device 400 and the selective correction value CVS2 corresponding to the ambient temperature in combination to correct the conversion value DS of the A / D converter 1, thereby suitably correcting the offset amount on the conversion value DS.

[0069] Other advantages of the semiconductor device 400 are the same as those of the semiconductor device according to the above-described embodiment, so redundant explanations will be omitted.

[0070] Embodiment 5 Embodiment 4 described an example in which the offset dependent on the operating frequency of the semiconductor device and the offset dependent on the ambient temperature are independent of each other. However, in real semiconductor devices, the influence of the operating frequency on the offset and the influence of the ambient temperature are inseparable and may not be independent of each other. In this case, it is inappropriate to set the correction value according to the operating frequency and the correction value dependent on the ambient temperature separately, as in Embodiment 4.

[0071] Therefore, in this embodiment, we will describe a semiconductor device that selects a single correction value by referring to information indicating two types of usage conditions that are not independent of each other. Figure 8 is a schematic block diagram showing the configuration of a semiconductor device according to Embodiment 5.

[0072] The semiconductor device 500 according to Embodiment 5 has a configuration in which the non-volatile memory 14 and correction circuit 24 of the semiconductor device 400 are replaced with a non-volatile memory 15 and a correction circuit 25, respectively.

[0073] The non-volatile memory 15 has a frequency f of the clock signal ADCLK. AD , the frequency f of the reference clock signal PCLK P It stores multiple preset correction values ​​corresponding to the combination of the clock signal ADCLK and temperature TMP. In Figure 8, the frequency f of the clock signal ADCLK AD [MHz], frequency f of the reference clock signal PCLK P [MHz] and temperature TMP corresponding correction values ​​C(f AD ,f P It is written as ,TL to TH.

[0074] The correction circuit 25 includes a select signal generation circuit 25A and a selector 25B. The calculation circuit 20 in the correction circuit 25 is the same as the calculation circuit 20 in the correction circuit 21.

[0075] The select signal generation circuit 25A receives the clock signal ADCLK, the reference clock signal PCLK, the temperature signal ST, and the reference voltage REF. The select signal generation circuit 25A then generates a select signal based on the frequency f of the clock signal ADCLK. AD , the frequency f of the reference clock signal PCLK P Based on the temperature TMP, a select signal SEL is generated to control the operation of selector 25B. The select signal generation circuit 25A outputs the generated select signal SEL to selector 25B.

[0076] The selector 25B selects the frequency f of the clock signal ADCLK indicated by the select signal SEL from a set of correction values ​​stored in the non-volatile memory 15. AD , the frequency f of the reference clock signal PCLK P A correction value corresponding to the combination of the clock signal ADCLK and temperature TMP is selected. Here, we assume an example where the frequency of the clock signal ADCLK is 8MHz, the frequency of the reference clock signal PCLK is 24MHz, and the temperature TMP is 28 degrees Celsius. In this case, the selector 25B outputs the corresponding correction value C (8MHz, 24MHz, 20 to 30 degrees) as the selected correction value CVS to the calculation circuit 20.

[0077] In this embodiment, the clock signal ADCLK, the reference clock signal PCLK, the temperature signal ST, and the reference voltage REF correspond to the status information INF described above.

[0078] The operation of the calculation circuit 20 in the correction circuit 25 is the same as that of the calculation circuit 20 in the correction circuit 24, so the explanation will be omitted.

[0079] Therefore, according to the semiconductor device 400, one selective correction value CVS corresponding to the operating frequency and ambient temperature of the semiconductor device 400 can be selected from a plurality of correction values ​​stored in the non-volatile memory 15. As a result, the semiconductor device 500 can suitably correct the offset amount on the converted value DS even when the effects of operating frequency and temperature on the offset are not independent.

[0080] Other advantages of the semiconductor device 500 are the same as those of the semiconductor device according to the above-described embodiment, so redundant explanations will be omitted.

[0081] Embodiment 6 In the above-described embodiment, a semiconductor device was described that selects a correction value to correct the offset of the conversion value based on the usage conditions. However, the offset on the conversion value of the A / D converter 1 mounted on the semiconductor device may depend on the combination of the semiconductor device and the external device connected to it. Therefore, in this embodiment, a semiconductor device that selects a correction value according to the connected external device will be described.

[0082] Figure 9 is a schematic block diagram showing the configuration of a semiconductor device according to Embodiment 6. In this embodiment, external devices 601 and 602 are connected to the semiconductor device 600. Operation enable signals EN1 and EN2, which instruct activation / deactivation, are respectively supplied to the external devices 601 and 602, and they are activated complementaryly. The operation enable signals EN1 and EN2 are input to enable signal terminals T1 and T2 provided on the semiconductor device 600, respectively. In this embodiment, it is assumed that the offset on the conversion value DS will vary depending on whether the external device 601 or 602 is activated.

[0083] The semiconductor device 600 has a configuration in which the non-volatile memory 11 and correction circuit 21 of the semiconductor device 100 are replaced with a non-volatile memory 16 and a correction circuit 26, respectively.

[0084] The non-volatile memory 16 has at least memory area 16A and memory area 16B. Memory area 16A stores a set of correction values ​​ST1 used when the external device 601 is activated. Memory area 16B stores a set of correction values ​​ST2 used when the external device 602 is activated.

[0085] The correction values ​​corresponding to each of the above-mentioned external devices may be prepared by the user of the semiconductor device, for example, by various methods such as actual measurement or simulation, depending on the external device used with the semiconductor device. In this case, as described above, the optional memory provided in the semiconductor device can be used as the non-volatile memory according to this embodiment, so the user can easily store the prepared correction values ​​in the non-volatile memory.

[0086] The correction circuit 26 includes a select signal generation circuit 26A and a selector 26B. The calculation circuit 20 in the correction circuit 26 is the same as the calculation circuit 20 in the correction circuit 21.

[0087] The select signal generation circuit 26A receives operation enable signals EN1 and EN2 via enable signal terminals T1 and T2. Based on which of the external devices 601 and 602 is activated, the select signal generation circuit 26A generates a select signal SEL indicating the correction value that the selector 26B should select. The select signal generation circuit 26A outputs the generated select signal SEL to the selector 26B.

[0088] The selector 26B selects the correction value set for the external device indicated by the select signal SEL from among multiple correction values ​​stored in memory areas 16A and 16B. Here, we assume an example where the external device 601 is activated. In this case, the selector 26B outputs the correction value stored in memory area 16A corresponding to the external device 601 to the arithmetic circuit 20.

[0089] In this embodiment, the operation enable signals EN1 and EN2 are included in the status information INF described above.

[0090] The operation of the calculation circuit 20 in the correction circuit 26 is the same as that of the calculation circuit 20 in the correction circuit 21, so the explanation will be omitted.

[0091] As a result, the semiconductor device 600 can select an appropriate correction value that can suitably correct the offset even when the offset on the conversion value DS is affected by the operation of an external device of the semiconductor device. As a result, similar to the semiconductor device according to the above embodiment, the offset on the conversion value of the A / D converter can be automatically corrected. In this way, the semiconductor device 600 can suitably correct the offset on the conversion value DS and obtain the desired output value OUT.

[0092] Other advantages of the semiconductor device 600 are the same as those of the semiconductor device according to the above-described embodiment, so redundant explanations will be omitted.

[0093] Embodiment 7 In the above-described embodiment, a semiconductor device for correcting the offset of the conversion value of the mounted A / D converter 1 was explained. However, by combining a non-volatile memory with the select signal generation circuit and selector of the correction circuit described above, it is possible to not only correct the offset of the conversion value but also adjust the operation of the hard macro mounted on the semiconductor device according to the usage conditions of the semiconductor device. Therefore, in this embodiment, a semiconductor device capable of adjusting the operation of the mounted hard macro will be described.

[0094] Figure 10 is a schematic block diagram showing the configuration of a semiconductor device according to Embodiment 7. The semiconductor device 700 has a configuration in which the non-volatile memory 12 and correction circuit 22 of the semiconductor device 200 are replaced with a non-volatile memory 17 and a correction circuit 27, respectively. The semiconductor device 700 is also provided with a register 710 that holds the value of the power supply voltage VCC supplied to the semiconductor device 700. Furthermore, the semiconductor device 700 is provided with a hard macro section 70 including a variable element that performs various processing.

[0095] The non-volatile memory 17 stores multiple trimming values ​​TRM_1 to TRM_M that should be given to the mard macro in accordance with the ambient temperature.

[0096] The correction circuit 27 includes a select signal generation circuit 27A and a selector 27B.

[0097] The select signal generation circuit 27A receives a temperature signal ST and a reference voltage REF from the temperature sensor 210 and the reference voltage source 220, respectively. The select signal generation circuit 27A compares the temperature signal ST and the reference voltage REF to detect the temperature TMP indicated by the temperature signal ST. The select signal generation circuit 27A also receives a power supply voltage signal SV, which indicates the power supply voltage, output by the register 710. Note that the power supply voltage may also be input to the select signal generation circuit 27A in order to specify the power supply voltage. The specification of the power supply voltage in the select signal generation circuit 27A is merely an example. The select signal generation circuit 27A may specify the power supply voltage by various other methods. The select signal generation circuit 27A then outputs a select signal SEL to the selector 27B, indicating the trimming value to be selected from a plurality of trimming values ​​stored in the non-volatile memory 17, corresponding to the temperature TMP and the power supply voltage indicated by the power supply voltage signal SV.

[0098] The selector 27B selects the trimming value indicated by the select signal SEL from among multiple trimming values ​​stored in the non-volatile memory 17. Then, it outputs the selected trimming value TRM to the hard macro unit 70.

[0099] The hard macro unit 70 performs trimming of the internal variable elements, for example, based on the trimming value TMR received from the selector 27B.

[0100] As described above, the semiconductor device 700 allows for adjustment of hardware such as hard macros installed inside the semiconductor device 700, depending on the usage conditions of the semiconductor device.

[0101] Other embodiments Although the present disclosure has been described above with reference to embodiments, the present disclosure is not limited to the embodiments described above. Various modifications to the structure and details of the present disclosure can be made that will be understood by those skilled in the art within the scope of the present disclosure. Furthermore, each embodiment can be combined with other embodiments as appropriate.

[0102] In embodiments 4 and 5, examples of selecting a correction value according to a combination of the operating frequency and ambient temperature of the semiconductor device were described, but the combinations of usage conditions referenced for selecting the correction value are not limited to these. For example, in the embodiments described above, the semiconductor device may select a correction value according to some or all of a plurality of combinations of usage conditions, including at least the operating frequency, ambient temperature, and the converted value after A / D conversion.

[0103] In the embodiments described above, the semiconductor device according to the disclosure has been described primarily as a hardware configuration, but is not limited thereto. The semiconductor device according to the disclosure can be realized by having a computer execute a computer program to perform any processing. These processing may be realized by having a computer, which includes at least one processor (e.g., a microprocessor, CPU, GPU, MPU, or DSP (Digital Signal Processor)), execute a program. Specifically, one or more programs containing a set of instructions for causing a computer to perform algorithms related to these transmission signal processing or reception signal processing can be created and supplied to the computer.

[0104] Computer programs can be stored and supplied to a computer using various types of non-transitory computer-readable media. Non-transitory computer-readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (e.g., flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (e.g., magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / Ws, and semiconductor memory (e.g., mask ROMs, PROMs (Programmable ROMs), EPROMs (Erasable PROMs), flash ROMs, and RAMs (random access memory)). Programs may also be supplied to a computer using various types of transient computer-readable media. Examples of transient computer-readable media include electrical signals, optical signals, and electromagnetic waves. Transitory computer-readable media can be supplied to a computer via wired communication channels such as electric wires and optical fibers, or via wireless communication channels.

[0105] The following shows an example of a computer configuration for realizing the semiconductor device according to the above-described embodiment. Figure 11 is a diagram showing an example of a computer configuration for realizing a semiconductor device. The semiconductor device can be realized by a computer 9000 such as a dedicated computer or a personal computer (PC). However, the computer does not need to be physically single; there may be multiple computers when performing distributed processing. As shown in Figure 11, the computer 9000 has, for example, a processor 9001, a ROM (Read Only Memory) 9002, a RAM (Random Access Memory) 9003, a storage unit 9004, a communication interface 9005, and a user interface 9006.

[0106] The processor 9001, ROM 9002, RAM 9003, memory unit 9004, communication interface 9005, and user interface 9006 are interconnected via bus 9007, enabling them to communicate with each other. While the operating system software necessary to run the computer is not described here, it will be implemented in the computer 9000 as appropriate.

[0107] ROM is composed of, for example, non-volatile semiconductor memory devices. ROM 9002 stores information such as various programs used in computer 9000.

[0108] The storage unit 9004 is composed of various storage devices, such as hard disks and solid-state disks. Furthermore, the storage unit 9004 is not limited to storage devices installed in the computer 9000, but may also be external storage devices. External storage devices may include various communication means, such as cloud storage connected to the computer 9000 via a network. The storage unit 9004 stores information such as various programs and data used by the computer 9000.

[0109] RAM 9003 is composed of volatile semiconductor memory devices. Programs and data used by the processor 9001 are loaded into RAM 9003 as needed from either ROM 9002 or memory unit 9004, or both.

[0110] The processor 9001 may be composed of, for example, a CPU (Central Processing Unit). Alternatively, the processor 9001 may include a GPU (Graphics Processing Unit) in addition to the CPU. A GPU is suitable for parallel processing of routine tasks, and can improve processing speed compared to a CPU, for example, by being used in neural network processing. The processor 9001 executes various processes based on various programs stored in the ROM 9002, or various programs and data held in the RAM 9003, as appropriate. The processor 9001 may also store the data generated by the processing in the RAM 9003 or the storage unit 9004 as appropriate.

[0111] The communication interface 9005 is an interface that connects the computer 9000 to a communication network such as the Internet or an intranet via various wired or wireless communication means. This allows the computer 9000 to communicate with other devices, systems, and sensors connected to the communication network.

[0112] The user interface 9006 includes, for example, a display unit that provides information so that the user can perceive it, such as through a display device, and an audio output unit that provides audio. The user interface 9006 also includes an input unit that allows the user to input information into the computer 9000 through user operation, such as a keyboard, mouse, and touch panel. Furthermore, the user interface 9006 may include devices such as sensors that acquire information useful to the user.

[0113] Here, the computer 9000 is described as a single device, but this is merely an example. The computer 9000 may consist of multiple physically separate devices. Some of these devices may be portable, while others may be stationary.

[0114] Each drawing is merely illustrative to illustrate one or more embodiments. Each drawing may be associated with one or more other embodiments rather than with only one specific embodiment. As those skilled in the art will understand, various features or steps described with reference to any one drawing can be combined with features or steps shown in one or more other drawings, for example, to create embodiments not explicitly shown or described. Not all features or steps shown in any one drawing to illustrate an exemplary embodiment are necessarily required, and some features or steps may be omitted. The order of steps shown in any of the drawings may be changed as appropriate. [Explanation of symbols]

[0115] 100, 200, 300, 400, 500, 600, 700 cookie dough 601, 602 External device 1 A / D converter 11 to 17 Non-volatile memory 14A, 14B, 16A, 16B memory areas 20 Arithmetic circuit 21 to 27 Correction circuits 21A to 27A, 24C Select Signal Generation Circuit 21B to 27B, 24D selector 70 Hard Macro Section 110 Clock generation circuit 210 Temperature Sensor 220 Reference voltage source 710 Registers ADCLK clock signal CVS, CVS1, CVS2 Selective Correction Values DS, DS_REF conversion value IN Input signal OUT output value PCLK reference clock signal REF Reference Voltage SEL, SEL1, SEL2 select signals ST temperature signal SV Power supply voltage signal

Claims

1. An analog-to-digital converter that outputs a converted value obtained by converting an input signal from analog to digital, A non-volatile memory containing multiple correction values, The analog / digital converter includes a correction circuit that selects a correction value from a plurality of correction values ​​corresponding to a given situation, depending on the situation affecting the offset on the conversion value, and outputs an output value with the offset on the conversion value corrected based on the selected correction value. Semiconductor equipment.

2. The correction circuit described above is A select signal generation unit receives information indicating the aforementioned situation and generates a select signal indicating a correction value to be selected from the plurality of correction values ​​based on the information, A select unit that outputs a correction value indicated by the select signal from the non-volatile memory as the select correction value, The system includes a calculation circuit that outputs an output value obtained by correcting the offset on the converted value based on the selection correction value. The semiconductor device according to claim 1.

3. The non-volatile memory stores the plurality of correction values ​​corresponding to the frequency of the clock signal that controls the operation of the semiconductor device, The correction circuit selects a correction value corresponding to the frequency of the clock signal as the selected correction value. The semiconductor device according to claim 1.

4. The non-volatile memory stores the plurality of correction values ​​corresponding to the combination of the frequency of a first clock signal that controls the operation of the semiconductor device and the frequency of a second clock signal that controls the analog / digital conversion operation of the analog / digital converter. The correction circuit selects a correction value as the selected correction value that corresponds to the combination of the frequency of the first clock signal and the frequency of the second clock signal. The semiconductor device according to claim 3.

5. The non-volatile memory stores the plurality of correction values ​​corresponding to the temperature of the semiconductor device, The correction circuit selects a correction value corresponding to the temperature as the selected correction value. The semiconductor device according to claim 1.

6. The non-volatile memory stores the plurality of correction values ​​corresponding to the input signal of the analog / digital converter, The correction circuit selects a correction value corresponding to the input signal of the analog / digital converter as the selected correction value. The semiconductor device according to claim 1.

7. The plurality of correction values ​​include some or all of the following sets: a first set of plurality of correction values ​​corresponding to a combination of the frequency of a first clock signal controlling the operation of the semiconductor device and the frequency of a second clock signal controlling the analog / digital conversion operation of the analog / digital converter; a second set of plurality of correction values ​​corresponding to the temperature of the semiconductor device; and a third set of plurality of correction values ​​corresponding to the conversion value of the analog / digital converter. The correction circuit selects one to three correction values ​​as the selected correction values, depending on the combination of previous frequencies, the temperature, and some or all of the conversion values ​​of the analog / digital converter, by selecting some or all of the first to third sets. The semiconductor device according to claim 1.

8. Each of the aforementioned plurality of correction values ​​is a correction value corresponding to a combination of the frequency of a first clock signal that controls the operation of the semiconductor device and the frequency of a second clock signal that controls the analog / digital conversion operation of the analog / digital converter, the temperature of the semiconductor device, and some or all of the conversion values ​​of the analog / digital converter. The correction circuit selects the selected correction value from the plurality of correction values ​​according to the combination of frequencies, the temperature, and some or all of the conversion value of the analog / digital converter. The semiconductor device according to claim 1.

9. The aforementioned set of correction values ​​includes multiple sets of correction values ​​corresponding to multiple external devices. The correction circuit selects the selected correction value from the set of correction values ​​corresponding to one of the multiple external devices. The semiconductor device according to claim 1.

10. The input signal is converted from analog to digital and the converted value is output. Depending on the circumstances affecting the offset in the conversion value, a correction value corresponding to the circumstances is selected from a plurality of correction values ​​stored in non-volatile memory. Based on the selected correction value, an output value is output that corrects the offset on the converted value. Methods for correcting the conversion value of an analog-to-digital converter.

11. The process involves selecting a correction value from a set of correction values ​​stored in a non-volatile memory that corresponds to a given situation, depending on the circumstances that affect the offset on the converted value obtained by converting the input signal from analog to digital using an analog-to-digital converter. The computer is instructed to perform the following steps: output an output value that corrects the offset on the converted value based on the selected correction value; program.

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