Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor having excellent life characteristics. 【Solution means】 A plurality of dielectric layers laminated along a first axis, A plurality of internal electrode layers respectively disposed between adjacent dielectric layers along the first axis, A dielectric layer, and an intermediate region disposed between the dielectric layer and the internal electrode layer, The dielectric layer contains a compound represented by the general formula ABO 3-α (0≦α≦1), having a perovskite structure, and an additive element, The internal electrode layer contains a base metal element and tellurium as main components, The intermediate region contains an additive element and tellurium, The additive element contains one or more elements selected from rare earth elements and silicon, a multilayer ceramic capacitor.

Description

[Technical Field]

[0001] This disclosure relates to multilayer ceramic capacitors. [Background technology]

[0002] A multilayer ceramic capacitor (MLCC) has a structure in which dielectric layers and internal electrode layers are stacked alternately.

[0003] Regarding multilayer ceramic capacitors, there is a growing demand for improvements in various characteristics, such as miniaturization and increased capacitance, as electronic devices such as mobile phones in which they are installed become more multifunctional and high-performance.

[0004] For example, Patent Document 1 discloses a multilayer ceramic capacitor in which, in the internal electrode, at least one metal A selected from the group consisting of Cu, Ag, Pd, Pt, Rh, Ir, Ru, and Os is solid-dissolved in Ni and Sn at a solid solution rate of 0.1 atomic percent or more, and the ratio of Sn to the total amount of Ni and Sn in the near-interface region of the internal electrode, which is a region at a depth of 2 nm from the surface facing the ceramic dielectric layer, is 1.4 atomic percent or more, and the relationship between the atomic percent value X representing the ratio of Sn in the near-interface region and the atomic percent value Y representing the ratio of Sn in the central region in the thickness direction of the internal electrode satisfies a predetermined relationship.

[0005] As with the multilayer ceramic capacitor disclosed in Patent Document 1, it has been conventionally considered to improve desired characteristics by adding various elements to the internal electrodes or dielectric layers. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2017-005019 [Overview of the project] [Problems that the invention aims to solve]

[0007] Incidentally, since multilayer ceramic capacitors are rarely replaced after being installed in electronic devices, there is a need to reduce the occurrence of failures due to dielectric breakdown and improve their lifespan characteristics.

[0008] This disclosure aims to provide a multilayer ceramic capacitor with excellent lifespan characteristics. [Means for solving the problem]

[0009] The multilayer ceramic capacitors disclosed herein are Multiple dielectric layers stacked along the first axis, A plurality of internal electrode layers are disposed between adjacent dielectric layers along the first axis, It has an intermediate region disposed between the dielectric layer and the internal electrode layer, The dielectric layer is of the general formula ABO 3-α A compound represented by (0≦α≦1) having a perovskite-type structure, and containing additive elements, The internal electrode layer contains base metal elements and tellurium as its main components. The aforementioned intermediate region contains the aforementioned additive element and tellurium, The aforementioned additive elements include one or more elements selected from rare earth elements, and silicon. [Effects of the Invention]

[0010] According to this disclosure, it is possible to provide a multilayer ceramic capacitor with excellent lifespan characteristics. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 is a partial cross-sectional perspective view illustrating a multilayer ceramic capacitor according to one aspect of the present disclosure. [Figure 2] Figure 2 is a cross-sectional view illustrating an example of a multilayer ceramic capacitor according to one aspect of the present disclosure. [Figure 3]FIG. 3 is a cross-sectional view illustrating a multilayer ceramic capacitor according to an aspect of the present disclosure. [Figure 4] FIG. 4 is an enlarged view of region C in FIG. 2. [Figure 5] FIG. 5 is an explanatory diagram of a method for specifying the presence or absence of an intermediate region. [Figure 6] FIG. 6 is the evaluation result of TEM-EDX in Example 1-1. [Figure 7] FIG. 7 is an explanatory diagram of the relationship between the maximum concentration of tellurium in the intermediate region, the life characteristics, and the capacitance. [Figure 8] FIG. 8 is a flowchart of a method for manufacturing a multilayer ceramic capacitor according to an aspect of the present disclosure. [Figure 9] FIG. 9 is a diagram illustrating a method for manufacturing a multilayer ceramic capacitor according to an aspect of the present disclosure. [Figure 10] FIG. 10 is a Weibull plot showing the relationship between the time until failure and the cumulative failure rate for Examples and Comparative Examples.

MODE FOR CARRYING OUT THE INVENTION

[0012] Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In this specification and the drawings, components having substantially the same functional configuration may be denoted by the same reference numerals, and redundant description may be omitted. In the drawings, an X-axis, a Y-axis, and a Z-axis that are orthogonal to each other are shown as appropriate. The X-axis, Y-axis, and Z-axis define a fixed coordinate system fixed to the multilayer ceramic capacitor. The X-axis, Y-axis, and Z-axis can correspond to the length, width, and height of the multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component, when the outer shape thereof is substantially a rectangular parallelepiped.

[0013] [Multilayer Ceramic Capacitor] (1) Regarding the structure of the multilayer ceramic capacitor Figure 1 is a partial cross-sectional perspective view illustrating a multilayer ceramic capacitor 100. Figures 2 and 3 are cross-sectional views illustrating a multilayer ceramic capacitor. Figure 2 is a cross-sectional view along line AA in Figure 1. Figure 3 is a cross-sectional view along line BB in Figure 1. As illustrated in Figures 1 to 3, the multilayer ceramic capacitor 100 comprises a body 10 having a substantially rectangular parallelepiped shape. In the body 10, two opposing surfaces are referred to as the top surface and the bottom surface, and the four surfaces connecting the top surface and the bottom surface are referred to as sides. Usually, the surface on the circuit board side when the multilayer ceramic capacitor is mounted on a circuit board is referred to as the bottom surface, but this is not limited to this. In the example of Figures 1 to 3, the body 10 has a first external electrode 20a and a second external electrode 20b provided on the two opposing sides, the first side 10a and the second side 10b (see Figure 2). The first external electrode 20a extends from the first side 10a to the four adjacent surfaces. The second external electrode 20b extends from the second side surface 10b to four adjacent surfaces. However, the first external electrode 20a and the second external electrode 20b are spaced apart from each other. The external electrodes may be provided on any surface of the base body 10, not limited to two opposing sides.

[0014] The stacking direction in which the dielectric layer 11 and the internal electrode layer 12 are stacked is the first axis. In Figures 1 to 3, the first axis, which is the stacking direction between the dielectric layer 11 and the internal electrode layer 12, is the Z axis, and is the direction in which each internal electrode layer faces the other.

[0015] The axis perpendicular to the first axis, which is the stacking direction, is the second axis. In Figures 1 to 3, the second axis, which is perpendicular to the first axis, which is the stacking direction, is the X-axis. The second axis runs along the length of the base body 10 and is the axis that runs along the direction in which the first side surface 10a and the second side surface 10b of the base body 10 face each other, and the direction in which the first external electrode 20a and the second external electrode 20b face each other.

[0016] The axis perpendicular to the first axis, which is the stacking direction, and perpendicular to the second axis is the third axis. The third axis is the axis along the width of the internal electrode layer 12. In Figures 1 to 3, the third axis, which is perpendicular to the first axis, which is the stacking direction, and perpendicular to the second axis, is the Y axis. The third axis is the axis along the direction in which the third side 10c and the fourth side 10d, which are two of the four sides of the base body 10 other than the first side 10a and the second side 10b, face each other (see Figure 3). The X axis, Y axis, and Z axis are orthogonal to each other.

[0017] The stacking direction is not limited to the Z direction, but can be any direction. For example, the first axis, which is the stacking direction, may be the X-axis in the X direction, or the Y-axis in the Y direction.

[0018] In this specification, while diagrams illustrating a specific embodiment may be used to describe a general embodiment, the coordinate system used in one embodiment is interpreted and applied in a general embodiment as a general coordinate system with the stacking direction as the first axis. For example, what is described as the X, Y, and Z axes in Figures 1 to 3, where the stacking direction coincides with the Z direction as a specific embodiment, can be interpreted and applied in a general embodiment as the second, third, and first axes.

[0019] The element 10 has a structure in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 are alternately stacked. The internal electrode layers 12 comprise a plurality of first internal electrode layers 12a and a plurality of second internal electrode layers 12b. The first internal electrode layers 12a and the second internal electrode layers 12b are alternately stacked. The edges of the first internal electrode layers 12a are led out to the surface of the element 10 on which the first external electrode 20a is provided, in the example of Figures 1 to 3, to the first side surface 10a. The edges of the second internal electrode layers 12b are led out to the surface of the element 10 on which the second external electrode 20b is provided, in the example of Figures 1 to 3, to the second side surface 10b. As a result, the first internal electrode layers 12a and the second internal electrode layers 12b are alternately conductive to the first external electrode 20a and the second external electrode 20b. Therefore, the multilayer ceramic capacitor 100 has a structure in which capacitor units are stacked. Furthermore, in the laminate of the dielectric layer 11 and the internal electrode layer 12, the internal electrode layer 12 is arranged as the outermost layer in the stacking direction, and the outer surfaces of the laminate in the stacking direction, in the examples of Figures 1 to 3, the top and bottom surfaces, are covered by a cover layer 13. The cover layer 13 mainly consists of a ceramic material. For example, the composition of the cover layer 13 may be the same as or different from that of the dielectric layer 11. Note that the configuration is not limited to that shown in Figures 1 to 3, as long as the first internal electrode layer 12a and the second internal electrode layer 12b are exposed in different regions of the surface of the laminate and conduct to different external electrodes. Different regions of the surface of the laminate may be the respective surface regions of opposing faces of the laminate, the respective surface regions of adjacent faces of the laminate, or different surface regions of the same face of the laminate. As long as the different external electrodes are spaced apart from each other, the first internal electrode layer 12a and the second internal electrode layer 12b may extend from the surface exposed to the surface region of the laminate to other surfaces.

[0020] As will be explained in more detail later, the base body 10 has multiple intermediate regions 40 (see Figure 4) between the dielectric layer 11 and the internal electrode layer 12. The intermediate regions 40 are not shown in Figures 1 to 3.

[0021] The size of the multilayer ceramic capacitor 100 is not particularly limited, but for example, it may be 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height; 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height; 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height; 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height; 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height; or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height. However, the sizes listed above for the multilayer ceramic capacitor 100 are merely examples, and the multilayer ceramic capacitor is not limited to the above sizes. The size of the multilayer ceramic capacitor 100 may be, for example, length > width ≥ height, width > length ≥ height, height > length ≥ width, or height > width ≥ length. For example, length represents the size in the X-axis direction, width represents the size in the Y-axis direction, and height represents the size in the Z-axis direction.

[0022] As described above, the multilayer ceramic capacitor 100 of this embodiment has a plurality of dielectric layers 11 stacked along the first axis, the Z-axis, and a plurality of internal electrode layers 12 each positioned between adjacent dielectric layers 11 along the first axis. Furthermore, the multilayer ceramic capacitor 100 of this embodiment has an intermediate region 40 positioned between the dielectric layers 11 and the internal electrode layers 12. The dielectric layers 11, internal electrode layers 12, and intermediate region 40 will be described below. (2) Regarding the dielectric layer The dielectric layer 11 is of the general formula ABO 3-α The compound is represented as (0≦α≦1), has a perovskite-type structure, and contains additive elements. (2-1) Components contained in the dielectric layer (Compounds having a perovskite-type structure) In the case of a compound having a perovskite structure, when in the stoichiometric composition, α representing an amount deviating from the stoichiometric composition is 0 and it is represented by the general formula ABO3. A compound having a perovskite structure represented by the above general formula may have α greater than 0 and less than or equal to 1. That is, a compound having a perovskite structure represented by the above general formula may be deficient in oxygen compared to the stoichiometric composition.

[0023] As compounds having a perovskite structure, barium titanate (BaTiO3), calcium zirconate (CaZrO3), calcium titanate (CaTiO3), strontium titanate (SrTiO3), magnesium titanate (MgTiO3), Ba forming a perovskite structure 1-x-y Ca x Sr y Ti 1-z Zr z One or more selected from O3 (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1) etc. can be used.

[0024] Ba 1-x-y Ca x Sr y Ti 1-z Zr z O3 includes barium strontium titanate, barium calcium titanate, barium zirconate, barium titanium zirconate, calcium titanium zirconate, and barium calcium titanium zirconate, etc. Note that a compound having a perovskite structure may contain oxygen deficiency in any material case.

[0025] The dielectric layer 11 preferably contains barium titanate as a compound having a perovskite-type structure, as it has particularly excellent dielectric properties. It may contain barium titanate as the main component, or it may consist solely of barium titanate. Barium titanate has excellent dielectric properties, such as an extremely high dielectric constant and low dielectric loss. Therefore, by containing barium titanate as a compound having a perovskite-type structure in the dielectric layer 11, the capacitance of the multilayer ceramic capacitor 100 can be increased. In this specification, "contained as the main component" means that it is contained in the largest amount of substance among the contained components.

[0026] Furthermore, the dielectric layer 11 may contain a compound having a perovskite-type structure as a main component. The dielectric layer 11 may contain, for example, 50 mol% or more of the compound having a perovskite-type structure, or 90 mol% or more. (Additional element) The dielectric layer 11 may further contain additive elements. These additive elements may be present in their elemental form or may form compounds with other elements.

[0027] The inclusion of additive elements in the dielectric layer 11 can extend the lifespan of the multilayer ceramic capacitor 100. In other words, the inclusion of additive elements in the dielectric layer 11 can improve the lifespan characteristics of the multilayer ceramic capacitor 100.

[0028] It has been confirmed that increasing the amount of additive elements added to the dielectric layer 11 improves the lifespan characteristics of the multilayer ceramic capacitor, and that the same trend is observed even when the dielectric layer 11 is made thinner. However, it is preferable to select the amount of additive elements according to the firing conditions during the manufacturing of the multilayer ceramic capacitor and the required lifespan characteristics, so that the additive elements are not unevenly distributed within the dielectric layer 11.

[0029] The proportion of additive elements contained in the dielectric layer 11 is not particularly limited and can be added and contained in an amount that allows for the formation of intermediate regions, as described later, depending on the required life characteristics of the multilayer ceramic capacitor.

[0030] The type of additive elements contained in the dielectric layer 11 is not particularly limited, but it may contain one or more elements selected from rare earth elements, as well as silicon, as additive elements.

[0031] Among the additive elements, rare earth elements include one or more selected from lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb).

[0032] The form in which silicon is added as an additive element is not particularly limited. Silicon may be included in its elemental form, or it may form compounds with other elements. (Additives) The dielectric layer 11 may also contain additives as optional components.

[0033] The additives that the dielectric layer 11 can contain are not particularly limited, but examples include oxides containing one or more elements selected from zirconium (Zr), magnesium (Mg), molybdenum (Mo), vanadium (V), chromium (Cr), scandium (Sc), and yttrium (Y), or oxides containing one or more elements selected from cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), and potassium (K), or glass containing one or more elements selected from cobalt, nickel, lithium, boron, sodium, and potassium. (2-2) Regarding the thickness of the dielectric layer The thickness of the dielectric layer 11 is not particularly limited. From the viewpoint of miniaturizing the multilayer ceramic capacitor 100 while increasing the number of layers to increase the capacitance, the thickness of the dielectric layer 11 is preferably 1.0 μm or less, and more preferably 0.8 μm or less.

[0034] By reducing the thickness of the dielectric layer 11 to 1.0 μm or less, the multilayer ceramic capacitor 100 can be miniaturized while increasing its capacitance. The multilayer ceramic capacitor of this embodiment has excellent insulation reliability, and even when the thickness of the dielectric layer 11 is reduced to 1.0 μm or less, it exhibits superior lifespan characteristics compared to conventional multilayer ceramic capacitors.

[0035] The minimum thickness of the dielectric layer 11 is not particularly limited, but from the viewpoint of improving productivity and yield, it can be set to a minimum of 2 to 4 times the average diameter of the dielectric material particles used. For example, if the average diameter of the dielectric material particles used is 0.1 μm, the minimum thickness of the dielectric layer 11 can be 0.2 μm or more and 0.4 μm or less, and the thickness of the dielectric layer 11 may be, for example, 0.2 μm or more, or 0.4 μm or more.

[0036] The particle size of dielectric material particles can be defined as the Heywood diameter (the diameter of a circle with an area equal to the area of ​​the dielectric material particle being evaluated) at the observed cross-section. The average diameter, which is the average value of the dielectric material particle sizes, can be defined as the arithmetic mean of the particle sizes of 50 to 200 arbitrarily selected dielectric material particles.

[0037] When evaluating the thickness of the dielectric layer 11, the evaluation can be performed in a cross-section that includes a first axis equal to the stacking direction. For example, it is preferable to evaluate in a cross-section that further includes a second axis set perpendicular to the stacking direction, or a cross-section that further includes a third axis set perpendicular to both the stacking direction and the second axis, due to the ease of polishing and measurement. In the former case, the multilayer ceramic capacitor 100 is polished in the third axis direction, and in the latter case, in the second axis direction. Five layers are selected from the central part, upper end, and lower end of the exposed dielectric layer 11 in the first axis direction. If the number of dielectric layers 11 is even, six layers are selected from the central part. Then, for each selected dielectric layer, the thickness is measured at three locations: the central part, the left end, and the right end, and the average of the measured thicknesses is taken as the thickness of each dielectric layer 11. Furthermore, the average of the thicknesses of all selected and evaluated dielectric layers 11 can be taken as the thickness of the dielectric layer 11 in the multilayer ceramic capacitor 100.

[0038] In the examples shown in Figures 1 and 2, the first axis, which is the stacking direction, is the Z-axis direction. Therefore, the multilayer ceramic capacitor 100 is polished along the third axis, the Y-axis, to expose the XZ plane where the dielectric layer 11 and the internal electrode layer 12 are stacked.

[0039] In this case, five dielectric layers 11 located in the center along the first axis (Z axis) of the exposed XZ plane are selected, and five dielectric layers 11 each are selected at the upper and lower ends along the first axis (Z axis). If the number of dielectric layers 11 is even, six layers may be selected for the central part. In this case, the dielectric layers 11 to be selected are selected from within the capacitance section 14.

[0040] Then, for each of the selected dielectric layers 11, the thickness is measured at three points along the second axis, the X-axis, at distances of 1 / 4, 1 / 2, and 3 / 4 of the length of the dielectric layer 11 along the X-axis from the edge, and the average value of these measurements is taken as the thickness of the dielectric layer 11. The same procedure is used to measure the thickness of all the selected dielectric layers 11 and evaluate the average value to obtain the thickness of the dielectric layers 11 in the multilayer ceramic capacitor 100.

[0041] The thickness of the dielectric layer 11 and the thickness of the internal electrode layer 12, described later, are measured from cross-sectional observation images of the multilayer ceramic capacitor 100. Since the intermediate region 40 is not clearly visible externally, when measuring the thickness of the dielectric layer 11 and the internal electrode layer 12, the measurement is performed based on the boundary between the dielectric layer 11 and the internal electrode layer 12 that can be visually confirmed. Therefore, the thickness of the dielectric layer 11 and the thickness of the internal electrode layer 12, described later, also include the intermediate region 40. (3) Regarding the internal electrode layer (3-1) Components contained in the internal electrode layer As illustrated in Figure 2, the region where the first internal electrode layer 12a connected to the first external electrode 20a and the second internal electrode layer 12b connected to the second external electrode 20b face each other is a region in the multilayer ceramic capacitor 100 where capacitance is generated. Therefore, the region where capacitance is generated is referred to as the capacitance region 14. In other words, the capacitance region 14 is a region where adjacent internal electrode layers face each other across a dielectric layer 11 connected to different external electrodes.

[0042] The region where the first internal electrode layers 12a connected to the first external electrode 20a face each other in the stacking direction without passing through the second internal electrode layer 12b connected to the second external electrode 20b is referred to as the first end margin 15a. Similarly, the region where the second internal electrode layers 12b connected to the second external electrode 20b face each other in the stacking direction without passing through the first internal electrode layer 12a connected to the first external electrode 20a is referred to as the second end margin 15b. Each end margin is a region where internal electrode layers connected to the same external electrode face each other in the stacking direction without passing through internal electrode layers connected to different external electrodes. The first end margin 15a and the second end margin 15b are regions where internal electrode layers 12 with equal potential face each other and are regions where no substantial capacitance is generated.

[0043] The side margin 16 is a region located outside the capacitance portion 14 in the third axis perpendicular to the stacking direction and the second axis, and in the example of Figure 3, in the direction along the Y axis. That is, the side margin 16 is the outer region adjacent to the capacitance portion 14 when viewed from the stacking direction, and is the outer region adjacent to the capacitance portion 14 on the side from which the internal electrode layer 12 is not drawn out. The side margin 16 is also a region that does not generate capacitance. (base metal) The internal electrode layer 12 can contain base metal elements as its main component.

[0044] The internal electrode layer 12 may contain components used in the internal electrode layer of a multilayer ceramic capacitor. In particular, the internal electrode layer 12 may mainly consist of a base metal such as nickel (Ni), tin (Sn), or tungsten (W), or an alloy containing one or more selected from the group of base metals, that is, it may contain the largest amount in terms of molar volume.

[0045] Because it offers excellent electrical properties and reduces costs, the internal electrode layer 12 may contain nickel as a base metal element, or it may contain nickel as the main component.

[0046] The main component of the first internal electrode layer 12a and the main component of the second internal electrode layer 12b may be the same or different. For example, the main components of both the first internal electrode layer 12a and the second internal electrode layer 12b may be the same, namely nickel. (tellurium) According to the inventors' research of the present invention, by including one or more elements selected from rare earth elements, silicon, and tellurium as additive elements in the intermediate region 40 described later, the insulation reliability of the multilayer ceramic capacitor 100 can be improved and its lifespan characteristics can be enhanced. Tellurium can be added to a metal conductive paste or the like to form the internal electrode layer 12 during manufacturing.

[0047] Therefore, the internal electrode layer 12 may also contain tellurium. Furthermore, the tellurium may form compounds with base metal elements contained in the internal electrode layer 12 and be contained within the internal electrode layer 12.

[0048] The proportion of tellurium contained in the internal electrode layer 12 is not particularly limited and can be added and contained in an amount sufficient to form the intermediate region 40. Details of the intermediate region 40 will be described later. (3-2) Regarding the thickness of the internal electrode layer The thickness of the internal electrode layer 12 is not particularly limited, but from the viewpoint of miniaturizing the multilayer ceramic capacitor 100 while increasing the number of layers to increase capacitance, it is preferably 1.0 μm or less, more preferably 0.8 μm or less, and even more preferably 0.6 μm or less.

[0049] The minimum thickness of the internal electrode layer 12 is not particularly limited, but from the viewpoint of improving productivity and yield, it can be set to 0.4 μm or more when formed by printing a metal conductive paste using methods such as screen printing or gravure printing. For example, when formed by thin-film processes such as sputtering or vapor deposition, it can be set to a thinner thickness of 0.1 μm or more than that achieved by printing methods. When evaluating the thickness of the internal electrode layer 12, it can be evaluated in a cross-section that includes a first axis equal to the stacking direction, similar to the evaluation of the thickness of the dielectric layer 11. For example, it is preferable to evaluate in a cross-section that further includes a second axis set perpendicular to the stacking direction, or a cross-section that further includes a third axis set perpendicular to both the stacking direction and the second axis, due to the ease of polishing and measurement.

[0050] The multilayer ceramic capacitor 100 is polished so that the above cross-section is visible, and five layers are selected from the central, upper, and lower ends of the exposed internal electrode layer 12 in the first axial direction. If the number of layers in the internal electrode layer 12 is even, six layers are selected from the central part. Then, the thickness of each selected internal electrode layer 12 is measured at three locations: the central part, the left end, and the right end, and the average of the measured thicknesses is taken as the thickness of each internal electrode layer 12. Furthermore, the average of the thicknesses of all the selected and evaluated internal electrode layers 12 can be taken as the thickness of the internal electrode layer 12 in the multilayer ceramic capacitor 100.

[0051] In the examples shown in Figures 1 and 2, the first axis, which is the stacking direction, is the Z-axis direction. Therefore, the multilayer ceramic capacitor 100 is polished along the Y-axis to expose the XZ plane where the dielectric layer 11 and the internal electrode layer 12 are stacked. In this case, from the XZ plane exposed by polishing, five internal electrode layers 12 located in the center along the first axis (Z-axis) are selected, and five internal electrode layers 12 located at the upper and lower ends along the first axis (Z-axis) are selected. If the number of internal electrode layers 12 is even, six layers may be selected in the central part. In this case, the selected internal electrode layers 12 are selected from within the capacitance section 14.

[0052] Then, for each selected internal electrode layer 12, the thickness is measured at three points along the second axis, the X-axis, at distances of 1 / 4, 1 / 2, and 3 / 4 of the length of the internal electrode layer 12 along the X-axis from the end, and the average value of these measurements is taken as the thickness of the internal electrode layer 12. By the same procedure, the thickness of all selected internal electrode layers 12 is measured, and the average value of the thicknesses of all selected and evaluated internal electrode layers 12 can be taken as the thickness of the internal electrode layers 12 in the evaluated multilayer ceramic capacitor 100. (4) Regarding the intermediate area Figure 4 shows a magnified view of the dielectric layer 11 and the internal electrode layer 12 of the base body 10. Figure 4 is, for example, a magnified view of region C in Figure 2.

[0053] The multilayer ceramic capacitor 100 has an intermediate region 40 disposed between the dielectric layer 11 and the internal electrode layer 12. The intermediate region 40 may contain, as additive elements, one or more elements selected from rare earth elements, as well as silicon and tellurium.

[0054] Since the additive elements have already been explained, we will omit further explanation.

[0055] Figure 4 is a schematic diagram, and therefore the intermediate region 40 is shown as having a constant thickness and as a continuous layer, but it is not limited to this configuration. The intermediate region 40 may be discontinuous, for example, and its thickness may vary depending on the location.

[0056] The presence or absence of the intermediate region 40 can be confirmed by elemental mapping using energy-dispersive X-ray (EDX) analysis with a transmission electron microscope (TEM) or scanning transmission electron microscope (SEM). TEM stands for transmission electron microscope, SEM stands for Scanning Transmission Electron Microscope, and EDX stands for energy dispersive X-ray spectroscopy.

[0057] The presence or absence of the intermediate region 40 can be evaluated in a cross-section that includes the first axis, which is equal to the stacking direction. For example, it is preferable to evaluate in a cross-section that includes either the second axis set perpendicular to the stacking direction, or the third axis set perpendicular to both the stacking direction and the second axis, due to the ease of polishing and measurement. In the examples shown in Figures 1 and 2, the first axis, which is the stacking direction, is the Z-axis direction, so the multilayer ceramic capacitor 100 is polished along the Y-axis, which is the third axis, to expose the XZ plane where the dielectric layer 11 and the internal electrode layer 12 are stacked. The presence or absence of the intermediate region 40 can then be confirmed by performing TEM / SEM-EDX analysis on the sample, which has been thinned to a thickness of about 0.1 μm.

[0058] For example, by observing the area where the dielectric layer 11 and the internal electrode layer 12 are stacked, the presence or absence of the formation of the intermediate region 40 can be determined from the obtained elemental mapping results.

[0059] When TEM / SEM-EDX analysis is performed on the above sample, the distribution region of elements contained in the dielectric layer 11 can be confirmed, as shown in Figure 5(A). In Figure 5(A), the distribution region 51 of titanium is shown, using the case where the dielectric layer 11 contains barium titanate as the dielectric as an example.

[0060] Furthermore, when TEM / SEM-EDX analysis is performed on the above sample, the distribution region of base metal elements contained as the main component in the internal electrode layer 12 can be confirmed, as shown in Figure 5(B). In Figure 5(B), the distribution region 52 of nickel is shown as an example when the internal electrode layer 12 contains nickel as a base metal.

[0061] When the intermediate region 40 is formed, as shown in Figure 5(C), the elemental mapping results for tellurium show that the tellurium distribution region 53 extends beyond the nickel distribution region 52, which is the distribution region of base metal elements that are mainly contained in the internal electrode layer 12. In this case, it is observed that the tellurium distribution region 53 extends to the titanium distribution region 51, which is the distribution region of elements contained in the dielectric material contained in the dielectric layer 11.

[0062] Furthermore, Figures 5(D) and 5(E) show the elemental mapping results for the rare earth elements and silicon, which are the additive elements. As shown in Figures 5(D) and 5(E), the distribution regions 54 for rare earth elements and 55 for silicon can extend beyond the distribution region 51 for titanium, which is the distribution region for elements contained in the dielectric material contained in the dielectric layer 11. In this case, the distribution regions 54 for rare earth elements and 55 for silicon may extend to the distribution region 52 for nickel, which is the distribution region for base metal elements that are mainly contained in the internal electrode layer 12.

[0063] In other words, when elemental mapping of tellurium, rare earth elements, and silicon is performed, if an overlapping region of tellurium distribution 53, rare earth element distribution 54, and silicon distribution 55 occurs near the boundary where the dielectric layer 11 and the internal electrode layer 12 are stacked, it can be determined that an intermediate region 40 has been formed.

[0064] Regarding tellurium, a bias in the elemental distribution may be observed within the tellurium distribution region 53. For example, as shown in Figure 5(C), in the part of the tellurium distribution region 53 that is thought to correspond to the intermediate region 40, an enriched area 531 can be observed where the concentration of tellurium is higher than inside the nickel distribution region 52. Thus, in the region corresponding to the intermediate region 40 shown in Figure 5(C), the tellurium concentration may be higher than inside the nickel distribution region 52, which is thought to correspond to the internal electrode layer 12.

[0065] Regarding rare earth elements and silicon, biases in elemental distribution may be observed in the rare earth element distribution region 54 and the silicon distribution region 55. For example, as shown in Figure 5(D), in the rare earth element distribution region 54, which is thought to correspond to the intermediate region 40, an enriched area 541 can be observed where the concentration of rare earth elements is higher than inside the titanium distribution region 51. Also, as shown in Figure 5(E), an enriched area 551 can be observed where the concentration of silicon is higher than inside the titanium distribution region 51 in the silicon distribution region 55, which is thought to correspond to the intermediate region 40. Thus, in the regions corresponding to the intermediate region 40 shown in Figures 5(D) and 5(E), the concentrations of the additive elements, such as rare earth elements and silicon, may be higher than inside the titanium distribution region 51, which is thought to correspond to the dielectric layer 11.

[0066] If tellurium is not added to the internal electrode layer 12 as in the conventional method, there are no concentrated areas 541 within the rare earth element distribution region 54 where the tellurium concentration is higher than in other areas. Tellurium, together with one or more elements selected from the added rare earth elements and silicon, forms a region that can only be defined as an intermediate region 40.

[0067] The intermediate region 40 only needs to contain one or more elements selected from rare earth elements, silicon, and tellurium as additive elements, and the state of the additive elements and tellurium in the intermediate region 40 is not particularly limited. In the intermediate region 40, the rare earth elements as additive elements, silicon, or both, and tellurium may form compounds, and the rare earth elements as additive elements, silicon, and tellurium may each form compounds with other elements, etc. Also, in the intermediate region 40, at least one of the rare earth elements as additive elements, silicon, and tellurium may exist in an elemental state without forming a compound.

[0068] The intermediate region 40 located between the dielectric layer 11 and the internal electrode layer 12 contains one or more elements selected from rare earth elements, as well as silicon and tellurium, as additive elements, which is thought to increase the height of the electrical barrier between the dielectric layer 11 and the internal electrode layer 12. Therefore, when a voltage is applied to the multilayer ceramic capacitor 100, the voltage applied to the dielectric layer 11 is reduced by the intermediate region 40, making the dielectric layer 11 less susceptible to damage even when the multilayer ceramic capacitor 100 is repeatedly subjected to voltage. As a result, the insulation reliability of the multilayer ceramic capacitor 100 is improved, and its lifespan characteristics are enhanced.

[0069] The components contained in the intermediate region 40 will be explained in "(5) Method for identifying the boundaries between each layer." (5) Method for identifying the boundaries between each layer The dielectric layer 11, the internal electrode layer 12, and the intermediate region 40 can have their boundaries identified and their elemental content analyzed by performing TEM / SEM-EDX analysis.

[0070] TEM / SEM-EDX analysis can be performed using a sample that includes, for example, the vicinity of the interface between the dielectric layer 11 and the internal electrode layer 12.

[0071] TEM / SEM-EDX evaluation can be performed on a cross-section that includes a first axis equal to the stacking direction. For example, evaluation on a cross-section that further includes a second axis set perpendicular to the stacking direction, or a cross-section that further includes a third axis set perpendicular to both the stacking direction and the second axis, is preferable due to the ease of polishing and measurement. In the examples shown in Figures 1 and 2, the first axis, which is the stacking direction, is the Z-axis direction, so the multilayer ceramic capacitor 100 is polished along the Y-axis, which is the third axis, to expose the XZ plane where the dielectric layer 11 and the internal electrode layer 12 are stacked. Then, TEM / SEM-EDX analysis can be performed on the sample that has been thinned to a thickness of about 0.1 μm.

[0072] Here, Figures 6(A) and 6(B) show the results of the TEM-EDX analysis performed in Example 1-1. Figure 6(B) is a magnified view of a portion of Figure 6(A), showing an enlarged view of the range in which the elemental concentration is between 0 and 10 at%.

[0073] In Figures 6(A) and 6(B), the vertical axis shows the concentration, or percentage, of each element among all detected elements. The horizontal axis shows the distance from the starting point of the measurement along the direction of analysis during TEM-EDX analysis. The TEM-EDX analysis shown in Figures 6(A) and 6(B) is the result of line analysis performed along the dotted line D from the measurement starting point 41 to the measurement ending point 42 in Figure 4. Therefore, the distance on the horizontal axis in Figures 6(A) and 6(B) can be said to be the distance from the measurement starting point 41. (Internal electrode layer) As shown in Figure 6(A), the internal electrode layer 12 is a region where the nickel concentration is 55 at% or higher. Therefore, as shown in Figure 6(A), the internal electrode layer 12 is a region where the nickel concentration is 55 at% or higher, with the line L61 passing through point 61 where the nickel concentration is 55 at% as the boundary line. (Dielectric layer) As shown in Figures 6(A) and 6(B), the dielectric layer 11 is a region where the nickel concentration is less than 2 at%. Therefore, as shown in Figures 6(A) and 6(B), the dielectric layer 11 is a region where the nickel concentration is less than 2 at% with respect to the straight line L62 passing through point 62 where the nickel concentration is 2 at%. (middle area) The intermediate region 40 is the region sandwiched between the dielectric layer 11 and the internal electrode layer 12, and as shown in Figures 6(A) and 6(B), it is the region where the nickel concentration is 2 at% or more and less than 55 at%. Therefore, the intermediate region 40 is the region sandwiched between the straight line L61 and the straight line L62.

[0074] As shown in Figure 6(B), within the intermediate region 40, peaks 64 for tellurium, 65 for silicon, and 66 for rare earth elements can be observed, starting from the position closest to the internal electrode layer 12. Note that in Figures 6(A) and 6(B), the measurement results are for a sample using holmium (Ho) as the rare earth element, so the rare earth element peak 66 is the holmium peak.

[0075] The intermediate region 40 may have a first intermediate region 401 and a second intermediate region 402, starting from the position closest to the dielectric layer 11.

[0076] The first intermediate region 401 may contain additive elements, i.e., one or more elements selected from rare earth elements, and silicon. The first intermediate region 401 may contain more additive elements, i.e., one or more elements selected from rare earth elements, and silicon than the second intermediate region 402.

[0077] The second intermediate region 402 may contain tellurium. The second intermediate region 402 may contain more tellurium than the first intermediate region 401.

[0078] The additive elements in the first intermediate region 401 and the second intermediate region 402, namely one or more elements selected from rare earth elements, as well as the content of silicon and tellurium, represent the cumulative values ​​of the concentrations of each element in each region.

[0079] The boundary between the first intermediate region 401 and the second intermediate region 402 can be defined as a straight line L63 passing through point 63, which is the point where the silicon concentration and the tellurium concentration are equal, i.e., the intersection point of the silicon concentration distribution curve and the tellurium concentration distribution curve.

[0080] Therefore, the first intermediate region 401 can be the region enclosed by the line L62 and the line L63. The second intermediate region can be the region enclosed by the line L63 and the line L61. The area on line L63 is included in the first intermediate region 401.

[0081] A first intermediate region 401 containing additive elements, i.e., one or more elements selected from rare earth elements, and silicon, and a second intermediate region 402 containing tellurium can be arranged in order from a position close to the dielectric layer 11. This arrangement increases the height of the electrical barrier between the dielectric layer 11 and the internal electrode layer 12, thereby improving the insulation reliability of the multilayer ceramic capacitor and enhancing its lifespan characteristics.

[0082] The concentration of tellurium in the intermediate region 40 is not particularly limited, but for example, the maximum concentration of tellurium in the intermediate region 40 may be 1 at% or more.

[0083] The maximum concentration of tellurium in the intermediate region 40 refers to the concentration of tellurium at the tellurium peak 64 in the tellurium concentration distribution curve located within the intermediate region 40, as shown in Figure 6(B). Note that the concentration of each element represents the proportion of the amount of substance of all elements detected. In Figures 6(A) and 6(B), the concentration of tellurium is the sum of titanium (Ti), barium (Ba), and oxygen (O) mainly contained in the dielectric layer 11, nickel (Ni) mainly contained in the internal electrode layer 12, and tellurium (Te), the additive elements holmium (Ho), and silicon (Si) contained in the intermediate region 40.

[0084] In other words, the concentration of tellurium C(Te) at each position (distance) in Figures 6(A) and 6(B) is expressed by the following formula. In the formula, Te etc. on the right side represent the content calculated from the intensity of the characteristic X-rays of each element at each position (distance).

[0085] C(Te)=[Te / (Ti+Ba+O+Ni+Te+Ho+Si)]×100 Here, the results of the HALT test on the multilayer ceramic capacitor fabricated under the same conditions as in Example 1-1, except that the maximum concentration of tellurium in the intermediate region 40 was changed, are shown in Figure 7(A) and Table 2.

[0086] For the HALT test, 50 samples of multilayer ceramic capacitors manufactured under the same conditions were prepared. Each of these samples was then subjected to an accelerated lifetime test (HALT). In the HALT test, a voltage of 10V was applied to each of the 50 samples manufactured under the same conditions in a 125°C constant temperature chamber, and the time until insulation degradation was measured.

[0087] During the evaluation, insulation resistance was measured, and if the insulation resistance value fell below 1 MΩ, it was determined that insulation degradation had occurred.

[0088] For the 50 samples evaluated, the time it takes for the cumulative failure rate to reach 50% was evaluated as the time until insulation degradation occurs, i.e., the lifetime, for each sample with the highest concentration of tellurium, and is shown as the HALT value in Figure 6(A). A higher HALT value indicates better lifetime characteristics.

[0089] As shown in Figure 7(A), it can be confirmed that the HALT time increases significantly by setting the maximum concentration of tellurium in the intermediate region 40 to 1 at% or more. In other words, the lifetime characteristics of the multilayer ceramic capacitor can be particularly improved by setting the maximum concentration of tellurium in the intermediate region 40 to 1 at% or more.

[0090] The upper limit of the maximum concentration of tellurium in the intermediate region 40 is not particularly limited. The maximum concentration of tellurium in the intermediate region 40 may be, for example, 4 at% or less, or 3 at% or less.

[0091] Here, Figure 7(B) shows the capacitance evaluation results for a multilayer ceramic capacitor fabricated under the same conditions as in Example 1-1, except that the maximum concentration of tellurium in the intermediate region 40 was changed.

[0092] Capacitance was measured using an LCR meter 24 hours after the multilayer ceramic capacitors being evaluated were left to stand in a 150°C constant temperature bath for 2 hours, then removed to room temperature, and measured at 1 kHz and 1 Vrms.

[0093] As shown in Figure 7(B), it can be confirmed that there is almost no change in the capacitance of the multilayer ceramic capacitor until the maximum concentration of tellurium in the intermediate region 40 reaches approximately 4 at%.

[0094] Therefore, by setting the maximum concentration of tellurium in the intermediate region 40 to 4 at% or less, the proportion of tellurium that does not contribute to improving the capacitance of the multilayer ceramic capacitor can be reduced, thereby increasing the capacitance of the multilayer ceramic capacitor.

[0095] By keeping the maximum concentration of tellurium in the intermediate region 40 below 3 at%, the capacitance of the multilayer ceramic capacitor can be particularly increased.

[0096] Therefore, the maximum concentration of tellurium in the intermediate region 40 may be between 1 at% and 4 at%, or between 1 at% and 3 at%.

[0097] By setting the maximum tellurium concentration in the intermediate region 40 to between 1 at% and 4 at%, the capacitance and lifespan characteristics of the multilayer ceramic capacitor can be improved. By setting the maximum tellurium concentration in the intermediate region 40 to between 1 at% and 3 at%, the capacitance and lifespan characteristics of the multilayer ceramic capacitor can be particularly improved.

[0098] The maximum concentration of tellurium within the regions of the dielectric layer 11 and the internal electrode layer 12 is not particularly limited.

[0099] However, it is preferable that tellurium be mainly contained within the intermediate region 40 in order to improve the lifetime characteristics of the multilayer ceramic capacitor, and it is preferable that it does not diffuse into the dielectric layer 11. For this reason, the maximum concentration of tellurium in the dielectric layer 11 may be, for example, 0.1 at% or less.

[0100] The internal electrode layer 12 is a layer to which tellurium is added during the manufacturing of the multilayer ceramic capacitor 100. Therefore, the maximum concentration of tellurium in the internal electrode layer 12 may be greater than the maximum concentration of tellurium in the dielectric layer 11. However, since it is preferable that the tellurium is sufficiently diffused into the intermediate region 40, the maximum concentration of tellurium in the internal electrode layer 12 may be 1 at% or less, and may be less than the maximum concentration of tellurium in the intermediate region 40.

[0101] [Manufacturing method for multilayer ceramic capacitors] Next, the manufacturing method of the multilayer ceramic capacitor 100 will be described. Figure 8 is a flowchart 80 illustrating the manufacturing method of the multilayer ceramic capacitor 100. Figure 9 is a diagram illustrating the manufacturing method of the multilayer ceramic capacitor 100. (1) Raw material powder preparation process (S1) In the raw material powder preparation process, first, a dielectric material for forming the dielectric layer 11 is prepared. The A-site element and B-site element contained in the dielectric layer 11 are usually ABO 3-α The dielectric layer 11 is contained in the form of a sintered body of particles with (0≦α≦1). For example, barium titanate is a tetragonal compound having a perovskite-type structure and exhibits a high dielectric constant. Barium titanate can generally be obtained by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been conventionally known for synthesizing the main component ceramic of the dielectric layer 11, such as the solid-phase method, the sol-gel method, and the hydrothermal method. In this embodiment, any of these can be employed.

[0102] In the raw material powder preparation process, additive elements and other predetermined additives can be added to the obtained ceramic raw material powder, depending on the purpose.

[0103] Examples of additive elements include one or more elements selected from rare earth elements, and silicon. The additive elements may be added as individual elements or as compounds such as oxides.

[0104] Examples of additives include oxides containing one or more elements selected from zirconium (Zr), magnesium (Mg), molybdenum (Mo), vanadium (V), chromium (Cr), scandium (Sc), and yttrium (Y); oxides containing one or more elements selected from cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), and potassium (K); or glasses containing one or more elements selected from cobalt, nickel, lithium, boron, sodium, and potassium.

[0105] For example, ceramic materials can be prepared by wet-mixing ceramic raw material powder with additive elements or compounds containing additives, followed by drying and pulverization. For example, the ceramic material obtained as described above may be subjected to pulverization as needed to adjust the particle size, or the particle size may be adjusted by combining this with a classification process. A dielectric material can be obtained through the above steps. (2) Dielectric green sheet formation process (S2) In the dielectric green sheet formation process, the raw material powder obtained in the raw material powder preparation process can be wet-mixed with a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer. Alternatively, the binder may be added at the same time as mixing the ceramic raw material powder in the raw material powder preparation process (S1), and then wet-mixed.

[0106] In the dielectric green sheet formation process, the obtained slurry can be used to coat a substrate using, for example, a die coater method or a doctor blade method, and then dried to form a dielectric green sheet. The substrate is, for example, polyethylene terephthalate (PET) film. A diagram illustrating the dielectric green sheet formation process has been omitted.

[0107] In the dielectric green sheet formation process (S2), the general formula ABO 3-α A dielectric material with a perovskite-type structure represented by (0 ≤ α ≤ 1), and a dielectric green sheet containing doped elements can be formed. (3) Internal electrode layer formation process (S3) The first internal electrode layer 12a and the second internal electrode layer 12b may have one or more base metals selected from nickel (Ni), tin (Sn), tungsten (W), and alloys containing these as their main components. The internal electrode layer 12 may also contain tellurium in addition to the above main components.

[0108] The main component of the first internal electrode layer 12a and the main component of the second internal electrode layer 12b may be the same or different. For example, the main components of both the first internal electrode layer 12a and the second internal electrode layer 12b may be the same, namely nickel.

[0109] The metal conductive paste for forming the precursors of the first internal electrode layer 12a and the second internal electrode layer 12b can be prepared by kneading a selected main component, tellurium, an organic binder, and a solvent. Tellurium may be added in elemental form, in the form of a compound such as an oxide, or as an alloy with a base metal.

[0110] In the internal electrode layer formation process, as illustrated in Figure 9(A), a metal conductive paste for forming the internal electrode layer, containing an organic binder, can be printed onto the surface of the dielectric green sheet 91 by screen printing, gravure printing, or the like. Examples of organic binders include ethyl cellulose (EC) and polyvinyl butyral (PVB) resin. This arranges a first internal electrode layer pattern 92a for the first internal electrode layer 12a or a second internal electrode layer pattern 92b for the second internal electrode layer 12b on the surface of the dielectric green sheet 91. Various auxiliary agents, such as dispersants, and ceramic particles as co-materials can also be added to the metal conductive paste. The main component of the ceramic particles is not particularly limited, but it is preferable that it be the same as the main ceramic component of the dielectric layer 11. When ceramic particles are added as co-materials, they can be added during the mixing of the metal conductive paste. The method for forming the internal electrode layer is not limited to printing; plating, vacuum deposition, sputtering, and CVD methods may also be used.

[0111] Alternatively, a dielectric pattern paste for the reverse pattern layer can be obtained by adding a binder such as ethyl cellulose and an organic solvent such as terpineol to the dielectric pattern material obtained in the raw material powder preparation process and kneading it in a roll mill. Then, as illustrated in Figure 9(A), the dielectric pattern 73 may be placed on the dielectric green sheet 91 by printing the dielectric pattern paste in the peripheral area where the internal electrode layer pattern is not printed, thereby filling the step difference with the internal electrode layer pattern. The dielectric green sheet 91 with the internal electrode layer pattern and dielectric pattern 93 printed on it is referred to as a laminated unit. (4) Lamination process (S4) In the lamination process, as illustrated in Figure 9(B), the lamination units can be stacked such that the internal electrode layers and dielectric layers are staggered, and the edges of the internal electrode layers are alternately exposed on both ends of the dielectric layer in the longitudinal direction, leading alternately to a pair of external electrodes. Specifically, a dielectric green sheet 91 printed with a first internal electrode layer pattern 92a and a dielectric pattern 93 is stacked in sequence with a dielectric green sheet 91 printed with a second internal electrode layer pattern 92b and a dielectric pattern 93. For example, the number of layers in the lamination unit can be 100 to 500. (5) Crimping process (S5) In the heat-sealing process, a predetermined number of cover sheets, for example, 2 to 10 layers, can be heat-sealed to the top and bottom of the laminated body in which the laminated units are stacked. (6) Singulation process (S6) In the individualization process, the crimped body is separated into individual pieces, and a laminate of individual pieces can be obtained. Existing methods such as dicing with a dicer or laser cutting can be used as appropriate for individualization. (7) Firing process (S7) In the firing process, the individual laminated pieces can be degreased and then fired. The degreasing and firing processes may be performed consecutively or separately. The conditions for degreasing and firing are not particularly limited. For example, degreasing may be performed in a nitrogen atmosphere at a temperature between 250°C and 500°C.

[0112] For firing, for example, if the oxygen partial pressure is 10 -12 atm over 10 -8 The firing may be carried out in a weakly oxidizing atmosphere or a reducing atmosphere with a temperature range of 1100°C to 1350°C, below atm, for 5 minutes to 10 hours. The oxygen partial pressure is preferably 10 -12 atm over 10 -10 It may also be set to atm or less.

[0113] When a reducing atmosphere is used, one or more reducing gases selected from hydrogen and carbon monoxide can be used. The reducing gas may also be an inert gas, such as nitrogen, or a mixed gas with a noble gas. Examples of noble gases include helium and argon. By using a weakly oxidizing or reducing atmosphere during calcination, an intermediate region containing copper and copper oxide can be formed.

[0114] The firing temperature range is preferably 1150°C to 1350°C. The firing time is preferably 5 minutes to less than 15 minutes. If necessary, a re-oxidation treatment may be performed after firing in a nitrogen atmosphere at 600°C to 1000°C. (8) External electrode formation process (S8) In the external electrode formation process, a metal conductive paste for forming the external electrode layer, containing a base metal such as nickel as a main component, a metal such as copper, and an organic binder, can be formed by screen printing, dipping, etc., and then baked. The method of forming the external electrode is not limited to printing or dipping; plating, vacuum deposition, sputtering, or CVD methods may also be used. Alternatively, a conductive resin paste may be formed by screen printing, dipping, etc., and the resin may be cured. If necessary, layers of copper, nickel, or tin may be formed by plating or other treatments. This allows for the formation of the first external electrode 20a and the second external electrode 20b. Through the above process, a multilayer ceramic capacitor 100 can be manufactured.

[0115] The above process is merely an example, and the manufacturing method of the multilayer ceramic capacitor of this embodiment is not limited to the above configuration. For example, the base layer for the external electrodes can be provided on the surface of the fragmented laminate, and the external electrodes can be formed by firing the ceramic simultaneously with the firing of the base layer for the external electrodes. In this case, in the external electrode formation process after firing, the external electrodes are completed by forming layers of copper, nickel, or tin on top of this base layer through a plating process.

[0116] [Other embodiments] Although embodiments have been described in detail above, this disclosure is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the claims.

[0117] For example, although the above embodiment is applied to a multilayer ceramic capacitor with two terminal electrodes, it may also be applied to a multilayer ceramic capacitor with three or more terminals. [Examples]

[0118] The present invention will be described with specific examples below, but it is not limited to these examples. (1) Evaluation method (1-1) Presence or absence of intermediate region The presence or absence of the intermediate region 40 was confirmed by elemental mapping using energy-dispersive X-ray (EDX) analysis with a transmission electron microscope (TEM). For the evaluation, since the first axis, which is the stacking direction in Figures 1 and 2, is the Z-axis direction, a sample was prepared by polishing the multilayer ceramic capacitor 100 along the Y-axis, which is the third axis, as shown in Figures 1 and 2, to expose the XZ plane where the dielectric layer 11 and the internal electrode layer 12 are stacked. Then, the presence or absence of the intermediate region 40 was confirmed by performing TEM-EDX analysis on the sample, which was thinned to a thickness of approximately 0.1 μm.

[0119] Specifically, we observed the areas where the dielectric layer 11 and the internal electrode layer 12 were stacked, based on the obtained elemental mapping results.

[0120] When an intermediate region 40 is formed, as shown in Figure 5(C), the mapping result for tellurium shows that the tellurium distribution region 53 extends beyond the nickel distribution region 52, which is the distribution region of base metal elements contained as the main component in the internal electrode layer 12. In this case, it is observed that the tellurium distribution region 53 extends to the titanium distribution region 51, which is the distribution region of elements contained in the dielectric contained in the dielectric layer 11. Furthermore, as shown in Figure 5(D), the mapping result for holmium, a rare earth element, shows that the rare earth element distribution region 54 extends beyond the titanium distribution region 51, which is the distribution region of elements contained in the dielectric contained in the dielectric layer 11. Also, as shown in Figure 5(E), the mapping result for silicon shows that the silicon distribution region 55 extends beyond the titanium distribution region 51, which is the distribution region of elements contained in the dielectric contained in the dielectric layer 11.

[0121] In this case, it can be observed that the distribution regions 54 of rare earth elements and 55 of silicon extend to the distribution region 52 of nickel, which is the distribution region of base metal elements that are mainly contained in the internal electrode layer 12.

[0122] In other words, the presence or absence of an intermediate region was determined by performing elemental mapping of tellurium and the added elements. Specifically, an intermediate region 40 was determined to be formed when an overlapping region of tellurium distribution 53, rare earth element distribution 54, and silicon distribution 55 occurred near the boundary where the dielectric layer 11 and the internal electrode layer 12 are stacked.

[0123] In contrast, if at least one of the distribution regions 53 for tellurium, 54 for rare earth elements, and 55 for silicon could not be identified, or if there were no overlapping regions for the distribution regions of each element, it was determined that the intermediate region 40 had not been formed.

[0124] For the evaluation, the multilayer ceramic capacitor 100 was polished, and from the exposed XZ plane, two internal electrode layers 12 located in the center along the first axis (Z axis), and two internal electrode layers 12 located at the upper and lower ends along the first axis (Z axis) were selected. The above observations were then performed over the entire outer circumference of the internal electrode layers 12, near the interface between the selected internal electrode layers 12 and the dielectric layer 11. When selecting internal electrode layers 12 from the upper, center, and lower ends along the first axis (Z axis), the number of first internal electrode layers 12a and second internal electrode layers 12b were selected to be equal. Furthermore, the selected internal electrode layers 12 were selected from within the capacitance section 14.

[0125] In Table 1, the "Intermediate Region" column indicates "Present" if intermediate region 40 was confirmed at any of the evaluated locations, and "Absent" if no intermediate region was confirmed at any of the evaluated locations of the sample.

[0126] In Experimental Example 2, intermediate regions were observed in all of Examples 2-1 through 2-9; therefore, the evaluation results for the presence or absence of intermediate regions are omitted in Table 2. (1-2) Evaluation of elemental concentrations in the dielectric layer, intermediate region, and internal electrode layer For the same samples used to evaluate the presence or absence of intermediate regions, line analysis was performed using TEM-EDX to evaluate elemental concentrations in the dielectric layer, intermediate regions, and internal electrode layers.

[0127] Line analysis was performed along the dotted line D in Figure 4, from the measurement start point 41 to the measurement end point 42, that is, along the stacking direction of the dielectric layer 11 and the internal electrode layer 12, so as to include the portion in which the intermediate region 40 was confirmed when evaluating the presence or absence of the intermediate region.

[0128] The evaluation results for Example 1-1 are shown in Figures 6(A) and 6(B). From the obtained evaluation results, the maximum concentration of tellurium in the dielectric layer 11, the internal electrode layer 12, and the intermediate region 40 was determined.

[0129] Experimental Example 2 shows only the maximum concentration of tellurium in the intermediate region 40, determined from the line analysis results. (1-3) Accelerated life testing For each example and comparative example, 50 samples of multilayer ceramic capacitors were prepared. Accelerated lifetime testing (HALT) was then performed on each of the selected samples. In the HALT test, a voltage of 10V was applied to each of the 50 samples manufactured under the same conditions in a 125°C constant temperature chamber, and the time until insulation degradation was measured.

[0130] During the evaluation, the insulation resistance was measured, and if the insulation resistance value fell below 1 MΩ, it was determined that the insulation had deteriorated, i.e., that the device had failed.

[0131] A Weibull plot showing the relationship between the time to failure and the cumulative failure rate was created and is shown in Figure 10. The time at which the cumulative failure rate reaches 50% is shown in the "HALT value" column of Tables 1 and 2. (2) Sample preparation conditions and evaluation results (2-1) Experimental Example 1 [Example 1-1] (2-1-1) Raw material powder preparation process A multilayer ceramic capacitor was manufactured according to the flowchart 80 shown in Figure 8.

[0132] Specifically, a slurry was first obtained by wet-mixing barium titanate powder, holmium, silicon, polyvinyl butyral (PVB) resin, a solvent, a plasticizer, and glass powder containing a sintering aid. (2-1-2) Dielectric Green Sheet Formation Process The obtained slurry was coated onto a base film, and the slurry coated onto the base film was dried to obtain a dielectric green sheet. (2-1-3) Internal electrode layer formation process Next, a Ni-Te alloy powder containing tellurium in addition to nickel, the main metal element, was wet-mixed with a binder such as ethylcellulose (EC) or polyvinyl butyral (PVB) resin, a solvent, and a plasticizer to obtain a metal conductive paste for forming the internal electrode layer.

[0133] The Ni-Te alloy powder used was an alloy powder containing tellurium at a ratio of 3 at% relative to the total amount of nickel and tellurium.

[0134] Then, a metallic conductive paste was printed onto a portion of the surface of the dielectric green sheet to form an internal electrode layer pattern on each of the dielectric green sheets, containing nickel and tellurium as the main base metal elements.

[0135] A laminated unit was fabricated by the dielectric green sheet formation process and the internal electrode layer formation process described above. The obtained laminated unit comprises a dielectric green sheet and an internal electrode layer pattern formed on the surface of the dielectric green sheet. (2-1-4) Lamination process Next, thirteen stacking units were stacked to form a laminate. (2-1-5) Crimping process, individual piece formation process Then, after the laminate was compressed, it was separated into individual pieces to obtain chip-shaped green laminates. (2-1-6) Firing process Next, this chip-shaped green laminate was degreased in a nitrogen atmosphere at 500°C.

[0136] After degreasing, a metal conductive paste containing nickel-based metal fillers, a binder, and a solvent was applied to the green laminate from both ends to each side as a base layer, and then dried. Subsequently, the green laminate with the base layer for the external electrodes was placed in a firing furnace and fired.

[0137] During the firing process, the oxygen partial pressure is 1.0 × 10⁻⁶. -10 The material was heated to 1300°C for 10 seconds under a reducing atmosphere, which is a mixture of hydrogen and nitrogen at an atm temperature. During the heating process, the supply rate of the green laminate and the oxygen partial pressure were adjusted to prevent abrupt changes in the firing atmosphere due to gases generated from the green laminate and to prevent cracks from forming in the fired product. (2-1-7) External electrode formation process A first external electrode 20a and a second external electrode 20b were formed on the laminated body after firing by plating.

[0138] The resulting multilayer ceramic capacitor had a chip shape of 1.0 mm × 0.5 mm × 0.5 mm, a dielectric layer 11 thickness of 0.8 μm, an internal electrode layer 12 thickness of 0.6 μm, and 13 layers. The thicknesses of the dielectric layer 11 and the internal electrode layer 12 were evaluated using the procedure already described.

[0139] The obtained multilayer ceramic capacitors were evaluated as described above. The elements added to the raw materials during manufacturing, the conditions for adding tellurium, and the evaluation results are shown in Table 1 and Figure 10. [Comparative Example 1-1] In the raw material powder preparation process, holmium and silicon were not added to the raw material powder. Furthermore, in the internal electrode layer formation process, Ni powder was used instead of Ni-Te alloy powder, and tellurium was not added. Except for the above points, a multilayer ceramic capacitor was fabricated and evaluated using the same procedure as in Example 1-1. The elements added to the raw materials during manufacturing, the conditions for adding tellurium, and the evaluation results are shown in Table 1 and Figure 10. [Comparative Example 1-2] In the internal electrode layer formation process, Ni powder was used instead of Ni-Te alloy powder, and tellurium was not added. Except for the above, a multilayer ceramic capacitor was fabricated and evaluated using the same procedure as in Example 1-1. The elements added to the raw materials during manufacturing, the conditions for adding tellurium, and the evaluation results are shown in Table 1 and Figure 10. [Comparative Examples 1-3] In the raw material powder preparation process, holmium and silicon were not added to the raw material powder. Except for the above, a multilayer ceramic capacitor was manufactured and evaluated using the same procedure as in Example 1-1. The elements added to the raw materials during manufacturing, the conditions for adding tellurium, and the evaluation results are shown in Table 1 and Figure 10. [Comparative Examples 1-4] In the raw material powder preparation process, holmium was added to the raw material powder, but silicon was not. Furthermore, in the internal electrode layer formation process, Ni powder was used instead of Ni-Te alloy powder, and tellurium was not added. Except for these points, a multilayer ceramic capacitor was fabricated and evaluated using the same procedure as in Example 1-1. Table 1 shows the elements added to the raw materials during manufacturing, the conditions for adding tellurium, and the evaluation results. Note that the Weibull plot is not shown; only the HALT value (50% failure time) is shown in Table 1. [Comparative Examples 1-5] In the raw material powder preparation process, silicon was added to the raw material powder instead of holmium. Furthermore, in the internal electrode layer formation process, Ni powder was used instead of Ni-Te alloy powder, and tellurium was not added. Except for these points, a multilayer ceramic capacitor was fabricated and evaluated using the same procedure as in Example 1-1. Table 1 shows the elements added to the raw materials during manufacturing, the conditions for adding tellurium, and the evaluation results. Note that the Weibull plot is not shown; only the HALT value (50% failure time) is shown in Table 1. [Comparative Examples 1-6] In the raw material powder preparation process, holmium was added to the raw material powder, but silicon was not. Except for the above, a multilayer ceramic capacitor was fabricated and evaluated using the same procedure as in Example 1-1. Table 1 shows the elements added to the raw materials during manufacturing, the conditions for adding tellurium, and the evaluation results. Note that the Weibull plot is not shown; only the HALT value (50% failure time) is shown in Table 1. [Comparative Examples 1-7] In the raw material powder preparation process, silicon was added to the raw material powder instead of holmium. Except for the above, a multilayer ceramic capacitor was fabricated and evaluated using the same procedure as in Example 1-1. Table 1 shows the elements added to the raw materials during manufacturing, the conditions for adding tellurium, and the evaluation results. Note that the Weibull plot is not shown; only the HALT value (50% failure time) is shown in Table 1.

[0140] [Table 1] According to Table 1, the multilayer ceramic capacitor fabricated in Example 1-1 was found to have an intermediate region. In contrast, the multilayer ceramic capacitors fabricated in Comparative Examples 1-1, 1-2, 1-3, 1-4, 1-5, 1-6, and 1-7 did not have an intermediate region.

[0141] From the results of the above examples and comparative examples, the following was confirmed.

[0142] (Effects of adding rare earth elements) As shown in Figure 10 and Table 1, the results confirm that the lifespan was slightly improved in Comparative Examples 1-2, 1-4, and 1-6, in which rare earth elements were added to the raw materials of the dielectric layer 11, compared to Comparative Example 1-1, in which no rare earth elements were added as additives to the raw materials of either the dielectric layer 11 or the internal electrode layer 12. Considering that there was no difference in lifespan between Comparative Examples 1-2 and 1-4, which did not have tellurium added to the raw materials of the internal electrode layer 12, and Comparative Example 1-6, which did have tellurium added, it can be seen that simply having rare earth elements as additives in the dielectric layer 11 does not provide the lifespan improvement effect of tellurium addition.

[0143] (Effects of silicon addition) As shown in Figure 10 and Table 1, among Comparative Examples 1-2, 1-5, and 1-7, in which silicon was added as an additive element to the raw materials of the dielectric layer 11, only Comparative Example 1-2 showed a slight improvement in lifespan compared to Comparative Example 1-1. In contrast, no improvement in lifespan was observed in Comparative Examples 1-5 and 1-7. Comparative Example 1-1, which was compared, is an example in which no rare earth elements are added as additive elements to the raw materials of either the dielectric layer 11 or the internal electrode layer 12.

[0144] In Comparative Examples 1-2, the improvement in lifespan is thought to be due to the effect of adding rare earth elements to the raw materials of the dielectric layer 11; therefore, it is considered that the lifespan improvement effect of adding silicon to the raw materials of the dielectric layer 11 was not observed. In the cases of Comparative Examples 1-5 and 1-7, it was confirmed that there was no difference in lifespan between Comparative Example 1-5, which did not have tellurium added to the raw materials of the internal electrode layer 12, and Comparative Example 1-7, which did have tellurium added. Therefore, it can be seen that simply adding silicon to the raw materials of the dielectric layer 11 does not provide the lifespan improvement effect of adding tellurium.

[0145] (Effects of adding tellurium) In Comparative Examples 1-3, where tellurium is added to the raw materials of the internal electrode layer, and neither rare earth elements nor silicon are added to the raw materials of the dielectric layer 11, it can be confirmed that no improvement in lifespan is observed compared to Comparative Example 1-1.

[0146] (Combined effect of rare earth element addition, silicon addition, and tellurium addition) In Example 1-1, which has an intermediate region 40 and includes rare earth elements and silicon added to the raw materials of the dielectric layer 11, and tellurium added to the raw materials of the internal electrode layer 12, it was confirmed that the lifetime characteristics were significantly improved compared to any of Comparative Examples 1-1 to 1-7.

[0147] In contrast, in Comparative Examples 1-2, 1-6, and 1-7, in which only two of the additive elements—tellurium and the rare earth elements and silicon—were added to the raw materials, it was confirmed that the improvement in lifespan was not sufficiently obtained compared to Example 1-1. This is thought to be because in Example 1-1, the intermediate region 40 contained the rare earth element silicon contained in the first intermediate region 401 and the tellurium contained in the second intermediate region 402, and the electrical barrier height between the two intermediate regions was increased, thereby improving the insulation reliability. (2-2) Experimental Example 2 [Examples 2-1 to 2-9] In the internal electrode layer formation process, the tellurium content of the Ni-Te alloy powder was changed. Except for the above, the multilayer ceramic capacitor was fabricated and evaluated using the same procedure as in Example 1-1. The evaluation results are shown in Table 2, Figure 7(A), and Figure 7(B).

[0148] Example 2-3 is the same as Example 1-1.

[0149] [Table 2] The method for evaluating capacity and the evaluation results have already been explained, so we will omit further explanation here.

[0150] The aspects of this disclosure are, for example, as follows:

[0151] <1> Multiple dielectric layers stacked along the first axis, A plurality of internal electrode layers are disposed between adjacent dielectric layers along the first axis, It has an intermediate region disposed between the dielectric layer and the internal electrode layer, The dielectric layer is of the general formula ABO 3-α A compound represented by (0≦α≦1) having a perovskite-type structure, and containing additive elements, The internal electrode layer contains base metal elements and tellurium as its main components. The aforementioned intermediate region contains the aforementioned additive element and tellurium, The aforementioned additive elements include one or more elements selected from rare earth elements, and silicon, in a multilayer ceramic capacitor.

[0152] <2> The aforementioned intermediate region comprises, in order from the position closest to the dielectric layer, a first intermediate region and a second intermediate region. The first intermediate region contains more of the additive element than the second intermediate region. The second intermediate region contains more tellurium than the first intermediate region. <1> The multilayer ceramic capacitor described above.

[0153] <3> The internal electrode layer contains nickel as the base metal element. <1> or <2> The multilayer ceramic capacitor described above.

[0154] <4> The dielectric layer contains barium titanate as the compound having the perovskite-type structure. <1> from <3> A multilayer ceramic capacitor as described in any of the following.

[0155] <5> The maximum concentration of tellurium in the aforementioned intermediate region is 1 at% or more. <1> from <4> A multilayer ceramic capacitor as described in any of the following.

[0156] <6> The maximum concentration of tellurium in the aforementioned intermediate region is 1 at% or more and 4 at% or less. <1> from <5> A multilayer ceramic capacitor as described in any of the following.

[0157] <7> The maximum concentration of tellurium in the aforementioned intermediate region is 1 at% or more and 3 at% or less. <1> from <6> A multilayer ceramic capacitor as described in any of the following.

[0158] <8> The thickness of the dielectric layer is 1.0 μm or less. <1> from <7> A multilayer ceramic capacitor as described in any of the following. [Explanation of Symbols]

[0159] 100 Multilayer Ceramic Capacitors 10 Base Body 10a First side 10b Second side 11 Dielectric layer 12 Internal electrode layer 12a 1st internal electrode layer 12b Second internal electrode layer 13. Cover layer 14 Capacity part 15a First end margin 15b Second End Margin 16 Side margins 20a 1st external electrode 20b 2nd external electrode C area 40 Intermediate area 41 Measurement start point 42 Measurement end point D Dotted line 51 Distribution area of ​​titanium 52 Nickel distribution area 53 Distribution area of ​​tellurium 531 Concentrated part 54 Distribution regions of rare earth elements 541 Concentrated part 55 Distribution regions of silicon 541 Concentrated part 61 points L61 straight line 62 points L62 straight line 63 points L63 Straight 64 Peak of Tellurium 65 Silicon peak 66. Peaks of rare earth elements 80 Flowcharts S1 Raw material powder preparation process S2 Dielectric Green Sheet Formation Process S3 Internal electrode layer formation process S4 Lamination process S5 Crimping process S6 singulation process S7 Firing Process S8 External electrode formation process 91 Dielectric Green Sheet 92a First internal electrode layer pattern 92b Second internal electrode layer pattern 93 Dielectric Pattern

Claims

1. Multiple dielectric layers stacked along the first axis, A plurality of internal electrode layers are disposed between adjacent dielectric layers along the first axis, It has an intermediate region disposed between the dielectric layer and the internal electrode layer, The dielectric layer is of the general formula ABO ３－α A compound represented as (0 ≤ α ≤ 1) having a perovskite-type structure, and containing additive elements, The internal electrode layer contains base metal elements and tellurium as its main components. The aforementioned intermediate region contains the aforementioned additive element and tellurium, The aforementioned additive elements include one or more elements selected from rare earth elements, and silicon, in a multilayer ceramic capacitor.

2. The aforementioned intermediate region comprises, in order from the position closest to the dielectric layer, a first intermediate region and a second intermediate region. The first intermediate region contains more of the additive element than the second intermediate region. The multilayer ceramic capacitor according to claim 1, wherein the second intermediate region contains more tellurium than the first intermediate region.

3. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the internal electrode layer contains nickel as the base metal element.

4. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the dielectric layer contains barium titanate as the compound having the perovskite-type structure.

5. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the maximum concentration of tellurium in the intermediate region is 1 at% or more.

6. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the maximum concentration of tellurium in the intermediate region is 1 at% or more and 4 at% or less.

7. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the maximum concentration of tellurium in the intermediate region is 1 at% or more and 3 at% or less.

8. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the thickness of the dielectric layer is 1.0 μm or less.

Images