ATS endpoint optimization for memory workloads

Abstract

We provide a data storage device equipped with an address translation cache (ATC) that enables efficient address translation. [Solution] The data storage device 100 comprises a memory device and a controller coupled to the memory device. The controller dynamically adjusts ATC assignments, selects a configuration of ATC attributes to operate the data storage device, operates the data storage device using the configuration, measures the performance of the data storage device using the configuration, changes from one configuration to a different configuration of ATC attributes based on the measurement, and repeats the operation, measurement, and change process.

Description

Technical Field

[0001] (Field of the Invention) Embodiments of the present disclosure generally relate to improved address translation.

[0002] (Description of Related Art) One use case of a multi-tenancy device is where a solid-state drive (SSD) is shared across multiple tenants (i.e., virtual machines (VMs)) without any hypervisor layer between the SSD and the VMs. There are various optimizations related to memory usage that occur when a host operating system (OS) (e.g., Windows Server) implements paging capabilities. That capability requires address translation service (ATS) and Page Request Interface (PRI) functionality in any peripheral component interconnect express (PCIe) device directly accessed by a guest VM. Moving a memory page means that the device receives a PCIe address that needs to be translated.

[0003] When using ATS + PRI, the translated address can be stored in an address translation cache (ATC). Since the ATC requires a large amount of memory (on the order of several megabytes (MB)) used as a cache buffer and a high-performance lookup operation, ATC features are very expensive. The ATC significantly increases the device's area, cost, and power consumption.

[0004] One approach to effectively utilize ATC is a global ATC, where all clients are served globally without considering client identification (ID). Another approach is a static ATC attribute approach, where the same amount of memory in the cache is allocated to each client. Both approaches face challenges in achieving optimal performance results.

[0005] Improved address translation is needed in this technical field. [Overview of the project]

[0006] Rather than simply providing a global approach to the Address Translation Cache (ATC) that ignores client needs, or a static ATC that ignores performance changes, ATC allocation can be dynamically adjusted. Dynamic allocation optimizes overall system performance by constraining the performance of each individual client as needed. Dynamic approaches involve periodic or strategic decisions on whether the currently used ATC allocation will deliver the desired performance. Dynamic reallocation of the ATC maximizes the efficiency and benefits of the ATC by achieving the best possible performance results for applications and / or workloads.

[0007] In one embodiment, the data storage device comprises a memory device and a controller coupled to the memory device, wherein the controller is configured to select a configuration of address translation cache (ATC) attributes for operating the data storage device, to operate the data storage device using the configuration, to measure the performance of the data storage device using the configuration, and to change from one configuration to a different configuration of ATC attributes based on the measurement, and to repeat the above operation, measurement, and change.

[0008] In another embodiment, the data storage device comprises a memory device and a controller coupled to the memory device, the controller comprising a host interface module (HIM), the HIM including a calibration logic module configured to adjust cache configurations, measure the performance of the data storage device and intelligently select the optimal cache configuration, a performance monitoring module configured to monitor the performance of the data storage device, and an address translation cache (ATC) configuration module configured to maintain one or more cache configurations used for adjustment by the calibration logic module.

[0009] In another embodiment, the data storage device comprises memory means and a controller coupled to the memory means, wherein the controller is configured to measure the performance of the data storage device, modify address translation cache (ATC) attributes based on the measurement, operate the data storage device using the modified ATC attributes, save the ATC attributes, repeat the measurement, modification, operation, and saving process one or more times, select the optimal ATC attributes, and operate the data storage device using the selected optimal ATC attributes. [Brief explanation of the drawing]

[0010] A more detailed description of the Disclosure, which is concisely summarized above, may be obtained by reference to embodiments, some of which are shown in the accompanying drawings, so that the above-mentioned features of the Disclosure may be understood in detail. However, it should be noted that the accompanying drawings show only typical embodiments of the Disclosure and should not be considered to limit its scope, as the Disclosure may allow for other equally valid embodiments. [Figure 1] This is a schematic block diagram showing a storage system in which, according to a particular embodiment, a data storage device may function as a storage device for a host device. [Figure 2]This is a schematic diagram showing a multi-tenancy system that supports ATS functionality according to a specific embodiment. [Figure 3] This is a schematic diagram of ATC attribute calibration according to one embodiment. [Figure 4] This flowchart shows ATC attribute calibration according to one embodiment. [Figure 5] This is a schematic diagram of a system block diagram according to one embodiment. [Figure 6] This is a flowchart illustrating dynamic ATC allocation according to one embodiment.

[0011] For ease of understanding, the same reference numerals are used to designate identical elements common to the drawings where possible. Elements disclosed in one embodiment are intended to be usefully utilized in other embodiments without specific description. [Modes for carrying out the invention]

[0012] The following refers to embodiments of the Disclosure. However, it should be understood that the Disclosure is not limited to the embodiments described herein. Instead, any combination of the following features and elements, whether related to a different embodiment or not, is intended to implement and practice the Disclosure. Furthermore, embodiments of the Disclosure may achieve advantages over other possible solutions and / or prior art, but whether a particular advantage is achieved by a given embodiment does not limit the Disclosure. Accordingly, the following aspects, features, embodiments, and advantages are merely illustrative and shall not be considered elements or limitations of the appended claims unless expressly enumerated in the claims. Similarly, references to “the Disclosure” shall not be construed as a generalization of the subject matter of any invention disclosed herein and shall not be considered elements or limitations of the appended claims unless expressly enumerated in the claims.

[0013] Rather than simply providing a global approach to the Address Translation Cache (ATC) that ignores client needs, or a static ATC that ignores performance changes, ATC allocation can be dynamically adjusted. Dynamic allocation optimizes overall system performance by constraining the performance of each individual client as needed. Dynamic approaches involve periodic or strategic decisions on whether the currently used ATC allocation will deliver the desired performance. Dynamic reallocation of the ATC maximizes the efficiency and benefits of the ATC by achieving the best possible performance results for applications and / or workloads.

[0014] Figure 1 is a schematic block diagram showing a storage system 100 having a data storage device 106 which may function as a storage device for a host device 104 according to a particular embodiment. For example, the host device 104 may store and retrieve data using non-volatile memory (NVM) 110 contained in the data storage device 106. The host device 104 includes host dynamic random access memory (DRAM) 138. In some examples, the storage system 100 may include multiple storage devices, such as the data storage device 106, which may operate as a storage array. For example, the storage system 100 may include multiple data storage devices 106 configured as a redundant array of inexpensive / independent disks (RAID) which collectively function as a high-capacity storage device for the host device 104.

[0015] The host device 104 may store data in and / or retrieve data from one or more storage devices, such as the data storage device 106. As shown in Figure 1, the host device 104 may communicate with the data storage device 106 via the interface 114. The host device 104 may include any of a wide range of devices, including a computer server, a network-attached storage (NAS) unit, a desktop computer, a notebook (i.e., laptop) computer, a tablet computer, a set-top box, a telephone handset such as a so-called "smart" phone, a so-called "smart" pad, a television, a camera, a display device, a digital media player, a video game console, a video streaming device, or other devices capable of sending or receiving data from a data storage device.

[0016] The host DRAM 138 may optionally include a host memory buffer (HMB) 150. The HMB 150 is a portion of the host DRAM 138 allocated to the data storage device 106 for exclusive use by the controller 108. For example, the controller 108 may store mapping data, buffered commands, logical-to-physical (L2P) tables, metadata, etc., in the HMB 150. In other words, the HMB 150 may be used by the controller 108 to store data that would normally be stored in the controller 108's internal memory, such as volatile memory 112, buffers 116, or static random access memory (SRAM). In an example where the data storage device 106 does not include DRAM (i.e., the optional DRAM 118), the controller 108 may utilize the HMB 150 as the DRAM for the data storage device 106.

[0017] The data storage device 106 includes a controller 108, an NVM 110, a power supply 111, volatile memory 112, an interface 114, a write buffer 116, and an optional DRAM 118. In some examples, the data storage device 106 may include additional components not shown in Figure 1 for clarity. For example, the data storage device 106 may include a printed circuit board (PCB) on which the components of the data storage device 106 are mechanically mounted and which includes conductive traces that electrically interconnect the components such as the data storage device 106. In some examples, the physical dimensions and connector configuration of the data storage device 106 may conform to one or more standard form factors. Some exemplary standard form factors include, but are not limited to, 3.5-inch data storage devices (e.g., HDD or SSD), 2.5-inch data storage devices, 1.8-inch data storage devices, peripheral component interconnect (PCI), PCI-extended (PCI-X), and PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe MiniCard, MiniPCI, etc.). In some examples, the data storage device 106 may be directly coupled to the motherboard of the host device 104 (e.g., directly soldered or plugged into a connector).

[0018] Interface 114 may include one or both of the following: a data bus for exchanging data with the host device 104, and a control bus for exchanging commands with the host device 104. Interface 114 may operate according to any preferred protocol. For example, interface 114 may operate according to one or more of the following protocols: advanced technology attachment (ATA) (e.g., serial-ATA (SATA) and parallel-ATA (PATA)), Fibre Channel Protocol (FCP), small computer system interface (SCSI), serially attached SCSI (SAS), PCI, and PCIe, non-volatile memory express (NVMe), OpenCAPI, GenZ, cache-coherent interface accelerator (CCIX), open channel SSD (OCSSD), etc. Interface 114 (e.g., a data bus, a control bus, or both) is electrically connected to the controller 108 to provide an electrical connection between the host device 104 and the controller 108, enabling data to be exchanged between the host device 104 and the controller 108. In some examples, the electrical connection of interface 114 may also allow a data storage device 106 to receive power from the host device 104. For example, as shown in Figure 1, a power supply 111 may receive power from the host device 104 via interface 114.

[0019] The NVM110 may include multiple memory devices or memory units. The NVM110 may be configured to store and / or retrieve data. For example, a memory unit of the NVM110 may receive data and messages from controller 108 instructing the memory unit to store the data. Similarly, a memory unit may receive messages from controller 108 instructing the memory unit to retrieve data. In some examples, each of the memory units may be called a die. In some examples, the NVM110 may include multiple dies (i.e., multiple memory units). In some examples, each memory unit may be configured to store relatively large amounts of data (e.g., 128MB, 256MB, 512MB, 1GB, 2GB, 4GB, 8GB, 16GB, 32GB, 64GB, 128GB, 256GB, 512GB, 1TB, etc.).

[0020] In some examples, each memory unit may include any type of non-volatile memory device, such as flash memory devices, phase-change memory (PCM) devices, resistive random-access memory (ReRAM) devices, magneto-resistive random-access memory (MRAM) devices, ferroelectric random-access memory (F-RAM), holographic memory devices, and any other type of non-volatile memory device.

[0021] The NVM110 may include multiple flash memory devices or memory units. The NVM flash memory devices may include NAND or NOR-based flash memory devices and may store data based on the charge contained in the floating gate of the transistor of each flash memory cell. In an NVM flash memory device, the flash memory device may be divided into multiple dies, each die containing multiple physical or logical blocks, and the multiple physical or logical blocks may be further divided into multiple pages. Each block of multiple blocks in a particular memory device may contain multiple NVM cells. Rows of NVM cells may be electrically connected using word lines to define one of the multiple pages. Each cell in each of the multiple pages may be electrically connected to its respective bit line. Furthermore, the NVM flash memory device may be a 2D or 3D device and may be a single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), or quad-level cell (QLC). The controller 108 writes data to the NVM flash memory device at the page level, reads data from the NVM flash memory device, and erases data from the NVM flash memory device at the block level.

[0022] Power supply 111 may provide power to one or more components of data storage device 106. When operating in standard mode, power supply 111 may use power provided by an external device such as host device 104 to provide power to one or more components. For example, power supply 111 may use power received from host device 104 via interface 114 to provide power to one or more components. In some examples, power supply 111 may include one or more power storage components configured to provide power to one or more components when operating in shutdown mode, such as when power is no longer received from an external device. In this way, power supply 111 may function as an on-board backup power supply. Some examples of one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, etc. In some examples, the amount of power that may be stored by one or more power storage components may be a function of the cost and / or size (e.g., area / volume) of the one or more power storage components. In other words, as the amount of power stored by one or more power storage components increases, the cost and / or size of the one or more power storage components also increases.

[0023] The volatile memory 112 may be used by the controller 108 to store information. The volatile memory 112 may include one or more volatile memory devices. In some examples, the controller 108 can use the volatile memory 112 as a cache. For example, the controller 108 may store cached information in the volatile memory 112 until the cached information is written to the NVM 110. As shown in Figure 1, the volatile memory 112 may consume power received from the power supply 111. Examples of volatile memory 112 include, but are not limited to, random-access memory (RAM), dynamic random-access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.)). Similarly, an optional DRAM 118 may be used to store mapping data, buffered commands, logical-to-physical (L2P) tables, metadata, cached data, etc. In some examples, the data storage device 106 does not include an optional DRAM 118, and is therefore DRAM-less. In other examples, the data storage device 106 includes an optional DRAM 118.

[0024] Controller 108 may manage one or more operations of data storage device 106. For example, controller 108 may manage reading data from NVM 110 and / or writing data to NVM 110. In some embodiments, when data storage device 106 receives a write command from host device 104, controller 108 may initiate a data storage command to store data in NVM 110 and monitor the progress of the data storage command. Controller 108 may determine at least one operating characteristic of storage system 100 and store the at least one operating characteristic in NVM 110. In some embodiments, when data storage device 106 receives a write command from host device 104, controller 108 temporarily stores the data associated with the write command in internal memory or write buffer 116 before transmitting the data to NVM 110. Controller 108 may include a circuit or processor configured to execute a program for operating data storage device 106.

[0025] Controller 108 may include an optional second volatile memory 120. The optional second volatile memory 120 may be similar to volatile memory 112. For example, the optional second volatile memory 120 may be SRAM. Controller 108 may allocate a portion of the optional second volatile memory as a controller memory buffer (CMB) 122 to host device 104. CMB 122 may be directly accessed by host device 104. For example, instead of maintaining one or more transmit queues within host device 104, host device 104 may use CMB 122 to store one or more transmit queues that are normally maintained within host device 104. In other words, host device 104 may generate a command and store the generated command, with or without associated data, in CMB 122, and controller 108 may access CMB 122 to retrieve the stored generated command and / or associated data.

[0026] ATC is a feature in PCIe where data storage devices receive untranslated addresses from a host device, and before those addresses can be used, they must be translated by a translation agent (TA). The TA maintains a table of translated addresses and their corresponding untranslated addresses. The host device, for example, sends a command to an endpoint (i.e., a data storage device), and that command contains an untranslated address. Before using the address, the endpoint must first obtain the translated address. The endpoint interacts with the TA to obtain the translated address. Upon receiving the translated address from the TA, the endpoint uses the translated address and stores the translated address in the ATC.

[0027] To improve performance and reduce overhead on the link, data storage devices negotiate with the TA to obtain a translated address. Before initiating negotiation with the TA, the endpoint first checks if the translated address is in the ATC. If the translated address is in the ATC, the endpoint uses the translated address stored in the ATC. Otherwise, the endpoint begins interacting with the TA.

[0028] In multi-host or multi-tenancy devices, such as when there are multiple functions, multiple physical functions, multiple virtual functions, or multiple hosts within a system, the system uses only a single ATC for all hosts or functions so that all hosts or functions have access to the same ATC. This disclosure provides a method for optimizing the system in terms of performance, quality, and QoS. In other words, this disclosure provides a method for improving performance while managing the ATC.

[0029] As described above, in the case of global ATC, all functions can use the ATC without special policies. For example, data is removed from the ATC based on being least recently used (LRU) or some other criterion. However, in global ATC, there is no space reserved for any particular function. Another approach described above is static ATC attribute, in which case the ATC is initially allocated to a function / host, for example, when a function requires a higher QoS compared to other functions. For functions requiring a higher QoS, perhaps half of the ATC can be allocated to that function and the rest to the remaining functions so that one function can provide better performance compared to other functions. With static ATC attribute, the ATC distribution does not change. This disclosure focuses on dynamic allocation of ATC to improve performance.

[0030] Figure 2 is a schematic diagram showing a multi-tenancy system 200 supporting ATS functionality according to a specific embodiment. The TA services memory translation requests. The ATC is called the translation look-aside buffer (TLB) in the TA. When an ATS-enabled SSD device accesses system memory, the SSD caches the translated address in its internal ATC. The ATC is different from the TLB translation cache used by the host. The ATS-enabled SSD device implements and maintains a specified ATC to minimize performance dependency on the TA and alleviate TA resource pressure.

[0031] Examples of PCIe addresses to be translated include caching of submission queue (SQ) and completion queue (CQ) address ranges, SQ entry decoding which includes standard decoding of data pointers for read or write that immediately submit translation requests, PRP and SGL which decode data pointers and follow linked lists, a translation limit per large command equal to rate-matched PRI translation at the Gen5 bandwidth (BW) maximum, and DIX translation requests for metadata pointers and linked lists of associated addresses.

[0032] ATC functions as a global resource shared among multiple clients, including PCIe functions and applications. Memory device performance and QoS depend on selected attributes of the shared resource. Using an algorithm capable of detecting the optimal ATC attributes for best performance results offers significant advantages.

[0033] As discussed herein, the device is designed to precisely calibrate the ATC attributes, aiming to optimize overall system performance while constraining the performance of each individual client as needed. The dynamic calibration process may be performed at regular intervals or otherwise triggered, ensuring that the current ATC attributes are seamlessly aligned with the current set of workloads, configurations, system conditions, and operational constraints.

[0034] The algorithm not only takes the current environment into account but also analyzes historical data to gain a comprehensive understanding of the system's performance trends over time. By doing so, the algorithm effectively adapts to fluctuating conditions and ensures continuous optimization of ATC attributes.

[0035] At the core of the device is the ability of algorithms to determine and recommend the optimal ATC size and evicting policy for each PCIe function or application. This approach ensures that the unique characteristics and requirements of each client are addressed, contributing to the maximization of overall system performance. The main benefit is to maximize the benefits and efficiency of the ATC by selecting the optimal cache attributes, thereby achieving the best possible performance results for the current application or workload.

[0036] As discussed herein, ATC can be used dynamically by finding the correct attributes for any host or function from an ATC perspective to maximize performance and QoS. Dynamic calibration techniques involve exploring ATC configurations to obtain the optimal configuration, whether ATC starts with a global configuration, static ATC attributes, or something else. For example, one could consider what the ATC size is for any host or function, and what the eviction policy is for any host or function. For example, one host may have one eviction policy, while another host may have a different eviction policy. Optimization involves attempting to explore configurations to find the best configuration for a particular system, where best means obtaining the best performance and best QoS results.

[0037] Figure 3 is a schematic diagram of ATC attribute calibration according to one embodiment. Figure 3 shows several phases that are to be repeated. First, the system, in particular the ATC, is configured based on the eviction policy for all hosts and the size to be allocated to each host is determined. Next, the configuration is put into operation, the results are measured, and after a certain period of time, the configuration is adapted. Collectively, configuring, operating, measuring, and adapting constitute the calibration process. The calibration process is repeated until a point is reached that is sufficiently good for the particular system. In addition, calibration is repeated from time to time to recalibrate the system.

[0038] To perform calibration, there are several parameters to consider, including the maximum allowable bandwidth per client in the system, the namespace used by each client, priority, performance QoS requirements per host, utilization, capacity, frequency, and historical data collected for a particular host.

[0039] As described above, the system may be calibrated from time to time to find the optimal ATC attributes. First, the ATC attributes consist of a set of default parameters. Next, the system is started while performing transmissions over the link. During this time, performance is measured, the results are analyzed, and the configured ATC attributes are adapted. This process is repeated until the optimal configuration is found.

[0040] If the default ATC configuration is global ATC, all clients are initially granted unrestricted access to the ATC by ignoring client IDs. The initial configuration is evaluated as a baseline. The configuration is then systematically adjusted and measured multiple times to investigate potential improvements. The configuration that yields the best results is then selected.

[0041] When defining the optimal cache configuration, several parameters are considered, in particular: the maximum allowable bandwidth per client, the namespace associated with each client, client priority, client usage (e.g., capacity, frequency, etc.), and the collection of historical data on the client.

[0042] It should be noted that the client may be either a physical or virtual PCIe function. In addition, the client may be a specific process address space identifier (PASID) used in a paravirtualized environment to identify a particular application. For the purposes of this disclosure, the virtual function ID, physical function ID, and process address space ID may all be used depending on the use case and host configuration.

[0043] Figure 4 shows a flowchart 400 summarizing a method for calibrating ATC attributes according to one embodiment. At a high level, the process begins by measuring the performance results of a default configuration that does not consider client IDs in ATC management. The configuration is then adjusted and re-evaluated based on these results. The iterative process continues until the optimal configuration is identified and selected for use. Periodic recalibration may occur to maintain optimal performance over time.

[0044] More specifically, the process begins with the initialization in block 402. Next, the system operates with the default configuration of the ATC attributes in block 404. For example, the default might be global ATC. Then, in block 406, the system measures performance based on some traffic, such as read / write commands on the bus. Based on the measurement, and after some time, the ATC attribute configuration is adapted in block 408 based on the results, and then performance is measured in block 410. Next, in block 412, a check is made to see if the last experiment has occurred. If not, the process returns to block 408, where the system adapts and changes the configuration, and then measures the results until the last experiment is complete. Once the last experiment is complete, in block 414, the optimal ATC configuration is selected based on the measured results. The system continues to operate in the selected mode and then checks whether recalibration is beneficial. Recalibration may occur hourly, or occasionally, such as when there is some inefficiency or performance degradation in the results. Based on the decision to recalibrate, the process is repeated again.

[0045] Figure 5 is a schematic diagram of a system block diagram 500 according to one embodiment. Figure 5 is a system block diagram 500 that includes a host interface module (HIM) which includes a calibrated logic performance monitor for measuring results and QoS performance. The HIM also has an ATC attribute configuration which is modified.

[0046] HIM integrates ATC with a dynamic calibration logic module. The calibration logic module actively adjusts the cache configuration, measures performance, and intelligently selects the optimal cache configuration. The goal is to achieve the best performance results tailored to the specific characteristics of the system, workload, and configuration.

[0047] The optimal configuration of ATC can be workload-dependent. Because the optimal configuration of ATC is workload-dependent, reconfiguration may be necessary when there are changes in the workload. Some static configurations can affect the outcome, such as which namespaces are associated with latency-sensitive features, and therefore the result may be to allocate more cache size to those specific features. For example, whether a namespace is SLC, or associated with an SLC that typically performs better than TLC or QLC and therefore requires a larger allocation. Cache size may also be adjusted by adapting evicting policies to specific namespaces. Finally, the frequency of triggering calibration may depend on several attributes. For example, the system may recalibrate if it detects any performance degradation, any changes in the workload, or simply from time to time even if nothing is detected.

[0048] In one embodiment, feature cache allocation is directed by previously analyzed workloads. Such allocation is primarily valuable in enterprise computing use cases where the benefits of ATS in a particular feature can be derived from the analysis of previous I / O transactions.

[0049] In another embodiment, feature cache allocation is influenced by static configuration. For example, a particular namespace associated with a feature might exhibit greater sensitivity to latency and higher allocation for ATS resources. A specific use case involves an automotive multi-host environment where some tenants may be pre-configured to use SLC namespaces. In the automotive multi-host environment example, ATS resource allocation would be weighted towards features predefined to require higher responsiveness.

[0050] In another embodiment, the frequency at which the presented calibration scheme is triggered may be modified according to different factors. For example, calibration may be triggered at a higher rate when the measured performance is relatively low, and at a lower rate when the measured performance is relatively high. A threshold may be provided to determine low / high performance. The value may be continuous.

[0051] The frequency at which calibration is triggered may also depend on external conditions and workload type. When the workload is very demanding and system resources are required to sustain it, calibration may be performed less frequently, while when the workload is less demanding, calibration may be performed more frequently.

[0052] Figure 6 is a flowchart 600 illustrating dynamic ATC assignment according to one embodiment. First, in block 602, initial ATC attributes are selected or set. The initial ATC attributes may be any ATC attribute distribution, to name a few, such as global ATC, static ATC, or simply the last ATC attribute setting used by the system. Once the initial ATC attributes are set, the system operates using those ATC attributes in block 604. Operating it is understood to mean any general operation, such as actual read / write command processing or system-generated dummy commands, to test the ATC attribute settings. The performance of the system operation using the ATC attribute settings is measured.

[0053] Next, system efficiency is determined in block 606. Essentially, a decision is made regarding whether the system is operating as efficiently as possible. If the system is not operating as efficiently as possible, the ATC attributes are changed in block 608, and then the system operates using the new ATC attributes in block 606.

[0054] If the system is operating as efficiently as possible, it continues to operate in block 610 using the same ATC attributes. The system tracks any possible changes and / or whether a time threshold has been exceeded. If any system parameter is changed in block 612, the process returns to block 606; otherwise, the process proceeds to block 614 to determine whether the time threshold has elapsed. If the time threshold has elapsed, the process returns to block 606 and continues; otherwise, it continues to operate in block 610. Note that blocks 612 and 614 may occur in any order, and both blocks do not necessarily need to be present.

[0055] By dynamically allocating ATCs through the selection of optimal cache attributes, the ATC achieves the best possible performance for the current application or workload. Efficiency can be measured in performance while assuming the same ATC size.

[0056] In one embodiment, the data storage device comprises a memory device and a controller coupled to the memory device, wherein the controller is configured to select a configuration of address translation cache (ATC) attributes for operating the data storage device, operate the data storage device using the configuration, measure the performance of the data storage device using the configuration, change from the configuration to a different configuration of ATC attributes based on the measurement, and repeat the above operation, measurement, and change. The configuration is a global ATC configuration. The configuration is a static ATC attribute configuration. The controller is configured to select an active ATC configuration, operate the data storage device using the active configuration, and determine whether recalibration should occur after operating the data storage device using the active ATC configuration. After determining that recalibration should occur, the controller is configured to change from the active ATC configuration to a new configuration of ATC attributes, operate the data storage device using the new configuration, measure the performance of the data storage device using the new configuration, select a new active ATC configuration for the data storage device, and operate the data storage device using the selected new active ATC configuration. The controller is configured to repeat changing to a new configuration, operating with the new configuration, and measuring performance with the new configuration. The controller comprises a Host Interface Module (HIM), and the ATC is located within the HIM. The HIM includes an ATC attribute configuration module, a performance monitoring module, and a calibration logic module. The controller is configured to interact with one or more of the following: virtual functions, physical functions, process address space identification information (ID) (PASID), and combinations thereof. The configuration is weighted towards functions that are predetermined to require higher responsiveness compared to other functions.

[0057] In another embodiment, the data storage device comprises a memory device and a controller coupled to the memory device, the controller comprising a host interface module (HIM), the HIM including a calibration logic module configured to adjust the cache configuration, measure the performance of the data storage device, and intelligently select the optimal cache configuration, a performance monitoring module configured to monitor the performance of the data storage device, and an address translation cache (ATC) configuration module configured to maintain one or more cache configurations used for adjustment by the calibration logic module. The calibration logic module is configured to adjust the cache configuration based on workloads that have been analyzed in the past. The calibration logic module is configured to adjust the cache configuration using pre-configured weights for functions that require higher responsiveness compared to other functions that require lower responsiveness. Calibration performed by the calibration logic module is triggered at a higher rate when the measured performance is below a threshold compared to when the measured performance is above a threshold. Calibration performed by the calibration logic module is triggered based on external conditions and the workload of the function. As the workload increases, the calibration frequency decreases. The module operates dynamically.

[0058] In another embodiment, the data storage device comprises memory means and a controller coupled to the memory means, wherein the controller is configured to measure the performance of the data storage device, modify address translation cache (ATC) attributes based on the measurement, operate the data storage device using the modified ATC attributes, save the ATC attributes, repeat the measurement, modification, operation, and saving process one or more times, select the optimal ATC attributes, and operate the data storage device using the selected optimal ATC attributes. The controller is configured to determine whether recalibration of the ATC attributes should occur, and this determination occurs after the data storage device has been operated using the selected optimal ATC attributes. Measuring, modifying, selecting, and saving occur in the controller's host interface module (HIM).

[0059] While the above applies to embodiments of the present disclosure, other embodiments and further embodiments of the present disclosure can be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the following claims.

Claims

1. A data storage device, Memory devices and, The memory device is coupled to a controller, and the controller is Select the configuration of the address translation cache (ATC) attributes for operating the data storage device, The data storage device is operated using the above configuration. The performance of the data storage device is measured using the above configuration. Based on the above measurement, the configuration is changed from the above configuration to a configuration with different ATC attributes, A data storage device configured to repeat the aforementioned operation, measurement, and modification.

2. The data storage device according to claim 1, wherein the above configuration is a global ATC configuration.

3. The data storage device according to claim 1, wherein the configuration is a static ATC attribute configuration.

4. The aforementioned controller Select the ATC configuration that is currently in operation. The data storage device is operated using the aforementioned operational configuration. The data storage device according to claim 1, configured to determine whether recalibration should occur after operating the data storage device using the operational ATC configuration.

5. After the controller determines that recalibration should occur, The ATC configuration currently in operation is changed to a new configuration of the ATC attributes. The data storage device is operated using the new configuration described above. The performance of the data storage device is measured using the new configuration described above. Select a new operational ATC configuration for the data storage device, The data storage device according to claim 4, configured to operate the data storage device using the selected new operational ATC configuration.

6. The data storage device according to claim 5, wherein the controller is configured to repeatedly perform the changes to the new configuration, the operation using the new configuration, and the measurement of the performance using the new configuration.

7. The data storage device according to claim 1, wherein the controller comprises a host interface module (HIM), and the ATC is located within the HIM.

8. The data storage device according to claim 7, wherein the HIM comprises an ATC attribute configuration module, a performance monitoring module, and a calibration logic module.

9. The aforementioned controller Virtual functions, physical functions, Process Address Space Identifier (ID) (PASID), and The data storage device according to claim 1, configured to interact with one or more of these combinations.

10. The data storage device according to claim 1, wherein the configuration is weighted towards functions that are predetermined to require higher responsiveness compared to other functions.

11. A data storage device, Memory devices and, The memory device is coupled to a controller, the controller comprises a host interface module (HIM), and the HIM is A calibration logic module configured to adjust the cache configuration, measure the performance of the data storage device, and intelligently select the optimal cache configuration, A performance monitoring module configured to monitor the performance of the data storage device, A data storage device comprising: an address translation cache (ATC) configuration module configured to maintain one or more cache configurations used for the adjustment by the calibration logic module.

12. The data storage device according to claim 11, wherein the calibration logic module is configured to adjust the cache configuration based on previously analyzed workloads.

13. The data storage device according to claim 11, wherein the calibration logic module is configured to adjust the cache configuration using pre-configured weights for functions requiring higher responsiveness compared to other functions requiring lower responsiveness.

14. The data storage device according to claim 11, wherein the calibration performed by the calibration logic module is triggered at a higher rate when the measured performance is below the threshold compared to when the measured performance is above the threshold.

15. The data storage device according to claim 11, wherein the calibration performed by the calibration logic module is triggered based on external conditions and functional workload.

16. The data storage device according to claim 15, wherein the calibration frequency decreases as the workload increases.

17. The data storage device according to claim 11, wherein the module operates dynamically.

18. A data storage device, Memory means and The system comprises a controller coupled to the memory means, and the controller is The performance of the aforementioned data storage device is measured, Based on the above measurement, the Address Translation Cache (ATC) attribute is changed, The data storage device is operated using the modified ATC attributes, The aforementioned ATC attributes are saved, Repeat the above measurement, modification, operation, and saving process one or more times. Select the optimal ATC attribute, A data storage device configured to operate the data storage device using the selected optimal ATC attributes.

19. The data storage device according to claim 18, wherein the controller is configured to determine whether a recalibration of the ATC attributes should occur, and the determination occurs after the data storage device has been operated using the selected optimal ATC attributes.

20. The data storage device according to claim 18, wherein the measurement, modification, selection, and saving occur in the host interface module (HIM) of the controller.

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