Memory device, its operation method, and memory system

Abstract

This invention provides a memory device, a method for operating the same, and a memory system. [Solution] The present disclosure provides a memory device, a method of operating the same, and a memory system. The memory device comprises a memory cell array and peripheral circuits coupled to the memory cell array. The method of operating the memory device includes receiving a first instruction instructing to write dummy data to a specified location in the memory cell array, generating dummy data to be written in response to the first instruction, and writing the dummy data to be written to the specified location.

Claims

1. A memory device, Memory cell array and The array comprises a peripheral circuit coupled to the memory cell array, and the peripheral circuit is Upon receiving a first command instructing that dummy data be written to a specified location in the memory cell array, In response to the first instruction, the dummy data to be written is generated, A memory device configured to write the dummy data to be written to the specified location.

2. The first instruction described above is composed of a set feature command, or The memory device according to claim 1, wherein the first instruction includes a first flag set on the reserved field of the write command.

3. When the first instruction is composed of the set feature command, the command in which the first instruction is placed does not include the dummy data to be written. When the first instruction includes the first flag set on the reserved field of the write command, the peripheral circuit, The memory device according to claim 2, configured to directly generate the dummy data to be written, without receiving data information included in the write command, in response to the first instruction.

4. The aforementioned peripheral circuitry is To randomly generate the dummy data to be written, or The memory device according to claim 1, configured to generate dummy data to be written in combination with a preset algorithm, according to data stored in a location adjacent to the specified location.

5. The memory device according to claim 4, wherein the preset algorithm relates to the coupling effect between memory cells in the memory cell array.

6. The memory cell array comprises a plurality of memory blocks, each of which comprises a plurality of valid memory pages and a plurality of dummy memory pages. The aforementioned designated location is, At least one of the aforementioned plurality of memory blocks, In one of the memory blocks, at least one of the valid memory pages in an erased state, at least one of the dummy memory pages in one of the memory blocks The memory device according to claim 1, comprising one of the following.

7. The aforementioned designated location is, The memory device according to claim 6, wherein one of the memory blocks includes at least one of the valid memory pages in an erased state, and the memory pages adjacent to the designated location are in a programmed state.

8. The aforementioned peripheral circuitry is Upon receiving a second command instructing to perform a read operation on the data in the memory cell array, Further configured to return the data to be read in response to the second instruction, The memory device according to claim 1, wherein when the data to be read includes the dummy data, a second flag is set on a reserved field in the frame header of the returned data frame, the second flag indicating that the read data includes the dummy data.

9. The aforementioned peripheral circuitry is After writing the dummy data to be written to the specified location, save the specified location. Before returning the data to be read, check whether the address corresponding to the data to be read is within the address range corresponding to the specified location where it is stored. The memory device according to claim 8, further configured to determine that the data to be read contains the dummy data when the address corresponding to the data to be read is within the address range corresponding to the designated location where it is stored.

10. It is a memory system, One or more memory devices according to any one of claims 1 to 9, A memory system comprising a memory controller coupled to the memory device and configured to control the memory device.

11. The memory system according to claim 10, comprising a solid-state disk.

12. It is a memory system, At least one memory device, Memory cell array and A memory device comprising at least one memory device and peripheral circuits coupled to the memory cell array, The memory device is coupled to a memory controller configured to control the memory device, The aforementioned memory controller It is configured to send a first command, the first command comprising a first instruction and a plurality of address instructions, the first instruction instructing to write dummy data to the specified locations corresponding to the plurality of address instructions, The peripheral circuit within the memory device is Upon receiving the aforementioned first command, Generate the dummy data to be written in response to the first command, A memory system configured to write the dummy data to be written to the specified locations corresponding to the plurality of address instructions.

13. The aforementioned memory controller It is configured to send a second command, the second command comprising a second instruction, the second instruction instructing a read operation to be performed on the data in the memory cell array, The aforementioned peripheral circuitry is Upon receiving the second command, Configured to return the data to be read in response to the second instruction, When the data to be read includes the dummy data, a second flag is set on the reserved field of the frame header of the returned data frame, and the second flag indicates that the read data includes the dummy data. The aforementioned memory controller Upon receiving the data to be returned and read, The memory system according to claim 12, further configured to stop receiving the remaining data frame or to not perform a decoding operation on the data to be returned to be read when the returned data frame includes the second flag.

14. The aforementioned memory controller It is configured to send a second command, the second command comprising a second instruction, the second instruction instructing a read operation to be performed on the data in the memory cell array, The aforementioned peripheral circuitry is Upon receiving the second command, Configured to return the data to be read in response to the second instruction, The data to be read includes the dummy data, The aforementioned memory controller Upon receiving the data to be returned and read, The memory system according to claim 12, further configured to discard the data to be read if decoding of the returned data to be read fails.

15. A method for operating a memory device, The steps include receiving a first instruction that instructs writing dummy data to a specified location in the memory cell array of the memory device, A step of generating the dummy data to be written in response to the first instruction, A method of operation, comprising the step of writing the dummy data to be written to the specified location.

16. The first instruction described above is composed of a set feature command, or The operation method according to claim 15, wherein the first instruction includes a first flag set on the reserved field of the write command.

17. When the first instruction is composed of the set feature command, the command in which the first instruction is placed does not include the dummy data to be written. The operation method according to claim 16, wherein when the first instruction includes the first flag set on the reserved field of the write command, in response to the first instruction, the system does not receive the data information included in the write command, but directly generates the dummy data to be written.

18. The step of generating the dummy data to be written is: A step of randomly generating the dummy data to be written, or The operation method according to claim 17, comprising the step of generating dummy data to be written in combination with a preset algorithm according to data stored in a location adjacent to the specified location.

19. The steps include receiving a second instruction that instructs to perform a read operation on the data in the memory cell array, The process further includes the step of returning the data to be read in response to the second instruction, The operation method according to claim 15, wherein when the data to be read contains the dummy data, a second flag is set on a reserved field in the frame header of the returned data frame, the second flag indicating that the read data contains the dummy data.

20. The steps include writing the dummy data to be written to the specified location, and then saving the specified location, Before returning the data to be read, the process includes checking whether the address corresponding to the data to be read is within the address range corresponding to the specified location where it is stored, The operation method according to claim 19, further comprising the step of determining that the data to be read contains dummy data when the address corresponding to the data to be read is within the address range corresponding to the designated location where it is stored.

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