Semiconductor memory

Abstract

To suppress the bending of the laminated structure. [Solution] The semiconductor memory device 1 of the embodiment comprises: a first laminate LM in which a plurality of conductive layers WL are stacked spaced apart from each other; a second laminate LMn arranged at a predetermined depth within the first laminate LM in the stacking direction of the first laminate LM, and stacked at height positions corresponding to the conductive layers WL located within the predetermined depth among the plurality of conductive layers WL, spaced apart from each other; a plurality of pillars PL arranged in a first region MR and extending in the stacking direction within the first laminate LM, with memory cells MC formed at their intersections with at least a portion of the plurality of conductive layers WL; and a plurality of columnar portions HR arranged in a second region SR different from the first region MR and extending in the stacking direction within the first and second laminates LM and LMn, wherein the second laminate LMn is arranged in an island-like manner within the first laminate LM at positions corresponding to one or more of the columnar portions HR when viewed from the stacking direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor memory devices.

Background Art

[0002] When manufacturing a semiconductor memory device such as a three-dimensional non-volatile memory, a process may include alternately stacking a plurality of sacrificial layers and a plurality of insulating layers one by one, and forming a plurality of conductive layers in voids between the insulating layers after removing these sacrificial layers. However, after removing the sacrificial layers, the remaining insulating layers may be bent or the overall structure may be distorted.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to provide a semiconductor memory device capable of suppressing bending and distortion of a stacked structure.

Means for Solving the Problems

[0005] The semiconductor memory device of the embodiment comprises: a first laminate in which a plurality of conductive layers are stacked spaced apart from each other; a second laminate disposed at a predetermined depth within the first laminate in the stacking direction of the first laminate, in which a plurality of first insulating layers are stacked spaced apart from each other at height positions corresponding to conductive layers located within the predetermined depth among the plurality of conductive layers; a plurality of pillars disposed in a first region and extending within the first laminate in the stacking direction, with memory cells formed at their intersections with at least a portion of the plurality of conductive layers; and a plurality of columnar portions disposed in a second region different from the first region and extending within the first and second laminates in the stacking direction, wherein the second laminate is arranged in an island-like manner within the first laminate at positions corresponding to one or more of the columnar portions when viewed from the stacking direction. [Brief explanation of the drawing]

[0006] [Figure 1] A diagram showing a schematic configuration example of a semiconductor memory device according to an embodiment. [Figure 2] A diagram showing an example of the configuration of a semiconductor memory device according to the embodiment. [Figure 3] A diagram showing an example of the configuration of a semiconductor memory device according to the embodiment. [Figure 4] A cross-sectional view illustrating, in sequence, a part of the procedure for manufacturing a semiconductor memory device according to an embodiment. [Figure 5] A cross-sectional view illustrating, in sequence, a part of the procedure for manufacturing a semiconductor memory device according to an embodiment. [Figure 6] A cross-sectional view illustrating, in sequence, a part of the procedure for manufacturing a semiconductor memory device according to an embodiment. [Figure 7] A cross-sectional view illustrating, in sequence, a part of the procedure for manufacturing a semiconductor memory device according to an embodiment. [Figure 8] A cross-sectional view illustrating, in sequence, a part of the procedure for manufacturing a semiconductor memory device according to an embodiment. [Figure 9] A cross-sectional view illustrating, in sequence, a part of the procedure for manufacturing a semiconductor memory device according to an embodiment. [Figure 10]A cross-sectional view illustrating, in sequence, a part of the procedure for manufacturing a semiconductor memory device according to an embodiment. [Figure 11] A cross-sectional view illustrating, in sequence, a part of the procedure for manufacturing a semiconductor memory device according to an embodiment. [Figure 12] An XY cross-sectional view at the height of a selected gate line showing several examples of the configuration of the block layer in a semiconductor memory device according to a modified embodiment 1. [Figure 13] A cross-sectional view showing an example of the configuration of a semiconductor memory device according to a modified example of the embodiment 2. [Figure 14] A cross-sectional view showing a schematic configuration example of a semiconductor memory device according to another modified embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is not limited to the embodiments described below. Furthermore, the components in the embodiments described below include those that are easily conceivable by those skilled in the art or that are substantially the same.

[0008] (Example of semiconductor memory device configuration) Figure 1 is a diagram showing a schematic configuration example of a semiconductor memory device 1 according to an embodiment. More specifically, Figure 1(a) is a cross-sectional view of the semiconductor memory device 1 along the X direction, and Figure 1(b) is a schematic plan view showing the layout of the semiconductor memory device 1.

[0009] However, in Figure 1(a), hatching is omitted for the sake of readability. Also, in Figure 1(a), components that do not necessarily exist in the same cross-section are shown, and some upper-level wiring, etc., are omitted.

[0010] In this specification, both the X direction and the Y direction are directions along the orientation of the plane of the word line WL, and the X direction and the Y direction are orthogonal to each other. Further, the electrical extraction direction of the word line WL may be referred to as the first direction, and this first direction is a direction along the X direction. Further, the direction intersecting the first direction may be referred to as the second direction, and this second direction is a direction along the Y direction. However, since the semiconductor memory device 1 may include manufacturing errors, the first direction and the second direction are not necessarily orthogonal.

[0011] As shown in FIG. 1(a), the semiconductor memory device 1 includes a semiconductor substrate SB provided with an electrode film EL, a source line SL, one or more select gate lines SGS, a plurality of word lines WL, one or more select gate lines SGD, and a peripheral circuit CBA in this order from the lower side of the paper surface.

[0012] A source line SL is disposed on the electrode film EL via an insulating layer 60. A plurality of plugs PG are disposed in the insulating layer 60, and electrical conduction is maintained between the source line SL and the electrode film EL via the plugs PG. Although not shown, electrode pads for supplying power and signals to the semiconductor memory device 1 from the outside are provided in the same layer as the electrode film EL. On the source line SL, a select gate line SGS, a plurality of word lines WL, and a select gate line SGD are stacked in this order to form a laminate LM.

[0013] In this specification, in the laminate LM, the side on which the select gate line SGD is disposed is defined as the upward direction in the semiconductor memory device 1, and the side on which the select gate line SGS is disposed is defined as the downward direction in the semiconductor memory device 1.

[0014] As shown in FIGS. 1(a) and 1(b), a memory region MR is disposed at the central portion in the X direction of the plurality of word lines WL, and staircase regions SR are respectively disposed at both ends in the X direction of the plurality of word lines WL. These memory regions MR and staircase regions SR are divided into a plurality of regions by a plurality of plate-like portions LI extending in the direction along the X direction through the plurality of word lines WL and the like.

[0015] Note that a region including a memory region MR and a staircase region SR, which is disposed between plate-like portions LI adjacent in the Y direction, is called a block region BLK. As will be described later, the memory region MR contains a plurality of memory cells that hold data non-volatilely, and the above-described block region BLK serves as an erasure unit for these data.

[0016] Also, between plate-like portions LI adjacent in the Y direction, a plurality of separation layers SHEd that penetrate the selection gate line SGD and extend in a direction along the X direction are disposed. The plurality of separation layers SHEd extend in a direction along the X direction across the entire memory region MR and reach a part of the staircase regions SR at both ends in the X direction.

[0017] Furthermore, between plate-like portions LI adjacent in the Y direction, one separation layer SHEs that penetrate the selection gate line SGS and extend in a direction along the X direction is disposed. In FIG. 1(b), one separation layer SHEs indicated by a broken line extends in a direction along the X direction across the entire memory region MR and the entire staircase regions SR at both ends in the X direction, and divides the selection gate line SGS in the Y direction.

[0018] The separation layer SHEs is preferably disposed at a position that vertically overlaps with the plurality of separation layers SHEd described above. However, in FIG. 1(b), for the sake of clarity of the drawing, the separation layer SHEs is shown at a position that does not vertically overlap with the separation layer SHEd.

[0019] In the memory region MR, a plurality of pillars PL that penetrate the word line WL and the selection gate lines SGD and SGS in the stacking direction are disposed. The lower end of the pillar PL reaches the source line SL. A plurality of memory cells are formed at the intersection of the pillar PL and the word line WL. Thus, the semiconductor memory device 1 is configured as, for example, a three-dimensional non-volatile memory in which memory cells are three-dimensionally arranged in the memory region MR.

[0020] In the stepped region SR, multiple word lines WL and selection gate lines SGD and SGS are processed and terminated in a stepped manner. As we move away from the memory region MR in the X direction, the multiple word lines WL and selection gate lines SGD and SGS that make up the terrace section move from the upper layer to the lower layer, causing the height of the terrace section to decrease towards the source line SL.

[0021] Furthermore, the aforementioned isolation layer SHEd extends from the memory region MR to the stepped portion of the stair region SR where the selected gate line SGD is processed in a stepped manner. As a result, within a single block region BLK, the selected gate line SGD is separated into multiple regions. In other words, the isolation layer SHEd penetrates the portion above multiple word lines WL, thereby dividing these upper portions into multiple patterns of selected gate line SGD.

[0022] Each terrace section of a layer, composed of multiple word lines WL and selection gate lines SGD and SGS, has contact CCs connected to the word lines WL and selection gate lines SGD and SGS of each layer. One contact CC is connected to each layer of the word lines WL and selection gate lines SGS. For the selection gate lines SGD, one contact CC is connected to each section separated by the isolation layer SHEd per layer.

[0023] Here, within a single block region BLK, multiple contacts CC are positioned on one side of the staircase region SR on both sides in the X direction. Also, looking at one side in the X direction, for example, multiple contacts CC are positioned every two block regions BLK.

[0024] In other words, in the example shown in Figure 1(b), in the block region BLK at the very top of the page, multiple contact CCs are located in the stair region SR on the left side of the page, among the stair regions SR at both ends in the X direction. Furthermore, in the block region BLK one level below and two levels below the above block region BLK, multiple contact CCs are located in the stair region SR on the right side of the page, among the stair regions SR at both ends in the X direction. Moreover, in the block region BLK at the very bottom of the page, multiple contact CCs are again located in the stair region SR on the left side of the page.

[0025] Therefore, as shown in Figure 1(a), the respective contact CCs of the stair region SR at both ends in the X direction belong to different block regions BLK and are not actually located in the same cross-section.

[0026] These contact CCs allow individual stacked word lines WLs to be drawn out. More specifically, these contact CCs apply write voltages and read voltages to memory cells included in the memory region MR at the center of multiple word lines WLs, via word lines WLs located at the same height as the memory cells.

[0027] Multiple word wires WL and selection gate wires SGD, SGS, pillar PL, and contact CC are covered with an insulating layer 50. The insulating layer 50 also extends around these components.

[0028] The semiconductor substrate SB above the insulating layer 50 is, for example, a silicon substrate. Peripheral circuits CBA, including transistors TR and wiring, are arranged on the surface of the semiconductor substrate SB. Various voltages applied to the memory cell from contacts CC are controlled by the peripheral circuits CBA that are electrically connected to these contacts CC. In this way, the peripheral circuits CBA control the electrical operation of the memory cell.

[0029] The peripheral circuit CBA is covered with an insulating layer 40, and by joining this insulating layer 40 with an insulating layer 50 that covers multiple word lines WL, etc., a semiconductor memory device 1 is formed that includes multiple word lines WL, selection gate lines SGD, SGS, pillar PL, contact CC, etc., and the peripheral circuit CBA.

[0030] Next, a detailed example of the configuration of the semiconductor memory device 1 will be described using Figures 2 and 3. Figures 2 and 3 are diagrams showing an example of the configuration of the semiconductor memory device 1 according to the embodiment.

[0031] More specifically, Figure 2(a) is a cross-sectional view along the Y direction in the memory region MR of the semiconductor memory device 1. In Figure 2(a), the structure below the insulating layer 60 and above the insulating layer 53, which will be described later, is omitted.

[0032] Figure 2(b) is an enlarged cross-sectional view of pillar PL at the height of the selection gate lines SGD and SGS. Figure 2(c) is an enlarged cross-sectional view of pillar PL at the height of the word line WL. Figure 2(d) is an enlarged cross-sectional view of columnar portion HR at the height of the word line WL and the selection gate line SGS.

[0033] Figure 2(e) is a cross-sectional view along the X direction in the step region SR of the semiconductor memory device 1. In Figure 2(e), the structure below the insulating layer 60 and above the insulating layer 53, which will be described later, is omitted.

[0034] Figure 3(a) is an XY cross-sectional view at the height of the selection gate line SGD, showing a portion of the memory area MR and the step area SR of the semiconductor memory device 1. Figure 3(b) is a perspective cross-sectional view showing a portion of the lower step area SP, including the selection gate line SGS.

[0035] As shown in Figure 2(a), the source wire SL has a multilayer structure in which, for example, the lower source wire DSLa, the intermediate source wire BSL, and the upper source wire DSLb are stacked on the insulating layer 60 in this order. The intermediate source wire BSL is located below the memory area MR of the stacked body LM.

[0036] The lower source line DSLa, the intermediate source line BSL, and the upper source line DSLb are, for example, polysilicon layers. Of these, at least the intermediate source line BSL may be a conductive polysilicon layer with diffused impurities.

[0037] The source wire SL is connected to the peripheral circuit CBA via the electrode film EL by a through-contact (not shown) that extends from the electrode film EL to the peripheral circuit CBA, through the aforementioned insulating layer 50 on the outside of the laminate LM.

[0038] A laminate LM is placed on the source line SL. The laminate LM comprises laminates LMa and LMb, in which multiple word lines WL and multiple insulating layers OL are alternately stacked one layer at a time.

[0039] The LMa laminate is positioned above the source line SL. Below the bottommost word line WL of the LMa laminate, multiple selectable gate lines SGS0 and SGS1 are arranged in this order from the top of the LMa laminate, via an insulating layer OL. The LMb laminate is positioned on top of the LMa laminate. Above the topmost word line WL of the LMB laminate, multiple selectable gate lines SGD0 and SGD1 are arranged in this order from the top of the LMB laminate, via an insulating layer OL.

[0040] However, the number of layers of these word lines WL and selective gate lines SGD,SGS in the laminate LM is arbitrary. The word lines WL and selective gate lines SGD,SGS are, for example, tungsten layers or molybdenum layers. The insulating layer OL is, for example, a silicon oxide layer.

[0041] The upper surface of the laminate LM is covered with an insulating layer 52. The insulating layer 52 is covered with an insulating layer 53. The insulating layers 52 and 53, together with the insulating layer 51 described later, each constitute a part of the insulating layer 50 in Figure 1.

[0042] As described above, the laminate LM is divided in the Y direction by multiple plate-like portions LI. That is, each of the plate-like portions LI is aligned with each other in the Y direction and extends in a direction along the stacking direction and the X direction of the laminate LM.

[0043] Thus, the plate-like portion LI extends continuously within the laminate LM from one end in the X direction to the other end. Furthermore, the plate-like portion LI penetrates the laminate LM and the upper source line DSLb, and reaches the intermediate source line BSL in the memory region MR.

[0044] Furthermore, the plate-like portion LI has a tapered shape in which its width in the Y direction decreases from the upper end to the lower end, for example. Alternatively, the plate-like portion LI has a bowing shape in which its width in the Y direction is maximum at a predetermined position between the upper end and the lower end, for example.

[0045] Each plate-shaped portion LI includes an insulating layer 54 and a conductive layer 24. The insulating layer 54 is, for example, a silicon oxide layer. The conductive layer 24 is, for example, a tungsten layer or a conductive polysilicon layer. The insulating layer 54 covers the side walls of the plate-shaped portion LI facing each other in the Y direction. The conductive layer 24 is filled inside the insulating layer 54.

[0046] However, instead of the plate-like portion LI described above, a plate-like member filled with an insulating layer may penetrate the laminate LM and extend in a direction along the X direction, thereby dividing the laminate LM in the Y direction.

[0047] Between adjacent plate-like portions LI in the Y direction, multiple isolation layers SHEd are arranged, extending in the direction along the X direction and penetrating the upper portion of the laminate LMb. These isolation layers SHEd are insulating layers 56 such as silicon oxide layers that penetrate the selection gate lines SGD0 and SGD1 and reach the insulating layer OL directly below the selection gate line SGD1.

[0048] In other words, these separation layers SHEd, which penetrate the upper portion of the laminated LMb, extend in the X direction between the plate-like portions LI, dividing the upper portion of the laminated LMb into the aforementioned selected gate lines SGD0 and SGD1.

[0049] Furthermore, between adjacent plate-like portions LI in the Y direction, a single isolation layer SHEs is positioned that penetrates the selection gate lines SGS0 and SGS1, which are the lower layers of the laminate LMa, and extends in a direction along the X direction. The isolation layer SHEs is an insulating layer 57 such as a silicon oxide layer that penetrates the insulating layer OL directly above the selection gate line SGS0, the selection gate lines SGS0 and SGS1, the insulating layer OL between the selection gate lines SGS0 and SGS1, and the insulating layer OL directly below the selection gate line SGS1, and reaches the upper source line DSLb.

[0050] It is preferable that the separation layers SHEs are positioned near the center in the Y direction between adjacent plate-like portions LI. Also, in Figure 2(a), due to drawing constraints, the separation layers SHEs are drawn in a position that does not overlap with the upper separation layers SHEd in the stacking direction. However, as mentioned above, it is preferable that the separation layers SHEs are positioned in a position that overlaps with one of the multiple separation layers SHEd in the stacking direction.

[0051] In the memory region MR, multiple pillars PL are distributed and arranged, penetrating the stacked structure LM, the upper source line DSLb, and the intermediate source line BSL, and reaching the lower source line DSLa.

[0052] Multiple pillars PL are arranged, for example, in a staggered pattern when viewed from the stacking direction of the laminate LM. Each pillar PL has a cross-sectional shape in the direction along the layering direction of the laminate LM, i.e., along the XY plane, such as a circular, elliptical, or oval shape.

[0053] Furthermore, the pillar PL has a tapered shape in the portion that penetrates the laminate LMa and the portion that penetrates the laminate LMb, where the diameter and cross-sectional area decrease from the upper layer side to the lower layer side. Alternatively, the pillar PL has a bowing shape in the portion that penetrates the laminate LMa and the portion that penetrates the laminate LMb, where the diameter and cross-sectional area are maximized at a predetermined position between the upper and lower layers, for example.

[0054] Each of the multiple pillar PLs has a memory layer ME extending in the stacking direction within the laminate LM, a channel layer CN penetrating the laminate LM and connecting to the intermediate source line BSL, a cap layer CP covering the upper surface of the channel layer CN, and a core layer CR that serves as the core material of the pillar PL.

[0055] As shown in Figures 2(b) and 2(c), the memory layer ME has a multilayer structure in which a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN are stacked in that order from the outer periphery of the pillar PL. More specifically, the memory layer ME is located on the side of the pillar PL, except at the depth position of the intermediate source line BSL. The memory layer ME is also located on the bottom surface of the pillar PL, which reaches the depth of the lower source line DSLa.

[0056] The channel layer CN is located inside the memory layer ME, penetrating the stack LM, the upper source line DSLb, and the intermediate source line BSL to the depth of the lower source line DSLa. More specifically, the channel layer CN is positioned on the sides and bottom of the pillar PL, with its outer periphery covered by the memory layer ME. However, a portion of the channel layer CN is in contact with the intermediate source line BSL on its side, thereby electrically connecting it to the source line SL, which includes the intermediate source line BSL. Further inside the channel layer CN is the core layer CR.

[0057] Furthermore, each of the multiple pillars PL has a cap layer CP at its upper end. The cap layer CP is positioned at the upper end of the pillar PL so as to cover at least the upper end of the channel layer CN and is connected to the channel layer CN. The cap layer CP is also connected to the bit wire BL located in the insulating layer 53 via a plug CH located in the insulating layer 52. The bit wire BL extends above the laminate LM in a direction along the Y direction so as to intersect with the drawing direction of the word wire WL.

[0058] In Figure 2(a), plugs CH are connected only to three of the six pillar PLs, each of which is electrically connected to the bit line BL shown in Figure 2(a) and passes through the three separated selection gate lines SGD. The other pillar PLs are connected to other bit lines BL that extend parallel to the bit line BL shown in Figure 2(a) in the Y direction, at positions different from the cross-section shown in Figure 2(a), via plugs CH (not shown in Figure 2(a)).

[0059] The block insulating layer BK and tunnel insulating layer TN of the memory layer ME, as well as the core layer CR, are, for example, silicon oxide layers. The charge storage layer CT of the memory layer ME is, for example, a silicon nitride layer. The channel layer CN and cap layer CP are semiconductor layers, such as polysilicon layers or amorphous silicon layers.

[0060] As shown in Figure 2(c), with the above configuration, memory cells MC are formed in the portions of the pillar PL side surface that face each word line WL. Data is written to and read from the memory cells MC by applying a predetermined voltage from the word line WL.

[0061] Furthermore, as shown in Figure 2(b), a selection gate STD is formed on the side of pillar PL where it faces the selection gate lines SGD0 and SGD1, which are above the word line WL. Also, a selection gate STS is formed on the side of pillar PL where it faces the selection gate lines SGS0 and SGS1, which are below the word line WL.

[0062] By applying predetermined voltages to the selection gate lines SGD and SGS, respectively, the selection gates STD and STS can be turned on or off, thereby selecting or deselecting the memory cell MC of the pillar PL to which the selection gates STD and STS belong.

[0063] As shown in Figure 2(e), the staircase region SR has a staircase section SP in which multiple word lines WL and selection gate lines SGD and SGS are processed in a staircase shape. The staircase section SP shown in Figure 2(e) is the part of the staircase region SR, which is divided into multiple block regions BLK, where the contact CC is located and which has the function of drawing out word lines WL, etc.

[0064] The staircase section SP is covered with an insulating layer 51. The insulating layer 51 reaches, for example, the height of the top layer of the laminate LM, and insulating layers 52 and 53 also cover the upper surface of insulating layer 51. As described above, insulating layer 51 also constitutes a part of the insulating layer 50 in Figure 1.

[0065] Furthermore, in the stepped region SR, the source line SL has an intermediate insulating layer SCO interposed between the upper source line DSLb and the lower source line DSLa, instead of the intermediate source line BSL. The intermediate insulating layer SCO is, for example, a silicon oxide layer.

[0066] Therefore, in the stepped region SR, the plate-like portion LI penetrates the insulating layer 51, the laminate LM, and the upper source wire DSLb to reach the intermediate insulating layer SCO.

[0067] Each contact CC of the staircase section SP penetrates the insulating layer 51, etc., and is connected to the word line WL or the select gate line SGD, SGS directly beneath the insulating layer OL that constitutes each step of the staircase section SP.

[0068] Each contact CC has a tapered shape, for example, where the diameter and cross-sectional area decrease from the upper end to the lower end. Alternatively, the contact CC has a bowing shape, for example, where the diameter and cross-sectional area are maximum at a predetermined position between the upper and lower ends.

[0069] Furthermore, the contact CC has an insulating layer 55 that covers the outer circumference of the contact CC, and a conductive layer 25, such as a tungsten layer or a copper layer, that is filled inside the insulating layer 55.

[0070] The insulating layer 55 is the liner layer of the contact CC. The conductive layer 25 is the core layer that forms the core material of the contact CC and is connected to the upper wiring MX located in the insulating layer 53 via a plug V0 located in the insulating layer 52. This upper wiring MX is electrically connected to the peripheral circuit CBA (see Figure 1) described above.

[0071] With this configuration, the word lines WL of each layer, and the selectable gate lines SGD and SGS of the upper and lower layers of the word lines WL, can be electrically drawn from one end or the other end of the stacked body LM in the X direction. In other words, with the above configuration, a predetermined voltage can be applied to the memory cell MC from the peripheral circuit CBA via the upper layer wiring MX, contact CC, and word lines WL, etc., thereby operating the memory cell MC as a memory element.

[0072] Furthermore, multiple columnar sections HR are distributed within the stepped region SR, penetrating the laminate LM, the upper source line DSLb, and the intermediate insulating layer SCO to reach the lower source line DSLa. These columnar sections HR play a role in supporting the structure when forming the laminate LM from the laminate, which is made up of a sacrificial layer and an insulating layer, during the manufacturing process of the semiconductor memory device 1 described later, and do not contribute to the function of the semiconductor memory device 1.

[0073] Therefore, each of the multiple columnar sections HR is a single insulating layer 59, such as a silicon oxide layer, extending in the lamination direction within the laminate LM, and is not electrically connected to the source wire SL.

[0074] Multiple columnar sections HR are arranged in a staggered or grid pattern, for example, when viewed from the stacking direction of the laminate LM, while avoiding interference with the plate-like sections LI and contact CC. Each columnar section HR has a cross-sectional shape such as a circle, ellipse, or oval shape in the direction along the layering direction of the laminate LM, i.e., along the XY plane.

[0075] Furthermore, the columnar portion HR has a tapered shape in the portion that penetrates the laminate LMa and the portion that penetrates the laminate LMb, where the diameter and cross-sectional area decrease from the upper layer side to the lower layer side. Alternatively, the columnar portion HR has a bowing shape in the portion that penetrates the laminate LMa and the portion that penetrates the laminate LMb, where the diameter and cross-sectional area are maximized at a predetermined position between the upper layer side and the lower layer side.

[0076] At the same height position in the laminate LM, the cross-sectional area of ​​the columnar portion HR in the direction along the XY plane is larger than, for example, the cross-sectional area of ​​the pillar PL in the direction along the XY plane. Also, the pitch between multiple columnar portions HR is larger than, for example, the pitch between multiple pillar PLs, and the arrangement density of columnar portions HR per unit area of ​​the word line WL in the laminate LM is lower than the arrangement density of pillar PL per unit area of ​​the word line WL.

[0077] Thus, by configuring the pillar PL to have a smaller cross-sectional area and a narrower pitch compared to, for example, the columnar portion HR, a large number of memory cells MC can be formed at high density within a laminate LM of a predetermined size, thereby increasing the storage capacity of the semiconductor memory device 1. On the other hand, since the columnar portion HR is used solely to support the laminate LM, by not having a precise configuration with a small cross-sectional area and narrow pitch like, for example, the pillar PL, the processing accuracy required when forming the columnar portion HR can be relaxed.

[0078] As shown in Figures 2(d)(e) and 3, within the laminate LMa, block layers BX are arranged around the lower end of each columnar section HR.

[0079] In addition, Figure 3(a) shows the block layer BX with a dashed line, as well as the contact CC connected to the selection gate line SGD with a dashed line. This is because, if Figure 3(a) is an XY cross-section at the height of the selection gate line SGD of the lowest layer, the block layer BX located in the lower part of the laminate LM and the contact CC located above the height of the selection gate line SGD of the lowest layer are not shown in the cross-section of Figure 3(a).

[0080] Furthermore, the perspective cross-sectional view in Figure 3(b) shows the cross-section in the X direction indicated by arrow A and the cross-section in the Y direction indicated by arrow Y. Also, the stair section SP shown in Figure 3(b) is a part of the stair section SR, which is divided into multiple block sections BLK, where contact CC is not placed and there are no drawer functions such as word lines WL. However, even in the stair section SP which has drawer functions such as word lines WL, the columnar section HR and block layer BX have the same configuration as in Figure 3(b).

[0081] The block layer BX is an insulating layer 57, such as a silicon oxide layer, similar to the separation layer SHEs described above, and extends from the insulating layer OL directly above the selected gate line SGS0, through the lower end of the laminate LMa, to the upper source line DSLb. In other words, the height positions of the upper ends of the separation layer SHEs and the block layer BX in the laminate LMa are approximately equal.

[0082] More specifically, as shown in Figure 3(b), in the stepped section SP, in the region near the memory area MR that includes the portion where the upper selection gate line SGS0 of the multiple selection gate lines SGS0 and SGS1 is processed in a stepped shape, the upper ends of the isolation layer SHEs and the block layer BX each reach, for example, the upper surface of the insulating layer OL directly above the selection gate line SGS0. On the other hand, in the portion where the lower selection gate line SGS1 of the multiple selection gate lines SGS0 and SGS1 is processed in a stepped shape, the upper ends of the isolation layer SHEs and the block layer BX each reach, for example, the upper surface of the insulating layer OL directly above the selection gate line SGS1, and do not extend any further upwards.

[0083] In the region enclosed by these block layers BX, an insulating layer NL, which is a sacrificial layer before the formation of the laminate LM, is placed in place of the selected gate line SGS. That is, within the region enclosed by the block layers BX, a laminated structure LMn of insulating layer NL and insulating layer OL is placed. As a result, the multiple laminated structures LMn placed in the laminate LM are arranged in an island-like manner at positions corresponding to each of the multiple columnar sections HR when viewed from the stacking direction of the laminate LM. In this way, the multiple laminated structures LMn locally surround the lower ends of each of the multiple columnar sections HR when viewed from the stacking direction of the laminate LM.

[0084] The block layer BX surrounding the lower end of each columnar portion HR may have a substantially rectangular shape when viewed from the stacking direction, as shown in the example in Figure 3, or it may have a circular, elliptical, or other shape. Regardless of the shape of the block layer BX, it is preferable that the area of ​​the region enclosed by the block layer BX is less than or equal to the cross-sectional area of ​​the columnar portion HR at the point where the tapered or bowed columnar portion HR has its maximum diameter. That is, it is preferable that the region enclosed by the block layer BX is contained within the outer edge of the columnar portion HR at the point where the columnar portion HR has its maximum diameter when viewed from the stacking direction.

[0085] Furthermore, among the multiple columnar sections HR, the block layer BX may surround only the lower ends of some of the columnar sections HR, and a laminated structure LMn of insulating layer NL and insulating layer OL may be arranged. Also, due to positional misalignment during the formation of the columnar sections HR, some of the columnar sections HR may be arranged to slightly protrude from the area surrounded by the block layer BX. In addition, when the columnar sections HR are arranged near the edge of the terrace portion of a stepped selection gate line SGS, the block layer BX may be arranged across the step between the upper selection gate line SGS and the lower selection gate line SGS.

[0086] Furthermore, the laminated structure LMn, consisting of insulating layer NL and insulating layer OL, located at the lower end of these columnar sections HR, can also be viewed as a second laminate separate from the laminate LM. Even if such a second laminate is formed with the columnar section HR slightly protruding from the area enclosed by the block layer BX, as described above, at least a portion of it will overlap with the columnar section HR when viewed from the lamination direction.

[0087] The following section will continue to use Figure 3(a) to explain in more detail the functions of the isolation layers SHEd and SHEs in the electrical operation of the semiconductor memory device 1.

[0088] Unlike the examples shown in Figures 1(b) and 2(a) above, in Figure 3(a), three separation layers SHEd are arranged between adjacent plate-like sections LI in the Y direction, extending to the stepped region where the selected gate lines SGD0 and SGD1 are processed, separating the selected gate line SGD into four sections in the Y direction. Contact CC is arranged in each of these four sections.

[0089] In other words, of these contact CCs, the four contact CCs aligned in the Y direction near the memory area MR are each connected to different sections of the selected gate line SGD0, while the four contact CCs aligned in the Y direction away from the memory area MR are each connected to different sections of the selected gate line SGD1.

[0090] Furthermore, near the center in the Y direction of adjacent plate-like portions LI in the Y direction, separation layers SHEs are arranged overlapping with separation layer SHEd in the stacking direction. In Figure 3(a), the separation layers SHEs, shown by the dashed lines, extend beyond the region where the selection gate line SGD is processed in a stepped manner, to the region where multiple word lines WL and selection gate line SGS are processed in a stepped manner.

[0091] Furthermore, the memory region MR sandwiched between the upper plate-like portion LI and the adjacent separation layer SHEd will be called region FGa. The memory region MR sandwiched between the separation layer SHEd adjacent to the upper plate-like portion LI and the central separation layer SHEd between the two plate-like portions LI will be called region FGb. The memory region MR sandwiched between the central separation layer SHEd between the two plate-like portions LI and the separation layer SHEd adjacent to the lower plate-like portion LI will be called region FGc. The memory region MR sandwiched between the separation layer SHEd adjacent to the lower plate-like portion LI and the lower plate-like portion LI will be called region FGd.

[0092] In this configuration, when reading data from a predetermined memory cell MC, if the pillar PL to which the memory cell MC to be read belongs is located within region FGa, a predetermined voltage is applied to the selection gate lines SGD0 and SGD1 corresponding to region FGa, and the selection gate STD of all pillar PLs located within region FGa is turned on. In addition, within the region between the two plate-like parts LI, a predetermined voltage is applied to the selection gate lines SGS0 and SGS1 corresponding to the region on the upper side of the paper relative to the isolation layer SHEs, and the selection gate STS of all pillar PLs located within regions FGa and FGb is turned on.

[0093] As a result, all pillars PL within region FGa are selected, with both selection gates STD and STS turned on. Furthermore, the target memory cell MC is identified by the word line WL and bit line BL corresponding to the memory cell MC to be read, and the data is read out.

[0094] Furthermore, if the pillar PL to which the memory cell MC to be read belongs is located within region FGb, a predetermined voltage is applied to the selection gate lines SGD0 and SGD1 corresponding to region FGb, and the selection gate STD of all pillar PLs located within region FGb is turned on. Also, within the region between the two plate-like parts LI, a predetermined voltage is applied to the selection gate lines SGS0 and SGS1 corresponding to the region on the upper side of the paper relative to the isolation layer SHEs, and the selection gate STS of all pillar PLs located within regions FGa and FGb is turned on.

[0095] As a result, all pillars PL within region FGb are selected, with both selection gates STD and STS turned on. Furthermore, the target memory cell MC is identified by the word line WL and bit line BL corresponding to the memory cell MC to be read, and the data is read.

[0096] Furthermore, if the pillar PL to which the memory cell MC to be read belongs is located within region FGc, a predetermined voltage is applied to the selection gate lines SGD0 and SGD1 corresponding to region FGc, and the selection gate STD of all pillar PLs located within region FGc is turned on. Also, within the region between the two plate-like parts LI, a predetermined voltage is applied to the selection gate lines SGS0 and SGS1 corresponding to the region on the lower side of the paper relative to the isolation layer SHEs, and the selection gate STS of all pillar PLs located within regions FGc and FGd is turned on.

[0097] As a result, all pillars PL within region FGc are selected, with both selection gates STD and STS turned on. Furthermore, the target memory cell MC is identified by the word line WL and bit line BL corresponding to the memory cell MC to be read, and the data is read.

[0098] Furthermore, if the pillar PL to which the memory cell MC to be read belongs is located within region FGd, a predetermined voltage is applied to the selection gate lines SGD0 and SGD1 corresponding to region FGd, and the selection gate STD of all pillar PLs located within region FGd is turned on. Also, within the region between the two plate-like parts LI, a predetermined voltage is applied to the selection gate lines SGS0 and SGS1 corresponding to the region on the lower side of the paper relative to the isolation layer SHEs, and the selection gate STS of all pillar PLs located within regions FGc and FGd is turned on.

[0099] As a result, all pillars PL within region FGd are selected, with both selection gates STD and STS turned on. Furthermore, the target memory cell MC is identified by the word line WL and bit line BL corresponding to the memory cell MC to be read, and the data is read.

[0100] In this state, a predetermined voltage is applied from the corresponding word line WL to the memory cells MC other than the one being read from the selected pillar PL. However, in the case of a non-selected pillar PL where only the selection gate STS is turned on, a potential difference is generated between the channel layer CN of the pillar PL and these word lines WL. This creates parasitic capacitance, and it takes time for the charge necessary for reading data from the memory cells MC to accumulate in the channel layer CN of the selected pillar PL.

[0101] As described above, by separating the selection gate lines SGS0 and SGS1 into two regions using separation layers SHEs in the region between adjacent plate-like sections LI in the Y direction, the number of unselected pillars PL in which the selection gate STS is turned on can be significantly reduced. In the example shown in Figure 3(a), the number of unselected pillars PL in which the selection gate STS is turned on can be reduced to about 1 / 3 compared to the case without separation layers SHEs.

[0102] (Method of manufacturing semiconductor memory devices) Next, the method for manufacturing the semiconductor memory device 1 according to the embodiment will be described using Figures 4 to 11. Figures 4 to 11 are diagrams illustrating, in order, some of the steps of the method for manufacturing the semiconductor memory device 1 according to the embodiment.

[0103] First, Figures 4 and 5 show the laminate LMsa, which is the lower layer of the laminate LM before the word line WL is formed, and the process by which various components are formed on the laminate LMsa.

[0104] Figures 4 and 5 are cross-sectional views along the X-direction of the regions that will later become the memory region MR and the stepped region SR.

[0105] As shown in Figure 4(a), the lower source wire DSLa, the intermediate sacrificial layer SCN or intermediate insulating layer SCO, and the upper source wire DSLb are formed on the support substrate SS in this order.

[0106] As the support substrate SS, a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, or a conductive substrate can be used. The insulating layer 60 (see Figure 2, etc.) described above may be formed on the upper surface of the support substrate SS.

[0107] The intermediate sacrificial layer SCN is formed in the region on the support substrate SS that will later become the memory region MR, and the intermediate insulating layer SCO is formed in the region on the support substrate SS that will later become the stepped region SR. The intermediate sacrificial layer SCN is, for example, a silicon nitride layer, and is a layer that will later be replaced with a polysilicon layer or the like to become the intermediate source line BSL. The intermediate insulating layer SCO is, as described above, for example, a silicon oxide layer.

[0108] Furthermore, multiple insulating layers NL and multiple insulating layers OL are alternately stacked one layer at a time on the upper source line DSLb. In this case, the number of insulating layers NL is the same as the number of selective gate line SGS layers that the semiconductor memory device 1 will ultimately have. The insulating layers NL are, for example, silicon nitride layers and function as sacrificial layers that will later be replaced by conductive materials to become the selective gate line SGS.

[0109] As shown in Figure 4(b), a frame-shaped groove TR is formed in the region that will later become the stepped region SR, penetrating multiple insulating layers NL and OL to reach the upper source wire DSLb.

[0110] As shown in Figure 4(c), an insulating layer 57 is filled into multiple grooves TR. This forms multiple block layers BX. At this time, as described above, it is preferable that the area of ​​the region surrounded by the block layers BX is less than or equal to the cross-sectional area of ​​the columnar portion HR at the point where the columnar portion HR that is later formed has the maximum diameter.

[0111] The processes shown in Figures 4(b) and 4(c) are performed in conjunction with the process of forming separation layers SHEs in the insulating layer NL, which will later become the selected gate wire SGS. Specifically, in parallel with the processes shown in Figures 4(b) and 4(c), grooves are formed that penetrate multiple insulating layers NL and OL and extend along the X direction within these insulating layers NL and OL, and the insulating layer 57 is filled into these grooves to form the separation layers SHEs.

[0112] As shown in Figure 4(d), a laminate LMsa is formed by alternately stacking multiple insulating layers NL and multiple insulating layers OL one layer at a time on multiple insulating layers NL and OL. The additional insulating layers NL formed in the laminate LMsa function as sacrificial layers that will later be replaced by conductive layers to become word lines WL.

[0113] As shown in Figure 4(e), in a portion of the laminated LMsa that will later become the stepped region SR, the insulating layer NL and the insulating layer OL are processed in a stepped manner. This processing can be achieved by repeatedly slimming the mask pattern of the photoresist layer, etc., and etching the insulating layer NL and the insulating layer OL of the laminated LMsa.

[0114] Specifically, a mask pattern is formed on the upper surface of the laminated LMsa, and, for example, the insulating layer NL and insulating layer OL in the exposed areas are etched away one layer at a time. Then, by processing with oxygen plasma or the like, the edges of the mask pattern are recessed, exposing the upper surface of the laminated LMsa again, and the insulating layer NL and insulating layer OL are etched away one layer at a time again. By repeating this process multiple times, the above-mentioned stepped shape is formed.

[0115] At this time, multiple block layers BX are formed in the region that will become the stepped region SR after the laminated body LMsa. When the lower insulating layers NL, excluding the uppermost insulating layer NL, which will later become the selected gate line SGS, are processed in a stepped shape, the upper ends of the block layers BX formed in those areas are also processed together, and become approximately the same height as the upper surfaces of the stepped insulating layers OL.

[0116] As shown in Figure 5(a), an insulating layer 51 is formed that covers the stepped portion and reaches the height of the top surface of the laminated LMsa. The insulating layer 51 is also formed in the outer region of the laminated LMsa.

[0117] As shown in Figure 5(b), the laminate LMsa is formed with multiple memory holes MHa and multiple holes HLa extending in the stacking direction.

[0118] Memory holes MHa are the parts that later become the substructure of pillar PL. Multiple memory holes MHa are located in the region that will later become the memory area MR, and penetrate the stack LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa.

[0119] The holes HLa are the parts that later become the substructure of the columnar section HR. Multiple holes HLa are arranged in the region that later becomes the stepped region SR, and penetrate the insulating layer 51, the laminate LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa. At this time, the lower end of each hole HLa is located within the region surrounded by the corresponding block layer BX among the multiple frame-shaped block layers BX.

[0120] Furthermore, even if some of the multiple holes HLa are misaligned at this time, and the holes HLa are formed slightly outside the area enclosed by the corresponding block layer BX, this will not affect subsequent processes.

[0121] As shown in Figure 5(c), these memory holes MHa and HLa are filled with a sacrificial layer 26 such as an amorphous silicon layer or a CVD-carbon layer. As a result, in the region that will later become the memory region MR, pillar PLc is formed in which multiple memory holes MHa are filled with the sacrificial layer 26. In addition, in the region that will later become the step region SR, columnar parts HRc are formed in which multiple holes HRa are filled with the sacrificial layer 26.

[0122] As shown in Figure 5(d), the laminate LMsa, which includes the stepped portion, is covered to form a laminate LMsb in which multiple insulating layers NL and multiple insulating layers OL are alternately laminated one layer at a time. The laminate LMsb is the upper layer of the laminate LM before the word line WL is formed. The insulating layer NL of the laminate LMsb functions as a sacrificial layer that will later be replaced by a conductive layer to become the word line WL or the selected gate line SGD.

[0123] Next, Figure 6 shows how various structures are formed on the laminates LMsa and LMsb. Figure 6, like Figures 4 and 5 described above, is a cross-sectional view along the X direction of the regions that will later become the memory region MR and the stepped region SR.

[0124] As shown in Figure 6(a), the insulating layer NL and insulating layer OL are processed in a stepwise manner in a portion of the laminated LMsb. This processing can be achieved by repeatedly performing the same process as shown in Figure 4(e) above, which involves slimming the mask pattern of the photoresist layer and etching the insulating layer NL and insulating layer OL of the laminated LMsb.

[0125] At this time, the uppermost step of the stair section already formed in the laminated LMsa and the lowermost step of the stair section formed in the laminated LMsb are brought into close proximity, so that they are formed to be continuously connected from the lower layer side of the laminated LMsa to the upper layer side of the laminated LMsb.

[0126] As shown in Figure 6(b), an insulating layer 51 is formed that covers the laminate LMsa and the newly formed stepped portion on the laminate LMsb, reaching the height of the top surface of the laminate LMsb. The insulating layer 51 is also formed in the outer regions of the laminates LMsa and LMsb.

[0127] As shown in Figure 6(c), the laminate LMsb is formed with multiple memory holes MHb and multiple holes HLb extending in the stacking direction.

[0128] The memory holes MHb are the parts that will later become the upper structure of the pillar PL. Multiple memory holes MHb are located in the region that will later become the memory area MR, and they penetrate the stacked LMsb and reach the upper end of the pillar PLc formed in the stacked LMsa.

[0129] Hole HLb is the part that will later become the superstructure of columnar section HR. Multiple holes HLb are located in the area that will later become the staircase area SR, and penetrate the laminate LMsb, each reaching the upper end of the columnar section HRc formed in the laminate LMsa.

[0130] As shown in Figure 6(d), the sacrificial layer 26 is removed from the pillar PLc at the bottom of the memory hole MHb. As a result, multiple memory holes MHa open at the bottom of multiple memory holes MHb, and multiple memory holes MH are formed that penetrate the laminate LMsb, LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa.

[0131] In parallel with this, the sacrificial layer 26 is removed from the columnar portion HRc at the bottom of hole HLb. As a result, multiple holes HL are formed, each with a hole HLa opening at the bottom of multiple holes HLb, penetrating the insulating layer 51, the laminates LMsb and LMsa, the upper source wire DSLb, and the intermediate sacrificial layer SCN, and reaching the lower source wire DSLa.

[0132] Furthermore, if the sacrificial layer 26 filled in the pillar PLc and columnar HRc is a CVD-carbon layer or the like, when the mask pattern used in the process shown in Figure 6(c) above is removed by ashing using oxygen plasma, the sacrificial layer 26 can be removed from these pillar PLc and columnar HRc all at once.

[0133] Next, although not shown in the diagram, an insulating layer 59 is filled into multiple holes HL. At this time, multiple memory holes MH are protected by a photoresist layer or the like. As a result, multiple columnar parts HR are formed in the region that will later become the stepped region SR.

[0134] Next, Figures 7 and 8 illustrate how a multilayer structure is formed within the memory hole MH to create a pillar PL. Figures 7 and 8 are cross-sectional views along the Y direction of the region that will later become the memory area MR.

[0135] As shown in Figure 7(a), multiple memory holes MH are formed in the region that will later become the memory region MR. In addition, in the lower part of the laminate LMsa, isolation layers SHEs, which were formed in parallel with the block layer BX in the process described in Figures 4(b) and 4(c) above, are arranged.

[0136] As shown in Figure 7(b), a multilayer insulating layer MEb, a semiconductor layer CNb, and an insulating layer CRb are formed in this order within the memory hole MH. As a result, the multilayer insulating layer MEb and the semiconductor layer CNb are positioned on the side surface of the memory hole MH and the bottom surface where the lower source line DSLa is exposed, and the insulating layer CRb is filled in the center of the memory hole MH.

[0137] The multilayer insulating layer MEb is a multilayer insulating layer that later becomes the memory layer ME. The semiconductor layer CNb is a layer that later becomes the channel layer CN. The insulating layer CRb is a silicon oxide layer, etc., that later becomes the core layer CR.

[0138] The multilayer insulating layer MEb, the semiconductor layer CNb, and the insulating layer CRb are formed in this order on the upper surface of the laminate LMsb.

[0139] As shown in Figure 7(c), in the region that will later become the memory area MR, the insulating layer CRb, the semiconductor layer CNb, and the multilayer insulating layer MEb are sequentially etched back and removed from the upper surface of the laminate LMsb, and a depression DN is formed at the upper end of the memory hole MH where the insulating layer CRb and the semiconductor layer CNb have been removed.

[0140] As a result, the memory layer ME, the channel layer CN, and the core layer CR are formed within the memory hole MH, in that order from the outer edge.

[0141] As shown in Figure 8(a), a semiconductor layer CPb is formed in the depression DN at the upper end of the memory hole MH in the region that will later become the memory region MR. The semiconductor layer CPb is the layer that will later become the cap layer CP. The semiconductor layer CPb is also formed on the upper surface of the laminate LMsb.

[0142] As shown in Figure 8(b), in the region that will later become the memory region MR, the semiconductor layer CPb on the upper surface of the stacked LMsb is removed by CMP or the like, and a cap layer CP is formed at the upper end of the memory hole MH.

[0143] As shown in Figure 8(c), the insulating layer OL on the top layer of the laminated LMsb, which has been thinned by CMP or the like, is stacked up.

[0144] This results in the formation of a pillar PL, in which the cap layer CP is embedded in the uppermost insulating layer OL. However, at this point, the memory layer ME covers the entire sidewall of the pillar PL, and no part of the side of the channel layer CN is exposed from the memory layer ME.

[0145] Furthermore, the step structure of the laminates LMsa and LMsb was to be carried out as appropriate for each laminate. However, the formation of the step structure on the laminates LMsa and LMsb may also be done all at once at this stage.

[0146] In this case, after forming pillars PL and columnar sections HR that penetrate the laminates LMsa and LMsb before the staircase structure is formed, the staircase structure is formed collectively in a portion of the laminates LMsa and LMsb. At that time, the columnar sections HR are processed in parallel with the processing of the insulating layers NL and OL into a staircase shape, and the upper end of each columnar section HR is at approximately the same height as the upper surface of the respective staircase-shaped insulating layer OL.

[0147] Next, Figures 9 to 11 illustrate how the source line SL and word line WL are formed. Figures 9 and 10, like Figures 7 and 8 described above, are cross-sectional views along the Y direction of the region that will later become the memory region MR.

[0148] As shown in Figure 9(a), a slit ST is formed that penetrates the laminates LMsb, LMsa and the upper source wire DSLb, and reaches the intermediate sacrificial layer SCN. In addition, an insulating layer 54s is formed on the side walls of the slit ST facing in the Y direction.

[0149] The slit ST has a tapered or bowed longitudinal section in the Y direction and extends along the X direction within the laminates LMsa and LMsb. Therefore, in the stepped region SR (not shown), the lower end of the slit ST reaches the intermediate insulating layer SCO.

[0150] As shown in Figure 9(b), a removal solution for the intermediate sacrificial layer SCN, such as thermal phosphoric acid, is introduced through the slit ST, whose sidewalls are protected by the insulating layer 54s, to remove the intermediate sacrificial layer SCN sandwiched between the lower source wire DSLa and the upper source wire DSLb.

[0151] As a result, a gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb. In addition, a portion of the memory layer ME on the outer periphery of the pillar PL is exposed within the gap layer GPs.

[0152] As shown in Figure 9(c), chemical solutions are introduced into the gap layer GPs through the slit ST as needed to sequentially remove the block insulating layer BK, charge storage layer CT, and tunnel insulating layer TN (see Figures 2(b) and 2(c)) of the memory layer ME exposed within the gap layer GPs. As a result, the memory layer ME is removed from a portion of the side wall of the pillar PL, and a portion of the inner channel layer CN is exposed within the gap layer GPs.

[0153] As shown in Figure 9(d), a raw material gas, such as amorphous silicon, is injected through the slit ST, whose sidewalls are protected by an insulating layer 54s, to fill the gap layer GPs with amorphous silicon or the like. The support substrate SS is then heat-treated to polycrystallize the amorphous silicon filled in the gap layer GPs, forming an intermediate source wire BSL containing polysilicon or the like.

[0154] As a result, a portion of the channel layer CN of the pillar PL is connected to the source line SL on the side via the intermediate source line BSL.

[0155] In this case, in the stepped region SR (not shown), no gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb. Furthermore, no intermediate source line BSL is formed.

[0156] As shown in Figure 10(a), the insulating layer 54s on the side wall of the slit ST is temporarily removed.

[0157] As shown in Figure 10(b), a solvent for removing the insulating layer NL, such as thermal phosphoric acid, is introduced into the laminates LMsa and LMsb through the slit ST to remove the insulating layer NL of the laminates LMsa and LMsb. This forms laminates LMga and LMgb having multiple gap layers GP from which the insulating layer NL between insulating layers OL has been removed.

[0158] In this case, the insulating layer NL on the lower side where the separation layer SHEs is placed is removed one side at a time in the Y direction by the removal liquid flowing in from the slits ST on both sides of the separation layer SHEs in the Y direction. In this way, it is possible to remove the entire insulating layer NL on the lower side even when the separation layer SHEs is placed.

[0159] LMga and LMgb laminates containing multiple gap layers (GP) have a fragile structure. In the region that later becomes the memory area (MR), multiple pillars (PL) support these fragile LMga and LMgb laminates.

[0160] This pillar PL support structure prevents the remaining insulating layer OL from bending, and the laminates LMga and LMgb from becoming distorted or collapsing.

[0161] As shown in Figure 10(c), a conductive material raw material gas, such as tungsten or molybdenum, is injected into the interior of the laminates LMga and LMgb through the slit ST, and the gap layer GP of the laminates LMga and LMgb is filled with the conductive material to form multiple word lines WL, etc. This forms a laminate LM containing laminates LMa and LMb, in which multiple word lines WL, etc. and multiple insulating layers OL are alternately stacked one layer at a time.

[0162] In this case as well, the gap layer GP on the lower side where the separation layer SHEs is located is filled with conductive material on one side at a time in the Y direction by the raw material gas flowing in from the slits ST on both sides of the separation layer SHEs in the Y direction. In this way, even with the separation layer SHEs in place, it is possible to fill the entire gap layer GP on the lower side with conductive material to form the selected gate line SGS.

[0163] Furthermore, the topmost layer and the second-to-last conductive layer of the laminate LMb are later partitioned into patterns of multiple selected gate lines SGD by the formation of a separation layer SHEd that penetrates them.

[0164] As described above, the process of forming the intermediate source line BSL from the intermediate sacrificial layer SCN, and the process of forming the word line WL from the insulating layer NL, are also called replacement processes.

[0165] Figure 11 is a cross-sectional view along the Y-direction of the region that will later become the staircase region SR, showing the process performed in the region that will become the staircase region SR in parallel with the process shown in Figure 10 above. Figure 11 shows the cross-section of the uppermost step of the staircase section SP.

[0166] As shown in Figure 11(a), multiple columnar sections HR have already been formed in the region that will later become the staircase region SR. In addition, the aforementioned slit ST is also formed in the region that will later become the staircase region SR. However, in the region that will later become the staircase region SR, the lower end of the slit ST reaches the intermediate insulating layer SCO. For this reason, the region that will later become the staircase region SR is not affected by the source wire replacement process SL shown in Figure 9.

[0167] As shown in Figure 11(b), in parallel with the process described in Figure 10(b), multiple insulating layers NL of the laminates LMsa and LMsb are removed in the region that will later become the stepped region SR, forming laminates LMga and LMgb having multiple gap layers GP.

[0168] In this region, which later becomes the stepped region SR, multiple columnar sections HR support the fragile laminates LMga and LMgb. This support structure of columnar sections HR prevents the remaining insulating layer OL from bending, and prevents the laminates LMga and LMgb from becoming distorted or collapsing.

[0169] However, as mentioned above, the columnar sections HR have, for example, a tapered or bowed shape, and the lower end of the columnar section HR is thinner than, for example, the upper end of the columnar section HR. In addition, the columnar sections HR are arranged at a lower density with more space between them than between the pillars PL. Therefore, the support function of the laminates LMga and LMgb by the columnar sections HR may be inferior to the support function of the laminates LMga and LMgb by the pillars PL, and the laminates LMga and LMgb may not be adequately supported in the region that later becomes the stepped region SR.

[0170] However, at the lower end of each columnar section HR, multiple block layers BX are formed so as to surround these lower ends. Therefore, the insulating layer NL removal liquid, such as thermal phosphoric acid, that flows in from the slit ST does not flow into the area surrounded by the block layers BX, and the insulating layer NL in this area is not removed.

[0171] In this case, as described above, some columnar portions HR may be formed slightly outside the area enclosed by the corresponding block layer BX due to, for example, misalignment during hole HLa formation. Even if the columnar portions HR are formed so as to penetrate a part of the frame of the block layer BX due to misalignment, the area within the block layer BX is shielded from the outer area by the columnar portions HR themselves and the remaining block layer BX, and the insulating layer NL within the area can be left intact.

[0172] In this way, by arranging the laminated structure LMn, in which the insulating layer NL within the block layer BX remains, in an island-like manner within the laminated body LMga, the bending of the remaining insulating layer OL, and the distortion or collapse of the entire laminated body LMga and the laminated bodies LMga,LMgb are further suppressed.

[0173] In summary, in the region that will later become the staircase region SR, the laminates LMga and LMgb are sufficiently supported by leaving the insulating layer NL within the block layer BX, in addition to the support function of the columnar portion HR.

[0174] As shown in Figure 11(c), in parallel with the process described in Figure 10(c), in the region that will later become the stepped region SR, multiple gap layers GP of the laminates LMga and LMgb are filled with conductive material, forming a laminate LM containing laminates LMa and LMb in which multiple word lines WL and multiple insulating layers OL are alternately laminated one layer at a time. In addition, a laminated structure LMn of insulating layer NL that remains without undergoing replacement processing is placed within the block layer BX.

[0175] As described above, the block layer BX is configured such that the area of ​​the region enclosed by the block layer BX is less than or equal to the cross-sectional area of ​​the columnar portion HR at the point where the columnar portion HR has its maximum diameter. This ensures that the planar area of ​​the laminated structure LMn portion of the insulating layer NL is sufficient to compensate for the tapering at the lower end of the columnar portion HR, thereby adequately supporting the laminates LMga and LMgb, and keeping the area such that the electrical resistance of the selected gate wire SGS in the laminate LM does not become excessively high.

[0176] Subsequently, an insulating layer 54 is formed on the side wall of the slit ST, and a conductive layer 24 is filled into the insulating layer 54 to form a plate-like portion LI. However, the insulating layer 54 and the like may be filled into the slit ST without forming the conductive layer 24 to form a plate-like member.

[0177] Furthermore, by forming grooves that penetrate the top layer and the second-to-last conductive layer of the laminate LMb, and filling the grooves with an insulating layer 56, an isolation layer SHEd is formed that partitions these conductive layers into a pattern of selected gate lines SGD.

[0178] Furthermore, after forming multiple contacts CC in the stepped section SP, an insulating layer 52 is formed on the upper surface of the insulating layer 51 covering the upper surface of the laminate LM and the stepped region SR, and a plug V0 is formed that penetrates the insulating layer 52 and is connected to the contacts CC. Also, a plug CH is formed that penetrates the insulating layer 52 and is connected to the pillar PL. Furthermore, an insulating layer 53 is formed on the insulating layer 52, and upper layer wiring MX and bit wire BL, etc., which are connected to plugs V0 and CH are formed. In addition, electrode pads, etc., are formed on the upper surface of the insulating layer 53 to establish electrical conductivity with the surrounding circuit CBA.

[0179] Furthermore, plugs V0, CH, upper layer wiring MX, and bit lines BL may be formed collectively, for example, by using a dual damascene method.

[0180] Furthermore, peripheral circuits CBA are formed on a semiconductor substrate SB, which is separate from the support substrate SS on which the laminated structure LM is formed, and covered with an insulating layer 40. Contacts, vias, wiring, etc. are formed in the insulating layer 40 to bring the peripheral circuits CBA to the surface of the insulating layer 40, and these are connected to electrode pads etc. formed on the upper surface of the insulating layer 40.

[0181] Next, the support substrate SS and the semiconductor substrate SB are bonded together by their respective insulating layers 50 and 40, and the electrode pads in the insulating layers 50 and 40 are connected. After that, the support substrate SS is removed to expose the source wire SL, and the electrode film EL is connected via the insulating layer 60 on which the plug PG is formed.

[0182] The semiconductor memory device 1 of the embodiment is manufactured as described above.

[0183] (Overview) In the manufacturing process of semiconductor memory devices such as 3D non-volatile memory, a sacrificial layer in a laminate is sometimes replaced with a conductive layer to form a laminate in which conductive and insulating layers are stacked. In this case, the fragile laminate containing multiple gap layers may bend or deform during the replacement process.

[0184] In this case, in the stepped region where columnar sections are arranged at a lower density than the pillars arranged in the memory region, the bending and distortion of the laminate are more likely to be pronounced. Furthermore, when the pillars and columnar sections are formed together, the processing conditions are adjusted to match the finer memory holes of the pillars, resulting in a noticeable tapering of the lower end of the columnar section. This also may contribute to the bending and distortion of the laminate in the stepped region.

[0185] According to the semiconductor memory device 1 of the embodiment, a laminated structure LMn is provided, which is arranged at a predetermined depth within the laminated body LM, and a plurality of insulating layers NL are spaced apart from each other and stacked at height positions corresponding to the selected gate lines SGS located within the predetermined depth, and a columnar portion HR extends in the stacking direction of the laminated body LM within the laminated body LM and the laminated structure LMn in the stepped region SR. This makes it possible to suppress the bending and distortion of the laminated bodies LMga and LMgb during replacement processing.

[0186] According to the semiconductor memory device 1 of this embodiment, the stacked structure LMn is arranged in an island-like manner within the stacked body LM, at positions corresponding to each of the multiple columnar portions HR when viewed from the stacking direction of the stacked body LM. By keeping the stacked structure LMn within the stacked body LM in this way, it is possible to suppress the increase in the electrical resistance of the selected gate line SGS caused by the arrangement of the stacked structure LMn.

[0187] According to the semiconductor memory device 1 of this embodiment, the laminated structure LMn of the insulating layer NL is positioned in the laminate LM at approximately the same height as the lower-layered selected gate line SGS among the multiple word lines WL and selected gate lines SGD and SGS. Since the columnar portion HR has a tapered shape at its lower end, by positioning the laminated structure LMn of the insulating layer NL on the lower layer side of the laminate LM, the bending and distortion of the laminates LMga and LMgb during replacement processing can be suppressed more effectively.

[0188] In the semiconductor memory device 1 of this embodiment, each of the multiple stacked structures LMn is positioned to correspond to one of the multiple columnar portions HR. By positioning the stacked structures LMn of the insulating layer NL at the lower end of each of the individual columnar portions HR in this way, the bending and distortion of the stacked bodies LMga and LMgb during replacement processing can be further suppressed.

[0189] In the semiconductor memory device 1 of this embodiment, the block layer BX surrounds the laminated structure LMn of the insulating layer NL when viewed from the stacking direction of the laminate LM. By arranging the block layer BX around the laminated structure LMn in this way, the laminated structure LMn can be left inside the laminate LM when the laminate LM is formed by the replacement process.

[0190] According to the semiconductor memory device 1 of this embodiment, among the multiple insulating layers NL in the stacked structure LMn, the uppermost insulating layer NL is positioned at approximately the same height as the uppermost selected gate line SGS of one or more selected gate lines SGS through which the isolation layers SHEs penetrate. This indicates that the block layer BX is formed in parallel with the isolation layers SHEs. By forming the block layer BX in parallel with the isolation layers SHEs, no additional processing is required to form the block layer BX. Therefore, the manufacturing cost of the semiconductor memory device 1 can be reduced.

[0191] (Variation 1) In the above-described embodiment, the block layer BX is, for example, rectangular in shape when viewed from the stacking direction of the laminate LM, and surrounds the individual columnar bodies HR. However, the configuration of the block layer is not limited to the configuration of the above-described embodiment. Figure 12 shows several examples of block layers having configurations different from those of the above-described embodiment.

[0192] Figure 12 is an XY cross-sectional view at the height of the selected gate line SGS, showing several examples of the configuration of block layers BXa to BXc in a semiconductor memory device according to modified embodiment 1. In Figure 12, components similar to those in the above-described embodiment are denoted by the same reference numerals, and their descriptions may be omitted.

[0193] In the example shown in Figure 12(a), the block layer BXa has a rectangular shape with the X direction as its longitudinal direction when viewed from the stacking direction of the laminate LM, and surrounds a plurality of columnar sections HR aligned in the X direction. Thus, a single block layer BXa may be provided to surround a plurality of columnar sections HR, rather than corresponding to each individual columnar section HR. Alternatively, a single block layer BXa may have a rectangular shape with the Y direction as its longitudinal direction when viewed from the stacking direction of the laminate LM, and surround a plurality of columnar sections HR aligned in the Y direction.

[0194] In the example shown in Figure 12(b), the block layer BXb has, for example, a frame on each side of the block layer BX that is longer than the maximum diameter of one columnar section HR, and surrounds multiple columnar sections HR arranged in the X and Y directions. In this way, when surrounding multiple columnar sections HR with a single block layer BXb, multiple columnar sections HR arranged in multiple rows in a predetermined direction may be surrounded together.

[0195] In the example shown in Figures 12(a) and 12(b) above, the number of columnar sections HR placed within a single block layer BXa, BXb is arbitrary. However, it is preferable to limit the number of columnar sections HR placed within a single block layer BXa, BXb to prevent the electrical resistance of the selected gate wire SGS from becoming too high due to the expansion of the planar area of ​​the laminated structure LMn within the block layers BXa, BXb.

[0196] In the examples shown in Figures 12(c) to 12(e), the block layer BXc is, for example, two plate-like structures spaced apart from each other in the Y direction and extending along the X direction, and is positioned on both sides in the Y direction of a plurality of columnar sections HR aligned in the X direction. Thus, the block layer BXc only needs to be positioned on at least both sides in the Y direction of the target columnar sections HR, and does not need to completely enclose these columnar sections HR.

[0197] As shown in Figure 12(c), when the insulating layer NL is placed across the entire XY cross-section before the replacement process, and as shown in Figure 12(d), the removal liquid for the insulating layer NL is introduced through the slit ST, the removal liquid is temporarily blocked by the block layer BXc and does not flow into the region sandwiched on both sides in the Y direction by the block layer BXc. Subsequently, if the process is completed before the removal liquid can flow around from both sides in the X direction, the laminated structure LMn of the insulating layer NL can be left in the region sandwiched on both sides in the Y direction by the block layer BXc, as shown in Figure 12(e).

[0198] Thus, in the example shown in Figure 12(c), by shielding a region of sufficient length with the block layer BXc to block the inflow of the removal liquid, while taking care not to make the electrical resistance of the selected gate line SGS too high, a laminated structure LMn surrounding the lower ends of multiple columnar sections HR aligned in the X direction can be obtained.

[0199] In the semiconductor memory device of Modified Example 1, each of the multiple columnar portions HR extends within a stacked structure LMn surrounded by a block layer BXa or block layer BXb. This eliminates the need to position the stacked structure LMn in correspondence with each individual columnar portion HR, thus allowing for a reduction in the alignment accuracy required during the formation of the block layers BXa and BXb.

[0200] Furthermore, according to the semiconductor memory device of Modification 1, block layers BXc are provided on both sides of the stacked structure LMn in the Y direction. This makes it possible to further loosen the alignment accuracy required when forming the block layers BXc.

[0201] The semiconductor memory device of Modified Example 1 also provides the same effects as the semiconductor memory device 1 of the above-described embodiment.

[0202] (Modification 2) Next, a modified example of the semiconductor memory device 2 of the embodiment will be described using Figure 13. The semiconductor memory device 2 of the modified example differs from the embodiment described above in that a block layer BXm is also formed on the stacked LMb.

[0203] Figure 13 is a cross-sectional view showing an example of the configuration of a semiconductor memory device 2 according to a modified example of the embodiment 2.

[0204] More specifically, Figure 13(a) is a cross-sectional view along the X direction in the stepped region SR of the semiconductor memory device 2. In Figure 13(a), the structures below the insulating layer 60 and above the insulating layer 53 are omitted.

[0205] Figure 13(b) is an enlarged cross-sectional view of the columnar portion HR at the height of the word line WL and the selection gate line SGS of the laminate LMa. Figure 13(c) is an enlarged cross-sectional view of the columnar portion HR at the height of the word line WL on the lower layer side of the laminate LMb.

[0206] In Figure 13, components similar to those in the embodiments described above are denoted by the same reference numerals, and their descriptions may be omitted.

[0207] As shown in Figure 13, in the semiconductor memory device 2 of the modified example 2, the lower layer of the laminated LMb has a laminated structure LMm consisting of a block layer BXm and an insulating layer NL.

[0208] The block layer BXm penetrates, for example, several word lines WL on the lower side of the laminate LMb and the insulating layer OL to reach the uppermost insulating layer OL of the laminate LMa. The block layer BXm may have a shape similar to the block layer BX placed within the laminate LMa, such as a rectangular shape, when viewed from the stacking direction of the laminate LM.

[0209] Within the region enclosed or sandwiched by the block layer BXm, a laminated structure LMm is arranged, in which multiple insulating layers NL and OL are alternately stacked one layer at a time. The number of insulating layers NL included in the laminated structure LMm is arbitrary. However, it is preferable that the number of these insulating layers NL is determined considering the electrical resistance of the entire word line WL in which these insulating layers NL are arranged.

[0210] As a result, the multiple laminated structures LMm placed within the laminated body LMb are arranged in an island-like fashion, corresponding to each of the multiple columnar sections HR when viewed from the stacking direction of the laminated body LM. In this way, the multiple laminated structures LMm locally surround the lower ends of the portions of each of the multiple columnar sections HR that penetrate the laminated body LMb when viewed from the stacking direction of the laminated body LM.

[0211] In the semiconductor memory device 2 of the modified example 2, the multiple columnar portions HR have a configuration in which the lower end of the portion that penetrates the laminated body LMb is surrounded by the laminated structure LMm, and the lower end of the portion that penetrates the laminated body LMa is surrounded by the laminated structure LMn.

[0212] As described above, the columnar portion HR has a tapered or bowed shape in both the portion that penetrates the laminate LMb and the portion that penetrates the laminate LMa, and thinning may occur at the lower end of the portion that penetrates the laminate LMb. Therefore, by placing the block layer BXm and the laminate structure LMm at the lower end of the portion that penetrates the laminate LMb, deflection and distortion during replacement of the laminate LM are further suppressed.

[0213] The block layer BXm and the laminated structure LMm described above are formed within the laminated body LMb, similar to the block layer BX and laminated structure LMn within the laminated body LMa, as explained in the above embodiments. However, when the block layer BXm is formed, the separation layer SHEs and the like are not formed, and the block layer BXm is formed independently.

[0214] Therefore, the block layer BXm does not necessarily have to be formed at a position that includes the height of the word line WL of the lowest layer of the laminate LMb. For example, it may be formed at a position on the lower side of the laminate LMb that does not include the height of the word line WL of the lowest layer, or at a height position between the upper and lower sides of the laminate LMb. However, as described above, it is preferable to arrange the block layer BXm and the laminate structure LMm near the lower end of the portion of the columnar portion HR that penetrates the laminate LMb, where the columnar portion HR becomes thinner and its support function is reduced.

[0215] According to the semiconductor memory device 2 of the modified example 2, a plurality of insulating layers NL are arranged at predetermined height positions within the laminated LMa in the stacking direction of the laminated LMa, including the height position of the selected gate line SGS of the bottom layer of the laminated LMa. These layers are stacked spaced apart from each other at height positions corresponding to the selected gate line SGS, and the laminated structure LMn locally surrounds the lower end of the portion of one or more of the columnar portions HR that penetrate the laminated LMa when viewed from the stacking direction of the laminated LMa. This makes it possible to suppress bending and distortion of the laminated LMa LMga,LMgb during replacement processing.

[0216] Furthermore, according to the semiconductor memory device 2 of the modified example 2, a plurality of insulating layers NL are stacked spaced apart from each other at height positions corresponding to the word line WL on the lower side of the stacked LMb, including the height position of the word line WL on the lower side of the stacked LMb, and the stacked structure LMm further comprises a stacked structure LMm that locally surrounds the vicinity of the lower end of the portion of one or more of the columnar portions HR that penetrate the stacked LMb when viewed from the stacked direction of the stacked LM. This makes it possible to further suppress the bending and distortion of the stacked LMga and LMgb during replacement processing.

[0217] The semiconductor memory device 2 of the modified example 2 also provides the same effects as the semiconductor memory device 1 of the above-described embodiment.

[0218] (Other variations) In the above-described embodiment and modifications 1 and 2, in the method of drawing out multiple word lines WL etc. from one side, contacts are placed in the step region SR on one side in the X direction every two block regions BLK. However, in the one-sided drawing out method for word lines WL etc., the layout is not limited to the above arrangement order, and it is sufficient to arrange the contacts on one side in the X direction within the same block region BLK.

[0219] Furthermore, in the above-described embodiments and modifications 1 and 2, before forming the word wire WL, which is a tungsten layer or a molybdenum layer, a metal element-containing block layer such as an aluminum oxide layer and a barrier metal layer such as a titanium nitride layer or a molybdenum nitride layer may be provided in this order from the outer periphery on the upper and lower surfaces of the word wire WL, which face the insulating layer OL, and on the portions facing the sides of the pillar PL.

[0220] Furthermore, the above-described embodiments and variations 1 and 2 include a laminated body LM with a 2-tier structure. However, the laminated body may have a 1-tier structure, or a 3-tier or higher structure.

[0221] Furthermore, in the embodiments and modifications 1 and 2 described above, the pillar PL is connected to the source line SL on the side of the channel layer CN, but this is not limited to this. For example, the pillar may be configured such that the memory layer on the bottom surface of the pillar is removed and the source line is connected at the lower end of the channel layer.

[0222] Furthermore, in the embodiments and modified examples 1 and 2 described above, the peripheral circuit CBA is positioned above the laminate LM. However, the peripheral circuit may be positioned below the laminate or on the same layer as the laminate.

[0223] When peripheral circuits are located below the laminate, for example, the source wire and the laminate can be formed on the insulating layer of a semiconductor substrate having peripheral circuits covered with an insulating layer. When peripheral circuits are located on the same layer as the laminate, the laminate can be formed at a different location on the semiconductor substrate from the peripheral circuits on which the peripheral circuits are formed.

[0224] Furthermore, in the embodiments and modifications 1 and 2 described above, the laminated LM is provided with a stepped region SR, but this is not the only option. Figure 14 shows an example of a semiconductor memory device 3 that does not have a stepped region SR.

[0225] Figure 14 is a cross-sectional view showing a schematic configuration example of a semiconductor memory device 3 according to another modified embodiment.

[0226] As shown in Figure 14, the memory area MR is located in the center of the stacked LMc of the semiconductor memory device 3, and the contact areas ER are located at both ends of the stacked LMc.

[0227] The contact area ER contains multiple contacts CC that penetrate the laminate LMc to a predetermined depth position of the word line WL, etc., and connect to each of the multiple word lines WL, etc. This configuration also allows for the individual extraction of multi-layered word lines WL, etc.

[0228] Furthermore, in such a configuration, multiple columnar parts can be arranged in the contact area ER, similar to the embodiments described above, and the configurations of the embodiments or modified versions 1 and 2 described above can be applied to these columnar parts.

[0229] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0230] 1-3... Semiconductor memory device, BX, BXa-BXc, BXm... Block layer, CC... Contact, ER... Contact area, LI... Plate-like part, LM, LMa, LMb, LMc, LMga, LMgb, LMsa, LMsb... Stacked structure, LMm, LMN... Stacked structure, MC... Memory cell, MR... Memory area, NL, OL... Insulating layer, PL... Pillar, SGD, SGS... Selected gate line, SHEd, SHEs... Isolation layer, SR... Stepped area, WL... Word line.

Claims

1. A first laminate in which multiple conductive layers are stacked spaced apart from each other, A second laminate is provided, which is located at a predetermined depth within the first laminate in the lamination direction of the first laminate, and in which a plurality of first insulating layers are spaced apart from each other and laminated at heights corresponding to the conductive layers among the plurality of conductive layers that are located within the predetermined depth, A plurality of pillars arranged in a first region and extending within the first stacked body in the stacking direction, each having a memory cell formed at its intersection with at least a portion of the plurality of conductive layers, It comprises a plurality of columnar portions arranged in a second region different from the first region and extending in the stacking direction within the first and second laminates, The second laminate is Viewed from the stacking direction, the following are arranged in an island-like manner within the first stacked body at positions corresponding to one or more of the columnar portions among the plurality of columnar portions: Semiconductor memory device.

2. The second laminate, which is arranged in an island-like manner within the first laminate, Among the plurality of conductive layers, the lower conductive layer is positioned at a height corresponding to the above-mentioned height, Of the plurality of first insulating layers, the lowest first insulating layer is Among the plurality of conductive layers in the first region, the lowest conductive layer is positioned at approximately the same height as the conductive layer in the first region. The semiconductor memory device according to claim 1.

3. The second laminate, which is arranged in an island-like manner within the first laminate, Among the plurality of conductive layers, the conductive layer between the upper conductive layer and the lower conductive layer is positioned at a height corresponding to the conductive layer. The semiconductor memory device according to claim 1.

4. A first laminate in which multiple conductive layers are stacked spaced apart from each other, A plurality of pillars arranged in a first region and extending within the first laminate in the stacking direction of the first laminate, with memory cells formed at each intersection with at least a portion of the plurality of conductive layers, A plurality of columnar portions are arranged in a second region different from the first region and extend within the first laminate in the lamination direction, A second laminate is provided, which is located at a predetermined depth in the stacking direction within the first laminate, and in which a plurality of first insulating layers are stacked spaced apart from each other at heights corresponding to conductive layers located within the predetermined depth among the plurality of conductive layers, and at least a portion thereof overlaps with one or more columnar portions of the plurality of columnar portions when viewed from the stacking direction, The assembly comprises a second insulating layer that surrounds the periphery of the second laminate when viewed from the lamination direction, Semiconductor memory device.

5. A first laminate in which multiple first conductive layers are stacked spaced apart from each other, A plurality of first pillar portions are arranged in a first region and extend within the first laminate in the stacking direction of the first laminate, with first memory cells being formed at each intersection with at least a portion of the plurality of first conductive layers, A plurality of first columnar portions are arranged in a second region different from the first region and extend within the first laminate in the lamination direction, The present invention comprises a second laminate, which is positioned at a predetermined height within the first laminate in the stacking direction, including the height position of the lowest first conductive layer among the plurality of first conductive layers in the first region, and wherein a plurality of first insulating layers are stacked spaced apart from each other at height positions corresponding to any of the plurality of first conductive layers, and which locally surrounds the lower end of one or more of the plurality of first columnar portions when viewed from the stacking direction, Semiconductor memory device.

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