Semiconductor devices, semiconductor chips, and semiconductor circuits
The semiconductor device with a JFET structure addresses increased channel resistance by using a high-impurity-concentration diffusion layer as a drift layer, enhancing breakdown voltage and reducing on-resistance and leakage current.
JP2026099171APending Publication Date: 2026-06-18MITSUBISHI ELECTRIC CORP
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- MITSUBISHI ELECTRIC CORP
- Filing Date
- 2024-12-06
- Publication Date
- 2026-06-18
AI Technical Summary
Technical Problem
Semiconductor devices with a JFET structure face increased channel resistance, which is not addressed by existing technologies.
Method used
A semiconductor device design comprising a semiconductor substrate, well region, source and drain regions, a first gate region, and a first diffusion layer with higher impurity concentration than the well region, positioned closer to the source region, functions as a drift layer to suppress channel resistance and parasitic behavior, enhancing breakdown voltage and reducing on-resistance.
Benefits of technology
The design achieves suppressed channel resistance and improved breakdown voltage, reducing on-resistance and leakage current while maintaining high body pressure resistance.
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Smart Images
Figure 2026099171000001_ABST
Abstract
The present invention provides a semiconductor device with suppressed channel resistance and a semiconductor chip equipped with the semiconductor device. [Solution] The semiconductor device 100 comprises a semiconductor substrate 1 of a first conductivity type having a first main surface 11, a well region 2 of a second conductivity type formed on the first main surface, a source region 4 of a second conductivity type, a drain region 3 of a second conductivity type, and a first gate region 5 of a first conductivity type, and a first diffusion layer 6 of a second conductivity type. The drain region is spaced apart from the source region 4. The first gate region is located between the source region and the drain region. The first diffusion layer is formed spaced apart from the first main surface. Each of the source region, drain region, and first gate region is located inside the well region. The concentration of impurities in the first diffusion layer is greater than the concentration of impurities in the well region. The first gate region is closer to the source region than the drain region. The first diffusion layer is closer to the source region than the drain region 3.
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