Multilayer ceramic electronic component, method for manufacturing a multilayer ceramic electronic component, and circuit board

Abstract

This invention provides a multilayer ceramic electronic component that reduces insulation failures, a method for manufacturing the same, and a circuit board. [Solution] The multilayer ceramic capacitor 101 comprises a laminate 16 having a plurality of ceramic layers stacked in the W-axis direction, a plurality of internal electrodes 12, 13 located between the plurality of ceramic layers, and a pair of sides perpendicular to the T-axis which is orthogonal to the W-axis, and on which the ends of the plurality of internal electrodes in the T-axis direction are located, and a pair of side margins covering the pair of sides, wherein the Si concentration in each of the pair of side margins is 1 at% or more, and the pair of side margins has a rectangular shape with four corners in a plan view perpendicular to the side, and has a first surface facing the side and a second surface opposite to the first surface, and the second surface has four first regions, each including each of the four corners, and a second region adjacent to the first region, and the first distance between the first surface and the first region is smaller than the second distance between the first surface and the second region.

Description

Technical Field

[0001] The present disclosure relates to a multilayer ceramic electronic component, a method for manufacturing a multilayer ceramic electronic component, and a circuit board.

Background Art

[0002] A technique of attaching a side margin portion during the manufacturing process of a multilayer ceramic capacitor is known (see, for example, Patent Document 1). Since this technique can reliably cover both end portions of a plurality of internal electrodes even with a thin side margin portion, it is advantageous for miniaturization and increased capacitance of the multilayer ceramic capacitor.

[0003] As an example, in the method for manufacturing a multilayer ceramic capacitor described in Patent Document 1, a laminated sheet in which ceramic sheets printed with internal electrodes are laminated is cut, and a plurality of laminated bodies having a cut surface where the internal electrodes are exposed as a side surface are produced. Then, by punching out the ceramic sheet on the side surface of the laminated body, side margin portions are formed on both side surfaces of the laminated body.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] In recent years, there has been an increasing demand for further reduction of insulation failure in multilayer ceramic capacitors.

[0006] An object of the present disclosure is to provide a multilayer ceramic electronic component, a method for manufacturing a multilayer ceramic electronic component, and a circuit board capable of reducing insulation failure.

Means for Solving the Problems

[0007] According to one aspect of the present disclosure, a multilayer ceramic electronic component comprises a laminate having a plurality of ceramic layers stacked in a first axial direction, a plurality of internal electrodes located between the plurality of ceramic layers, and a pair of sides perpendicular to a second axis orthogonal to the first axis, on which the ends of the plurality of internal electrodes in the second axial direction are located, and a pair of side margins covering the pair of sides, wherein the Si concentration in each of the pair of side margins is 1 at% or more, each of the pair of side margins has a rectangular shape with four corners in a plan view perpendicular to the side, each of the pair of side margins has a first surface facing the side, and a second surface opposite to the first surface, each of the second surfaces having four first regions, each including each of the four corners, and a second region adjacent to the first region, and the first distance between the first surface and the first region is smaller than the second distance between the first surface and the second region. [Effects of the Invention]

[0008] According to this disclosure, insulation failures can be reduced. [Brief explanation of the drawing]

[0009] [Figure 1] This is a plan view showing a multilayer ceramic capacitor according to the first embodiment. [Figure 2] This is a cross-sectional view (part 1) showing a multilayer ceramic capacitor according to the first embodiment. [Figure 3] This is a cross-sectional view (part 2) showing a multilayer ceramic capacitor according to the first embodiment. [Figure 4] This is a cross-sectional view (part 3) showing a multilayer ceramic capacitor according to the first embodiment. [Figure 5] This is a cross-sectional view (part 4) showing a multilayer ceramic capacitor according to the first embodiment. [Figure 6] This is a plan view showing the side margin portion in the first embodiment. [Figure 7]It is a flowchart showing a method for manufacturing a multilayer ceramic capacitor according to the first embodiment. [Figure 8] It is a diagram (part 1) showing the manufacturing process of a multilayer ceramic capacitor. [Figure 9] It is a diagram (part 2) showing the manufacturing process of a multilayer ceramic capacitor. [Figure 10] It is a diagram (part 3) showing the manufacturing process of a multilayer ceramic capacitor. [Figure 11] It is a cross-sectional view showing a method for processing the side margin portion. [Figure 12] It is a plan view showing a multilayer ceramic capacitor according to the second embodiment. [Figure 13] It is a cross-sectional view showing a multilayer ceramic capacitor according to the second embodiment. [Figure 14] It is a plan view showing a multilayer ceramic capacitor according to the third embodiment. [Figure 15] It is a cross-sectional view showing a multilayer ceramic capacitor according to the third embodiment. [Figure 16] It is a plan view showing a multilayer ceramic capacitor according to the fourth embodiment. [Figure 17] It is a cross-sectional view showing a multilayer ceramic capacitor according to the fourth embodiment. [Figure 18] It is a plan view showing a multilayer ceramic capacitor according to the fifth embodiment. [Figure 19] It is a cross-sectional view showing a multilayer ceramic capacitor according to the fifth embodiment. [Figure 20] It is a plan view showing a multilayer ceramic capacitor according to the sixth embodiment. [Figure 21] It is a cross-sectional view (part 1) showing a multilayer ceramic capacitor according to the sixth embodiment. [Figure 22] It is a cross-sectional view (part 2) showing a multilayer ceramic capacitor according to the sixth embodiment. [Figure 23] It is a plan view showing a multilayer ceramic capacitor according to the seventh embodiment. [Figure 24]It is a cross-sectional view showing a multilayer ceramic capacitor according to the 7th embodiment. [Figure 25] It is a plan view showing a multilayer ceramic capacitor according to the 8th embodiment. [Figure 26] It is a cross-sectional view showing a multilayer ceramic capacitor according to the 8th embodiment. [Figure 27] It is a plan view showing a multilayer ceramic capacitor according to the 9th embodiment. [Figure 28] It is a cross-sectional view showing a multilayer ceramic capacitor according to the 9th embodiment. [Figure 29] It is a plan view showing a multilayer ceramic capacitor according to the 10th embodiment. [Figure 30] It is a cross-sectional view showing a multilayer ceramic capacitor according to the 10th embodiment. [Figure 31] It is a plan view showing a multilayer ceramic capacitor according to the 11th embodiment. [Figure 32] It is a cross-sectional view showing a multilayer ceramic capacitor according to the 11th embodiment. [Figure 33] It is a plan view showing a multilayer ceramic capacitor according to the 12th embodiment. [Figure 34] It is a cross-sectional view showing a multilayer ceramic capacitor according to the 12th embodiment. [Figure 35] It is a plan view showing a multilayer ceramic capacitor according to the 13th embodiment. [Figure 36] It is a cross-sectional view showing a multilayer ceramic capacitor according to the 13th embodiment. [Figure 37] It is a plan view showing a multilayer ceramic capacitor according to the 14th embodiment. [Figure 38] It is a cross-sectional view showing a multilayer ceramic capacitor according to the 14th embodiment.

Modes for Carrying Out the Invention

[0010] Multiple multilayer ceramic capacitors are sometimes transported in a single case. The inventors of this invention have found that during such handling, the multilayer ceramic capacitors can collide with each other, causing damage to the corners of the side margins, and that this damage can lead to insulation failure. Therefore, the inventors of this invention have conducted extensive research to reduce such damage and have arrived at the following embodiment.

[0011] Embodiments of this disclosure will be described in detail below, but this disclosure is not limited to these embodiments. In this specification and in the drawings, components having substantially the same functional configuration are denoted by the same reference numerals to avoid redundant descriptions. In addition, L-axis, T-axis, and W-axis are shown in the drawings as appropriate, as they are mutually orthogonal. The L-axis, T-axis, and W-axis define a fixed coordinate system fixed to the multilayer ceramic capacitor.

[0012] (First Embodiment) First, the first embodiment will be described. The first embodiment relates to a multilayer ceramic capacitor.

[0013] [Structure of multilayer ceramic capacitors] Figure 1 is a plan view showing a multilayer ceramic capacitor according to the first embodiment. Figures 2 to 5 are cross-sectional views showing a multilayer ceramic capacitor according to the first embodiment. Figure 2 is a cross-sectional view along line II-II in Figures 1, 4, and 5. Figure 3 is a cross-sectional view along line III-III in Figures 1, 4, and 5. Figure 4 is a cross-sectional view along line IV-IV in Figures 2, 3, and 5. Figure 5 is a cross-sectional view along line VV in Figures 1 to 4.

[0014] The multilayer ceramic capacitor 101 according to the first embodiment comprises a ceramic body 11, a first external electrode 14, and a second external electrode 15. The ceramic body 11 is configured as a substantially hexahedron having a pair of end faces perpendicular to the L axis, a pair of side faces perpendicular to the T axis, and a pair of main faces perpendicular to the W axis. The first external electrode 14 and the second external electrode 15 cover the pair of end faces of the ceramic body 11.

[0015] The pair of end faces, the pair of side faces, and the pair of main faces of the ceramic body 11 are all configured as flat surfaces. In this disclosure, a flat surface does not have to be strictly planar as long as it is perceived as flat when viewed as a whole, and includes, for example, surfaces having minute irregularities or gently curved shapes within a predetermined range.

[0016] The first external electrode 14 and the second external electrode 15 face each other in the L-axis direction with the ceramic body 11 in between. The first external electrode 14 and the second external electrode 15 extend from each end face of the ceramic body 11 to the main surface and side surface, respectively. As a result, the cross-sections of the first external electrode 14 and the second external electrode 15, parallel to the LW plane and parallel to the LT plane, are both U-shaped.

[0017] The first external electrode 14 and the second external electrode 15 are formed of a good electrical conductor. Examples of good electrical conductors forming the first external electrode 14 and the second external electrode 15 include metals or alloys mainly composed of copper (Cu), nickel (Ni), tin (Sn), palladium (Pd), platinum (Pt), silver (Ag), and gold (Au). In this disclosure, "main component" refers to the component with the highest content ratio.

[0018] The ceramic body 11 comprises a laminate 16 and a pair of side margin portions 17. The laminate 16 constitutes a pair of main surfaces and a pair of end surfaces of the ceramic body 11 and has a pair of side surfaces F parallel to the W axis (first axis) and perpendicular to the T axis (second axis). The pair of side margin portions 17 each cover the pair of side surfaces F of the laminate 16 and constitute a pair of side surfaces of the ceramic body 11.

[0019] The laminate 16 has a configuration in which a plurality of flat ceramic layers extending along the LT plane are stacked in the W-axis direction. The laminate 16 has a capacitance forming section 18 and a pair of cover margin sections 19. The pair of cover margin sections 19 cover the capacitance forming section 18 from above and below in the W-axis direction and constitute a pair of main surfaces of the ceramic body 11. The plurality of ceramic layers have a plurality of inter-electrode ceramic layers 21 included in the capacitance forming section 18 and a pair of outermost ceramic layers 22 included in the pair of cover margin sections 19. The pair of outermost ceramic layers sandwich the capacitance forming section 18 in the W-axis direction. The pair of cover margin sections 19 are stacked so as to sandwich the plurality of inter-electrode ceramic layers 21, a plurality of first internal electrodes 12, and a plurality of second internal electrodes 13 from both sides in the W-axis direction.

[0020] The capacitance forming section 18 has a plurality of sheet-like first internal electrodes 12 and second internal electrodes 13 extending along the LT plane. The first internal electrodes 12 and second internal electrodes 13 are arranged between a plurality of ceramic layers. The first internal electrodes 12 and second internal electrodes 13 are arranged alternately along the W-axis direction. In other words, in the capacitance forming section 18, the first internal electrodes 12 and second internal electrodes 13 face each other in the W-axis direction with a ceramic layer in between.

[0021] The first internal electrode 12 is drawn out to the end face covered by the first external electrode 14. On the other hand, the second internal electrode 13 is drawn out to the end face covered by the second external electrode 15. As a result, the first internal electrode 12 is connected only to the first external electrode 14, and the second internal electrode 13 is connected only to the second external electrode 15.

[0022] The first internal electrode 12 and the second internal electrode 13 are formed across the entire width of the capacitance forming section 18 in the T-axis direction, with both ends in the T-axis direction positioned on both sides F of the laminate 16. As a result, in the ceramic substrate 11, the positions of the ends of the multiple first internal electrodes 12 and second internal electrodes 13 in the T-axis direction are aligned within a range of 0.5 μm or less in the T-axis direction on both sides F of the laminate 16.

[0023] The first internal electrode 12 and the second internal electrode 13 are formed from a good electrical conductor. Typical good electrical conductors forming the first internal electrode 12 and the second internal electrode 13 include nickel (Ni), but other examples include metals or alloys mainly composed of copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), etc.

[0024] Figure 6 is a plan view showing the side margin portion in the first embodiment. The side margin portion 17 has a rectangular shape with four corners 171 (171A, 171B, 171C, and 171D) in a plan view perpendicular to the side surface F. The corners 171 are the inner parts of a perpendicular isosceles triangle with two sides perpendicular to each other and with lengths of 5 μm. Corner 171B is located on the +W side of corner 171A, corner 171C is located on the +L side of corner 171B, corner 171D is located on the -W side of corner 171C, and corner 171A is located on the -L side of corner 171D. For example, the side margin portion 17 has a rectangular shape with a pair of long sides and a pair of short sides in a plan view. The sides connecting corner 171B and corner 171C, and the sides connecting corner 171D and corner 171A are the longer sides, and the sides connecting corner 171A and corner 171B, and the sides connecting corner 171C and corner 171D are the shorter sides.

[0025] The side margin portion 17 has a first surface 51 facing the side surface F and a second surface 52 opposite to the first surface 51. The second surface 52 constitutes a pair of side surfaces of the ceramic body 11. The second surface 52 has four first regions 1 (1A, 1B, 1C, and 1D) and a second region 2 adjacent to the first regions 1. The first region 1A includes a corner 171A, the first region 1B includes a corner 171B, the first region 1C includes a corner 171C, and the first region 1D includes a corner 171D. For example, in a plan view perpendicular to the second surface 52, the first regions 1 are arranged symmetrically with respect to the line bisector parallel to the W-axis of the second surface 52 as the axis of symmetry. In a plan view, the four first regions 1A, 1B, 1C, and 1D overlap with the cover margin portion 19. The first region 1A and the first region 1B are joined together to form one third region 3A, and the first region 1C and the first region 1D are joined together to form another third region 3B. The second region 2 extends along the short side of the side margin portion 17 and reaches both ends of the side margin portion 17 in the W-axis direction. The edge of the third region 3A has an arc-shaped planar shape that is convex toward the +L side, and the edge of the third region 3B has an arc-shaped planar shape that is convex toward the -L side. The first distance T1 between the first surface 51 and the first region 1 is smaller than the second distance T2 between the first surface 51 and the second region 2. The first distance T1 may be 0.1 times or more the second distance T2, and the first distance T1 may be 0.9 times or less the second distance T2. The first distance T1 and the second distance T2 are the maximum distances among the measurement results at 10 locations.

[0026] As shown in Figure 1, the +L-side edge of the first external electrode 14 extends over a portion of the second region 2, a portion of the third region 3A, and a portion of the second region 2 in the W-axis direction. That is, the first external electrode 14 covers at least the first region 1. The portion of the first external electrode 14 covering the second region 2 protrudes more than the portion covering the third region 3A. Also, as shown in Figure 3, the minimum value of the distance T3 between the outer surface 13A of the portion of the first external electrode 14 covering the third region 3A and the first surface 51 is greater than or equal to the second distance T2 between the first surface 51 and the second region 2. When the minimum value of distance T3 is greater than the second distance T2, the first external electrode 14 has a portion that is further away from the first surface 51 than the second surface 52 in the T-axis direction, which is the thickness direction of the side margin portion 17.

[0027] As shown in Figure 1, the +L-side edge of the second external electrode 15 extends over a portion of the second region 2, a portion of the third region 3B, and a portion of the second region 2 in the W-axis direction. That is, the second external electrode 15 covers at least the first region 1. The portion of the second external electrode 15 that covers the second region 2 protrudes more than the portion that covers the third region 3B. Also, as shown in Figure 3, the minimum value of the distance T3 between the outer surface 13B of the portion of the second external electrode 15 that covers the third region 3B and the first surface 51 is greater than or equal to the second distance T2 between the first surface 51 and the second region 2. When the minimum value of distance T3 is greater than the second distance T2, the second external electrode 15 has a portion that is further away from the first surface 51 than the second surface 52 in the T-axis direction, which is the thickness direction of the side margin portion 17.

[0028] In the multilayer ceramic capacitor 101, when a voltage is applied between the first external electrode 14 and the second external electrode 15, a voltage is applied to the multiple interelectrode ceramic layers 21 between the first internal electrode 12 and the second internal electrode 13. As a result, the multilayer ceramic capacitor 101 stores charge corresponding to the voltage between the first external electrode 14 and the second external electrode 15.

[0029] In the ceramic body 11 of the multilayer ceramic capacitor 101, the multiple ceramic layers (inter-electrode ceramic layer 21) constituting the capacitance forming portion 18, the pair of cover margin portions 19, and the pair of side margin portions 17 are all mainly composed of a polycrystalline dielectric ceramic.

[0030] In the ceramic substrate 11, a high dielectric ceramic is used to increase the capacitance of each ceramic layer in the capacitance forming section 18. Examples of high dielectric ceramics include perovskite materials containing barium (Ba) and titanium (Ti), such as barium titanate (BaTiO3).

[0031] The ceramic layer may also be composed of a system of materials such as strontium titanate (SrTiO3), calcium titanate (CaTiO3), magnesium titanate (MgTiO3), calcium zirconate (CaZrO3), calcium zirconate titanate (Ca(Zr,Ti)O3), barium zirconate (BaZrO3), and titanium dioxide (TiO2).

[0032] In this embodiment, as will be described in detail later, an organosilicon compound is used as a sintering aid to form the side margin portion 17, and Si is contained in the side margin portion 17. The side margin portion 17 may also contain glass particles mainly composed of Si. On the other hand, an organosilicon compound is not used to form the interelectrode ceramic layer 21 included in the volume forming portion 18 and the outermost ceramic layer 22 included in the cover margin portion 19, and the Si concentration in the interelectrode ceramic layer 21 and the outermost ceramic layer 22 is lower than the Si concentration in the side margin portion 17. For example, the Si concentration in the side margin portion 17 is 1 at% or more, preferably 2 at% or more.

[0033] [Manufacturing method for multilayer ceramic capacitors] Next, the manufacturing method of the multilayer ceramic capacitor 101 will be described. Figure 7 is a flowchart showing the manufacturing method of the multilayer ceramic capacitor 101 according to the first embodiment. Figures 8 to 10 show the manufacturing process of the multilayer ceramic capacitor 101. Hereinafter, the manufacturing method of the multilayer ceramic capacitor 101 will be described in accordance with Figure 7, with appropriate reference to Figures 8 to 10.

[0034] (Step S01: Preparation of the laminate) In step S01, an unfired laminate 16, as shown in Figure 8, is prepared. The unfired laminate 16 can be made using a laminate sheet in which multiple large ceramic sheets are stacked in the W-axis direction. A conductive paste for forming the first internal electrode 12 and the second internal electrode 13 is patterned on the ceramic sheet corresponding to the volume forming section 18.

[0035] The unfired laminate 16 is obtained by cutting the laminated sheet along the LW plane and the TW plane. For cutting the laminated sheet, a cutting device equipped with, for example, a push-cutting blade or a rotary blade can be used. As a result, the laminate 16 has a pair of side surfaces F as cut surfaces where both ends of the first internal electrode 12 and the second internal electrode 13 in the T-axis direction are aligned.

[0036] (Step S02: Formation of side margins) In step S02, a pair of unfired side margins 17 are provided on each of the pair of side surfaces F of the unfired laminate 16 fabricated in step S01. As a result, an unfired ceramic body 11 is obtained in which a pair of side surfaces are formed by the unfired side margins 17, as shown in Figure 9.

[0037] For the unfired side margin portion 17, a ceramic slurry mixed with an organosilicon compound as a sintering aid is used. Silicone resin and silicon oligomers can be used as the organosilicon compound. The ceramic slurry can be prepared as follows: First, a dispersion of the organosilicon compound and a binder is prepared. Polyvinyl butyral (PVB) can be used as the binder. Next, the slurry of the dielectric ceramic constituting the side margin portion 17, such as barium titanate, is dispersed in the dispersion and then emulsified. In this way, a ceramic slurry for the side margin portion 17 in which the organosilicon compound is uniformly dispersed can be prepared.

[0038] The side margin portion 17 can be formed by any method. For example, the side margin portion 17 can be formed using a ceramic sheet obtained by forming a ceramic slurry into a sheet. In this case, the ceramic sheet can be punched out on the side F of the laminate 16, for example, or it can be pre-cut and attached to the side F of the laminate 16.

[0039] Furthermore, in order to form the side margin portion 17, an unformed ceramic slurry can be used as is, instead of a pre-formed ceramic sheet. In this case, the ceramic slurry can be applied to the side surface F of the laminate 16 by, for example, immersing the side surface F of the laminate 16.

[0040] (Step S03: Machining of the side margin area) In step S03, the side margin portion 17 of the ceramic body 11 obtained in step S02 is processed. As a result, the second surface 52 of the side margin portion 17 will have a first region 1 and a second region 2, as shown in Figure 10. For example, the side margin portion 17 is pressurized as follows. Figure 11 is a cross-sectional view showing the processing method of the side margin portion 17.

[0041] As shown in Figure 11(a), one side margin portion 17 is attached to the carrier tape 73 and placed on a base plate 71 with a rubber material 72 attached to its upper surface. A top plate 80 is also prepared, with a convex portion 81 formed in the portion forming the first region 1 and a concave portion 82 formed in the portion forming the second region 2, and the convex portion 81 and concave portion 82 are positioned opposite the other side margin portion 17.

[0042] Next, as shown in Figure 11(b), the top plate 80 is brought into contact with the other side margin portion 17 and pressurized. As a result, the second surface 52 of the other side margin portion 17 comes to have a first region 1 and a second region 2.

[0043] This process is performed on a pair of side margin sections 17.

[0044] Alternatively, multiple ceramic bodies 11 may be attached to the carrier tape 73, and multiple sets of protrusions 81 and recesses 82 corresponding to the multiple ceramic bodies 11 may be provided on the top plate 80, and the multiple ceramic bodies 11 may be pressed together.

[0045] (Step S04: Firing) In step S04, the ceramic body 11 obtained in step S03 is fired to produce the ceramic body 11 of the multilayer ceramic capacitor 101 shown in Figures 1 to 5.

[0046] (Step S05: Formation of external electrodes) In step S04, a multilayer ceramic capacitor 101, as shown in Figures 1 to 5, is fabricated by forming a first external electrode 14 and a second external electrode 15 at both ends in the L-axis direction of the ceramic body 11 fired in step S04. The method for forming the first external electrode 14 and the second external electrode 15 in step S05 can be arbitrarily selected from known methods. Alternatively, the first external electrode 14 and the second external electrode 15 may be formed on the body and then fired simultaneously.

[0047] As a result of the above, the multilayer ceramic capacitor 101 shown in Figures 1 to 5 is completed. In this manufacturing method, a side margin portion 17 is formed on the side surface F of the laminate 16 where the first internal electrode 12 and the second internal electrode 13 are exposed, so that the positions of the ends of the multiple first internal electrodes 12 and second internal electrodes 13 in the ceramic body 11 in the T-axis direction are aligned within a range of 0.5 μm or less in the T-axis direction.

[0048] In the multilayer ceramic capacitor 101 according to the first embodiment, the first distance T1 between the first surface 51 and the first region 1 is smaller than the second distance T2 between the first surface 51 and the second region 2. Therefore, when the multilayer ceramic capacitor 101 is subjected to an external impact, such as a collision between two multilayer ceramic capacitors 101, the impact is applied not only to the corners 171 of the side margin portion 17 but also to the portion of the second region 2 that is close to the corners 171. In other words, compared to the case where the second surface 52 is flat, the impact applied to the corners 171 of the side margin portion 17 is reduced. Accordingly, the multilayer ceramic capacitor 101 can reduce insulation failures due to defects, etc.

[0049] Furthermore, since the second surface 52 has the first region 1, the adhesion between the side margin portion 17 and the first external electrode 14 and the second external electrode 15 can be improved.

[0050] Furthermore, during the manufacturing process of the multilayer ceramic capacitor 101, pressure is applied to the side margin portion 17 to form the first region 1 on the second surface 52. As a result, the gap between the side margin portion 17 and the laminate 16 is reduced in the portion that overlaps with the first region 1. Consequently, the intrusion of moisture into the laminate 16 through the gap between the corner portion 171 of the side margin portion 17 and the laminate 16 is reduced, thereby reducing insulation failures caused by moisture intrusion.

[0051] Furthermore, since the Si concentration in the interelectrode ceramic layer 21 and the outermost ceramic layer 22 is lower than the Si concentration in the side margin portion 17, it is easier to apply pressure to the side margin portion 17. In other words, it is easier to deform the side margin portion 17 by applying pressure. From the viewpoint of processability, the Si concentration in the side margin portion 17 is 1 at% or more. Also, the Si concentration in the side margin portion 17 is preferably 10 at% or less. Having a Si concentration of 10 at% or less in the side margin portion 17 makes it easier to form and process the side margin portion 17.

[0052] The third distance L (see Figure 6) between the corner 171 and the second region 2 in a plan view is preferably twice the fourth distance T4 (see Figure 2) between the first region 1 and the second region 2 in the T-axis direction, which is the thickness direction of the side margin portion 17. When the third distance L is twice the fourth distance T4 or less, impact is more likely to occur in the portion of the second region 2 close to the corner 171, which can further reduce insulation failures due to defects, etc.

[0053] The shapes of the first external electrode 14 and the second external electrode 15 are not limited to those shown in Figures 1 to 4. For example, the first external electrode 14 and the second external electrode 15 may extend from both end faces of the ceramic body 11 to only one main face, and their cross-section parallel to the LW plane may be L-shaped. Also, the first external electrode 14 and the second external electrode 15 do not have to extend to either main face or side face.

[0054] (Second Embodiment) Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in the configuration of the second surface 52. Figure 12 is a plan view showing a multilayer ceramic capacitor according to the second embodiment. Figure 13 is a cross-sectional view showing a multilayer ceramic capacitor according to the second embodiment. Figure 13 is a cross-sectional view along the line XIII-XIII in Figure 12.

[0055] In the multilayer ceramic capacitor 102 according to the second embodiment, the area of ​​the four first regions 1 (1A, 1B, 1C, and 1D) is larger than in the first embodiment. The +L side edge of the first external electrode 14 extends only to the third region 3A in the W-axis direction and not to the second region 2. Also, the -L side edge of the second external electrode 15 extends only to the third region 3B in the W-axis direction and not to the second region 2.

[0056] Other configurations of the second embodiment are the same as those of the first embodiment.

[0057] The same effects as the first embodiment can be obtained with the second embodiment. Furthermore, in the second embodiment, since the first external electrode 14 and the second external electrode 15 do not overlap with the second region 2 in a plan view, the distance between the second region 2 and the mounting substrate becomes shorter than in the first embodiment when the multilayer ceramic capacitor 102 is mounted on the mounting substrate. Therefore, when the mounting substrate bends convexly toward the multilayer ceramic capacitor 102 due to thermal deformation or the like, the mounting substrate comes into contact with the multilayer ceramic capacitor 102, and the bending of the mounting substrate is suppressed. Consequently, external stress is less likely to act on the multilayer ceramic capacitor 102, and fracture associated with external stress can be suppressed.

[0058] Furthermore, when the second region 2 is flush with the outer surface of the first external electrode 14 and the outer surface of the second external electrode 15, the orientation of the multilayer ceramic capacitor 102 is stabilized, and it is easier to suppress the tipping of the multilayer ceramic capacitor 102.

[0059] (Third embodiment) Next, a third embodiment will be described. The third embodiment differs from the first embodiment mainly in the configuration of the second surface 52. Figure 14 is a plan view showing a multilayer ceramic capacitor according to the third embodiment. Figure 15 is a cross-sectional view showing a multilayer ceramic capacitor according to the third embodiment. Figure 15 is a cross-sectional view along the line XV-XV in Figure 14.

[0060] In the multilayer ceramic capacitor 103 according to the third embodiment, the third region 3A and the third region 3B have a rectangular planar shape. The +L side edge of the first external electrode 14 extends only to the second region 2 in the W-axis direction and not to the third region 3A. Similarly, the -L side edge of the second external electrode 15 extends only to the second region 2 in the W-axis direction and not to the third region 3B.

[0061] Other configurations of the third embodiment are the same as those of the first embodiment.

[0062] The same effects as those of the first embodiment can be obtained with the third embodiment as well.

[0063] (Fourth Embodiment) Next, a fourth embodiment will be described. The fourth embodiment differs from the third embodiment mainly in the configuration of the second surface 52. Figure 16 is a plan view showing the multilayer ceramic capacitor according to the fourth embodiment. Figure 17 is a cross-sectional view showing the multilayer ceramic capacitor according to the fourth embodiment. Figure 17 is a cross-sectional view along the line XVII-XVII in Figure 16.

[0064] In the multilayer ceramic capacitor 104 according to the fourth embodiment, the area of ​​the four first regions 1 (1A, 1B, 1C, and 1D) is larger than that of the third embodiment. The +L side edge of the first external electrode 14 extends only to the third region 3A in the W-axis direction and not to the second region 2. Similarly, the -L side edge of the second external electrode 15 extends only to the third region 3B in the W-axis direction and not to the second region 2.

[0065] The other configurations of the fourth embodiment are the same as those of the third embodiment.

[0066] The same effects as the third embodiment can be obtained with the fourth embodiment. Furthermore, in the fourth embodiment, since the first external electrode 14 and the second external electrode 15 do not overlap with the second region 2 in a plan view, fracture due to external stress can be suppressed when the multilayer ceramic capacitor 102 is mounted on the mounting substrate, similar to the second embodiment.

[0067] (Fifth embodiment) Next, a fifth embodiment will be described. The fifth embodiment differs from the fourth embodiment mainly in the configuration of the second surface 52. Figure 18 is a plan view showing the multilayer ceramic capacitor according to the fifth embodiment. Figure 19 is a cross-sectional view showing the multilayer ceramic capacitor according to the fifth embodiment. Figure 19 is a cross-sectional view along the line XIX-XIX in Figure 18.

[0068] In the multilayer ceramic capacitor 105 according to the fifth embodiment, the third region 3A has a planar shape that is convex toward the +L side by adding a triangular planar shape to the planar shape of the fourth embodiment. The third region 3B has a planar shape that is convex toward the -L side by adding a triangular planar shape to the planar shape of the fourth embodiment. The +L side edge of the first external electrode 14 extends only to the third region 3A in the W-axis direction and not to the second region 2. Also, the -L side edge of the second external electrode 15 extends only to the third region 3B in the W-axis direction and not to the second region 2.

[0069] The other configurations of the fifth embodiment are the same as those of the fourth embodiment.

[0070] The same effects as those of the fourth embodiment can be obtained with the fifth embodiment as well.

[0071] (Sixth Embodiment) Next, a sixth embodiment will be described. The sixth embodiment differs from the fourth embodiment mainly in the configuration of the second surface 52. Figure 20 is a plan view showing the multilayer ceramic capacitor according to the sixth embodiment. Figures 21 and 22 are cross-sectional views showing the multilayer ceramic capacitor according to the sixth embodiment. Figure 21 is a cross-sectional view along the line XXI-XXI in Figure 20. Figure 22 is a cross-sectional view along the line XXII-XXII in Figure 20.

[0072] In the multilayer ceramic capacitor 106 according to the sixth embodiment, the second region 2 has a cross-shaped planar form and reaches both ends of the side margin portion 17 in the W-axis direction and both ends in the L-axis direction. The second region 2 is located between the first region 1A and the first region 1B, and the first region 1A and the first region 1B are not connected. The second region 2 is located between the first region 1C and the first region 1D, and the first region 1C and the first region 1D are not connected.

[0073] The other configurations of the sixth embodiment are the same as those of the fourth embodiment.

[0074] The same effects as those of the fourth embodiment can be obtained with the sixth embodiment as well.

[0075] (Seventh Embodiment) Next, the seventh embodiment will be described. The seventh embodiment differs from the sixth embodiment mainly in the configuration of the second surface 52. Figure 23 is a plan view showing the multilayer ceramic capacitor according to the seventh embodiment. Figure 24 is a cross-sectional view showing the multilayer ceramic capacitor according to the seventh embodiment. Figure 24 is a cross-sectional view along the line XXIV-XXIV in Figure 23.

[0076] In the multilayer ceramic capacitor 107 according to the seventh embodiment, each boundary between the first region 1 and the second region 2 has an arc-shaped planar form that is convex toward the second region 2.

[0077] The other configurations of the seventh embodiment are the same as those of the sixth embodiment.

[0078] The same effects as those of the sixth embodiment can be obtained with the seventh embodiment.

[0079] (Eighth embodiment) Next, the eighth embodiment will be described. The eighth embodiment differs from the sixth embodiment mainly in the configuration of the second surface 52. Figure 25 is a plan view showing the multilayer ceramic capacitor according to the eighth embodiment. Figure 26 is a cross-sectional view showing the multilayer ceramic capacitor according to the eighth embodiment. Figure 26 is a cross-sectional view along the line XXVI-XXVI in Figure 25.

[0080] In the multilayer ceramic capacitor 108 according to the eighth embodiment, the boundary between each of the first region 1 and the second region 2 has an arc-shaped planar shape that is convex toward each of the first regions 1.

[0081] Other configurations of the eighth embodiment are the same as those of the sixth embodiment.

[0082] The same effects as those of the sixth embodiment can be obtained with the eighth embodiment.

[0083] (Ninth Embodiment) Next, the ninth embodiment will be described. The ninth embodiment differs from the eighth embodiment mainly in the configuration of the second surface 52. Figure 27 is a plan view showing the multilayer ceramic capacitor according to the ninth embodiment. Figure 28 is a cross-sectional view showing the multilayer ceramic capacitor according to the ninth embodiment. Figure 28 is a cross-sectional view along the line XXVIII-XXVIII in Figure 27.

[0084] In the multilayer ceramic capacitor 109 according to the ninth embodiment, four first regions 1 (1A, 1B, 1C, and 1D) are connected around the second region 2. The second region 2 has an elliptical planar shape with the L axis as its major axis.

[0085] Other configurations of the ninth embodiment are the same as those of the eighth embodiment.

[0086] The ninth embodiment can also achieve the same effects as the eighth embodiment.

[0087] (Tenth embodiment) Next, the tenth embodiment will be described. The tenth embodiment differs from the ninth embodiment mainly in the configuration of the second surface 52. Figure 29 is a plan view showing the multilayer ceramic capacitor according to the tenth embodiment. Figure 30 is a cross-sectional view showing the multilayer ceramic capacitor according to the tenth embodiment. Figure 30 is a cross-sectional view along the line XXX-XXX in Figure 29.

[0088] In the multilayer ceramic capacitor 110 according to the 10th embodiment, the second region 2 has a rectangular planar shape with the L axis as its major axis. Furthermore, the +L side edge of the first external electrode 14 extends only to the first region 1 in the W-axis direction and not to the second region 2, and the -L side edge of the second external electrode 15 extends only to the first region 1 in the W-axis direction and not to the second region 2.

[0089] Other configurations of the tenth embodiment are the same as those of the ninth embodiment.

[0090] The same effects as those of the ninth embodiment can be obtained with the tenth embodiment.

[0091] (11th embodiment) Next, the 11th embodiment will be described. The 11th embodiment differs from the 6th embodiment mainly in the configuration of the second surface 52. Figure 31 is a plan view showing the multilayer ceramic capacitor according to the 11th embodiment. Figure 32 is a cross-sectional view showing the multilayer ceramic capacitor according to the 11th embodiment. Figure 32 is a cross-sectional view along the line XXXII-XXXII in Figure 31.

[0092] In the multilayer ceramic capacitor 111 according to the 11th embodiment, the first region 1A and the first region 1D are connected to form one third region 3C, and the first region 1B and the first region 1D are connected to form another third region 3D. The second region 2 extends along the long side of the side margin portion 17 and reaches both ends of the side margin portion 17 in the L-axis direction. The third region 3C has a rectangular planar shape, and the third region 3D has a rectangular planar shape.

[0093] Other configurations of the 11th embodiment are the same as those of the 6th embodiment.

[0094] The same effects as those of the sixth embodiment can be obtained with the eleventh embodiment.

[0095] (12th embodiment) Next, the twelfth embodiment will be described. The twelfth embodiment differs from the eleventh embodiment mainly in the configuration of the second surface 52. Figure 33 is a plan view showing the multilayer ceramic capacitor according to the twelfth embodiment. Figure 34 is a cross-sectional view showing the multilayer ceramic capacitor according to the twelfth embodiment. Figure 34 is a cross-sectional view along the line XXXIV-XXXIV in Figure 33.

[0096] In the multilayer ceramic capacitor 112 according to the 12th embodiment, the second surface 52 has two second regions 2. The two second regions 2 are separated from each other in the W-axis direction. The second regions 2 reach both ends of the side margin portion 17 in the L-axis direction. Between the two second regions is a fourth region 4. The distance of the fourth region 4 from the first surface 51 is equal to the first distance T1.

[0097] Other configurations of the 12th embodiment are the same as those of the 11th embodiment.

[0098] The 12th embodiment can also obtain the same effects as the 11th embodiment. Furthermore, in the 12th embodiment, since the second surface 52 has two second regions 2, the orientation of the multilayer ceramic capacitor 112 is stabilized and it is easier to suppress the tipping of the multilayer ceramic capacitor 112.

[0099] (13th embodiment) Next, the 13th embodiment will be described. The 13th embodiment differs from the 12th embodiment mainly in the configuration of the second surface 52. Figure 35 is a plan view showing the multilayer ceramic capacitor according to the 13th embodiment. Figure 36 is a cross-sectional view showing the multilayer ceramic capacitor according to the 13th embodiment. Figure 36 is a cross-sectional view along the line XXXVI-XXXVI in Figure 35.

[0100] In the multilayer ceramic capacitor 113 according to the 13th embodiment, two second regions 2 extend in directions inclined from the W-axis and L-axis directions. One end of one second region 2A is between the first region 1A and the first region 1B, and the other end is between the first region 1B and the first region 1C. One end of the other second region 2B is between the first region 1C and the first region 1D, and the other end is between the first region 1D and the first region 1A. The diagonally opposite first regions 1A and 1C connect to form a single third region 3E. The third region 3E is between the second region 2A and the second region 2B.

[0101] Other configurations of the 13th embodiment are the same as those of the 12th embodiment.

[0102] The same effects as those of the 12th embodiment can be obtained with the 13th embodiment.

[0103] (14th Embodiment) Next, the 14th embodiment will be described. The 14th embodiment differs from the first embodiment mainly in the configuration of the second surface 52. Figure 37 is a plan view showing the multilayer ceramic capacitor according to the 14th embodiment. Figure 38 is a cross-sectional view showing the multilayer ceramic capacitor according to the 14th embodiment. Figure 38 is a cross-sectional view along the line XXXVIII-XXXVIII in Figure 37.

[0104] In the multilayer ceramic capacitor 114 according to the 14th embodiment, the second surface 52 has multiple, for example, eight, second regions 2. Each of the second regions 2 has a circular planar shape. Four first regions 1 (1A, 1B, 1C, and 1D) are arranged in a row around the eight second regions 2.

[0105] Other configurations of the 14th embodiment are the same as those of the first embodiment.

[0106] The same effects as those of the first embodiment can be obtained by the 14th embodiment.

[0107] It is preferable that the proportion of the area occupied by the second region 2 of the second surface 52 is 10% or more. This is because it is easier to increase the load applied to the portion forming the first region 1 of the side margin 17 when machining the side margin 17.

[0108] The number of second regions 2 on the second surface 52 is not particularly limited, and can be, for example, between 1 and 100. Having 100 or fewer second regions 2 makes it easier to form a wide first region 1 and to reduce the impact applied to the corners 171 of the side margin portion 17.

[0109] [Examples and Comparative Examples] The characteristics of multilayer ceramic capacitors with different side margin configurations, as examples and comparative examples of the above embodiment, will be described. Table 1 shows the conditions and characteristics of Comparative Examples 1-2 and Examples 1-13.

[0110] In Table 1, "Si concentration x" indicates the Si concentration (at%) of the side margin portion 17. "Second region" indicates the percentage (%) of the area occupied by the second region 2 of the second surface 52. In "Planar shape of the second surface", "No processing" indicates that no processing by pressure is performed after the formation of the side margin portion 17, and "Xth embodiment" indicates that the planar shape is processed according to the Xth embodiment. "First distance" indicates how many times the first distance T1 is compared to the second distance T2. In "Processability", "A" indicates that the first distance T1 is less than 0.8 times the second distance T2, "B" indicates that the first distance T1 is 0.8 times or more but less than 0.95 times the second distance T2, and "C" indicates that the first distance T1 is 0.95 times or more the second distance T2. In the "peeling" category, "A" indicates that the peeling rate of the side margin portion 17 is less than 2%, "B" indicates that the peeling rate of the side margin portion 17 is 2% or more but less than 10%, and "C" indicates that the peeling rate of the side margin portion 17 is 10% or more. In the overall evaluation, "A" is assigned to products where "processability" is "A" or "B" and "peeling" is "A", "B" is assigned to products where "processability" is "A" or "B" and "peeling" is "B", and "C" is assigned to products where "peeling" is "C" regardless of the evaluation of "processability".

[0111] [Table 1]

[0112] As shown in Table 1, in Comparative Example 1, where no processing by pressure is performed after the formation of the side margin portion 17, the second surface 52 having the first region 1 and the second region 2 cannot be obtained, resulting in significant peeling of the side margin portion 17 and an overall evaluation of "C". In Comparative Example 2, where the Si concentration of the side margin portion 17 is less than 1 at%, the processability is poor, and significant peeling of the side margin portion 17 occurs, resulting in an overall evaluation of "C". In contrast to these, Examples 1 to 13 show good processability and suppressed peeling of the side margin portion 17, resulting in an overall evaluation of "A".

[0113] (15th Embodiment) The 15th embodiment relates to a circuit board. The circuit board according to the 15th embodiment includes a substrate such as a mounting substrate and a multilayer ceramic capacitor according to any of the 1st to 14th embodiments. The substrate has a mounting surface. The multilayer ceramic capacitor is mounted on the mounting surface such that the first region 1 and the second region 2 face the mounting surface.

[0114] (Other embodiments) Although embodiments have been described in detail above, this disclosure is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the claims.

[0115] For example, in the above embodiment, a multilayer ceramic capacitor was described as an example of a multilayer ceramic electronic component, but this disclosure is applicable to multilayer ceramic electronic components in general. Examples of such multilayer ceramic electronic components include chip varistors, chip thermistors, and multilayer inductors.

[0116] The aspects of this disclosure are, for example, as follows:

[0117] <1> The laminate comprises a plurality of ceramic layers stacked in a first axial direction, a plurality of internal electrodes located between the plurality of ceramic layers, a pair of side surfaces perpendicular to a second axis orthogonal to the first axis, on which the ends of the plurality of internal electrodes in the second axial direction are located, and a pair of side margins covering the pair of side surfaces. The Si concentration in each of the pair of side margin portions is 1 at% or more. Each of the pair of side margin portions has a rectangular shape with four corners in a plan view perpendicular to the side surface, Each of the pair of side margin portions is A first surface facing the aforementioned side surface, The second side is the opposite of the first side, It has, The second side is, Each of the four first regions includes each of the four corners, A second region adjacent to the first region, It has, The first distance between the first surface and the first region is smaller than the second distance between the first surface and the second region. Multilayer ceramic electronic components.

[0118] <2> The Si concentration in each of the pair of side margin portions is 10 at% or less. <1> Multilayer ceramic electronic components as described above.

[0119] <3> The proportion of the area occupied by the second region within the second surface is 10% or more. <2> Multilayer ceramic electronic components as described above.

[0120] <4> The aforementioned second distance is 0.1 times or more the aforementioned first distance. <1> ~ <3> A multilayer ceramic electronic component as described in any of the following.

[0121] <5> The second distance is 0.9 times or less the first distance. <1> A multilayer ceramic electronic component as described in any of (1) to (4).

[0122] <6> The third distance between the corner and the second region in the plan view is no more than twice the fourth distance between the first region and the second region in the thickness direction of the side margin. <1> ~ <5> A multilayer ceramic electronic component as described in any of the following.

[0123] <7> The second surface has one to 100 of the second regions. <1> ~ <6> A multilayer ceramic electronic component as described in any of the following.

[0124] <8> Each of the pair of side margins has a rectangular shape in plan view, comprising a pair of long sides and a pair of short sides. The second region extends along the pair of long sides. <1> ~ <7> A multilayer ceramic electronic component as described in any of the following.

[0125] <9> Each of the pair of side margins has a rectangular shape in plan view, comprising a pair of long sides and a pair of short sides. The second region extends along the pair of short sides. <1> ~ <7> A multilayer ceramic electronic component as described in any of the following.

[0126] <10> Two of the first regions, each including two corners located diagonally opposite each other, are connected. <1> ~ <7> A multilayer ceramic electronic component as described in any of the following.

[0127] <11> Each of the pair of side margins has a rectangular shape in plan view, comprising a pair of long sides and a pair of short sides. The second region extends in a direction inclined from the pair of long sides and the pair of short sides. <10> Multilayer ceramic electronic components as described above.

[0128] <12> Having an external electrode connected to the internal electrode, The external electrode has a portion in the thickness direction of the side margin that is further away from the first surface than the second surface. <1> ~ <11> A multilayer ceramic electronic component as described in any of the following.

[0129] <13> The external electrode covers at least the first region <12> Multilayer ceramic electronic components as described above.

[0130] <14> The laminate has a pair of cover margins laminated so as to sandwich the plurality of ceramic layers and the plurality of internal electrodes from both sides in the first axial direction. In the aforementioned plan view, the four first regions overlap with the cover margin portion. <1> ~ <13> A multilayer ceramic electronic component as described in any of the following.

[0131] <15> In a plan view perpendicular to the second surface, the first region is arranged symmetrically with respect to the line bisector parallel to the first axis of the second surface. <1> ~ <14> A multilayer ceramic electronic component as described in any of the following.

[0132] <16> A step of preparing a laminate having a plurality of ceramic layers stacked in a first axial direction, a plurality of internal electrodes located between the plurality of ceramic layers, and a pair of sides perpendicular to a second axis orthogonal to the first axis, on which the ends of the plurality of internal electrodes in the second axial direction are located, A step of forming a pair of side margin portions that cover the pair of sides, have a Si concentration of 1 at% or more, have a rectangular shape with four corners in a plan view perpendicular to the sides, and have a first surface facing the sides and a second surface opposite to the first surface, A step of pressurizing a portion of the pair of side margin portions, It has, By applying pressure to a portion of the pair of side margin portions, The second side is, Each of the four first regions includes each of the four corners, A second region adjacent to the first region, It has, The first distance between the first surface and the first region is smaller than the second distance between the first surface and the second region. A method for manufacturing multilayer ceramic electronic components.

[0133] <17> The step of pressurizing a portion of the pair of side margin portions is: The process includes pressing a mold having a recess in the portion where the first region is formed and a convex portion in the portion where the second region is formed against the side margin portion. <16> A method for manufacturing multilayer ceramic electronic components as described above.

[0134] <18> circuit board and The substrate comprises a multilayer ceramic electronic component mounted on the mounting surface of the substrate, The aforementioned multilayer ceramic electronic component is The laminate comprises a plurality of ceramic layers stacked in a first axial direction, a plurality of internal electrodes located between the plurality of ceramic layers, a pair of side surfaces perpendicular to a second axis orthogonal to the first axis, on which the ends of the plurality of internal electrodes in the second axial direction are located, and a pair of side margins covering the pair of side surfaces. The Si concentration in each of the pair of side margin portions is 1 at% or more. Each of the pair of side margin portions has a rectangular shape with four corners in a plan view perpendicular to the side surface, Each of the pair of side margin portions is A first surface facing the aforementioned side surface, The second side is the opposite of the first side, It has, The second side is, Each of the four first regions includes each of the four corners, A second region adjacent to the first region, It has, The first distance between the first surface and the first region is smaller than the second distance between the first surface and the second region. The first region and the second region are opposite the mounting surface. Circuit board. [Explanation of symbols]

[0135] 1, 1A, 1B, 1C, 1D 1st area 2, 2A, 2B 2nd area 3A, 3B, 3C, 3D, 3E 3rd area 4 4th area 11 Ceramic Body 12 1st internal electrode 13 Second internal electrode 14 1st external electrode 15 2nd external electrode 16 Laminate 17 Side margin section 18 Capacity forming part 19 Cover margin section 21 Interelectrode ceramic layer 22. Outermost ceramic layer 51 Page 1 52 2nd page 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 Multilayer ceramic capacitors 171, 171A, 171B, 171C, 171D Corner F side

Claims

1. The laminate comprises a plurality of ceramic layers stacked in the first axial direction, a plurality of internal electrodes located between the plurality of ceramic layers, a pair of side surfaces perpendicular to a second axis orthogonal to the first axis, on which the ends of the plurality of internal electrodes in the second axial direction are located, and a pair of side margins covering the pair of side surfaces. The Si concentration in each of the pair of side margin portions is 1 at% or more. Each of the pair of side margin portions has a rectangular shape with four corners in a plan view perpendicular to the side surface. Each of the pair of side margin portions is A first surface facing the aforementioned side surface, The second side is opposite to the first side, It has, The second side is, Each of the four first regions includes each of the four corners, A second region adjacent to the first region, It has, The first distance between the first surface and the first region is smaller than the second distance between the first surface and the second region. Multilayer ceramic electronic components.

2. The Si concentration in each of the pair of side margin portions is 10 at% or less. The multilayer ceramic electronic component according to claim 1.

3. The proportion of the area occupied by the second region within the second surface is 10% or more. The multilayer ceramic electronic component according to claim 2.

4. The second distance is 0.1 times or more the first distance. A multilayer ceramic electronic component according to any one of claims 1 to 3.

5. The second distance is 0.9 times or less the first distance. A multilayer ceramic electronic component according to any one of claims 1 to 3.

6. The third distance between the corner and the second region in the plan view is less than or equal to twice the fourth distance between the first region and the second region in the thickness direction of the side margin. A multilayer ceramic electronic component according to any one of claims 1 to 3.

7. The second surface has one to 100 of the second regions. A multilayer ceramic electronic component according to any one of claims 1 to 3.

8. Each of the pair of side margins has a rectangular shape in plan view, comprising a pair of long sides and a pair of short sides. The second region extends along the pair of long sides. A multilayer ceramic electronic component according to any one of claims 1 to 3.

9. Each of the pair of side margins has a rectangular shape in plan view, comprising a pair of long sides and a pair of short sides. The second region extends along the pair of short sides. A multilayer ceramic electronic component according to any one of claims 1 to 3.

10. Two of the first regions, each including two corners located diagonally opposite each other, are connected. A multilayer ceramic electronic component according to any one of claims 1 to 3.

11. Each of the pair of side margins has a rectangular shape in plan view, comprising a pair of long sides and a pair of short sides. The second region extends in a direction inclined from the pair of long sides and the pair of short sides. The multilayer ceramic electronic component according to claim 10.

12. Having an external electrode connected to the internal electrode, The external electrode has a portion in the thickness direction of the side margin that is further away from the first surface than the second surface. A multilayer ceramic electronic component according to any one of claims 1 to 3.

13. The external electrode covers at least the first region The multilayer ceramic electronic component according to claim 12.

14. The laminate has a pair of cover margins laminated so as to sandwich the plurality of ceramic layers and the plurality of internal electrodes from both sides in the first axial direction. In the aforementioned plan view, the four first regions overlap with the cover margin portion. A multilayer ceramic electronic component according to any one of claims 1 to 3.

15. In a plan view perpendicular to the second surface, the first region is arranged symmetrically with respect to the line bisector parallel to the first axis of the second surface. A multilayer ceramic electronic component according to any one of claims 1 to 3.

16. A step of preparing a laminate having a plurality of ceramic layers stacked in a first axial direction, a plurality of internal electrodes located between the plurality of ceramic layers, and a pair of sides perpendicular to a second axis orthogonal to the first axis, on which the ends of the plurality of internal electrodes in the second axial direction are located, A step of forming a pair of side margin portions that cover the pair of sides, have a Si concentration of 1 at% or more, have a rectangular shape with four corners in a plan view perpendicular to the side, and have a first surface facing the side and a second surface opposite to the first surface, A step of pressurizing a portion of the pair of side margin portions, It has, By applying pressure to a portion of the pair of side margin portions, The second side is, Each of the four first regions includes each of the four corners, A second region adjacent to the first region, It has, The first distance between the first surface and the first region is smaller than the second distance between the first surface and the second region. A method for manufacturing multilayer ceramic electronic components.

17. The step of pressurizing a portion of the pair of side margin portions is: The process includes pressing a mold having a recess in the portion where the first region is formed and a protrusion in the portion where the second region is formed against the side margin portion. A method for manufacturing a multilayer ceramic electronic component according to claim 16.

18. circuit board and The substrate comprises a multilayer ceramic electronic component mounted on the mounting surface of the substrate, The aforementioned multilayer ceramic electronic component is The laminate comprises a plurality of ceramic layers stacked in the first axial direction, a plurality of internal electrodes located between the plurality of ceramic layers, a pair of side surfaces perpendicular to a second axis orthogonal to the first axis, on which the ends of the plurality of internal electrodes in the second axial direction are located, and a pair of side margins covering the pair of side surfaces. The Si concentration in each of the pair of side margin portions is 1 at% or more. Each of the pair of side margin portions has a rectangular shape with four corners in a plan view perpendicular to the side surface. Each of the pair of side margin portions is A first surface facing the aforementioned side surface, The second side is opposite to the first side, It has, The second side is, Each of the four first regions includes each of the four corners, A second region adjacent to the first region, It has, The first distance between the first surface and the first region is smaller than the second distance between the first surface and the second region. The first region and the second region are opposite the mounting surface. Circuit board.

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