Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor capable of suppressing structural defects. [Solution] The multilayer ceramic capacitor 1 comprises a laminate 2 and a pair of external electrodes 3 arranged in pairs in the longitudinal direction L. The laminate 2 has an inner layer 11 formed by an effective portion 15a and an inner dielectric layer 14, and a pair of outer layers 12 arranged sandwiching the inner layer 11 in the lamination direction T. The width dimension W of the laminate 2 is greater than the length dimension L of the laminate 2. The internal electrodes 15 contain Cu. The dielectric portion 10 contains Zr and an alkaline earth metal element which is at least one of Ca and Sr. The inner dielectric layer 14 has an inner layer Zr-rich region RA1. The outer layers 12 have an outer layer Zr-rich region RA2.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor.

Background Art

[0002] Conventionally, there is a multilayer ceramic capacitor including an inner layer portion in which a plurality of dielectric layers and internal electrodes are laminated, and an outer layer portion disposed sandwiching the inner layer portion. Among multilayer ceramic capacitors, there are those having excellent high-frequency characteristics (for example, Patent Document 1).

[0003] In the multilayer ceramic capacitor of Patent Document 1, the internal electrode contains Cu as a main component. According to such a configuration, since Cu has a relatively small specific resistance, signal loss in the high-frequency region can be suppressed.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, the difference in the ease of shrinkage between the inner layer portion where the internal electrode containing Cu with a relatively large linear expansion coefficient is disposed and the outer layer portion where the internal electrode is not disposed is considered to be relatively large. Therefore, it is considered that structural defects such as peeling and cracks are likely to occur at the boundary between the inner layer portion and the outer layer portion.

[0006] An object of the present invention is to provide a multilayer ceramic capacitor capable of suppressing the occurrence of structural defects.

Means for Solving the Problems

[0007] To solve the above problems, the multilayer ceramic capacitor of the present invention includes a dielectric portion and a plurality of internal electrodes stacked on either side of the dielectric portion, and comprises a laminate having a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction, and a pair of external electrodes arranged in pairs in the length direction and connected to the internal electrodes, wherein the laminate has an internal electrode facing an adjacent internal electrode. The laminate comprises an inner layer formed by an inner dielectric layer which is a portion of the dielectric layer sandwiched between adjacent effective portions, and a pair of outer layers which are arranged sandwiching the inner layer in the stacking direction, wherein the width dimension of the laminate is greater than the length dimension of the laminate, the internal electrode contains Cu, the dielectric layer contains Zr and an alkaline earth metal element which is at least one of Ca and Sr, the inner dielectric layer has an inner Zr-rich region, and the outer layers have an outer Zr-rich region. [Effects of the Invention]

[0008] This provides a multilayer ceramic capacitor that can suppress the occurrence of structural defects. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic perspective view of a multilayer ceramic capacitor according to an embodiment. [Figure 2] This is a cross-sectional view taken along line II-II in Figure 1. [Figure 3] This is a cross-sectional view taken along line III-III in Figure 1. [Figure 4] This is an enlarged view of section IV in Figure 2. [Figure 5] This is an enlarged view of section V in Figure 2. [Modes for carrying out the invention]

[0010] Hereinafter, a multilayer ceramic capacitor 1 according to an embodiment of the present invention will be described with reference to Figures 1 to 5.

[0011] (Multilayer ceramic capacitor 1) As shown in Figure 1, the multilayer ceramic capacitor 1 is a two-terminal type multilayer ceramic capacitor. The multilayer ceramic capacitor 1 is an LW reverse type multilayer ceramic capacitor. The multilayer ceramic capacitor 1 comprises a laminate 2 and a pair of external electrodes 3. The laminate 2 is substantially rectangular in shape and has six outer surfaces. The laminate 2 includes a dielectric portion 10 and a plurality of internal electrodes 15 stacked on either side of the dielectric portion 10.

[0012] In this specification, the direction in which the dielectric portion 10 and the internal electrodes 15 are stacked in a multilayer ceramic capacitor 1 is defined as the stacking direction T. One of the directions perpendicular to the stacking direction T is defined as the length direction L. The directions perpendicular to the length direction L and the stacking direction T are defined as the width direction W.

[0013] Of the six outer surfaces of the laminate 2, a pair of outer surfaces provided on both sides in the lamination direction T are designated as the first main surface AA and the second main surface AB, a pair of outer surfaces extending in the lamination direction T and provided on both sides in the width direction W are designated as the first side surface BA and the second side surface BB, and a pair of outer surfaces extending in the lamination direction T and provided on both sides in the length direction L are designated as the first end surface CA and the second end surface CB.

[0014] The first main surface AA and the second main surface AB are sometimes collectively referred to as "each main surface A". The first side surface BA and the second side surface BB are sometimes collectively referred to as "each side surface B". The first end surface CA and the second end surface CB are sometimes collectively referred to as "each end surface C".

[0015] A cross-section parallel to the stacking direction T and the length direction L is defined as the "LT cross-section". The cross-section in Figure 2 is the LT cross-section passing through the center of the width direction W of the multilayer ceramic capacitor 1. A cross-section parallel to the stacking direction T and the width direction W is defined as the "WT cross-section". The cross-section in Figure 3 is the WT cross-section passing through the center of the length direction L of the multilayer ceramic capacitor 1.

[0016] (Laminate 2) The laminate 2 has a substantially rectangular parallelepiped shape. The dimension in the width direction W of the laminate 2 is larger than the dimension in the length direction L of the laminate 2. The dimension in the length direction L of the laminate 2 is, for example, 0.2 mm or more and 2.2 mm or less. The dimension in the width direction W of the laminate 2 is, for example, 0.1 mm or more and 1.5 mm or less. The dimension in the stacking direction T of the laminate 2 is, for example, 0.1 mm or more and 1.0 mm or less. The outer dimensions of the multilayer ceramic capacitor 1 can be measured with a micrometer.

[0017] A portion where three outer surfaces of the laminate 2 intersect is defined as a "corner portion". A portion where two outer surfaces of the laminate 2 intersect is defined as a "ridge line portion". It is preferable that the corner portions and the ridge line portions of the laminate 2 are rounded.

[0018] As shown in FIGS. 2 and 3, the laminate 2 includes a dielectric part 10 and a plurality of internal electrodes 15.

[0019] (Dielectric part) The dielectric part 10 is formed in a substantially rectangular parallelepiped shape as a whole. The dielectric part 10 is mainly composed of, for example, a ceramic containing at least any one of Ca, Sr, Zr, and Ti. The main component of the dielectric part 10 is, for example, a dielectric ceramic having a perovskite structure represented by the general formula ABO3 containing Ca and Zr. The main component of the dielectric part 10 is, for example, a composite oxide having a composition represented by (Ca 1-x , Sr x )m(Zr 1-z , Ti z )O3, where x is 0 or more and 1 or less, m is 1.0 or more and 1.1 or less, and z is 0 or more and 0.2 or less. The main component of the dielectric part 10 is, for example, CaZrO3 (calcium zirconate). The dielectric part 10 may contain CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), BaZrO3 (proton-conductive metal oxide), titanium oxide (TiO2), etc. Note that the main component of the dielectric part means a component that is 50 mass% or more of the components constituting the dielectric part.

[0020] The main component of the ceramic material forming the dielectric part 10 may include all of Ca, Zr, and Ti. For example, the dielectric part 10 may be Ca(Zr0.9Ti0.1)O3, which is a substance in which a portion of ZrO3 or Zr in CaZrO3 is substituted with Ti. The dielectric part 10 may contain all of Ca, Zr, and Ti. For example, the dielectric part 10 may contain Ca(Zr0.9Ti0.1)O3, which is a substance in which a portion of ZrO3 or Zr in CaZrO3 is substituted with Ti.

[0021] The dielectric portion 10 has glass containing Si oxide, Li, B, Na, K, etc. By adjusting the amount of glass contained in the dielectric portion 10, the temperature at which the laminate 2 sintersects can be adjusted.

[0022] The dielectric portion 10 may contain additives. Examples of additives include oxides of Mn, Mg, Dy, Cr, or rare earth elements such as V, Sm, Eu, Gd, Tb, Ho, Er, Tm, Yb, Y, or Co, Ni, etc.

[0023] (Internal electrode) The internal electrodes 15 are arranged inside the dielectric portion 10. Multiple internal electrodes 15 are arranged at intervals in the stacking direction T. Layers of dielectric portion 10 are arranged between adjacent internal electrodes 15. In other words, the internal electrodes 15 and a portion of the dielectric portion 10 are stacked in the stacking direction T. The total number of internal electrodes 15 is, for example, between 1 and 100.

[0024] The internal electrode 15 contains at least Cu among metals such as Ni, Cu, Ag, Pd, Ag-Pd alloy, Au, and Sn. The main component of the internal electrode is Cu. The internal electrode 15 is formed by sintering a conductive paste containing conductive metal powder, an organic solvent, a binder, and a dispersant on a dielectric sheet. The main component of the internal electrode refers to the component that makes up 50% by mass or more of the components constituting the internal electrode.

[0025] The internal electrode 15 has a plurality of first internal electrodes 15A and a plurality of second internal electrodes 15B. The first internal electrodes 15A and the second internal electrodes 15B are arranged alternately, for example.

[0026] The first internal electrode 15A is exposed to the first end face CA. The first internal electrode 15A has a first effective portion 15Aa and a first lead-out portion 15Ab. The first effective portion 15Aa is the part of the first internal electrode 15A that faces the adjacent second internal electrode 15B. The first lead-out portion 15Ab is the part of the first internal electrode 15A that is led out from the first effective portion 15Aa toward the first end face CA.

[0027] The second internal electrode 15B is exposed to the second end face CB. The second internal electrode 15B has a second effective portion 15Ba and a second lead portion 15Bb. The second effective portion 15Ba is the part of the second internal electrode 15B that faces the adjacent first internal electrode 15A (first effective portion 15Aa). The second lead portion 15Bb is the part of the second internal electrode 15B that is led out from the second effective portion 15Ba toward the second end face CB.

[0028] Note that the first internal electrode 15A and the second internal electrode 15B are sometimes collectively referred to as "internal electrode 15". The first effective part 15Aa and the second effective part 15Ba are sometimes collectively referred to as "effective part 15a".

[0029] Furthermore, the laminate 2 includes an inner layer 11, a pair of outer layer 12 positioned between the inner layer 11 in the stacking direction T, a pair of side gap portions 13S positioned between the inner layer 11 and each outer layer 12 in the width direction W, and a pair of end gap portions 13E positioned between the inner layer 11 and each outer layer 12 in the length direction L.

[0030] (Inner layer 11) The inner layer 11 is a portion of the laminate 2 consisting of an effective portion 15a and an inner dielectric layer 14, which is the portion of the dielectric portion 10 sandwiched between adjacent effective portions 15a. In the inner layer 11, the first effective portion 15Aa and the second effective portion 15Ba face each other with the inner dielectric layer 14 in between. This forms a portion that generates capacitance.

[0031] (outer layer) The outer layer 12 consists of a portion of the laminate 2 sandwiched between the inner layer 11 and the first main surface AA, and a portion of the laminate 2 sandwiched between the inner layer 11 and the second main surface AB. The outer layer 12 is composed of a part of the dielectric portion 10. The outer layer 12 is composed of dielectric ceramic. No internal electrodes 15 are arranged in the outer layer 12.

[0032] (Side gap area) The side gap portion 13S consists of the portion of the laminate 2 sandwiched between the inner layer portion 11 and the first side surface BA, and the portion of the laminate 2 sandwiched between the inner layer portion 11 and the second side surface BB. The side gap portion 13S is composed of a part of the dielectric portion 10. No internal electrodes 15 are located in the side gap portion 13S.

[0033] (End gap section) The side gap portion 13S is the portion of the laminate 2 sandwiched between the inner layer portion 11 and the first end face CA, and the portion of the laminate 2 sandwiched between the inner layer portion 11 and the second end face CB. Of the pair of end gap portions 13E, one is composed of a part of the dielectric portion 10 and the first lead portion 15Ab, and the other is composed of a part of the dielectric portion 10 and the second lead portion 15Bb.

[0034] (External electrode 3) The external electrodes 3 are arranged on the laminate 2. The external electrodes 3 are arranged in pairs in the longitudinal direction L. The external electrodes 3 are connected to the internal electrodes 15. The external electrodes 3 have a first external electrode 3A and a second external electrode 3B.

[0035] The first external electrode 3A is positioned on the first end face CA and connected to the first internal electrode 15A. The first external electrode 3A covers not only the first end face CA, but also, for example, a part of the main surface A and a part of the side surface B. The first external electrode 3A has a first base electrode layer 31A and a first plating layer 32A positioned on the first base electrode layer 31A. The first plating layer 21A includes a first inner plating layer 321A positioned on the first base electrode layer 31A and a first outer plating layer 322A positioned on the first inner plating layer 321A.

[0036] The second external electrode 3B is positioned on the second end face CB and connected to the second internal electrode 15B. The second external electrode 3B covers not only the second end face CB, but also, for example, a portion of the main surface A and a portion of the side surface B. The second external electrode 3B has a second base electrode layer 31B and a second plating layer 32B positioned on the second base electrode layer 31B. The second plating layer 21B includes a second inner plating layer 321B positioned on the second base electrode layer 31B and a second outer plating layer 322B positioned on the second inner plating layer 321B.

[0037] Note that the first base electrode layer 31A and the second base electrode layer 31B are sometimes collectively referred to as "base electrode layer 31". The first plating layer 32A and the second plating layer 32B are sometimes collectively referred to as "plating layer 32". The first inner plating layer 321A and the second inner plating layer 321B are sometimes collectively referred to as "inner plating layer 321". The first outer plating layer 322A and the second outer plating layer 322B are sometimes collectively referred to as "outer plating layer 322".

[0038] The external electrode 3 includes a base electrode layer 31 placed on the surface of the laminate 2 and a plating layer 32 placed on the base electrode layer 31.

[0039] The base electrode layer 31 mainly consists of conductive metals such as Cu, Ni, Ag, Pd, Au, and Ag-Pd alloys. Preferably, the base electrode layer 31 contains Cu as its main component. The base electrode layer 31 is, for example, a baked layer containing a conductive metal and glass. The main component of the base electrode layer refers to the component that makes up 50% by mass or more of the components constituting the base electrode layer.

[0040] The plating layer 32 is composed of, for example, one metal selected from the group consisting of Cu, Ni, Ag, Pd, Au, and Sn, or an alloy containing this metal. The plating layer 32 includes, for example, an inner plating layer 321 disposed on the underlay electrode layer 31 and an outer plating layer 322 disposed on the inner plating layer 321. The inner plating layer 321 is, for example, a Ni plating layer. The outer plating layer 322 is, for example, a Sn (tin) plating layer. The plating layer 32 may also have a single-layer structure.

[0041] Here, the width dimension W of the laminate 2 is greater than the length dimension L of the laminate 2. The internal electrode 15 contains Cu. The dielectric portion 10 contains Zr and an alkaline earth metal element which is at least one of Ca and Sr.

[0042] As shown in Figure 4, the inner dielectric layer 14 has an inner Zr-rich region RA1. As shown in Figure 5, the outer layer 12 has an outer Zr-rich region RA2. The inner Zr-rich region RA1 and the outer Zr-rich region RA2 are sometimes collectively referred to as the "Zr-rich region RA".

[0043] The term "Zr-rich region" refers to a region in the dielectric portion 10 that satisfies both of the following conditions (A) and (B) in the cross-section LT passing through the center of the width W of the multilayer ceramic capacitor. A region containing both Zr and alkaline earth metal elements, where the content of the alkaline earth metal element is 1 / 4 or less of the content of Zr... (A) A region with a maximum diameter of 500 nm or more in length...(B) The "maximum regional diameter" of a given region refers to the distance between two parallel lines that enclose the region in such a way that the distance between the lines is maximized.

[0044] The content of metal elements in the dielectric portion 10 is measured, for example, by energy-dispersive X-ray spectroscopy (TEM-EDX).

[0045] The alkaline earth metal element contained in the dielectric portion 10 is, for example, Ca, and the dielectric portion 10 contains, for example, a composite oxide containing Zr and Ca.

[0046] More specifically, the dielectric part 10 is (Ca 1-x Sr x )m(Zr 1-z Ti z A composite oxide represented by O3, having a composition in which x is between 0 and 1, m is between 1.0 and 1.1, and z is between 0 and 0.2, and containing a composite oxide containing Zr and Ca.

[0047] For example, the inner dielectric layer 14 contains a composite oxide containing Zr and Ca. The outer layer 12 contains a composite oxide containing Zr and Ca.

[0048] The alkaline earth metal element contained in the dielectric part 10 may be Sr, and the dielectric part 10 may contain a composite oxide containing Zi, Ti and Sr, and the Zr content in the dielectric part 10 may be greater than the Ti content in the dielectric part 10.

[0049] For example, the inner dielectric layer 14 may contain a composite oxide containing Zi, Ti, and Sr, and the Zr content in the inner dielectric layer 14 may be greater than the Ti content in the inner dielectric layer 14. The outer layer 12 may contain a composite oxide containing Zr, Ti, and Sr, and the Zr content in the outer layer 12 may be greater than the Ti content in the outer layer 12.

[0050] The dielectric portion 10 contains at least one of Li, Na, Mn, B, and Si.

[0051] For example, the inner dielectric layer 14 contains at least one of Li, Na, Mn, B, and Si. The outer layer 12 contains at least one of Li, Na, Mn, B, and Si.

[0052] The external electrode 3 (more specifically, the base electrode layer 31) contains Cu.

[0053] For example, the first external electrode 3A (more specifically, the first base electrode layer 31A) contains Cu. The second external electrode 3B (more specifically, the second base electrode layer 31B) contains Cu.

[0054] The area of ​​the inner Zr-rich region RA1 per unit area in the inner dielectric layer 14 is smaller than the area of ​​the outer Zr-rich region RA2 per unit area in the outer layer 12.

[0055] The area of ​​the inner Zr-rich region per unit area in the inner dielectric layer is sometimes simply referred to as the "area ratio of the inner Zr-rich region." Similarly, the area of ​​the outer Zr-rich region per unit area in the outer layer is sometimes simply referred to as the "area ratio of the outer Zr-rich region." The area ratio of the inner Zr-rich region and the area ratio of the outer Zr-rich region are sometimes collectively referred to as the "area ratio of the Zr-rich region." The area ratio of the Zr-rich region is also the area of ​​the Zr-rich region per unit area in the dielectric layer.

[0056] The area ratio of the Zr-rich region is defined as the value obtained by dividing the total area of ​​the Zr-rich region within the field of view by the total area of ​​the dielectric portion within the field of view. The field of view is, for example, 0.1 μm × 0.1 μm.

[0057] The ratio of the area of ​​the inner Zr-rich region RA1 per unit area in the inner dielectric layer 14 to the area of ​​the outer Zr-rich region RA2 per unit area in the outer layer 12 is between 0.05 and 0.9.

[0058] Furthermore, the ratio of the area of ​​the inner Zr-rich region RA1 per unit area in the inner dielectric layer 14 to the area of ​​the outer Zr-rich region RA2 per unit area in the outer layer 12 is sometimes simply called the "area ratio of the Zr-rich region." In other words, the area ratio of the Zr-rich region is the value obtained by dividing the area ratio of the inner Zr-rich region by the area ratio of the outer Zr-rich region.

[0059] (Method for manufacturing a multilayer ceramic capacitor 1) Next, the manufacturing method of the multilayer ceramic capacitor 1 according to this embodiment will be described.

[0060] (Dielectric sheet manufacturing process) First, a ceramic slurry is prepared as the material for the dielectric sheet. The ceramic slurry for the dielectric part contains ceramic raw materials including dielectric ceramics, as well as a binder and a solvent.

[0061] The materials constituting the ceramic raw material are, for example, powders of CaZrO3, SrZrO3, SrTiO3, and CaTiO3. Each powder is obtained, for example, by wet mixing, drying, firing in air at a predetermined temperature, and grinding the raw material powders. For example, the raw materials for CaZrO3 powder are CaCO3 powder and ZrO2 powder. For example, the raw materials for SrZrO3 powder are SrCO3 powder and ZrO2 powder. For example, the raw materials for SrTiO3 powder are SrCO3 powder and TiO2 powder. For example, the raw materials for CaTiO3 powder are CaCO3 powder and TiO2 powder. Three or more powders from CaCO3 powder, ZrO2 powder, SrCO3 powder, and TiO2 powder may be mixed. The content of Zr, Ti, Ca, and Sr in the ceramic is adjusted by the blending of powders such as CaZrO3, SrZrO3, SrTiO3, and CaTiO3.

[0062] Glass is added to the ceramic slurry for dielectric sheets. Additives may also be added to the ceramic raw materials. Examples of additives include B2O3, SiO2, Li2CO3, BaCO3, SrCO3, MgCO3, etc.

[0063] For dielectric sheets, two ceramic slurries are prepared: one for the inner layer, side gap, and end gap (sometimes referred to as the "first ceramic slurry"), and another for the outer layer (sometimes referred to as the "second ceramic slurry"). The composition of the first ceramic slurry and the composition of the second ceramic slurry are different. At a minimum, the glass content of the second ceramic slurry is greater than that of the first ceramic slurry.

[0064] The first ceramic slurry is formed into a sheet. This yields a dielectric sheet (sometimes referred to as the "first dielectric sheet") that will be the material for the inner layer, side gap, and end gap. The second ceramic slurry is also formed into a sheet. This yields a dielectric sheet (sometimes referred to as the "second dielectric sheet") that will be the material for the outer layer. However, the portion of the side gap aligned with the outer layer in the width direction W, and the portion of the end gap aligned with the outer layer in the length direction L, are formed by the second dielectric sheet, respectively.

[0065] (Internal electrode pattern formation process) Next, an internal electrode pattern (sometimes simply called the "internal electrode pattern") is printed onto the first dielectric sheet using conductive paste. The internal electrode pattern is formed by printing methods such as screen printing, gravure printing, or letterpress printing. The shape of the internal electrode pattern, when viewed in the stacking direction T, is, for example, rectangular. Note that the internal electrode pattern is not printed on the second dielectric sheet.

[0066] (Lamination process) Next, a first dielectric sheet is laminated. The first dielectric sheets are laminated such that the internal electrode patterns are offset by half a pitch in the length direction L between adjacent sheets. Then, second dielectric sheets are laminated on both sides of the laminated first dielectric sheets in the lamination direction T. The second dielectric sheets are thermocompressed onto the laminated first dielectric sheets. This gives rise to a mother block.

[0067] Each outer layer may consist of multiple laminated second dielectric sheets, or it may consist of a single second dielectric sheet.

[0068] (cutting process) Next, the mother block is cut along cutting lines corresponding to the dimensions of the laminate 2. The mother block is cut, for example, in the length direction L and the width direction W. This yields multiple rectangular blocks (referred to as "laminated chips"). Preferably, the corners and edges of the laminated chips are rounded, for example, by barrel polishing.

[0069] (Laminate firing process) Next, the laminated chips are heated in a nitrogen atmosphere at a predetermined firing temperature for a predetermined time. This yields the laminated body 2. The firing conditions were appropriately adjusted to form a Zr-rich region.

[0070] The dielectric sheet contains Zr, alkaline earth metal elements (Ca or Sr), and glass. By appropriately adjusting the firing conditions during the firing of the laminated chip, only the alkaline earth metal elements migrate toward the glass. As a result, in the region where Zr and alkaline earth metal elements were present, the ratio of Zr to alkaline earth metal elements becomes larger. This causes Zr segregation in the dielectric portion, forming a Zr-rich region. The glass content of the second dielectric sheet is higher than that of the first dielectric sheet. This makes it possible to make the area ratio of the Zr-rich region in the outer layer larger than the area ratio of the Zr-rich region in the inner dielectric layer.

[0071] (Base electrode layer formation process) Next, a base electrode layer 31 is formed on each end face C of the laminate 2. A conductive paste containing glass and metal is applied to the laminate 2. The conductive paste is applied, for example, from the end face C to a portion of each main surface A and a portion of each side surface B.

[0072] (Underlay electrode layer curing process) Next, the laminate 2 on which the base electrode layer 31 is formed is heated in a nitrogen atmosphere at a predetermined firing temperature for a predetermined time. This causes the base electrode layer 31 to be baked onto the laminate 2. Note that the laminate firing process and the base electrode layer baking process may be performed simultaneously after the base electrode layer material has been placed on the laminate chip.

[0073] (Plating process) Next, a plating layer 32 is formed on the base electrode layer 31. First, an inner plating layer 321 is formed on the base electrode layer 31. Then, an outer plating layer 322 is formed on the inner plating layer 321. The inner plating layer 321 is formed, for example, by Ni plating. The outer plating layer 322 is formed, for example, by Sn plating. The inner plating layer 321 and the outer plating layer 322 are formed sequentially, for example, by an electroplating method.

[0074] Based on the above, the multilayer ceramic capacitor 1 shown in Figure 1 is obtained.

[0075] <Example of experiment> Using the manufacturing method described above, multilayer ceramic capacitors were fabricated as experimental samples. Various tests were conducted using these experimental samples.

[0076] 1. Manufacturing of multilayer ceramic capacitors As samples for experimental examples and comparative examples, multilayer ceramic capacitors having the same structure as the above-described multilayer ceramic capacitor 1 were fabricated. The alkaline earth metal element contained in the dielectric part was Ca. The experimental examples were Experimental Examples 1 to Experimental Examples 7. The comparative example was Comparative Example 1. For each of the experimental examples and the comparative example, 500 multilayer ceramic capacitors of each sample were fabricated.

[0077] In each of the experimental examples and the comparative example, the dimensions of the multilayer ceramic capacitor were all L×W×T = 0.33 mm×0.63 mm×0.22 mm.

[0078] The area ratio of the Zr-rich region (that is, the area ratio of the inner-layer Zr-rich region / the area ratio of the outer-layer Zr-rich region) differed for each of the experimental examples and the comparative example. By adjusting the glass content rate of the dielectric sheet, the area of the Zr-rich region was adjusted for each of the experimental examples and the comparative example. More specifically, at the time of manufacturing the samples of the examples, the glass content rate of the first dielectric sheet and the glass content rate of the second dielectric sheet were each adjusted within the range of 2% or more and 12% or less. As the glass, glass containing Ca was used. At the time of manufacturing the samples of the comparative example, the glass content rate of the first dielectric sheet and the glass content rate of the second dielectric sheet were each set to 1% or less.

[0079] 2. Evaluation Next, for the fabricated samples, the ratio of the area ratio of the inner-layer Zr-rich region to the area ratio of the outer-layer Zr-rich region (that is, the area ratio of the Zr-rich region) and the structure defect occurrence rate were measured, and the obtained results were evaluated.

[0080] <Area ratio of Zr-rich region> The LT cross-section passing through the central part in the width direction W of the multilayer ceramic capacitor was exposed by polishing. The exposed cross-section was subjected to elemental analysis by TEM-EDX. The visual field range was set to 0.1 μm×0.1 μm. Zr and Ca were used as the elements to be analyzed.

[0081] A region in which Zr and Ca at an intensity of 1 / 4 or less of the maximum intensity of Zr are detected, and which has a maximum region diameter of 500 nm or more, was defined as a Zr-rich region. The area of ​​the inner Zr-rich region was measured in the inner dielectric layer. The area ratio of the inner Zr-rich region was calculated by dividing the area of ​​the inner dielectric layer in the field of view. The area of ​​the outer Zr-rich region was measured in the outer layer. The area ratio of the outer Zr-rich region was calculated by dividing the area of ​​the outer layer in the field of view. The area ratio of the Zr-rich region was calculated by dividing the area ratio of the inner Zr-rich region by the area ratio of the outer Zr-rich region.

[0082] For each example and comparative example, the area ratio of the Zr-rich region was measured for 500 samples. The area ratio of the Zr-rich region for each sample was averaged for each example and comparative example. The resulting average value was used as the area ratio of the Zr-rich region for each example and comparative example.

[0083] <Structural defect rate> The LT cross-section passing through the center of the laminate in the width direction was observed using an optical microscope. Samples in which at least one of the following was observed—delamination between the inner and outer layers, or cracks—were designated as defective samples. The number of defective samples out of 500 samples was defined as the structural defect incidence rate.

[0084] For each experimental example and comparative example, the number of defective samples out of 500 samples, specifically those whose insulation resistance value fell outside the specified range, was evaluated as follows: 0 samples were rated as "good," 1 to 10 samples were rated as "generally good," and 11 or more samples were rated as "poor."

[0085] 3.Measurement results Table 1 shows the measurement results of the area ratio of the Zr-rich region, as well as the measurement and evaluation results of the structural defect occurrence rate for Comparative Example 1 and Experimental Examples 1 to 7, respectively.

[0086] [Table 1]

[0087] In Comparative Example 1, no Zr-rich regions were observed. In Comparative Example 1, the incidence of structural defects was relatively high.

[0088] Experimental examples 2-6 confirmed that the occurrence of structural defects is suitably suppressed when the area ratio of the Zr-rich region is between 0.05 and 0.9.

[0089] Experimental Example 1 suggests that when the area ratio of the Zr-rich region is less than 0.01, the effect of suppressing the occurrence of structural defects may be slightly reduced. This is thought to be because if the area ratio of the outer layer Zr-rich region is too large compared to the area ratio of the inner layer Zr-rich region, the outer layer becomes too prone to shrinking relative to the inner dielectric layer.

[0090] Experimental Example 7 suggests that when the area ratio of the Zr-rich region is 0.980 or higher, the effect of suppressing the occurrence of structural defects may be slightly reduced. This is thought to be because if the difference between the area ratio of the outer layer Zr-rich region and the area ratio of the inner layer Zr-rich region is too small, the ease with which the outer layer shrinks becomes insufficient compared to the ease with which the inner dielectric layer shrinks.

[0091] (Effects according to the embodiment) According to this embodiment, the following effects can be obtained.

[0092] According to the above embodiment, the multilayer ceramic capacitor 1 includes a dielectric portion 10 and a plurality of internal electrodes 15 stacked on either side of the dielectric portion 10, and comprises a laminated body 2 having a first main surface AA and a second main surface AB facing the stacking direction T, a first side surface BA and a second side surface BB facing the width direction W perpendicular to the stacking direction T, and a first end surface CA and a second end surface CB facing the length direction L perpendicular to the stacking direction T and the width direction W, and a pair of external electrodes 3 arranged in pairs in the length direction L and each connected to the internal electrodes 15. The laminated body 2 has an inner layer portion 11 formed by an effective portion 15a of the internal electrodes 15 that faces adjacent internal electrodes 15 and an inner dielectric layer 14 that is sandwiched between adjacent effective portions 15a of the dielectric portion 10, and a pair of outer layer portions 12 arranged sandwiching the inner layer portion 11 in the stacking direction T. The width direction W dimension of the laminated body 2 is larger than the length direction L dimension of the laminated body 2. The internal electrode 15 contains Cu. The dielectric portion 10 contains Zr and an alkaline earth metal element which is at least one of Ca and Sr. The inner dielectric layer 14 has an inner Zr-rich region RA1. The outer layer 12 has an outer Zr-rich region RA2.

[0093] In this configuration, the multilayer ceramic capacitor 1 is an LW inverted type multilayer ceramic capacitor in which the width W dimension of the laminate 2 is larger than the length L dimension of the laminate 2. This makes it possible to shorten the current path by shortening the distance between the external electrodes 3, or to widen the current path by increasing the width W dimension of the external electrodes 3 and the internal electrodes 15, thereby reducing ESL.

[0094] The internal electrode 15 contains Cu. Since Cu has a relatively low resistivity, it can reduce ESR.

[0095] The dielectric portion 10 contains Zr and an alkaline earth metal element, which is at least one of Ca and Sr. This reduces dielectric loss.

[0096] These factors allow for improved high-frequency characteristics.

[0097] Furthermore, an inner Zr-rich region RA1 is formed in the inner dielectric layer 14, and an outer Zr-rich region RA2 is formed in the outer layer 12. The larger the area of ​​the Zr-rich region RA within a region, the more easily that region shrinks. Therefore, by adjusting the area of ​​the inner Zr-rich region RA1 and the area of ​​the outer Zr-rich region RA2, the ease with which the inner dielectric layer 14 shrinks and the ease with which the outer layer 12 shrinks can be balanced. This allows the shrinkage behavior of the inner layer 11 and the shrinkage behavior of the outer layer 12 to be synchronized, thereby suppressing the occurrence of structural defects.

[0098] According to the above embodiment, the alkaline earth metal element is Ca, and the dielectric portion 10 contains a composite oxide containing Zr and Ca.

[0099] With this configuration, ESR can be suitably reduced. The occurrence of structural defects can be suitably suppressed.

[0100] According to the above embodiment, the alkaline earth metal element may be Sr, and the dielectric part 10 may contain a composite oxide containing Zr, Ti, and Sr, and the Zr content in the dielectric part 10 may be greater than the Ti content in the dielectric part 10.

[0101] With this configuration, in a configuration in which the dielectric portion 10 contains a composite oxide containing Ti and alkaline earth metal elements, the occurrence of structural defects can be suitably suppressed.

[0102] According to the above embodiment, the dielectric portion 10 contains at least one of Li, Na, Mn, B, and Si.

[0103] This configuration lowers the temperature at which the dielectric portion 10 sintersects. Furthermore, since the amount of glass added to lower the temperature at which the dielectric portion 10 sintersects can be reduced, it becomes easier to ensure the mechanical strength of the dielectric portion 10.

[0104] According to the above embodiment, the external electrode 3 (more specifically, the base electrode layer 31) contains Cu.

[0105] With this configuration, since Cu has low electrical resistance and low conductor loss due to the conductor, the multilayer ceramic capacitor 1 can be made even more lossless.

[0106] According to the above embodiment, the area of ​​the inner Zr-rich region RA1 per unit area in the inner dielectric layer 14 is smaller than the area of ​​the outer Zr-rich region RA2 per unit area in the outer layer 12.

[0107] With this configuration, by reducing the area ratio of the inner layer Zr-rich region, the inner layer can be made less prone to shrinkage. By increasing the area ratio of the outer layer Zr-rich region, the outer layer can be made more prone to shrinkage. The inner dielectric layer tends to shrink more easily than the outer layer, but the difference in shrinkage ease between the inner dielectric layer and the outer layer can be reduced. This makes it possible to suppress the occurrence of structural defects caused by the difference in shrinkage ease between the inner dielectric layer and the outer layer.

[0108] According to the above embodiment, the ratio of the area of ​​the inner layer Zr-rich region RA1 per unit area in the outer layer 12 to the area of ​​the outer layer Zr-rich region RA2 per unit area in the inner layer dielectric layer 14 is 0.05 or more and 0.9 or less.

[0109] With this configuration, the occurrence of structural defects can be effectively suppressed.

[0110] Although embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above, and various modifications and variations are possible.

[0111] The side gap portion 13S may be formed by a dielectric sheet for the side gap portion (sometimes referred to as the "third dielectric sheet"). In this case, during the cutting process, the mother block is cut so that the conductive paste is exposed on the end face and side surface of the laminated chip. The third dielectric sheet is bonded to the side surface of the laminated chip. The conductive paste exposed on the side surface of the laminated chip is covered by the third dielectric sheet. The third dielectric sheet becomes the side gap portion after firing. The side gap portion may consist of multiple laminated third dielectric sheets or may consist of a single third dielectric sheet.

[0112] The composition of the ceramic slurry for the third dielectric sheet (sometimes referred to as the "third ceramic slurry") is, for example, the same as that of the first ceramic slurry. However, it is not limited to this; the composition of the third ceramic slurry may be the same as that of the second ceramic slurry, or it may be a composition different from both the first and second ceramic slurry. By adjusting the composition of the third ceramic slurry, the shrinkage behavior of the side gap can be adjusted.

[0113] If the outer layer is made up of multiple laminated second dielectric sheets, one outer layer may be composed of multiple second dielectric sheets with different compositions. By making one outer layer out of second dielectric sheets with different compositions, the ease of expansion and contraction can be partially adjusted within the outer layer. The same applies when the side gap is made up of multiple laminated third dielectric sheets. [Explanation of symbols]

[0114] 1. Multilayer ceramic capacitor 2 Laminate 3 External electrode 10 Dielectric part 11 Inner layer 12 Outer layer 14. Inner dielectric layer 15 Internal electrode 15a Effective part RA1 Inner layer Zr-rich region RA2 Outer layer Zr-rich region AA First Main Surface AB Second Main Surface BA First side BB 2nd side CA 1st end face CB 2nd end face

Claims

1. A laminate comprising a dielectric portion and a plurality of internal electrodes stacked on either side of the dielectric portion, having a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction, A pair of external electrodes are arranged in pairs in the longitudinal direction and connected to the internal electrodes, Equipped with, The laminate comprises an inner layer formed by an effective portion which is the portion of the internal electrode facing adjacent internal electrodes and an inner dielectric layer which is the portion of the dielectric portion sandwiched between adjacent effective portions, and a pair of outer layers arranged to sandwich the inner layer in the stacking direction. The width dimension of the laminate is greater than the length dimension of the laminate. The internal electrode contains Cu, The dielectric portion contains Zr and an alkaline earth metal element which is at least one of Ca and Sr. The inner dielectric layer has an inner Zr-rich region, The outer layer portion is a multilayer ceramic capacitor having an outer layer Zr-rich region.

2. The aforementioned alkaline earth metal element is Ca, The multilayer ceramic capacitor according to claim 1, wherein the dielectric portion contains a composite oxide containing Zr and Ca.

3. The aforementioned alkaline earth metal element is Sr, The dielectric portion contains a composite oxide containing Zr, Ti, and Sr. The multilayer ceramic capacitor according to claim 1, wherein the Zr content in the dielectric portion is greater than the Ti content in the dielectric portion.

4. The dielectric portion contains at least one of Li, Na, Mn, B, and Si, as described in any one of claims 1 to 3, for the multilayer ceramic capacitor.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the external electrode contains Cu.

6. The multilayer ceramic capacitor according to any one of claims 1 to 5, wherein the area of ​​the Zr-rich region per unit area in the inner dielectric layer is smaller than the area of ​​the Zr-rich region per unit area in the outer layer.

7. The multilayer ceramic capacitor according to any one of claims 1 to 6, wherein the ratio of the area of ​​the Zr-rich region per unit area in the inner dielectric layer to the area of ​​the Zr-rich region per unit area in the outer layer is 0.05 or more and 0.9 or less.

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