Semiconductor memory

Abstract

To provide a semiconductor memory device that can ensure high reliability. [Solution] The semiconductor memory device according to this embodiment comprises a laminate, a semiconductor layer, a first insulating layer, a charge storage layer, a second insulating layer, a third insulating layer, a first layer, and a second layer. The laminate is a laminate in which conductive layers containing molybdenum (Mo) and insulating layers are alternately stacked in a first direction. The semiconductor layer is provided within the laminate along the first direction. The first insulating layer is provided between the laminate and the semiconductor layer along the first direction. The charge storage layer is provided between the laminate and the first insulating layer along the first direction. The second insulating layer is provided between the laminate and the charge storage layer along the first direction. The third insulating layer has a first portion provided between the conductive layer and the second insulating layer. The first layer is provided between the conductive layer and the third insulating layer and contains HfO. The second layer is provided between the conductive layer and the first layer, or between the first layer and the third insulating layer, and contains a nitride.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device.

Background Art

[0002] In a three-dimensional non-volatile memory in which a plurality of memory cells are stacked on a semiconductor substrate, it is important to ensure high reliability.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Provided is a semiconductor memory device capable of ensuring high reliability.

Means for Solving the Problems

[0005] The semiconductor memory device according to the present embodiment includes a laminate, a semiconductor layer, a first insulating layer, a charge storage layer, a second insulating layer, a third insulating layer, a first layer, and a second layer. The laminate is a laminate in which a conductive layer containing molybdenum (Mo) and an insulating layer are alternately laminated in a first direction. The semiconductor layer is provided in the laminate along the first direction. The first insulating layer is provided between the laminate and the semiconductor layer along the first direction. The charge storage layer is provided between the laminate and the first insulating layer along the first direction. The second insulating layer is provided between the laminate and the charge storage layer along the first direction. The third insulating layer has a first portion and a second portion. The first portion is provided between the conductive layer and the second insulating layer. The second portion is provided along a second direction intersecting the first direction between the conductive layer and the insulating layer and is connected to the first portion. The first layer is provided between the conductive layer and the third insulating layer and contains HfO. The second layer is provided between the conductive layer and the first layer or between the first layer and the third insulating layer and contains a nitride. [Brief explanation of the drawing]

[0006] [Figure 1] This figure schematically shows the planar pattern of the basic configuration of the semiconductor memory device according to the first embodiment. [Figure 2] This is a cross-sectional view along line AA in Figure 1. [Figure 3] This is a schematic cross-sectional view showing the detailed configuration of the pillar structure and partition structure of the semiconductor memory device according to the first embodiment. [Figure 4] This is a schematic cross-sectional view showing the detailed configuration of the pillar structure and partition structure of the semiconductor memory device according to the first embodiment. [Figure 5] This is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to the first embodiment. [Figure 6A] This is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 6B] This is a cross-sectional view showing an example of a semiconductor memory device manufacturing method, following Figure 6A. [Figure 6C] Figure 6B is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 7] This is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to the first comparative example. [Figure 8] This is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to the second comparative example. [Figure 9] This is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to the second embodiment. [Figure 10A] This is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the second embodiment. [Figure 10B] Figure 10A is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings. These embodiments are not limiting to the present invention. The drawings are schematic or conceptual, and the proportions of each part may not necessarily be the same as those of actual objects. In the specification and drawings, elements similar to those described above with respect to previously shown drawings are denoted by the same reference numerals, and detailed explanations are omitted as appropriate.

[0008] (First Embodiment) Figure 1 is a schematic diagram showing the planar pattern of the basic configuration of a semiconductor memory device (NAND-type non-volatile semiconductor memory device) according to the first embodiment. Figure 2 is a cross-sectional view along line AA in Figure 1. Note that the X, Y, and Z directions shown in each figure are directions that intersect each other. Specifically, the X, Y, and Z directions are directions that are orthogonal to each other.

[0009] As shown in Figures 1 and 2, the semiconductor memory device according to the first embodiment comprises a stacked body 10, a plurality of pillar structures 20, a plurality of compartment structures 30, an interlayer insulating layer 40, and a plurality of contacts 50.

[0010] The laminate 10 is provided on a semiconductor substrate 100 and has a structure in which a plurality of conductive layers 11 and a plurality of insulating layers 12 are alternately stacked in the Z direction. That is, the plurality of conductive layers 11 are stacked spaced apart from each other in the Z direction, and the plurality of conductive layers 11 are electrically insulated by the plurality of insulating layers 12.

[0011] The conductive layer 11 is made of molybdenum (Mo). The insulating layer 12 is made of an insulating material such as silicon oxide. Both the conductive layer 11 and the insulating layer 12 are arranged parallel to the XY plane perpendicular to the Z direction. The conductive layer 11 functions as an electrode layer. Specifically, each conductive layer 11 functions as a word line or a selection gate line.

[0012] Each of the pillar structures 20 extends in the Z direction within the laminate 10, and includes a semiconductor layer extending in the Z direction and a charge storage layer surrounding the side surface of the semiconductor layer. The lower end of the semiconductor layer is connected to a common source region. Here, the well region of the semiconductor substrate 100 may function as the common source region, or a source line as the common source region may be formed on the substrate via various elements, wirings, etc. that constitute the peripheral circuit.

[0013] The pillar structure 20 is surrounded by a plurality of conductive layers 11 and a plurality of insulating layers 12. The pillar structure 20 and the plurality of conductive layers 11 surrounding the pillar structure 20 form a NAND string including a plurality of memory cells connected in series and a plurality of selection transistors provided on both sides of the plurality of memory cells connected in series.

[0014] Specifically, the conductive layer 11 surrounding the pillar structure 20 functions as a gate electrode, and the memory cell and the selection transistor are constituted by a portion functioning as the gate electrode of the conductive layer 11 and a portion surrounded by the conductive layer 11 of the pillar structure 20. That is, the memory cell is formed by the conductive layer 11 functioning as a word line and a portion surrounded by the conductive layer 11 functioning as the word line of the pillar structure 20. Also, the selection transistor is formed by the conductive layer 11 functioning as a selection gate line and a portion surrounded by the conductive layer 11 functioning as the selection gate line of the pillar structure 20.

[0015] Each of the partition structures 30 extends in the Y direction and the Z direction within the laminate 10. The laminate 10 is divided into a plurality of parts in the X direction by the plurality of partition structures 30, and the pillar structures 20 are partitioned into a plurality of groups in the X direction. The partition structures 30 are arranged at substantially equal intervals in the X direction, and the number of columns of the pillar structures 20 arranged between adjacent partition structures 30 is constant. Each region divided by the partition structure 30 forms, for example, one block that is a data erasure unit.

[0016] The partition structure 30 is formed by filling a slit used for a replacement process described later with a predetermined material, and includes a conductive portion 31 formed of a conductive material and an insulating portion 32 formed of an insulating material. The conductive portion 31, for example, has its lower end connected to the common source region of the semiconductor substrate 100 and functions as a source contact. Note that the partition structure 30 may be such that the slit after the replacement process is filled exclusively with an insulating material without forming a conductive material that functions as a source contact.

[0017] The structure including the laminate 10, the pillar structure 20, and the partition structure 30 is covered with an interlayer insulating layer 40. Further, a plurality of contacts 50 penetrate the interlayer insulating layer 40. The lower ends of the plurality of contacts 50 are connected to the semiconductor layers of the plurality of pillar structures 20, and the upper ends are connected to bit lines, for example, via vias.

[0018] FIG. 3 and FIG. 4 are cross-sectional views schematically showing the detailed configurations of the pillar structure 20 and the like. FIG. 3 is a cross-sectional view in a direction parallel to the Z direction, and FIG. 4 is a cross-sectional view in a direction perpendicular to the Z direction.

[0019] The pillar structure 20 includes a semiconductor layer 21, a tunnel insulating layer 22, a charge storage layer 23, a block insulating layer 24, and a core insulating layer 25. The semiconductor layer 21, the tunnel insulating layer 22, the charge storage layer 23, and the block insulating layer 24 all have a cylindrical shape, and the core insulating layer 25 has a columnar shape. More specifically, the semiconductor layer 21 surrounds the side surface of the core insulating layer 25, the tunnel insulating layer 22 surrounds the side surface of the semiconductor layer 21, the charge storage layer 23 surrounds the side surface of the tunnel insulating layer 22, and the block insulating layer 24 surrounds the side surface of the charge storage layer 23. For example, the semiconductor layer 21 is formed of silicon, the tunnel insulating layer 22 is formed of silicon oxide, the charge storage layer 23 is formed of silicon nitride, the block insulating layer 24 is formed of silicon oxide, and the core insulating layer 25 is formed of silicon oxide.

[0020] A layer 81 is provided on the surface of each conductive layer 11. A layer 82 is provided on the surface of layer 81. Specifically, layer 82 includes a first portion 82a and a second portion 82b. Specifically, layer 81 includes a first portion 81a and a second portion 81b.

[0021] The first portion 82a is provided between the pillar structure 20 and the conductive layer 11. The first portion 82a is provided along the side surface of the pillar structure 20 and surrounds the side surface of the pillar structure 20. Furthermore, the side surface of the first portion 82a is surrounded by the conductive layer 11 and is in contact with the conductive layer 11.

[0022] The second portion 82b is provided between the conductive layer 11 and the insulating layer 12. That is, the second portion 82b is provided along the lower and upper surfaces of the conductive layer 11 and is in contact with the lower and upper surfaces of the conductive layer 11. The second portion 81b is connected to the first portion 82a.

[0023] The first portion 81a is provided between the pillar structure 20 and the conductive layer 11. The first portion 81a is provided along the side surface of the pillar structure 20 and surrounds the side surface of the pillar structure 20. Furthermore, the side surface of the first portion 81a is surrounded by the first portion 82a of layer 82 and is in contact with the first portion 82a of layer 82.

[0024] The second portion 81b is provided between the conductive layer 11 and the insulating layer 12. That is, the second portion 81b is provided along the lower and upper surfaces of the conductive layer 11 and is in contact with the second portion 82b of layer 82. The second portion 81b is connected to the first portion 81a.

[0025] A block insulating layer 62 is provided on the outside of the pillar structure 20. Specifically, the block insulating layer 62 includes a first portion 62a (the portion provided between the pillar structure 20 and the first portion 81a of layer 81) provided between the pillar structure 20 and the conductive layer 11, and a second portion 62b (the portion provided between the second portion 81b of layer 81 and the insulating layer 12) provided between the conductive layer 11 and the insulating layer 12. In other words, the first portions 81a, 82a and the second portions 81b, 82b of layers 81 and 82 are provided between the conductive layer 11 and the block insulating layer 62. The second portion 62b is connected to the first portion 62a.

[0026] For example, the block insulating layer 62 is formed of a compound of aluminum (Al) and oxygen (O) (aluminum oxide, Al2O3).

[0027] Figure 5 is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to the first embodiment. Figure 5 is also an enlarged cross-sectional view showing the region between the pillar structure 20 and the conductive layer 11. Figure 5 also shows the diffusion of oxygen (oxygen radicals) and hydrogen (hydrogen radicals).

[0028] Layer 81 is provided between the conductive layer 11 and the block insulating layer 62. Layer 81 suppresses the diffusion of oxygen from the conductive layer 11 to the pillar structure 20. The oxygen originates, for example, from MoO2Cl2 contained in the film formation gas when the conductive layer 11 is formed.

[0029] Layer 81 contains a material capable of suppressing oxygen diffusion. Layer 81 contains, for example, a metal oxide or a metal nitride. The metal oxide includes, for example, HfO. The metal oxide is not limited to HfO and may be AlO or the like, but if the conductive layer 11 contains Mo, it is more preferable that the metal oxide is HfO. The metal nitride includes, for example, MoN.

[0030] Layer 82 is provided between the conductive layer 11 and layer 81. Layer 82 suppresses the diffusion of hydrogen from the conductive layer 11 to the pillar structure 20. The hydrogen originates from a subsequent process, which includes, for example, film formation or annealing.

[0031] Layer 82 contains a material capable of suppressing hydrogen diffusion. The material of layer 82 reduces the amount of hydrogen, for example, by reacting with hydrogen. Layer 82 contains, for example, a nitride. The nitride is, for example, SiN.

[0032] Furthermore, while layer 81 also suppresses hydrogen diffusion, layer 82 can suppress hydrogen diffusion even more effectively than layer 81.

[0033] By suppressing the diffusion of both oxygen and hydrogen, it is possible to prevent the formation of trap levels in the block insulating layer 24, which would otherwise degrade the data retention characteristics, as will be explained later. As a result, it is possible to prevent a decrease in the characteristics and reliability of the semiconductor memory device.

[0034] Furthermore, since oxygen in the conductive layer 11 moves by diffusion, some of the diffusing oxygen may remain in the conductive layer 11, while other parts may remain in layers 81 and 82. Since hydrogen in the conductive layer 11 moves by diffusion, some of the diffusing hydrogen may remain in the conductive layer 11, while other parts may remain in layers 81 and 82. Here, the hydrogen concentration in layer 82 may be higher than the hydrogen concentration in layer 81. The oxygen concentration in layer 81 may be higher than the oxygen concentration in layer 82.

[0035] Furthermore, the thickness of layer 81 is, for example, approximately 1 nm. The thickness of layer 82 is about the same as or less than the thickness of layer 81. The thickness of layer 82 is, for example, 1 nm or less.

[0036] Next, we will explain the manufacturing process flow.

[0037] Figures 6A to 6C are cross-sectional views showing an example of a semiconductor memory device manufacturing method according to the first embodiment.

[0038] First, a structure including a preliminary laminate and a pillar structure 20 is formed. The preliminary laminate has a structure in which multiple insulating layers 12 and multiple sacrificial layers are alternately stacked in the Z direction.

[0039] Next, a preliminary laminate is patterned to form slits that penetrate the preliminary laminate and extend in the Y and Z directions.

[0040] Next, the sacrificial layer is etched through the slits and removed. This creates a plurality of voids 72, each between adjacent insulating layers 12.

[0041] Next, as shown in Figure 6A, an Al2O3 layer is formed on the surface of the slit and the cavity 72 as a block insulating layer 62.

[0042] Next, as shown in Figure 6B, an HfO layer is formed as layer 81 on the surface of the block insulating layer 62.

[0043] Next, as shown in Figure 6C, a SiN layer is formed as layer 82 on the surface of layer 81. Subsequently, a Mo layer is formed as a conductive layer 11 in the cavity 72 where layers 81, 82 and the block insulating layer 62 are formed through the slit, and the conductive layer 11 deposited at a position corresponding to the side surface of the insulating layer 12 is removed. Subsequently, layers 81, 82 and the block insulating layer 62 are removed down to a position corresponding to the side surface of the insulating layer 12. This yields the first portions 81a, 82a, 62a and the second portions 81b, 82b, 62b of layers 81, 82 and the block insulating layer 62. In this way, the sacrificial layer is replaced with the conductive layer (Mo layer) 11.

[0044] Furthermore, heat treatment may be added before forming layer 81 or layer 82. This may help suppress increased warping or deterioration of coverage due to the addition of layers.

[0045] As described above, according to the first embodiment, layer 81 is provided between the conductive layer 11 and the block insulating layer 62 and contains HfO. Layer 82 is provided between the conductive layer 11 and layer 81 and contains nitride. This makes it possible to suppress the diffusion of both oxygen and hydrogen from the conductive layer 11 to the block insulating layer 62. Therefore, it is possible to suppress the generation of trap levels in the block insulating layer 24 and the deterioration of data retention characteristics. As a result, it is possible to suppress a deterioration in the characteristics and reliability of the semiconductor memory device.

[0046] (Comparative example) Figure 7 is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to the first comparative example. The first comparative example differs from the first embodiment in that layers 81 and 82 are not provided. Figure 7 also shows the diffusion of oxygen and hydrogen.

[0047] There are two main possible causes for the diffusion of oxygen from the conductive layer (Mo layer) 11. The first cause is that oxygen contained in the raw material gas for Mo (e.g., MoO2Cl2) is mixed into the Mo layer, and this mixed oxygen diffuses into the Mo layer. The second cause is that oxygen that penetrates into the Mo layer from the oxide layer 91 formed on the surface of the Mo layer diffuses into the Mo layer.

[0048] The diffusion of hydrogen from the conductive layer 11 is caused by processing in a subsequent step.

[0049] Diffused oxygen and hydrogen generate OH in the block insulating layer 62 or block insulating layer 24, creating trap levels in the block insulating layer 24. As a result, electrons in the charge storage layer 23 may be trapped in the trap levels in the block insulating layer 24, potentially degrading the data retention characteristics of the charge storage layer 23. This can lead to problems such as a decrease in the characteristics and reliability of the semiconductor memory device.

[0050] Figure 8 is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to the second comparative example. The second comparative example differs from the first embodiment in that layer 82 is not provided.

[0051] Layer 81 can suppress the diffusion of oxygen. However, since hydrogen diffuses through layer 81, there is a risk that OH will be generated in the block insulating layer 62 or the block insulating layer 24.

[0052] In contrast, in the first embodiment, by providing a layer 82 that suppresses hydrogen diffusion, the generation of OH in the block insulating layer 62 or block insulating layer 24 can be suppressed. Therefore, the generation of trap levels in the block insulating layer 24 and the resulting deterioration of data retention characteristics can be suppressed. As a result, the deterioration of the characteristics and reliability of the semiconductor memory device can be suppressed.

[0053] (Second Embodiment) Figure 9 is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to the second embodiment. The second embodiment differs from the first embodiment in that the positions of layers 81 and 82 are reversed.

[0054] Layer 82 is provided between layer 81 and the block insulating layer 62.

[0055] Furthermore, since oxygen in the conductive layer 11 moves by diffusion, some of the diffusing oxygen may remain in the conductive layer 11, while other parts may remain in layer 81. Since hydrogen in the conductive layer 11 moves by diffusion, some of the diffusing hydrogen may remain in the conductive layer 11, while other parts may remain in layers 81 and 82.

[0056] Next, we will explain the manufacturing process flow.

[0057] Figures 10A and 10B are cross-sectional views showing an example of a method for manufacturing a semiconductor memory device according to the second embodiment. The steps shown in Figures 10A and 10B are performed after the steps shown in Figure 6A.

[0058] After forming an Al2O3 layer as the block insulating layer 62 (see Figure 6A), a SiN layer is formed on the surface of the block insulating layer 62 as layer 82, as shown in Figure 10A.

[0059] Next, as shown in Figure 10B, an HfO layer is formed as layer 81 on the surface of layer 82. Then, the conductive layer 11 is formed in the same manner as shown in Figure 6C.

[0060] As in the second embodiment, the positions of layers 81 and 82 may be reversed. The semiconductor memory device according to the second embodiment can obtain the same effects as the first embodiment.

[0061] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0062] 10 Laminate, 10p Preliminary laminate, 11 Conductive layer, 12 Insulating layer, 20 Pillar structure, 21 Semiconductor layer, 22 Tunnel insulating layer, 23 Charge storage layer, 24 Block insulating layer, 25 Core insulating layer, 30 Compartment structure, 31 Conductive portion, 32 Insulating portion, 40 Interlayer insulating layer, 50 Contact, 61a...First part, 61b Second part, 61c Third part, 62 Block insulating layer, 71 Slit, 72 Void, 81 Layer, 82 Layer, 100 Semiconductor substrate

Claims

1. A laminate in which a conductive layer containing molybdenum (Mo) and an insulating layer are alternately stacked in a first direction, A semiconductor layer provided within the laminate along the first direction, A first insulating layer is provided between the laminate and the semiconductor layer along the first direction, A charge storage layer is provided between the laminate and the first insulating layer along the first direction, A second insulating layer is provided between the laminate and the charge storage layer along the first direction, A third insulating layer having a first portion and a second portion, wherein the first portion is provided between the conductive layer and the second insulating layer, and the second portion is provided between the conductive layer and the insulating layer along a second direction intersecting the first direction and connected to the first portion of the third insulating layer, A first layer containing HfO is provided between the conductive layer and the third insulating layer, A second layer containing a nitride is provided between the conductive layer and the first layer, or between the first layer and the third insulating layer. A semiconductor memory device equipped with the following features.

2. The semiconductor memory device according to claim 1, wherein the nitride includes SiN.

3. The semiconductor memory device according to claim 1, wherein the thickness of the second layer is less than or equal to the thickness of the first layer.

4. The conductive layer contains oxygen (O) and hydrogen (H), The first layer contains oxygen, The semiconductor memory device according to claim 1, wherein the second layer contains hydrogen.

Images