Semiconductor memory device and method for manufacturing the same

Abstract

The present invention provides a memory device that suppresses the bending of the insulating layer during the process of replacing the sacrificial layer of a laminated structure with a conductive material. [Solution] The memory comprises a laminate in which a plurality of electrode films and a plurality of first insulating films are alternately stacked in a first direction. The first columnar body includes a semiconductor layer provided penetrating the laminate in the first direction, and a memory cell is formed at the intersection with one of the plurality of electrode films. The plurality of first pillar portions penetrate the laminate in the first direction and are made of insulating material. The plurality of second pillar portions penetrate the laminate in the first direction, are made of conductive material, and are electrically connected to each of the plurality of electrode films. The width of the plurality of second pillar portions in a plane perpendicular to the first direction differs between the upper part of the pillar, which is above the connecting electrode film in the first direction, and the lower part of the pillar, which is below the connecting electrode film in the first direction, with the connecting electrode film connected to each of the plurality of second pillar portions being the boundary.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device and a method for manufacturing the same.

Background Art

[0002] A semiconductor memory device such as a NAND-type flash memory may have a three-dimensional memory cell array in which a plurality of memory cells are three-dimensionally arranged. There is a process (replacement process) of replacing a sacrificial layer with a conductive material in a stacked structure of an insulating layer and a sacrificial layer to form a stacked structure of a word line and an insulating layer. When the sacrificial layer in this replacement process is removed, the insulating layer may bend due to its own weight. In order to suppress the bending of this insulating layer, a plurality of support pillars penetrating the stacked structure are provided. However, since no support pillar is provided under the word line contact, there is still concern about the bending of the insulating layer.

[0003] Also, when forming the support pillars, a sacrificial material may be temporarily embedded in the contact hole of the word line contact. If the material is selected so that this sacrificial material functions as a support pillar in the replacement process, it may be difficult to remove the sacrificial material.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0005] The present invention provides a semiconductor memory device and a method for manufacturing the same, which can suppress the bending of the insulating layer in a replacement process in which the sacrificial layer in a laminated structure of an insulating layer and a sacrificial layer is replaced with a conductive material to form a laminated structure of a word line and an insulating layer. [Means for solving the problem]

[0006] The semiconductor memory device according to this embodiment comprises a laminate in which a plurality of electrode films and a plurality of first insulating films are alternately stacked in a first direction. The first columnar body includes a semiconductor layer provided penetrating the laminate in the first direction, and a memory cell is formed at the intersection with one of the plurality of electrode films. The plurality of first pillar portions penetrate the laminate in the first direction and are made of an insulating material. The plurality of second pillar portions penetrate the laminate in the first direction, are made of a conductive material, and are electrically connected to each of the plurality of electrode films. The width of the plurality of second pillar portions in a plane perpendicular to the first direction differs between the upper part of the pillar, which is above the connecting electrode film in the first direction, and the lower part of the pillar, which is below the connecting electrode film in the first direction, with the connecting electrode film connected to each of the plurality of second pillar portions being the boundary. [Brief explanation of the drawing]

[0007] [Figure 1] A cross-sectional view showing an example configuration of a semiconductor memory device according to the first embodiment. [Figure 2] A plan view showing the laminated structure. [Figure 3] A cross-sectional view illustrating a three-dimensional memory cell structure. [Figure 4] A cross-sectional view illustrating a three-dimensional memory cell structure. [Figure 5] A cross-sectional view showing an example of the configuration of the contact region of the laminate according to the first embodiment. [Figure 6] A diagram showing the arrangement of support columns and contact plugs. [Figure 7] A diagram showing the arrangement of the support column and contact plug in a comparative example where the lower part of the pillar is not provided. [Figure 8] A cross-sectional view showing an example configuration of a semiconductor memory device according to the second embodiment. [Figure 9] Cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the second embodiment. [Figure 10] Cross-sectional view showing a method for manufacturing a semiconductor memory device, following FIG. 9. [Figure 11] Cross-sectional view showing a method for manufacturing a semiconductor memory device, following FIG. 10. [Figure 12] Cross-sectional view showing a method for manufacturing a semiconductor memory device, following FIG. 11. [Figure 13] Cross-sectional view showing a method for manufacturing a semiconductor memory device, following FIG. 12. [Figure 14] Cross-sectional view showing a method for manufacturing a semiconductor memory device, following FIG. 13. [Figure 15] Cross-sectional view showing a method for manufacturing a semiconductor memory device, following FIG. 14. [Figure 16] Cross-sectional view showing a method for manufacturing a semiconductor memory device, following FIG. 15. [Figure 17] Cross-sectional view showing a method for manufacturing a semiconductor memory device, following FIG. 16. [Figure 18] Cross-sectional view showing a method for manufacturing a semiconductor memory device, following FIG. 17. [Figure 19] Cross-sectional view showing a method for manufacturing a semiconductor memory device, following FIG. 18. [Figure 20] Cross-sectional view showing a method for manufacturing a semiconductor memory device, following FIG. 19. [Figure 21] Cross-sectional view showing a method for manufacturing a semiconductor memory device, following FIG. 20. [Figure 22] Cross-sectional view showing a method for manufacturing a semiconductor memory device, following FIG. 21. [Figure 23] Cross-sectional view showing a method for manufacturing a semiconductor memory device, following FIG. 22. [Figure 24] Cross-sectional view showing a method for manufacturing a semiconductor memory device, following FIG. 23. [Figure 25] Cross-sectional view showing a method for manufacturing a semiconductor memory device, following FIG. 24. [Figure 26] Cross-sectional view showing a method for manufacturing a semiconductor memory device, following FIG. 25. [Figure 27] Cross-sectional view showing a method for manufacturing a semiconductor memory device, following FIG. 26. [Figure 28] A cross-sectional view showing a method of manufacturing a semiconductor memory device, following FIG. 27. [Figure 29] A cross-sectional view showing a method of manufacturing a semiconductor memory device, following FIG. 28. [Figure 30] A cross-sectional view showing a method of manufacturing a semiconductor memory device, following FIG. 29.

Best Mode for Carrying Out the Invention

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. This embodiment does not limit the present invention. The drawings are schematic or conceptual. In the specification and the drawings, the same reference numerals are given to the same elements.

[0009] (First Embodiment) FIG. 1 is a cross-sectional view showing a configuration example of a semiconductor memory device 1 according to the first embodiment. Hereinafter, the stacking direction of the stacked body 20 is defined as the Z direction. One direction intersecting, for example, orthogonal to the Z direction is defined as the Y direction. One direction intersecting, for example, orthogonal to each of the Z direction and the Y direction is defined as the X direction. In FIG. 1, the semiconductor memory device 1 is shown with the -Z direction being upward. In the cross-sectional views after FIG. 5, the semiconductor memory device 1 is shown with the +Z direction being upward. In this specification, the ±Z directions are examples of the first direction.

[0010] The semiconductor memory device 1 includes an array chip 2 having a memory cell array and a CMOS chip 3 having a CMOS circuit. The array chip 2 and the CMOS chip 3 are bonded at a bonding surface B1 and are electrically connected to each other via wirings bonded at the bonding surface B1. In FIG. 1, a state where the array chip 2 is provided on the CMOS chip 3 is shown.

[0011] The CMOS chip 3 includes a substrate 30, transistors 31, vias 32, wirings 33 and 34, and an interlayer insulating film 35.

[0012] The substrate 30 is, for example, a semiconductor substrate such as a silicon substrate. The transistor 31 is an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or a P-type MOSFET provided on the substrate 30. The transistor 31 constitutes, for example, a CMOS (Complementary MOS) circuit that controls the memory cell array 2m of the array chip 2. Multiple transistors 31 constitute logic circuits such as a sense amplifier, a row decoder, and a column decoder. Semiconductor elements other than transistors 31, such as resistors and capacitive elements, may be formed on the substrate 30.

[0013] Via 32 electrically connects transistor 31 to wiring 33, or wiring 33 to wiring 34. Wires 33 and 34 constitute a multilayer wiring structure within the interlayer insulating film 35. Wire 34 is embedded within the interlayer insulating film 35 and is exposed almost flush with the surface of the interlayer insulating film 35. Wires 33 and 34 are electrically connected to transistor 31, etc. Metals such as copper and tungsten are used for vias 32, wiring 33 and 34. The interlayer insulating film 35 covers and protects transistor 31, vias 32, wiring 33 and 34. An insulating film such as a silicon oxide film is used for the interlayer insulating film 35.

[0014] The array chip 2 comprises a laminate 20, a columnar body CL, a source layer BSL, a metal layer 40, a contact plug CC, a contact plug 29, a bonding pad 50, wiring 23 and 24, a via 28, and an interlayer insulating film 25.

[0015] The laminate 20 is located above the transistor 31 and is positioned in the -Z direction relative to the substrate 30. The laminate 20 is constructed by alternately stacking multiple electrode films 21 and multiple insulating films 22 in the +Z direction. The laminate 20, together with the columnar body CL, constitutes a memory cell array. For the electrode films 21, conductive metals such as tungsten are used. For the insulating films 22, silicon oxide films are used, for example. The insulating films 22 insulate the electrode films 21 from each other. That is, multiple electrode films 21 are stacked in an insulated state from each other. The number of stacks of each electrode film 21 and insulating film 22 is arbitrary. The insulating film 22 may be, for example, a porous insulating film or an air gap.

[0016] One or more electrode films 21 at the upper and lower ends of the stacked body 20 in the Z direction function as a source-side selection gate SGS and a drain-side selection gate SGD, respectively. The electrode film 21 between the source-side selection gate SGS and the drain-side selection gate SGD functions as a word line WL. The word line WL is the gate electrode of the memory cell MC. The source-side selection gate SGS is the gate electrode of the source-side selection transistor. The drain-side selection gate SGD is the gate electrode of the drain-side selection transistor. The source-side selection gate SGS is located in the -Z-side region of the stacked body 20. The drain-side selection gate SGD is located in the +Z-side region of the stacked body 20. The -Z-side region refers to the region of the stacked body 20 that is farther from the CMOS chip 3 (closer to the metal layer 40), and the +Z-side region refers to the region of the stacked body 20 that is closer to the CMOS chip 3.

[0017] The semiconductor memory device 1 has multiple memory cells MC connected in series between a source-side selection transistor and a drain-side selection transistor. The structure in which the source-side selection transistor, memory cells MC, and drain-side selection transistor are connected in series is called a “memory string” or “NAND string”. The memory string is connected to a bit line BL via, for example, a via 28. The bit line BL is a wiring 23 located below the stack 20 and extending in the X direction. Therefore, hereafter, the bit line BL will also be referred to as the bit line 23.

[0018] Multiple columnar bodies CL are provided within the laminate 20. The columnar bodies CL extend through the laminate 20 in the stacking direction (Z direction) and are provided from vias 28 connected to bit lines 23 to the source layer BSL. The internal structure of the columnar bodies CL will be described later. In Figure 1, the columnar bodies CL are shown formed in two stages in the Z direction. However, the columnar bodies CL may be formed in three or more stages.

[0019] Although not shown in Figure 1, multiple slits ST (see Figure 2) are provided within the laminate 20. The slits ST extend in the Y direction and penetrate the laminate 20 in the stacking direction (Z direction). The slits ST are filled with an insulating film such as a silicon oxide film, and the insulating film is configured in a plate shape. The slits ST electrically divide the electrode film 21 of the laminate 20. Alternatively, the inner walls of the slits ST may be coated with an insulating film such as a silicon oxide film, and a conductive material may be embedded inside the insulating film. In this case, the conductive material can also function as source wiring that reaches the source layer BSL.

[0020] A source layer BSL is provided on the laminate 20. The source layer BSL is provided in correspondence with the laminate 20. The laminate 20 (memory cell array 2m) is provided on the side F1 of the source layer BSL, and a metal layer 40 is provided on the opposite side F2. The source layer BSL is commonly connected to one end of multiple columnar bodies CL, and provides a common source voltage to multiple columnar bodies CL in the same memory cell array 2m. In other words, the source layer BSL functions as a common source electrode for the memory cell array 2m. Conductive materials such as doped polysilicon are used for the source layer BSL. A metal material with lower resistance than the source layer BSL is used for the metal layer 40, such as copper, aluminum, or tungsten.

[0021] On the other hand, a bonding pad 50 is provided in the region above the surface F2 of the source layer BSL where the source layer BSL is not provided. The bonding pad 50 is connected to a metal wire or the like (not shown) and receives power or signals from outside the semiconductor memory device 1. The bonding pad 50 is provided to be connected to one end of the contact plug 29 in the Z direction. The bonding pad 50 is connected to the transistor 31 of the CMOS chip 3 via the contact plug 29, wiring 24 and wiring 34. External power supplied from the bonding pad 50 is supplied to the transistor 31. Alternatively, a signal is supplied to the transistor 31 via the bonding pad 50.

[0022] The contact plug CC is provided in the peripheral part of the laminate 20 and extends in the Z direction within the laminate 20. The contact plug CC is electrically connected between the electrode film 21 (word line WL) and the wiring 24. The contact plug CC is provided in the contact region 2c formed at the end of the laminate 20 and is electrically connected to each electrode film 21. The contact plug CC is provided to transmit the word line voltage from the CMOS chip 3 to each electrode film 21. For example, metals such as copper and tungsten can be used for the contact plug CC.

[0023] The contact plug 29 is located on the periphery of the laminate 20 and extends in the Z direction within the interlayer insulating film 25. The contact plug 29 is electrically connected between the bonding pad 50 and the wiring 24. The contact plug 29 is used to supply power or signals from the bonding pad 50 to the array chip 2 or CMOS chip 3. The contact plug 29 is made of a metal such as copper or tungsten. The power supply is, for example, the power supply voltage VDD, or a reference voltage (e.g., ground voltage) VSS lower than the power supply voltage VDD. The signal may be an external control signal, or it may be write data or read data.

[0024] In this embodiment, the array chip 2 and the CMOS chip 3 are formed individually and bonded together at the bonding surface B1. Therefore, no transistors 31 are provided within the array chip 2. Furthermore, no stacked structure 20 (memory cell array 2m) is provided within the CMOS chip 3.

[0025] Vias 28, wiring 23, and wiring 24 are provided in the +Z direction of the laminate 20. Wires 23 and 24 are embedded in the interlayer insulating film 25. Wire 24 is exposed almost flush with the surface of the interlayer insulating film 25. Wires 23 and 24 are electrically connected to the semiconductor body of the columnar body CL (210 in Figures 3 and 4), etc. Metals such as copper and tungsten are used for the vias 28, wiring 23, and wiring 24. The interlayer insulating film 25 covers and protects the laminate 20, vias 28, wiring 23, and wiring 24. An insulating film such as a silicon oxide film is used for the interlayer insulating film 25.

[0026] The interlayer insulating film 25 and the interlayer insulating film 35 are bonded together at the bonding surface B1, and consequently, the wiring 24 and the wiring 34 are joined almost flush at the bonding surface B1. As a result, the array chip 2 and the CMOS chip 3 are electrically connected via the wiring 24 and the wiring 34.

[0027] Figure 2 is a plan view showing the stacked structure 20. The stacked structure 20 includes a contact region 2c and a memory cell array 2m. The contact region 2c is provided, for example, at the end of the stacked structure 20. The contact region 2c may also be provided in the central part of the stacked structure 20. The memory cell array 2m is sandwiched or surrounded by the contact region 2c. The slit ST is provided from the contact region 2c at one end of the stacked structure 20, through the memory cell array 2m, to the contact region 2c at the other end of the stacked structure 20. The slit SHE is provided at least in the memory cell array 2m. The slit SHE is shallower in the Z direction than the slit ST and extends substantially parallel to the slit ST. The slit SHE electrically divides the electrode film 21 on the lower region side of the stacked structure 20 for each drain-side selection gate SGD. An insulating film such as a silicon oxide film is used for the slit SHE. Furthermore, the slit ST may include source wiring that is electrically isolated from the electrode film 21 of the laminate 20 while being electrically connected to the source layer BSL.

[0028] The portion of the laminate 20 sandwiched between the two slits ST shown in Figure 2 is called a block. A block constitutes, for example, the smallest unit for data erasure. Slit SHE is located within the block. The laminate 20 between slit ST and slit SHE is called a finger. The drain-side selection gate SGD is separated for each finger. Therefore, during data writing and reading, the drain-side selection gate SGD can select one finger within the block as a unit.

[0029] Figures 3 and 4 are cross-sectional views illustrating a three-dimensional memory cell structure. Multiple columnar bodies CL are each provided within memory holes MH in a stack 20. Each columnar body CL extends from one end of the stack 20 along the Z-direction, penetrating the stack 20 and extending within the stack 20 and the source layer BSL. Each of the multiple columnar bodies CL includes a semiconductor body 210, a memory film 220, and a core layer 230. Each columnar body CL includes a core layer 230 located in its center, a semiconductor body (semiconductor layer) 210 surrounding the core layer 230, and a memory film 220 surrounding the semiconductor body 210. The semiconductor body 210 extends in the stacking direction (Z-direction) within the stack 20. The semiconductor body 210 is electrically connected to the source layer BSL. The memory film 220 is provided between the semiconductor body 210 and the electrode film 21 and has charge trapping portions. Multiple columnar bodies CL, one selected from each finger, are connected in common to a single bit line 23 via vias 28 in Figure 1. Each columnar body CL is provided, for example, in the region of the memory cell array 2m. The columnar bodies CL are provided penetrating the stacked body 20 in the Z direction and constitute memory cells MC at their intersections with each electrode film 21.

[0030] As shown in Figure 4, the shape of the memory hole MH in the XY plane is, for example, a circle or an ellipse. A block insulating film 221a, which constitutes part of the memory film 220, may be provided between the electrode film 21 and the insulating film 22. The block insulating film 221a is, for example, silicon oxide or a metal oxide. One example of a metal oxide is aluminum oxide. A barrier film 21b may be provided between the electrode film 21 and the insulating film 22, and between the electrode film 21 and the memory film 220. The barrier film 21b is, for example, titanium nitride when the electrode film 21 is tungsten. The block insulating film 221a suppresses back tunneling of charge from the electrode film 21 to the memory film 220. The barrier film 21b improves the adhesion between the electrode film 21 and the block insulating film 221a.

[0031] The semiconductor body 210 has a cylindrical shape, for example, with a bottom. For example, polysilicon is used for the semiconductor body 210. For example, the semiconductor body 210 is undoped silicon. Alternatively, the semiconductor body 210 may be p-type silicon. The semiconductor body 210 serves as the channel for the drain-side selection transistor, the memory cell MC, and the source-side selection transistor. That is, multiple memory cell MCs have a storage area between the semiconductor body 210 and the electrode film 21 which becomes the word line WL, and are stacked in the Z direction. One end of multiple semiconductor bodies 210 within the same memory cell array 2m is electrically connected in common to the source layer BSL.

[0032] The memory film 220 includes, for example, a cover insulating film 221, a charge trapping film 222, a tunnel insulating film 223, and a block insulating film 221a. The portion of the memory film 220 other than the block insulating film 221a is provided between the inner wall of the memory hole MH and the semiconductor body 210. The shape of the memory film 220 is, for example, cylindrical. The charge trapping film 222 and the tunnel insulating film 223 are each stretched in the Z direction.

[0033] The cover insulating film 221 is provided between the insulating film 22 and the charge trapping film 222, and between the block insulating film 221a and the charge trapping film 222. The cover insulating film 221 includes, for example, silicon oxide. The cover insulating film 221 protects the charge trapping film 222 from etching when the sacrificial film (21a in Figure 9) is replaced with the electrode film 21 (replacement step).

[0034] The charge trapping film 222 is provided between the cover insulating film 221 and the tunnel insulating film 223. The charge trapping film 222 contains, for example, silicon nitride and has trapping sites that trap charges within the film. The portion of the charge trapping film 222 sandwiched between the electrode film 21, which becomes the word line WL, and the semiconductor body 210 constitutes the memory area of ​​the memory cell MC as a charge trapping section. The threshold voltage of the memory cell MC changes depending on the presence or absence of charge in the charge trapping section, or the amount of charge trapped in the charge trapping section. As a result, the memory cell MC retains information.

[0035] The tunnel insulating film 223 is provided between the semiconductor body 210 and the charge trapping film 222. The tunnel insulating film 223 includes, for example, silicon oxide, or silicon oxide and silicon nitride. The tunnel insulating film 223 is a potential barrier between the semiconductor body 210 and the charge trapping film 222. For example, when electrons are injected from the semiconductor body 210 to the charge trapping film 222 (writing operation), and when holes are injected from the semiconductor body 210 to the charge trapping film 222 (erasing operation), the electrons and holes pass through the potential barrier of the tunnel insulating film 223 (tunneling).

[0036] The core layer 230 fills the internal space of the cylindrical semiconductor body 210. The shape of the core layer 230 is, for example, columnar. The core layer 230 contains, for example, silicon oxide and is insulating.

[0037] Figure 5 is a cross-sectional view showing an example of the configuration of the contact region 2c of the laminate 20 according to the first embodiment. In Figure 5, the contact region 2c of the laminate 20 of Figure 1 is shown with the top and bottom in the Z direction reversed. That is, from Figure 5 onward, the +Z direction is considered upward.

[0038] The contact area 2c includes the laminate 20, a plurality of support columns HR, and a plurality of contact plugs CC.

[0039] The support column HR, which serves as the first pillar, penetrates the laminate 20 in the Z direction. The support column HR is made of an insulating material such as silicon oxide. The support column HR is provided to support the insulating film 22 when the electrode film 21 is removed in the replacement process described later, and to prevent the insulating film 22 from bending or collapsing under its own weight.

[0040] The contact plugs CC, which serve as the second pillars, penetrate the laminate 20 in the Z direction. The contact plugs CC are made of a conductive material such as tungsten. Each contact plug CC is provided corresponding to one of the multiple electrode films 21 and is electrically connected to the corresponding electrode film 21. For example, contact plug CC1 is electrically connected to the bottommost electrode film 21_1 among the multiple electrode films 21 of the laminate 20. Contact plug CC3 is electrically connected to the third electrode film 21_3 from the bottom among the multiple electrode films 21. Contact plug CC6 is electrically connected to the sixth electrode film 21_6 from the bottom among the multiple electrode films 21. Although not shown, other contact plugs CC connected to other electrode films 21 are also provided.

[0041] Each contact plug CC is electrically insulated from all electrode films (word lines) 21 except for the connecting electrode film (connecting word line) 21 to which it is electrically connected. For example, contact plug CC1 is electrically connected only to the connecting electrode film 21_1 among the multiple electrode films 21, and is electrically isolated from the other electrode films 21 (including 21_3 and 21_6). Contact plug CC3 is electrically connected only to the connecting electrode film 21_3 among the multiple electrode films 21, and is electrically isolated from the other electrode films 21 (including 21_1 and 21_6). Contact plug CC6 is electrically connected only to the connecting electrode film 21_6 among the multiple electrode films 21, and is electrically isolated from the other electrode films 21 (including 21_1 and 21_3). Contact plug CCn (where n is an integer) is electrically connected only to the connecting electrode film 21_n among the multiple electrode films 21, and is electrically isolated from the other electrode films 21.

[0042] The block film BLK and spacer SP are provided between each contact plug CC and other electrode films 21 located above (in the +Z direction) the corresponding connecting electrode film 21. The block film BLK and spacer SP are made of an insulating material such as silicon oxide.

[0043] The insulating film 21c, which serves as the third insulating film, is provided between the lower pillars CC3L and CC6L of each contact plug CC and other electrode films 21 located below (in the -Z direction) the corresponding connecting electrode film 21. The insulating film 21c is provided at the same height level as the electrode films 21 and is composed of an insulating material such as silicon oxide. Note that the connecting electrode film 21_1 corresponding to contact plug CC1 is the lowest layer among the multiple electrode films 21, and therefore the insulating film 21c is not provided for it.

[0044] In this way, each of the multiple contact plugs CC is electrically isolated from other electrode films 21 located above (in the +Z direction) the corresponding connecting electrode film 21 by a blocking film BLK and a spacer SP. Each of the multiple contact plugs CC is electrically isolated from other electrode films 21 located below (in the -Z direction) the corresponding connecting electrode film 21 by an insulating film 21c.

[0045] Furthermore, as shown in Figure 5, the width (diameter) of the contact plug CC1 corresponding to the connecting electrode film 21_1 differs between the upper part of the pillar CC1U of the contact plug CC1 located above (+Z direction) the connecting electrode film 21_1 and the lower part of the pillar CC1L located below (-Z direction) the connecting electrode film 21_1. The width W1L of the lower part of the pillar CC1L is smaller than the width W1U of the upper part of the pillar CC1U.

[0046] The width (diameter) of the contact plug CC3 corresponding to the connecting electrode film 21_3 differs between the upper part CC3U of the contact plug CC3 located above (+Z direction) the connecting electrode film 21_3 and the lower part CC3L of the pillar located below (-Z direction) the connecting electrode film 21_3. The width W3L of the lower part CC3L is smaller than the width W3U of the upper part CC3U of the pillar.

[0047] The width (diameter) of the contact plug CC6 corresponding to the connecting electrode film 21_6 differs between the upper part CC6U of the contact plug CC6 located above (+Z direction) the connecting electrode film 21_6 and the lower part CC6L of the pillar located below (-Z direction) the connecting electrode film 21_6. The width W6L of the lower part CC6L is smaller than the width W6U of the upper part CC6U of the pillar.

[0048] The same applies to other contact plugs CC not shown. Therefore, the width of the contact plug CCn differs between the upper pillar CCnU, which is above (+Z direction) the connecting electrode film 21_n connected to the contact plug CCn, and the lower pillar CCnL, which is below (-Z direction) the connecting electrode film 21_n. The width WnL of the lower pillar CCnL is smaller than the width WnU of the upper pillar CCnU.

[0049] Furthermore, the width WnL of the lower part of the pillar CCnL may be approximately equal to the width Whr of the support column HR.

[0050] Figure 6 shows the arrangement of the support column HR and the contact plug CC. Figure 6 is a cross-section along line 6-6 in Figure 5, that is, a cross-section taken along the bottom layer of the laminate 20, the connecting electrode film 21_1, in a plane perpendicular to the Z direction (XY plane), as viewed from the Z direction. Note that the connecting electrode film 21_1 itself is not shown in Figure 6.

[0051] As shown in Figure 6, in the bottommost connecting electrode film 21_1 of the laminate 20, the upper part of the pillar CC1U is visible for contact plug CC1, while the lower parts of the pillars CC3L and CC6L are visible for contact plugs CC3 and CC6. Therefore, in the bottommost connecting electrode film 21_1 of the laminate 20, the width W1U of contact plug CC1 is larger than the widths W3L and W6L of the other contact plugs CC3 and CC6.

[0052] Furthermore, in the bottommost connecting electrode film 21_1 of the laminate 20, the first interval D_CC-HR between adjacent support column HR and contact plug CC is greater than the second interval D_HR-HR between adjacent support column HR without the contact plug CC in between. All of the first intervals D_CC-HR are approximately equal to each other. All of the second intervals D_HR-HR are approximately equal to each other.

[0053] According to this embodiment, as shown in Figures 5 and 6, the contact plug CCn has a lower pillar CCnL below (in the -Z direction) the connecting electrode film 21_n. The lower pillar CCnL extends downward (in the -Z direction) from the upper pillar CCnU of the contact plug CCn, with the connecting electrode film 21_n as the boundary, and is provided below the electrode film 21 of the lowest layer of the laminate 20. As a result, in the replacement process described later, the lower pillar CCnL of the contact plug CCn, together with the support column HR, supports the insulating film 22 located below the upper pillar CCnU when the electrode film 21 is removed, and prevents the insulating film 22 from bending or collapsing under its own weight.

[0054] If the lower pillar CCnL is not provided, the insulating film 22 located below the upper pillar CCnU shown in Figure 5 will no longer be supported.

[0055] For example, Figure 7 shows the arrangement of support column HR and contact plug CC in a comparative example where the lower pillar CCnL is not provided. As shown in Figure 7, contact plugs CC3 and CC6 do not appear in the bottommost connecting electrode film 21_1 of the laminate 20. In this case, the width between adjacent support columns HR with contact plugs CC3 and CC6 in between becomes 2 × D_CC-HR, which is wide. In this case, the insulating film 22 of the laminate 20 is more prone to bending during the replacement process.

[0056] In contrast, the contact plug CCn according to this embodiment has a lower pillar CCnL below (in the -Z direction) the connecting electrode film 21_n. Therefore, the support column HR and the lower pillar CCnL can support the insulating film 22 at a relatively narrow pitch. This makes it possible to suppress bending or indentation of the insulating film 22 below the upper pillar CCnU during the replacement process.

[0057] (Second Embodiment) Figure 8 is a cross-sectional view showing an example of the configuration of a semiconductor memory device 1 according to the second embodiment. In the second embodiment, the stacked body 20 includes a first stacked portion T1 and a second stacked portion T2.

[0058] The first and second laminated sections T1 and T2 each have a plurality of electrode films 21 and a plurality of insulating films 22 stacked in the Z direction. The second laminated section T2 is stacked above the first laminated section T1 (in the +Z direction).

[0059] The contact plug CC penetrates the first and second laminated sections T1 and T2, and the first laminated section T1 has the same configuration as that of the first embodiment.

[0060] However, although not shown in the figures, the multiple contact plugs CC also include contact plugs CCn connected to one of the electrode films 21 of the second laminated section T2. ​​In this case, the connecting electrode film 21_n connected to the contact plug CCn is located within the second laminated section T2. ​​Therefore, the lower pillar CCnL of the contact plug CCn is the portion of the contact plug CCn that is below (-Z direction) the connecting electrode film 21_n within the second laminated section T2. ​​The upper pillar CCnU of the contact plug CCn is the portion of the contact plug CCn that is above (+Z direction) the connecting electrode film 21_n within the second laminated section T2. ​​In the second embodiment as well, the width WnL of the lower pillar CCnL is smaller than the width WnU of the upper pillar CCnU.

[0061] As a result, in the second embodiment as well, during the replacement process, the lower pillar CCnL of the contact plug CCn can support the insulating film 22 which is below the height of the connecting electrode film 21_n. This prevents the insulating film 22 from bending or collapsing.

[0062] Furthermore, as shown in Figure 8, when the connecting electrode film 21_n is located within the first laminated portion T1, the connection portion JT of the contact plug CC between the first laminated portion T1 and the second laminated portion T2 is constricted. That is, the width of the contact plug CC in the XY plane is W1U within the first and second laminated portions T1 and T2, and WJT at the connection portion JT between the first laminated portion T1 and the second laminated portion T2. ​​The width WJT is smaller than the width W1U. Therefore, the contact plug CC has a constricted shape at the connection portion JT.

[0063] Conversely, the insulating film 25 between the first laminated portion T1 and the second laminated portion T2 protrudes toward the center of the contact plug CC in the XY plane. As a result, the contact plug CC has a constricted shape at the connection portion JT. Furthermore, the insulating film 25 has an opening in the portion of the contact plug CC so that the contact plug CC does not become electrically separated at the connection portion JT.

[0064] Thus, even if the laminate 20 includes multiple laminated sections T1 and T2, the effects of this embodiment are not lost. The number of laminated sections included in the laminate 20 is not limited.

[0065] Next, the method for manufacturing the semiconductor memory device 1 according to this embodiment will be described.

[0066] Figures 9 to 30 are cross-sectional views showing an example of a method for manufacturing a semiconductor memory device 1 according to the second embodiment. Here, the method for manufacturing the contact plug CC formation region 2c of the electrode film 21 (word line) is illustrated, while the method for manufacturing the memory cell array 2m including the columnar body CL is omitted from the illustration.

[0067] First, a laminated portion T1 is formed by alternately stacking multiple sacrificial films 21a and multiple insulating films 22 on a substrate 10 in the +Z direction. The sacrificial films 21a are made of a material that is etch-selective to the insulating film 22, such as a silicon nitride film. The insulating films 22 are made of an insulating material, such as a silicon oxide film.

[0068] Next, an insulating film 25 is formed on the laminated portion T1, and then mask materials 310 and 320 are formed on the insulating film 25. The insulating film 25 is composed of, for example, a silicon oxide film formed using TEOS. The mask material 310 is composed of, for example, a material that has etching selectivity for silicon oxide films and silicon nitride films, such as an amorphous silicon film. The mask material 320 is composed of, for example, a material such as a silicon nitride film. This results in the structure shown in Figure 9.

[0069] Next, using lithography and etching techniques, contact holes CH1 are formed in the contact plug CC formation region, as shown in Figure 10. The contact holes CH1 are formed to extend in the -Z direction to a position one layer shallower (higher) than the height of the connecting electrode film 21_n corresponding to the contact plug CCn. At this stage, since the electrode film 21 has not yet been formed, the contact holes CH1 do not reach the sacrificial film 21a corresponding to the connecting electrode film 21_n, but are formed to the depth (first depth) of the insulating film 22, which is one layer shallower (higher) before it.

[0070] Next, as shown in Figure 11, a block film 330 and a spacer film 340 are formed on the mask material 320 and on the inner wall of the contact hole CH1. The block film 330 and the spacer film 340 are made of an insulating material such as a silicon oxide film.

[0071] Next, as shown in Figure 12, the block film 330 and spacer film 340 are anisotropically etched back to remove the block film 330 and spacer film 340 at the bottom of the contact hole CH1, leaving the block film 330 and spacer film 340 on the sides of the contact hole CH1 in place. Furthermore, the sacrificial film 21a and insulating film 22 directly below the bottom of the contact hole CH1 are anisotropically etched to form the contact hole CH1 so that it extends in the -Z direction to a position deeper (lower) than the depth of the corresponding connecting electrode film 21_n. At this stage, since the electrode film 21 has not yet been formed, the contact hole CH1 penetrates the sacrificial film 21a corresponding to the connecting electrode film 21_n and is formed to the depth of the insulating film 22 (second depth) at a position deeper (lower) beyond it.

[0072] Next, a sacrificial film 350 is embedded in the contact hole CH1. As shown in Figure 13, the sacrificial film 350 is etched back to the height of the mask material 310 or insulating film 25. The sacrificial film 350 is made of a material that is etching selective to silicon, silicon oxide film, or silicon nitride film, such as carbon.

[0073] Next, as shown in Figure 14, the block film 330 and the spacer film 340 are wet-etched so that the sacrificial film 350 protrudes somewhat from the block film 330 and the spacer film 340 within the contact hole CH1.

[0074] Next, after removing the sacrificial film 350, a narrowing film 360 is formed at the opening of the contact hole CH1 to narrow the opening, as shown in Figure 15. The narrowing film 360 is, for example, an epitaxially grown silicon film. If the mask material 310 is made of amorphous silicon, a silicon film can be selectively epitaxially grown on the side wall of the mask material 310 exposed in the contact hole CH1. Also, when the sacrificial film 350 is removed, the sacrificial film 21a at the height of the corresponding connecting electrode film 21 is exposed at the bottom of each contact hole CH1.

[0075] Next, as shown in Figure 16, a thin barrier film 370 is formed on the mask material 320 and on the inner wall of the contact hole CH1. The barrier film 370 is made of an insulating material such as a silicon oxide film. The barrier film 370 covers the sacrificial film 21a that is exposed at the bottom of each contact hole CH1.

[0076] Specifically, the sidewalls of the contact holes CH1 corresponding to the upper CCnU of the pillar above the sacrificial film 21a on which the connecting electrode film 21 is to be formed are protected by the block film 330 and the spacer film 340. The sacrificial film 21a on which the connecting electrode film 21 is to be formed is protected by the barrier film 370.

[0077] Next, a sacrificial film 380 is formed on the barrier film 370. The sacrificial film 380 is formed to close the opening of the contact hole CH1 while leaving a seam or void (hereinafter simply referred to as a seam) SM inside the contact hole CH1. Since the sacrificial film 380 has a seam SM inside, it is easily removed by etching.

[0078] Next, the surface of the structure is planarized using methods such as CMP (Chemical Mechanical Polishing). As a result, as shown in Figure 17, the mask materials 310 and 320 and the barrier film 370 and sacrificial film 380 on top of them are removed, and the surfaces of the insulating film 25 and sacrificial film 380 are exposed.

[0079] Next, contact holes CH1, holes H1 in the support columns HR, and memory holes (not shown) are formed using lithography and etching techniques. As shown in Figure 18, the sacrificial film 21a and insulating film 22 directly below the bottom of the contact hole CH1 are anisotropically etched through the seam SM. This processes the contact hole CH1 so that it penetrates the laminated portion T1. The holes H1 in the support columns HR are positioned around the contact hole CH1 and are formed to penetrate the laminated portion T1 in the -Z direction. Although not shown, memory holes may also be formed to penetrate the laminated portion T1 in the -Z direction at this time.

[0080] Next, as shown in Figure 19, a sacrificial film 351 is formed in the contact hole CH1, hole H1, and memory hole.

[0081] Next, an insulating film 25 is further deposited on the sacrificial film 351 of the contact hole CH1, hole H1, and memory hole.

[0082] Next, multiple sacrificial films 21a and multiple insulating films 22 are alternately stacked on the insulating film 25 in the +Z direction to form a laminated portion T2. ​​Similar to the process for forming the laminated portion T1, the insulating film 25 and mask materials 310 and 320 are formed on the laminated portion T2. ​​This results in the structure shown in Figure 19.

[0083] Next, as shown in Figure 20, above each of the contact holes CH1, a plurality of contact holes CH2 are formed that penetrate the laminated portion T2 in the +Z direction and reach the insulating film 25 below the laminated portion T2, corresponding to the contact holes CH1.

[0084] Furthermore, when a connecting electrode film 21_n is formed in the laminated portion T1, the contact hole CH2 is formed to reach the insulating film 25 below the laminated portion T2, as shown in Figure 20. On the other hand, when a connecting electrode film 21_n is formed in the laminated portion T2, the contact hole CH2 is formed within the laminated portion T2 to the depth of the connecting electrode film 21_n formation position, although this is not shown in the figure. In this case, a sacrificial film 351 is provided below the contact hole CH2, penetrating the laminated portion T1 in the Z direction.

[0085] Next, similar to the block film 330 and spacer film 340 in the laminated portion T1, a block film 330 and a spacer film 340 are formed on the side walls of the contact hole CH2 in the laminated portion T2. ​​The block film 330 and spacer film 340 at the bottom of the contact hole CH2 are removed by etch-back.

[0086] Next, similar to the narrowing film 360 of the contact hole CH1 in the laminated portion T1, a narrowing film 360 is selectively formed at the opening of the contact hole CH2 to narrow the opening of the contact hole CH2.

[0087] Next, a barrier film 370 is formed on the spacer film 340 on the side wall of the contact hole CH2, and then the barrier film 370 at the bottom of the contact hole CH2 is removed by etch-back. Using the mask material 320 and the barrier film 370 as a mask, the insulating film 25 at the bottom of the contact hole CH2 is partially etched. This results in the structure shown in Figure 21. At this time, the insulating film 25 of the connection part JT remains between the contact hole CH2 and the sacrificial film 351 in the contact hole CH1.

[0088] Next, similar to the sacrificial film 380 in the contact hole CH1 in the laminated portion T1, a sacrificial film 380 is also formed in the contact hole CH2. That is, as shown in Figure 22, the sacrificial film 380 is formed to close the opening of the contact hole CH2 while leaving a seam SM inside the contact hole CH2. As a result, the sacrificial film 380 has a seam SM inside, making it easily removable by etching.

[0089] Next, the surface of the structure is planarized using methods such as CMP. This removes the mask materials 310 and 320 and the barrier film 370 and sacrificial film 380 on top of them, as shown in Figure 21, exposing the surfaces of the insulating film 25 and the sacrificial film 380. This results in the structure shown in Figure 22.

[0090] Next, contact holes CH2, holes H2 in the support column HR, and memory holes (not shown) are formed using lithography and etching techniques. As shown in Figure 23, the insulating film 25 directly below the bottom of the contact hole CH2 is anisotropically etched through the seam SM. As a result, the contact hole CH2 penetrates the laminated portion T2 and communicates with the contact hole CH1. The sacrificial film 351 in the contact hole CH1 is exposed at the bottom of the contact hole CH2. Also, holes H2 in the support column HR are formed around the contact hole CH2. Hole H2 is formed to penetrate the laminated portion T2 in the -Z direction and communicates with hole H1. The sacrificial film 351 in the hole H1 is exposed at the bottom of hole H2. Although not shown, memory holes may also be formed to penetrate the laminated portion T2 in the -Z direction at this time. The memory holes in the laminated portion T2 communicate with the memory holes that were formed in the laminated portion T1. Furthermore, the sacrificial film formed within the memory holes in the stacked portion T1 is exposed at the bottom of the memory holes in the stacked portion T2.

[0091] Next, as shown in Figure 24, the sacrificial film 351 in the contact holes CH1, CH2, holes H1, H2, and memory holes is removed. At this time, in the lower part of the contact hole CH1, the sacrificial film 21a that is below the barrier film 370 is exposed on the side wall of the contact hole CH1.

[0092] Next, using lithography technology, the memory holes and contact holes CH1 and CH2 are covered with resist to form insulating material within holes H1 and H2. As a result, support columns HR are formed within holes H1 and H2, as shown in Figure 24.

[0093] Next, after removing the resist, the support pillars HR and contact holes CH1 and CH2 are again coated with resist using lithography techniques to form the memory film 220, semiconductor body 210, and core layer 230 shown in Figures 3 and 4 within the memory holes. This forms the columnar body CL within the memory holes. Note that the formation of the columnar body CL may be performed before the formation of the support pillars HR.

[0094] Next, after removing the resist, the support columns HR and columnar bodies CL are coated with resist again using lithography techniques to remove the sacrificial film 380 in the contact holes CH1 and CH2. At this time, the sacrificial film 380 is removed by wet etching, and the exposed sacrificial film 21a located below the barrier film 370 in the contact hole CH1 is isotropically etched. Since the sacrificial film 380 has a seam SM inside, it is easily removed by etching. As a result, as shown in Figure 25, a first space SP1 is formed between the insulating films 22 that are located below the barrier film 370 and adjacent in the Z direction.

[0095] Next, as shown in Figure 26, an insulating film 21c is embedded in the first space SP1. The insulating film 21c is composed of an insulating material that has etching selectivity with respect to the sacrificial film 21a, such as a silicon oxide film.

[0096] Next, after removing the barrier film 370, a sacrificial film 390 is formed in the contact holes CH1 and CH2, as shown in Figure 27. The sacrificial film 390 is made of a material that has etching selectivity for silicon oxide films such as amorphous silicon, silicon nitride films, etc. Next, the insulating film 25 material (for example, a silicon oxide film) is further deposited on the laminated portion T2.

[0097] Next, using lithography and etching techniques, slits (ST in Figure 2) are formed that penetrate the laminated portions T1 and T2 (laminated body 20) in the -Z direction and reach the substrate 10.

[0098] Next, using a wet etching method or the like, the sacrificial film 21a is removed from the laminated portions T1 and T2 through the slit ST to form a second space SP2 between adjacent insulating films 22 in the Z direction.

[0099] Next, as shown in Figure 28, an electrode film 21 is formed in the second space SP2. The electrode film 21 is made of a conductive material such as tungsten. This process of replacing the sacrificial film 21a with the electrode film 21 is called the "replacement process". The electrode film 21 functions as a control electrode (word line) of the memory cell MC.

[0100] Here, as shown in Figure 28, the connecting electrode films 21_1, 21_3, and 21_6 of the electrode film 21 are in contact with the sacrificial film 390 embedded in the corresponding contact holes CH1 and CH2, respectively. The electrode films 21 located above (+Z direction) the connecting electrode films 21_1, 21_3, and 21_6 are separated from the sacrificial film 390 embedded in the contact holes CH1 and CH2 by the spacer 340 and the block film 330. Also, the electrode films 21 located below (-Z direction) the connecting electrode films 21_1, 21_3, and 21_6 are separated from the sacrificial film 390 embedded in the contact holes CH1 and CH2 by the insulating film 21c.

[0101] Next, using lithography and etching techniques, the insulating film 25 on the contact holes CH1 and CH2 is selectively removed, as shown in Figure 29.

[0102] Next, the sacrificial film 390 inside the contact holes CH1 and CH2 is removed using a wet etching method or the like. At this time, the corresponding connecting electrode films 21_1, 21_3, and 21_6 are exposed on the side walls of the contact holes CH1 or CH2, respectively.

[0103] Next, as shown in Figure 30, the material for the contact plug CC is embedded in the contact holes CH1 and CH2. The contact plug CC is made of a conductive material such as tungsten. The contact plug CC is electrically connected to the connecting electrode films 21_1, 21_3, and 21_6 exposed in the contact holes CH1 or CH2.

[0104] Here, as shown in Figure 30, the connecting electrode films 21_1, 21_3, and 21_6 of the electrode film 21 are in contact with their respective contact plugs CC1, CC3, and CC6. The electrode films 21 located above (+Z direction) the connecting electrode films 21_1, 21_3, and 21_6 are electrically isolated from the contact plugs CC1, CC3, and CC6 by the spacer 340 and the block film 330. The electrode films 21 located below (-Z direction) the connecting electrode films 21_1, 21_3, and 21_6 are electrically isolated from the contact plugs CC1, CC3, and CC6 by the insulating film 21c.

[0105] Subsequently, a multilayer wiring layer and interlayer insulating film (23-25, 28 in Figure 1) are formed above the laminated section T2. ​​This completes the array wafer having multiple array chips.

[0106] On the other hand, a CMOS wafer containing CMOS chips is formed separately from the memory wafer. For example, multiple semiconductor elements such as transistors are formed on a semiconductor substrate, and an interlayer insulating film is formed to cover the multiple semiconductor elements. In addition, a wiring layer is formed which is electrically connected to the semiconductor elements and is partially exposed from the interlayer insulating film.

[0107] The memory wafer and the CMOS wafer are bonded together at the bonding surface B1 in Figure 1, electrically connecting the wiring layer on the CMOS wafer side to the contacts on the array wafer side.

[0108] Subsequently, the substrate 10 of the memory wafer is removed, and the metal layer 40 and bonding pad 50 shown in Figure 1 are formed. Furthermore, the bonded memory wafer and CMOS wafer are diced into semiconductor chips in a dicing process. This completes the semiconductor memory device 1 shown in Figure 1.

[0109] The semiconductor memory device 1 according to the second embodiment can be formed through the manufacturing process described above.

[0110] Furthermore, the method for manufacturing the semiconductor memory device 1 according to the first embodiment can be easily understood from the manufacturing method of the second embodiment.

[0111] For example, the sacrificial film 351 is formed in the contact hole CH1 and hole H1 through the process described with reference to Figures 9 to 18.

[0112] The process of forming the laminated portion T2, as explained with reference to Figures 19 to 23, will be omitted.

[0113] Subsequently, the support column HR and columnar body CL are formed, as explained with reference to Figure 24.

[0114] Furthermore, after going through the replacement process and other steps described with reference to Figures 25 to 30, a contact plug CC is formed in the contact hole CH1.

[0115] Other manufacturing steps in the first embodiment may be the same as those in the second embodiment. This makes it possible to form the semiconductor memory device 1 of the first embodiment shown in Figure 5.

[0116] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0117] 1. Semiconductor memory 2 array chips 3 CMOS chips 20 Laminate CL columnar body 25 Insulating film 2c Contact area HR support pillar CC Contact Plug 21 Electrode membrane 22 Insulating film 21c insulating film

Claims

1. A laminate in which multiple electrode films and multiple first insulating films are alternately stacked in a first direction, A first columnar body includes a semiconductor layer provided penetrating the laminate in a first direction, and a memory cell is formed at the intersection with one of the plurality of electrode films, The laminate penetrates in the first direction and comprises a plurality of first pillar portions made of insulating material, The laminate comprises a plurality of second pillar portions that penetrate in the first direction, are made of a conductive material, and are electrically connected to each of the plurality of electrode films, A semiconductor memory device wherein the width of the plurality of second pillar portions in a plane perpendicular to the first direction differs between the upper part of the pillar, which is above the connecting electrode film in the first direction, and the lower part of the pillar, which is below the connecting electrode film in the first direction, with respect to the connecting electrode film that is connected to each of the plurality of second pillar portions among the plurality of electrode films.

2. The semiconductor memory device according to claim 1, wherein the width of the plurality of second pillar portions in a plane perpendicular to the first direction is smaller at the lower part of the pillar than at the upper part of the pillar.

3. The semiconductor memory device according to claim 1, wherein, in the vertical surface of the electrode film in the lowest layer of the laminate, the width of some of the plurality of second pillar portions is greater than the width of the other second pillar portions.

4. The semiconductor memory device according to claim 1, wherein, in the vertical plane of the electrode film of the lowest layer of the laminate, the first interval between adjacent first pillar portions and second pillar portions is greater than the second interval between adjacent first pillar portions without the second pillar portion in between.

5. The semiconductor memory device according to claim 1 or claim 4, wherein the second spacing between adjacent first pillar portions without a second pillar portion in between is substantially equal in all cases.

6. The laminate includes a first laminated portion and a second laminated portion, each having the plurality of electrode films and the plurality of first insulating films stacked in the first direction, The semiconductor memory device according to claim 1, wherein the width of the plurality of second pillar portions in a plane perpendicular to the first direction is smaller in the connection portion between the first and second stacked portions than within the first and second stacked portions.

7. The semiconductor memory device according to claim 1, further comprising a second insulating film provided between the electrode film located below the connecting electrode film in the first direction and the lower part of the pillar.

8. A first laminated portion is formed by alternately stacking multiple first sacrificial films and multiple first insulating films in a first direction. A plurality of first holes are formed within the first laminated portion, extending in the first direction to a first depth of the shallower first insulating film one layer before each of the plurality of first sacrificial films. A first material film is formed on the side walls of the plurality of first holes. The first sacrificial film located directly below the bottom of the plurality of first holes is anisotropically etched to form the plurality of first holes to a second depth of the first insulating film that is one layer deeper than each of the plurality of first sacrificial films. A second material film is formed on the side walls of the plurality of first holes. A second sacrificial film having seams or voids is formed within the plurality of first holes. The first sacrificial film and the first insulating film located directly below the bottom of the plurality of first holes are anisotropically etched through the seams or voids to process the plurality of first holes so as to penetrate the first laminated portion, and a plurality of second holes and a plurality of memory holes are formed around the first holes, penetrating the first laminated portion in the first direction. A first pillar portion made of insulating material is formed within the plurality of second holes. A plurality of first columnar bodies, each containing a semiconductor layer and a memory film, are formed within the plurality of memory holes. The first sacrificial film located below the first material film in the plurality of first holes is removed to form a first space between adjacent first insulating films in the first direction. A second insulating film is formed in the first space. A third sacrificial membrane is formed within the plurality of first holes. The plurality of first sacrificial films are removed from the first laminated portion to form a second space between the first insulating films adjacent in the first direction. Multiple electrode films made of conductive material are formed in the second space. Remove the third sacrificial film, A method for manufacturing a semiconductor memory device, comprising forming a conductive material in the plurality of first holes to form a plurality of contacts connected to each of the plurality of electrode films.

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