Wiring board and method for manufacturing a wiring board

Abstract

To maintain adhesion between the wiring layer and the insulating layer while forming appropriate openings in the insulating layer. [Solution] The wiring board has a wiring layer, an insulating layer, and an opening. The insulating layer is laminated on the wiring layer. The opening penetrates the insulating layer to the wiring layer. The surface of the wiring layer has a roughened area formed in areas other than the area overlapping with the periphery of the bottom surface of the opening, and a roughness reduction area formed in the area overlapping with the periphery of the bottom surface of the opening, where the surface roughness is lower than that of the roughened area.

Description

Technical Field

[0001] The present invention relates to a wiring board and a method for manufacturing the wiring board.

Background Art

[0002] Conventionally, for example, some wiring boards on which semiconductor chips are mounted have a multilayer wiring structure formed by using, for example, a semi-additive method. Specifically, a wiring layer is formed on an insulating layer by electroless plating and electrolytic plating, and further an insulating layer covering this wiring layer is formed. Thus, by repeating the lamination of the insulating layer and the wiring layer, a wiring board having a multilayer wiring structure is formed.

[0003] In such a wiring board, the wiring layer on the outermost layer of the multilayer wiring structure is covered by an insulating insulating layer called a solder resist layer. And, by providing connection terminals penetrating the insulating layer as needed, the wiring layer on the outermost layer and electronic components such as semiconductor chips mounted on the insulating layer can be electrically connected.

[0004] The connection terminal is formed by covering the wiring layer on the outermost layer with an insulating layer, forming an opening penetrating to the wiring layer in the insulating layer by exposure and development, forming a seed layer on the surface of the insulating layer including the inner wall surface of the opening by electroless plating, and performing electrolytic plating on the seed layer.

[0005] Also, in a wiring board having a multilayer wiring structure, before covering the wiring layer on the outermost layer with an insulating layer, roughening treatment may be performed on the surface of the wiring layer. By performing roughening treatment on the surface of the wiring layer, the surface of the wiring layer becomes a roughened surface including irregularities, and by filling a part of the insulating layer into this roughened surface, the adhesion between the wiring layer and the insulating layer can be improved by an anchor effect.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

[0007] However, in wiring boards where the surface of the wiring layer is roughened, there is a problem in that it is difficult to form appropriate openings in the insulating layer while maintaining adhesion between the wiring layer and the insulating layer. Specifically, when forming openings in the insulating layer by exposure and development, the fluidity of the developer decreases near the periphery of the bottom surface of the opening due to the frictional resistance of the roughened surface, so that the resin residue constituting the insulating layer tends to remain in a drooping shape. As a result, openings of an appropriate shape are not formed in the insulating layer, and the reliability of the connection between the connection terminals at the opening and the wiring layer is reduced.

[0008] Alternatively, one could consider covering the wiring layer with an insulating layer without roughening its surface. However, in this case, the adhesion between the wiring layer and the insulating layer may decrease, potentially leading to delamination of the insulating layer.

[0009] The disclosed technology has been made in view of the above, and aims to provide a wiring board and a method for manufacturing a wiring board that can form appropriate openings in the insulating layer while maintaining adhesion between the wiring layer and the insulating layer. [Means for solving the problem]

[0010] In one embodiment, the wiring board disclosed in this application has a wiring layer, an insulating layer, and an opening. The insulating layer is laminated on the wiring layer. The opening penetrates the insulating layer to the wiring layer. The surface of the wiring layer has a roughened portion formed in areas other than the region overlapping with the periphery of the bottom surface of the opening, and a roughness reduction portion formed in the region overlapping with the periphery of the bottom surface of the opening, where the surface roughness is lower than that of the roughened portion. [Effects of the Invention]

[0011] According to one embodiment of the wiring substrate disclosed in this application, it is possible to form appropriate openings in the insulating layer while maintaining adhesion between the wiring layer and the insulating layer. [Brief explanation of the drawing]

[0012] [Figure 1] Figure 1 shows the configuration of a wiring board according to an embodiment. [Figure 2] Figure 2 is a magnified view of the area around the connection terminal according to the embodiment. [Figure 3] Figure 3 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 4] Figure 4 shows a specific example of the core substrate formation process. [Figure 5] Figure 5 shows a specific example of the build-up process. [Figure 6] Figure 6 shows a specific example of the solder resist layer formation process. [Figure 7] Figure 7 shows a specific example of the connection terminal formation process. [Figure 8] Figure 8 shows a specific example of the semiconductor chip mounting process. [Figure 9] Figure 9 is a flowchart showing the connection terminal formation process according to the embodiment. [Figure 10] Figure 10 is a magnified view of the topmost wiring layer. [Figure 11] Figure 11 shows a specific example of a roughening process. [Figure 12] Figure 12 shows a specific example of a roughness reduction process. [Figure 13] Figure 13 shows the appearance of the pad surface when viewed from above. [Figure 14] Figure 14 shows the stacking state of the solder resist layers. [Figure 15] Figure 15 shows a specific example of the opening formation process. [Figure 16] Figure 16 shows a specific example of an electroless plating process. [Figure 17] FIG. 17 is a diagram showing a specific example of the DFR layer forming process. [Figure 18] FIG. 18 is a diagram showing a specific example of the electrolytic plating process. [Figure 19] FIG. 19 is a diagram showing a specific example of the DFR layer removing process. [Figure 20] FIG. 20 is a diagram showing an enlarged view of the periphery of the connection terminal according to Modification Example 1 of the embodiment. [Figure 21] FIG. 21 is a diagram showing a modification example of the roughness reduction process. [Figure 22] FIG. 22 is a diagram showing the appearance of the surface of the pad when viewed from above. [Figure 23] FIG. 23 is a diagram showing an enlarged view of the periphery of the connection terminal according to Modification Example 2 of the embodiment. [Figure 24] FIG. 24 is a flowchart showing the connection terminal forming process according to Modification Example 2 of the embodiment. [Figure 25] FIG. 25 is a diagram showing a specific example of the solder ball mounting process. [Figure 26] FIG. 26 is a diagram showing a specific example of the reflow process.

BEST MODE FOR CARRYING OUT THE INVENTION

[0013] Hereinafter, embodiments of the wiring board and the method for manufacturing a wiring board disclosed in the present application will be described in detail based on the drawings. Note that the disclosed technology is not limited by this embodiment.

[0014] (Embodiment) FIG. 1 is a diagram showing the configuration of a wiring board 100 according to an embodiment. In FIG. 1, a cross-section of the wiring board 100 is schematically shown. The wiring board 100 shown in FIG. 1 can be used, for example, as a substrate of a semiconductor device that mounts a semiconductor chip.

[0015] The wiring board 100 has a laminated structure and includes a core substrate 110, a multilayer wiring structure 120, and solder resist layers 130 and 140. In the following description, as shown in Figure 1, the solder resist layer 140 is the bottom layer and the solder resist layer 130 is the top layer. However, the wiring board 100 may be used upside down, for example, or in any orientation.

[0016] The core substrate 110 is formed by plating metal on both sides of a base material 111, which is a plate-shaped insulator. The wiring layers 113 on both sides are connected by through-wiring 112 that penetrates the base material 111 as needed.

[0017] The multilayer wiring structure 120 is formed by laminating layers, each comprising an insulating insulating layer 121 and a conductive wiring layer 122. The insulating layer 121 is formed using an insulating, non-photosensitive resin such as epoxy resin and polyimide resin. The wiring layer 122 is formed using a metal such as copper or a copper alloy. In Figure 1, two layers are laminated in the multilayer wiring structure 120 above the core substrate 110, and two layers are laminated in the multilayer wiring structure 120 below the core substrate 110, but the number of laminated layers may be one or three or more. Adjacent wiring layers 113 and 122 are connected via vias 123 that penetrate the insulating layer 121 as needed.

[0018] The uppermost wiring layer 122 has pads 124 that connect to connection terminals 150 with the semiconductor chip and wiring patterns 125 located around the pads 124. As will be described later, the surface of the uppermost wiring layer 122 is roughened overall, but the surface roughness of the wiring layer 122 is locally reduced near the periphery of the bottom surface of the openings 131 formed in the solder resist layer 130.

[0019] The solder resist layer 130 is a layer that covers the uppermost wiring layer 122 of the multilayer wiring structure 120 and protects the wiring. The solder resist layer 130 is a layer made of an insulating photosensitive resin such as acrylic resin and polyimide resin, and is one of the insulating layers.

[0020] The solder resist layer 130 side of the wiring board 100 is the side on which electronic components such as semiconductor chips are mounted. An opening 131 is formed in the solder resist layer 130 at the location where the semiconductor chip is mounted. Since the solder resist layer 130 is formed using a photosensitive resin, the opening 131 can be formed by exposure and development. A connection terminal 150 is formed in the opening 131 to connect the wiring layer 122 of the multilayer wiring structure 120 to the electrodes of the semiconductor chip. That is, a pad 124 is exposed on the bottom surface of the opening 131, and the connection terminal 150 is connected to the pad 124.

[0021] The solder resist layer 140, like the solder resist layer 130, is a layer that covers the wiring layer 122 on the surface of the multilayer wiring structure 120 and protects the wiring. The solder resist layer 140 is a layer made of an insulating photosensitive resin such as acrylic resin and polyimide resin, and is one of the insulating layers.

[0022] The solder resist layer 140 side of the wiring board 100 is the side that connects to external components and equipment. At the locations where external connection terminals that electrically connect to external components and equipment are formed, an opening 141 is formed in the solder resist layer 140, and the wiring layer 122 of the multilayer wiring structure 120 is exposed through the opening 141. External connection terminals, such as solder balls, are formed in the opening 141. Since the solder resist layer 140 is formed using a photosensitive resin, the opening 141 can be formed by exposure and development.

[0023] Figure 2 is a magnified view of the area around the connection terminal 150 according to the embodiment. In Figure 2, the area near the connection between the connection terminal 150 and the uppermost wiring layer 122 of the multilayer wiring structure 120 is shown in magnified view.

[0024] As shown in Figure 2, the connection terminal 150 has a seed layer 151 which is an electroless plating film formed by electroless plating, and a post 152 which is an electroplating film formed on the seed layer 151 by electroplating. In addition, the surface of the wiring layer 122 is roughened overall to form a roughened portion 122a. However, near the periphery of the bottom surface of the opening 131 formed in the solder resist layer 130, the surface roughness of the wiring layer 122 is locally reduced to form a roughened portion 122b.

[0025] Specifically, roughened areas 122a are formed on the surface of the wiring layer 122, excluding the area overlapping with the periphery of the bottom surface of the opening 131, and roughness reduction areas 122b, which have a lower surface roughness than the roughened areas 122a, are formed on the surface of the wiring layer 122, in the area overlapping with the periphery of the bottom surface of the opening 131. A portion of the solder resist layer 130 fills the irregularities in the roughened areas 122a, and the adhesion between the wiring layer 122 and the solder resist layer 130 is improved by the anchoring effect. Since the roughness reduction areas 122b have less frictional resistance in the direction parallel to the surface of the wiring layer 122 compared to the roughened areas 122a, the decrease in the fluidity of the developer used to form the opening 131 is suppressed near the periphery of the bottom surface of the opening 131. As a result, residue of the resin constituting the solder resist layer 130 is less likely to remain near the periphery of the bottom surface of the opening 131, and an opening 131 of an appropriate shape is formed in the solder resist layer 130. As a result, it is possible to form appropriate openings 131 in the solder resist layer 130 while maintaining adhesion between the wiring layer 122 and the solder resist layer 130. In other words, it is possible to improve the reliability of the connection between the connection terminal 150 and the wiring layer 122 at the opening 131 without causing the solder resist layer 130 to peel off from the wiring layer 122.

[0026] Furthermore, the roughened portion 122a is formed on the surface of the pad 124 included in the wiring layer 122, excluding the area overlapping with the periphery of the bottom surface of the opening 131, and on the surface of the wiring pattern 125. The roughness reduction portion 122b is formed on the surface of the pad 124, in the area overlapping with the periphery of the bottom surface of the opening 131. By forming the roughness reduction portion 122b only on a portion of the surface of the pad 124, and forming the roughened portion 122a on the other areas of the surface of the pad 124 and on the surface of the wiring pattern 125, the adhesion between the wiring layer 122 and the solder resist layer 130 can be stably maintained.

[0027] In the example shown in Figure 2, the roughness reduction portion 122b is formed in a region of the surface of the wiring layer 122 that overlaps with the periphery of the bottom surface of the opening 131 but does not overlap with the center of the bottom surface of the opening 131. In other words, the roughness reduction portion 122b is not formed in the region of the surface of the wiring layer 122 that overlaps with the center of the bottom surface of the opening 131, and in such a region, the roughened portion 122a is formed.

[0028] Next, a method for manufacturing a semiconductor device having the wiring board 100 configured as described above will be explained with reference to Figure 3, with specific examples. Figure 3 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment.

[0029] First, a core substrate 110, which will serve as a support member for the wiring board 100, is formed (step S101). Specifically, as shown in Figure 4, for example, through-wiring 112 is formed on a base material 111, which is a plate-shaped insulator, and metal wiring layers 113, such as copper or a copper alloy, are formed on both sides of the base material 111, for example, by copper foil or copper plating. Figure 4 shows a specific example of the core substrate formation process. The wiring layers 113 on both sides of the base material 111 are connected by through-wiring 112 formed by metal plating, such as copper or a copper alloy, as needed. As the base material 111, for example, a reinforcing material such as glass woven fabric impregnated with an insulating resin such as epoxy resin can be used. As the reinforcing material, in addition to glass woven fabric, glass nonwoven fabric, aramid woven fabric, or aramid nonwoven fabric can be used. As the insulating resin, in addition to epoxy resin, polyimide resin or cyanate resin can be used.

[0030] Then, a multilayer wiring structure 120 is formed on the upper and lower surfaces of the core substrate 110 by a build-up method (step S102). Specifically, as shown in Figure 5, for example, an insulating layer 121 is formed on the upper and lower surfaces of the core substrate 110, and a wiring layer 122 is formed on the surface of the insulating layer 121. Figure 5 is a diagram showing a specific example of the build-up process. The insulating layer 121 is formed using an insulating, non-photosensitive resin such as epoxy resin and polyimide resin. The wiring layer 122 is formed by a semi-additive method, for example, by plating with a metal such as copper or a copper alloy.

[0031] The wiring layers 113 and 122 of the core substrate 110, or the wiring layers 122 of adjacent layers, are connected by vias 123 formed by metal plating, such as copper or a copper alloy, as needed. Multiple insulating layers 121 and wiring layers 122 may be stacked on the upper and lower surfaces of the core substrate 110, respectively. The uppermost wiring layer 122 has pads 124 that are connected to connection terminals 150 with a semiconductor chip, and wiring patterns 125 located around the pads 124.

[0032] Once the multilayer wiring structure 120 is formed by the build-up method, a roughening treatment is performed to roughen the surface of the uppermost wiring layer 122 of the multilayer wiring structure 120. That is, for example, an organic acid-based chemical solution is used to roughen the surface of the uppermost wiring layer 122, forming a roughened portion 122a. Once the roughened portion 122a is formed, a roughness reduction treatment is performed to lower the surface roughness of a part of the surface of the wiring layer 122. That is, near the periphery of the bottom surface of the opening 131 formed in the solder resist layer 130, for example, laser processing is used to locally reduce the surface roughness of the wiring layer 122, forming a roughness reduction portion 122b.

[0033] Then, the outermost wiring layer 122 of the multilayer wiring structure 120 is covered with solder resist layers 130 and 140 (step S103). That is, the uppermost wiring layer 122 of the multilayer wiring structure 120 laminated on the upper surface of the core substrate 110 is covered with solder resist layer 130, and the lowermost wiring layer 122 of the multilayer wiring structure 120 laminated on the lower surface of the core substrate 110 is covered with solder resist layer 140. The solder resist layers 130 and 140 are formed from insulating photosensitive resins such as acrylic resin and polyimide resin.

[0034] Then, as shown in Figure 6, for example, an opening 131 is formed in the solder resist layer 130 on the side on which the semiconductor chip is mounted, at the location where the connection terminals 150 to the semiconductor chip are provided (step S104). Figure 6 is a diagram showing a specific example of the solder resist layer formation process. The topmost wiring layer 122 of the multilayer wiring structure 120 is exposed at the bottom of the opening 131. On the other hand, an opening 141 is formed in the solder resist layer 140 on the side that is connected to external components or equipment, at the location where the external connection terminals are provided. The bottommost wiring layer 122 of the multilayer wiring structure 120 is exposed at the bottom of the opening 141.

[0035] Since the solder resist layers 130 and 140 are formed of a photosensitive resin, it is possible to form openings 131 and 141 by exposure and development.

[0036] During the formation of the opening 131 by development, the opening 131 penetrates to the uppermost wiring layer 122 of the multilayer wiring structure 120. However, near the periphery of the bottom surface of the opening 131, a roughness reduction portion 122b is formed on the surface of the wiring layer 122, which suppresses a decrease in the fluidity of the developer. As a result, resin residue constituting the solder resist layer 130 is less likely to remain near the periphery of the bottom surface of the opening 131, and an opening 131 of an appropriate shape is formed in the solder resist layer 130.

[0037] Then, a connection terminal 150 is formed at the opening 131 of the solder resist layer 130 (step S105). That is, a seed layer is formed on the surface of the solder resist layer 130, for example by electroless copper plating, and electrolytic copper plating is applied to the seed layer at the location of the opening 131, thereby forming a connection terminal 150 consisting of a seed layer 151 and a post 152. The connection terminal 150 is connected to the uppermost wiring layer 122 of the multilayer wiring structure 120 at the location of the opening 131 of the solder resist layer 130, as shown in Figure 7. Figure 7 is a diagram showing a specific example of the connection terminal formation process. The seed layer 151 may be formed by sputtering of a metal such as copper. When forming the connection terminal 150, after the post 152 is formed on the seed layer 151 by electrolytic copper plating, the unnecessary portion of the seed layer is removed by etching. The formation of the connection terminal 150 will be described in detail later.

[0038] The wiring board 100 is completed when the connection terminals 150 are formed. Then, a semiconductor chip is mounted on the solder resist layer 130 side of the wiring board 100 (step S106), and the connection terminals 150 are connected to the electrodes of the semiconductor chip.

[0039] Specifically, as shown in Figure 8, for example, the semiconductor chip 180 is mounted above the connection terminal 150. Figure 8 is a diagram showing a specific example of the semiconductor chip mounting process. The semiconductor chip 180 is mounted on the wiring board 100 by joining the electrodes 181 to the connection terminal 150, for example, with solder, and the joint between the electrodes 181 and the connection terminal 150 is sealed with underfill resin 182. Next, external connection terminals such as solder balls 170 are formed in the opening 141 of the solder resist layer 140 (step S107). Note that the order of the process of mounting the semiconductor chip 180 and the process of forming the external connection terminals may be reversed. Alternatively, the portion of the wiring layer 122 exposed from the opening 141 of the solder resist layer 140 may be used as the external connection terminal without providing the solder balls 170.

[0040] Next, the process of forming the connection terminal 150 will be explained in more detail with reference to Figure 9. Figure 9 is a flowchart of the connection terminal formation process according to the embodiment. Here, for example, the process of covering the uppermost wiring layer 122 of the multilayer wiring structure 120 shown in Figure 10 with a solder resist layer 130 and forming the connection terminal 150 on this solder resist layer 130 will be explained. Figure 10 is an enlarged view of the uppermost wiring layer 122.

[0041] Once the multilayer wiring structure 120 is formed, a roughening treatment is performed on the surface of the uppermost wiring layer 122 of the multilayer wiring structure 120 (step S201). That is, for example, using an organic acid-based chemical solution, the surface of the uppermost wiring layer 122 is roughened overall, as shown in Figure 11, to form roughened portions 122a. In other words, roughened portions 122a are formed on the surface of the pads 124 and the wiring pattern 125 contained in the wiring layer 122. Figure 11 shows a specific example of the roughening treatment process.

[0042] When a roughened area 122a is formed on the surface of the uppermost wiring layer 122, a roughness reduction treatment is performed to lower the surface roughness of a portion of the wiring layer 122's surface (step S202). That is, near the periphery of the bottom surface of the opening 131 formed in the solder resist layer 130, for example, as shown in Figure 12, the surface roughness of the wiring layer 122's surface is locally reduced to form a roughness reduction area 122b. Figure 12 is a diagram showing a specific example of the roughness reduction treatment process. The roughness reduction area 122b is formed, for example, by laser processing. For laser processing, for example, a CO2 laser or a UV laser is used, and the laser is irradiated onto the area of ​​the wiring layer 122's surface that overlaps with the periphery of the bottom surface of the opening 131 to reduce the surface roughness. Specifically, in the roughness reduction treatment, the laser irradiation melts the convex parts of the irregularities in the roughened area 122a, reducing the amount of protrusion of the convex parts and thereby reducing the surface roughness. In other words, a roughness reduction portion 122b is formed on the surface of the wiring layer 122 in a region that overlaps with the periphery of the bottom surface of the opening 131, resulting in a lower surface roughness compared to the other roughened portions 122a.

[0043] Specifically, the arithmetic mean roughness Ra representing the surface roughness of the roughened portion 122a is, for example, between 300 nm and 600 nm, while the arithmetic mean roughness Ra representing the surface roughness of the roughness-reduced portion 122b is, for example, less than 300 nm. Because the surface roughness of the roughness-reduced portion 122b is smaller than that of the roughened portion 122a, the frictional resistance in the direction parallel to the surface of the wiring layer 122 is reduced in the roughness-reduced portion 122b.

[0044] The roughness reduction portion 122b is formed in a region on the surface of the wiring layer 122 that overlaps with the peripheral edge C1 of the bottom surface of the opening 131 but does not overlap with the center C0 of the bottom surface of the opening 131, as shown in Figure 13, for example. Figure 13 shows the appearance of the surface of the pad 124 when viewed from above. That is, as shown in Figure 13, for example, the pad 124 and the opening 131 have a circular shape in plan view, and the roughness reduction portion 122b is formed in an annular region that extends radially inward and radially outward from the peripheral edge C1 of the bottom surface of the opening 131. The inner peripheral edge of the roughness reduction portion 122b is located radially inward of the opening 131 than the peripheral edge C1 of the bottom surface of the opening 131, and the outer peripheral edge of the roughness reduction portion 122b is located radially outward of the opening 131 than the peripheral edge C1 of the bottom surface of the opening 131. The diameter of the inner periphery of the roughness reduction portion 122b is about 10 μm smaller than the diameter of the periphery C1 of the bottom surface of the opening 131, and the diameter of the outer periphery of the roughness reduction portion 122b is about 10 μm larger than the diameter of the periphery C1 of the bottom surface of the opening 131.

[0045] In this way, the roughness reduction portion 122b is formed in an annular region that extends inward and outward from the peripheral edge C1 of the bottom surface of the opening 131, so that the roughened portion 122a remains near the center C0 of the bottom surface of the opening 131 without a decrease in the surface roughness of the wiring layer 122.

[0046] When a roughness reduction portion 122b is formed near the periphery of the bottom surface of the opening 131, the uppermost wiring layer 122 of the multilayer wiring structure 120 is covered by the solder resist layer 130 (step S203). Specifically, as shown in Figure 14, for example, the solder resist layer 130 is laminated so as to cover the surface of the wiring layer 122 including the roughened portion 122a and the roughness reduction portion 122b. Figure 14 is a diagram showing the laminated state of the solder resist layer 130. The solder resist layer 130 is formed from an insulating photosensitive resin such as acrylic resin and polyimide resin.

[0047] When the solder resist layer 130 is formed using a photosensitive resin, an opening 131 is formed in the solder resist layer 130 (step S204). Specifically, as shown in Figure 15, for example, the opening 131 is formed in the solder resist layer 130 at the position where the pads 124 of the wiring layer 122 are placed. Figure 15 is a diagram showing a specific example of the opening formation process. The pads 124 of the wiring layer 122 are exposed at the bottom of the opening 131.

[0048] Since the solder resist layer 130 is formed of a photosensitive resin, it is possible to form an opening 131 by exposure and development.

[0049] During the formation of the opening 131 by development, the opening 131 penetrates to the uppermost wiring layer 122 of the multilayer wiring structure 120. However, near the periphery of the bottom surface of the opening 131, a roughness reduction portion 122b is formed on the surface of the wiring layer 122, which suppresses a decrease in the fluidity of the developer. As a result, resin residue constituting the solder resist layer 130 is less likely to remain near the periphery of the bottom surface of the opening 131, and an opening 131 of an appropriate shape is formed in the solder resist layer 130.

[0050] Once an opening 131 is formed in the solder resist layer 130, a seed layer 151 is formed by electroless plating (step S205). Specifically, as shown in Figure 16, for example, the seed layer 151 is formed by electroless copper plating on the surface of the solder resist layer 130. Figure 16 shows a specific example of the electroless plating process. The thickness of the seed layer 151 is, for example, about 0.5 to 1.5 μm. The seed layer 151 covers the surface of the solder resist layer 130 and the upper surface of the wiring layer 122 (pad 124) exposed from the opening 131. The seed layer 151 may also be formed by sputtering of a metal such as copper.

[0051] Once the seed layer 151 is formed, a dry film resist (DFR) layer is formed to serve as a mask for electroplating (step S206). That is, the DFR is laminated on the seed layer 151, and exposure and development are performed according to the position of the connection terminal 150, so that, as shown in Figure 17, for example, the DFR 210 is formed on the seed layer 151 in the area excluding the position where the connection terminal 150 is formed. Figure 17 is a diagram showing a specific example of the DFR layer formation process.

[0052] Then, electroplating is performed to form a post 152 on the seed layer 151 (step S207). Specifically, by performing electroplating using, for example, a copper sulfate plating solution, copper is deposited in the areas where DFR210 has not been formed, and a post 152 is formed on the seed layer 151, as shown in Figure 18. At this time, the opening 131 is filled by electroplating. Figure 18 is a diagram showing a specific example of the electroplating process.

[0053] Once post 152 is formed, DFR210 is removed (step S208). For the removal of DFR210, for example, caustic soda or an amine-based alkaline stripping solution is used. After the removal of DFR210, as shown in Figure 19, for example, post 152 protrudes from the solder resist layer 130 and connects to the wiring layer 122 via the seed layer 151. Figure 19 is a diagram showing a specific example of the DFR layer removal process. At this stage, the seed layer 151 remains over the entire surface, and post 152 is short-circuited with other posts, so it is necessary to remove the unnecessary parts of the seed layer 151 that do not overlap with post 152.

[0054] Therefore, the seed layer 151 is etched using the post 152 as a mask (step S209). Specifically, the seed layer 151 formed on the upper surface of the solder resist layer 130 is immersed in an etching solution that selectively dissolves copper, for example, and the unnecessary parts of the seed layer 151 that do not overlap with the post 152 are removed. As a result, a connection terminal 150 consisting of the seed layer 151 and the post 152 is formed at the location of the opening 131, which connects to the wiring layer 122.

[0055] Because the opening 131 has an appropriate shape and there is little resin residue remaining near the periphery of the bottom surface of the opening 131, the close contact between the connection terminal 150 and the wiring layer 122 is not easily hindered by resin residue. As a result, the connection terminal 150 is securely fixed to the surface of the wiring layer 122, and the reliability of the connection between the connection terminal 150 and the wiring layer 122 can be improved.

[0056] (modified version) Next, modified examples of the embodiment will be described with reference to Figures 20 to 26. In the modified examples shown below, the same reference numerals are used for parts that are the same as in the embodiment, and redundant explanations may be omitted.

[0057] (Variation 1) Figure 20 is a magnified view of the area around the connection terminal 150 according to a modified example of the embodiment 1. In Figure 20, the area near the connection between the connection terminal 150 and the uppermost wiring layer 122 of the multilayer wiring structure 120 is shown in magnified view.

[0058] As shown in Figure 20, in the wiring board 100 according to Modified Example 1, the roughness reduction portion 122b is formed in a region of the wiring layer 122 that overlaps with the periphery of the bottom surface of the opening 131 and the center of the bottom surface of the opening 131. In other words, the roughness reduction portion 122b is formed in a region of the wiring layer 122 that overlaps with the entire bottom surface of the opening 131.

[0059] Next, a roughness reduction treatment for forming the roughness reduction portion 122b shown in Figure 20 will be described. Figure 21 is a diagram showing a modified example of the roughness reduction treatment. In the roughness reduction treatment according to the modified example, a laser is irradiated onto the area of ​​the surface of the wiring layer 122 that overlaps with the periphery of the bottom surface of the opening 131 and the center of the bottom surface of the opening 131, thereby reducing the surface roughness. In other words, a roughness reduction portion 122b is formed on the surface of the wiring layer 122 in the area that overlaps with the periphery of the bottom surface of the opening 131 and the center of the bottom surface of the opening 131, and the surface roughness becomes lower compared to the other roughened portions 122a.

[0060] The roughness reduction portion 122b is formed in the region of the surface of the wiring layer 122 that overlaps with the periphery C1 of the bottom surface of the opening 131 and the center C0 of the bottom surface of the opening 131, as shown in Figure 22, for example. Figure 22 is a diagram showing the appearance of the surface of the pad 124 when viewed from above. That is, as shown in Figure 22, for example, the pad 124 and the opening 131 have a circular shape in plan view, and the roughness reduction portion 122b is formed in a circular region that extends radially outward from the opening 131 beyond the periphery C1 of the bottom surface of the opening 131, starting from the center C0 of the bottom surface of the opening 131. The outer edge of the roughness reduction portion 122b is located radially outward from the opening 131 beyond the periphery C1 of the bottom surface of the opening 131. The diameter of the outer edge of the roughness reduction portion 122b is about 10 μm larger than the diameter of the periphery C1 of the bottom surface of the opening 131.

[0061] Thus, in the modified example 1, since the roughness reduction portion 122b is formed in an area that overlaps with the entire bottom surface of the opening 131, the precision required for aligning the opening 131 with respect to the roughness reduction portion 122b can be relaxed, and the formation of the opening 131 can be facilitated.

[0062] (Modification 2) Figure 23 is a magnified view of the area around the connection terminal 150 according to a modified example of the embodiment 2. In Figure 23, the area near the connection between the connection terminal 150 and the uppermost wiring layer 122 of the multilayer wiring structure 120 is shown in magnified view.

[0063] As shown in Figure 23, in the wiring board 100 according to the modified example 2, the connection terminal 150 may be formed as a solder bump 150A.

[0064] Next, the process of forming the connection terminal 150 as a solder bump 150A will be explained with reference to Figure 24. Figure 24 is a flowchart showing a specific example of the connection terminal formation process according to modified example 2 of the embodiment. In Figure 24, steps S201 to S204 are the same as steps S201 to S204 shown in Figure 9, so a detailed explanation will be omitted.

[0065] Once an opening 131 is formed in the solder resist layer 130 (step S204), solder balls 150B are mounted on the solder resist layer 130 at the location of the opening 131, as shown in Figure 25 (step S305). Figure 25 shows a specific example of the solder ball mounting process. The solder balls 150B are mounted by, for example, a casting method. As the solder balls 150B, for example, an alloy of tin (Sn), silver (Ag), and copper (Cu) can be used.

[0066] Once the solder ball 150B is placed, a reflow process is performed at a reflow temperature that melts the solder ball 150B (step S306). That is, the solder ball 150B is melted at a high temperature and then solidified by cooling. As a result, a solder bump 150A is formed on the pad 124, for example, as shown in Figure 26, with its upper surface protruding spherically and its base (root) contained in the opening 131. Figure 26 is a diagram showing a specific example of the reflow process.

[0067] Thus, even when the connection terminal 150 is formed as a solder bump 150A, the opening 131 has an appropriate shape, and there is little resin residue remaining near the periphery of the bottom surface of the opening 131. Therefore, the close contact between the connection terminal 150 and the wiring layer 122 is not easily hindered by resin residue. As a result, the connection terminal 150 is securely fixed to the surface of the wiring layer 122, improving the reliability of the connection between the connection terminal 150 and the wiring layer 122.

[0068] In the modified example 1, the connection terminal 150 may also be a solder bump 150A.

[0069] As described above, the wiring board according to the embodiment (for example, the wiring board 100) has a wiring layer (for example, the wiring layer 122), an insulating layer (for example, the solder resist layer 130), and an opening (for example, the opening 131). The insulating layer is laminated on the wiring layer. The opening penetrates the insulating layer to the wiring layer. The surface of the wiring layer has a first roughened portion formed in other regions excluding the region overlapping with the periphery of the bottom surface of the opening (for example, the periphery C1), and a roughness reduction portion formed in the region overlapping with the periphery of the bottom surface of the opening and having a lower surface roughness than the first roughened portion. Thereby, while maintaining the adhesion between the wiring layer and the insulating layer, an appropriate opening can be formed in the insulating layer.

Explanation of Signs

[0070] 100 Wiring board 110 Core board 111 Base material 112 Through-wiring 113,122 Wiring layer 120 Multilayer wiring structure 121 Insulating layer 122a Roughened portion 122b Roughness reduction portion 123 Via 124 Pad 125 Wiring pattern 130,140 Solder resist layer 131,141 Opening 150 Connection terminal 151 Seed layer 152 Post 170 Ball 180 Semiconductor chip

Claims

1. Wiring layer and An insulating layer laminated on the aforementioned wiring layer, The insulating layer has an opening that penetrates to the wiring layer and It has, The surface of the aforementioned wiring layer is A roughened portion formed in a region other than the region overlapping with the periphery of the bottom surface of the opening, A roughness reduction portion is formed in a region that overlaps with the periphery of the bottom surface of the opening, and has a lower surface roughness than the roughened portion. A wiring board characterized by having the following features.

2. The roughness reduction portion is, Formed in a region that overlaps with the periphery of the bottom surface of the opening and does not overlap with the center of the bottom surface of the opening. The wiring board according to feature 1.

3. The roughness reduction portion is, Formed in an annular region that extends radially inward and radially outward from the periphery of the bottom surface of the opening. The wiring board according to feature 1.

4. The roughness reduction portion is, Formed in the region where the periphery of the bottom surface of the opening and the center of the bottom surface of the opening overlap. The wiring board according to feature 1.

5. The roughness reduction portion is, Formed in a circular region that extends radially outward from the center of the bottom surface of the opening, beyond the periphery of the bottom surface of the opening. The wiring board according to feature 1.

6. The arithmetic mean roughness representing the surface roughness of the roughened portion is 300 nm or more and 600 nm or less. The arithmetic mean roughness representing the surface roughness of the roughness reduction portion is less than 300 nm. The wiring board according to feature 1.

7. The aforementioned wiring layer is pads and, The wiring pattern located around the aforementioned pad and It has, The aforementioned opening is The insulating layer penetrates to the pad, The roughened portion is, Formed on the surface of the pad, excluding the area that overlaps with the periphery of the bottom surface of the opening, and on the surface of the wiring pattern, The roughness reduction portion is, Formed on the surface of the pad in a region that overlaps with the periphery of the bottom surface of the opening. The wiring board according to feature 1.

8. Form a wiring layer, The surface of the aforementioned wiring layer is roughened, The surface roughness of a portion of the surface of the aforementioned wiring layer is reduced, An insulating layer is laminated on the aforementioned wiring layer, The process includes forming an opening in the insulating layer that penetrates to the wiring layer, The aforementioned step of lowering the level is The surface roughness of the wiring layer is reduced in the region that overlaps with the periphery of the bottom surface of the opening. A method for manufacturing a wiring board, characterized by the following:

9. The aforementioned step of lowering the level is By irradiating the surface of the wiring layer with a laser in a region that overlaps with the periphery of the bottom surface of the opening, the surface roughness of the region is reduced. The method for manufacturing a wiring board according to claim 8.

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