Novel LGA architecture to improve the reliability performance of metal definition pads

Abstract

To solve problems with the prior art.SOLUTION: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate with a die side and a land side. In an embodiment, a pad is on the land side. In an embodiment, a dielectric layer covers sidewalls of the pad, and a surface finish is over an exposed surface of the pad.SELECTED DRAWING: Figure 1A

Description

Technical Field

[0001] Embodiments of the present disclosure relate to electronic packages, and more specifically, to metal defined pads having an improved architecture for increasing reliability performance.

Background Art

[0002] With the increasing electrical performance requirements, the budget for electrical losses (e.g., insertion loss, return loss, crosstalk, etc.) is shrinking. This requires optimization of the physical connections within the package. One approach that the microelectronics industry is aiming for is the use of metal defined (MD) pads. MD pads are smaller in size compared to current solder mask defined (SMD) pads. Although the size of SMD pads can also be small, due to their architecture, a part of them is embedded under the solder mask. This reduces the active area of socket engagement. MD pads provide a middle ground for socket swipe needs and a smaller copper area for reducing electrical losses.

[0003] One of the major issues identified with the MD pad approach is cracking of the build-up film (build-up film) near the feet of the MD pads. This is an inherent problem associated with the pad design. In particular, during thermal cycling, high stresses occur at the outer edges of the MD pads within the build-up film. These high stresses can cause cracks that propagate into the build-up layer under the package substrate.

Brief Description of the Drawings

[0004] [Figure 1A] It is a plan view of a metal defined (MD) pad.

[0005] [Figure 1B] Figure 1A is a cross-sectional view of the MD pad illustrating cracks in the build-up film of the package substrate.

[0006] [Figure 2] This is a cross-sectional view of a package substrate having an MD pad having a dielectric layer on the side wall surface of the MD pad, according to one embodiment.

[0007] [Figure 3] This is a cross-sectional view of a package substrate having an MD pad having a solder resist layer on the side wall surface of the MD pad, according to one embodiment.

[0008] [Figure 4] This chart illustrates the reduction in stress near the footing of the MD pad described herein compared to an existing MD pad architecture according to one embodiment.

[0009] [Figure 5A] This is a cross-sectional view of a package substrate having a pad formed on a seed layer, according to one embodiment.

[0010] [Figure 5B] This is a cross-sectional view of a package substrate after the seed layer has been removed, according to one embodiment.

[0011] [Figure 5C] This is a cross-sectional view of a package substrate after a dielectric layer has been provided on a pad, according to one embodiment.

[0012] [Figure 5D] This is a cross-sectional view of a package substrate after the dielectric layer has been recessed to expose the surface of the pad, according to one embodiment.

[0013] [Figure 5E]A cross-sectional view of a package substrate after a solder resist is provided on a dielectric layer according to an embodiment.

[0014] [Figure 5F] A cross-sectional view of a package substrate after a surface finish is applied on the exposed surface of pads according to an embodiment.

[0015] [Figure 6A] A cross-sectional view of a package substrate having a die side and a land side, with MD pads provided on the land side according to an embodiment.

[0016] [Figure 6B] A cross-sectional view of a package substrate after a protective layer is provided on the die side of the package substrate according to an embodiment.

[0017] [Figure 6C] A cross-sectional view of a package substrate after a dielectric layer is provided on MD pads according to an embodiment.

[0018] [Figure 6D] A cross-sectional view of a package substrate after a dielectric layer is recessed to expose the surface of MD pads according to an embodiment.

[0019] [Figure 6E] A cross-sectional view of a package substrate after a protective layer is removed from the die side according to an embodiment.

[0020] [Figure 6F] A cross-sectional view of a package substrate after a solder resist layer is provided on the die side and the land side according to an embodiment.

[0021] [Figure 6G]This is a cross-sectional view of a package substrate after a solder resist opening has been formed through the land-side solder resist layer to expose an MD pad, according to one embodiment.

[0022] [Figure 6H] This is a cross-sectional view of a package substrate after a surface finish has been applied to the MD pad, according to one embodiment.

[0023] [Figure 6I] This is a cross-sectional view of a package substrate after a first level interconnect (FLI) has been formed on the die side of the package substrate, according to one embodiment.

[0024] [Figure 7A] This is a cross-sectional view of an electronic system having a package substrate with MD land-side pads bonded to a circuit board by solder balls, according to one embodiment.

[0025] [Figure 7B] This is a cross-sectional view of an electronic system having a package substrate with MD land-side pads coupled to a circuit board by a socket, according to one embodiment.

[0026] [Figure 8] This is a schematic diagram of a computing device constructed according to a certain embodiment. [Modes for carrying out the invention]

[0027] This specification describes electronic packages comprising metal-defined pads having an improved architecture that enhances reliability performance according to various embodiments. The following description uses terminology commonly used by those skilled in the art to convey the nature of their work to them. However, it will be apparent to those skilled in the art that the invention may be carried out in only some of the embodiments described. For illustrative purposes, specific numbers, materials, and configurations are given to provide a complete understanding of the exemplary implementations. However, it will be apparent to those skilled in the art that the invention may be carried out without specific details. In other examples, well-known configurations are omitted or simplified so as not to obscure the exemplary implementations.

[0028] The various operations are described sequentially as several distinct operations in the manner most useful for understanding the present invention; however, the order of description should not be interpreted as implying that these operations are necessarily order-dependent. In particular, these operations do not need to be performed in the order presented.

[0029] As mentioned above, metal-defined (MD) pads have reliability issues. In particular, the package substrate beneath the MD pad is susceptible to cracking due to stress concentration at the footing of the MD pad. An example of such an MD pad is shown in Figures 1A and 1B. Figure 1A is a plan view of an electronic package 100 having an MD pad 110. As shown, the solder resist 120 is spaced apart from the edge of the MD pad 110. That is, the portion of the package substrate 105 located below is visible in the plan view.

[0030] Referring next to Figure 1B, a cross-sectional view of the electronic package 100 of Figure 1A along line B-B' is shown. As shown, a solder resist opening 122 is provided within the solder resist 120 to expose the MD pad 110. The MD pad 110 may include surface finishes 112 on its top and sidewall surfaces. The width of the solder resist opening 122 may be wider than the width of the MD pad 110 so that a portion of the underlying package substrate 105 is exposed. The package substrate 105 may include conductive routing 108, such as pads, traces, vias, and equivalents.

[0031] Such an MD pad 110 architecture results in high stress formation in the footing of the MD pad 110 during thermal cycling. In particular, the high-stress region is adjacent to the bottom portion of the side wall of the MD pad 110. High stress poses a reliability risk to the electronic package. For example, concentrated stress leads to the formation of cracks 107 in the build-up layer located beneath the package substrate 105. The formation of cracks in the build-up layer presents a substantial reliability risk.

[0032] Accordingly, embodiments disclosed herein include MD pad architectures that minimize stress concentration in the footing of the MD pad. For example, embodiments may include providing a dielectric layer on top of a build-up layer surrounding the sidewalls of the MD pad. In alternative embodiments, the solder resist may be formed along the sidewalls of the MD pad to reduce stress. Such embodiments differ from solder mask defined pads in that the solder resist does not contact the top surface of the MD pad.

[0033] Referring next to Figure 2, a cross-sectional view of an electronic package 200 according to one embodiment is shown. In one embodiment, the electronic package 200 includes a package substrate 205. The package substrate 205 may include a dielectric build-up layer. In the illustrated embodiment, the package substrate 205 is shown as a coreless package substrate. However, it should be understood that in some embodiments, the package substrate 205 may be a cored package substrate 205. In a cored package substrate 205, the dielectric build-up layer may be provided above and below the core. In one embodiment, conductive wiring 208 is provided within the package substrate 205. The conductive wiring 208 may include pads, traces, vias, and equivalents. The conductive wiring 208 provides electrical coupling from the die side (i.e., the bottom surface in Figure 2) of the package substrate 205 to the MD pads 210 on the land side (i.e., the top surface in Figure 2) of the package substrate 205.

[0034] In one embodiment, the electronic package 200 may include one or more MD pads 210 on the land side of the package substrate 205. The MD pads 210 may be provided on top of the dielectric build-up layer of the package substrate 205. For example, the first surface 213 of the MD pad 210 may be in contact with the build-up layer of the package substrate 205 located below. In one embodiment, the MD pad 210 includes a second surface 214 facing outward from the first surface 213. A sidewall surface 215 connects the first surface 213 to the second surface 214. In one embodiment, the sidewall surface 215 and the second surface 214 are above the build-up layer of the package substrate 205. That is, the MD pad 210 is not embedded in the package substrate 205.

[0035] To minimize stress concentration at the footing of the MD pad 210 (i.e., the corner of the MD pad 210 that contacts the underlying package substrate 205), a stress-relieving dielectric layer 230 is provided along the sidewall surface 215 of the MD pad 210. In some embodiments, the stress-relieving dielectric layer 230 may be made of a different material from the build-up layer of the package substrate 205. In other embodiments, the stress-relieving dielectric layer 230 may be made of the same material as the build-up layer of the package substrate 205. The stress-relieving dielectric layer 230 may be a layer that extends over the entire top surface of the package substrate. That is, in some embodiments, the stress-relieving dielectric layer 230 is not merely localized at the edge of the MD pad 210. In some embodiments, the stress-relieving dielectric layer 230 has a thickness substantially equal to the thickness of the MD pad 210. The stress-relieving dielectric layer 230 may cover the entire height of the sidewall 215 of the MD pad 210 without covering the second surface 214 of the MD pad 210.

[0036] In one embodiment, a solder resist layer 220 may be provided on top of a stress-relaxing dielectric layer 230. The solder resist layer 220 may include solder resist openings (SROs) 222. The SROs 222 may expose the top surface of the MD pad 210. For example, the width of the SROs 222 may be greater than the width of the MD pad 210. In one embodiment, the sidewalls of the SROs 222 may be tapered, as shown in Figure 2. In another embodiment, the sidewalls of the SROs 222 may be substantially vertical.

[0037] In one embodiment, a surface finish 212 is provided on a second surface 214 of the MD pad 210. The surface finish 212 may be any suitable surface finish for microelectronic applications. For example, the surface finish 212 may consist of one or more layers. In one embodiment, the surface finish includes electroless nickel electroless palladium immersion gold (ENEPIG), but other surface finishes may also be used. In one embodiment, the surface finish 212 may have a thickness of less than about 10 μm. In a particular embodiment, the surface finish 212 may have a thickness of about 6 μm or less, or about 3 μm or less.

[0038] In one embodiment, the surface finish 212 is provided only on the second surface 214 of the MD pad 210. That is, the surface finish 212 does not cover the sidewall surface 215 of the MD pad 210, as is typical of existing MD pads as shown in Figure 1B. In one embodiment, the surface finish 212 may extend over a portion of the stress-relaxing dielectric layer 230. That is, in some embodiments, the surface finish 212 may have a width greater than the width of the MD pad 210.

[0039] A dedicated stress-relaxing dielectric layer 230 is shown in Figure 2, but it should be understood that embodiments are not limited to such configurations. For example, Figure 3 is a cross-sectional view of an electronic package 300 that utilizes a solder resist 320 as a stress-relaxing layer for the MD pad 310 instead of using a stress-relaxing dielectric layer 230.

[0040] As shown in Figure 3, the electronic package 300 includes a package substrate 305. The package substrate 305 may include a dielectric build-up layer. In the illustrated embodiment, the package substrate 305 is shown as a coreless package substrate. However, it should be understood that in some embodiments, the package substrate 305 may be a cored package substrate 305. In a cored package substrate 305, the dielectric build-up layer may be provided above and below the core. In some embodiments, conductive wiring 308 is provided within the package substrate 305. The conductive wiring 308 may include pads, traces, vias, and equivalents. The conductive wiring 308 provides electrical coupling from the die side (i.e., the bottom surface in Figure 3) of the package substrate 305 to the MD pad 310 on the land side (i.e., the top surface in Figure 3) of the package substrate 305.

[0041] In one embodiment, the electronic package 300 may include one or more MD pads 310 on the land side of the package substrate 305. The MD pads 310 may be provided on the dielectric build-up layer of the package substrate 305. For example, the first surface 313 of the MD pad 310 may be in contact with the build-up layer of the package substrate 305 located below. In one embodiment, the MD pad 310 includes a second surface 314 facing outward from the first surface 313. A sidewall surface 315 connects the first surface 313 to the second surface 314. In one embodiment, the sidewall surface 315 and the second surface 314 are above the build-up layer of the package substrate 305. That is, the MD pad 310 is not embedded in the package substrate 305.

[0042] To reduce stress at the footing of the MD pad 310 (i.e., the corner of the MD pad 310 that contacts the underlying package substrate 305), the solder resist layer 320 may be in direct contact with the sidewall 315 of the MD pad 310. Such embodiments differ from existing SMD pads in that the solder resist layer 320 does not contact the top surface of the MD pad 310. In one embodiment, the solder resist layer 320 has a thickness substantially equal to the thickness of the MD pad 310. The solder resist layer 320 may cover the entire height of the sidewall 315 of the MD pad 310 without covering the second surface 314 of the MD pad 310.

[0043] In one embodiment, the surface finish 312 is provided on the second surface 314 of the MD pad 310. The surface finish 312 may be any suitable surface finish for microelectronic applications. For example, the surface finish 312 may consist of one or more layers. In one embodiment, the surface finish includes ENEPIG, but other surface finishes may be used. In one embodiment, the surface finish 312 may have a thickness of less than about 10 μm. In a particular embodiment, the surface finish 312 may have a thickness of about 6 μm or less, or about 3 μm or less.

[0044] In one embodiment, the surface finish 312 is provided only on the second surface 314 of the MD pad 310. That is, the surface finish 312 does not cover the side wall surface 315 of the MD pad 310, as is typical of existing MD pads as shown in Figure 1B. In one embodiment, the surface finish 312 may extend over the solder resist layer 320. That is, in some embodiments, the surface finish 312 may have a width greater than the width of the MD pad 310.

[0045] Referring next to Figure 4, a chart is shown illustrating the stress near the footing of the MD pad at the interface between the surface finish (SF) and the build-up layer. The first bar illustrates the stress in a typical MD pad with a 6 μm thick surface finish, similar to the MD pad 110 shown in electronic package 100. The stress in the first bar is shown as 1. That is, the stress values ​​shown in the other bars are normalized to the stress level in the first bar. The second bar illustrates the stress at the footing of the MD pad 210 with a 6 μm thick surface finish, similar to the MD pad 210 in electronic package 200 shown in Figure 2. Compared to the first bar, the stress is reduced by only about 30% by using a dielectric stress relaxation layer. Reducing the thickness of the surface finish to about 3 μm, as shown in the third bar, reduces the stress by only about 10%. Similar reductions in stress may also be provided when using a solder resist layer as a stress relaxation layer for the MD pad, similar to the embodiment shown in Figure 3.

[0046] Referring next to Figures 5A to 5F, a series of cross-sectional views illustrating the process of forming the electronic package 500 are shown according to one embodiment. In one embodiment, the electronic package 500 of Figures 5A to 5F includes a stress-relieving dielectric layer 530 to minimize stress concentration in the footing of the MD pad 510.

[0047] Next, referring to Figure 5A, a cross-sectional view of an electronic package 500 is shown according to one embodiment. In one embodiment, the electronic package 500 includes a package substrate 505. The package substrate 505 may include a dielectric build-up layer having conductive wiring (not shown) embedded therein. The package substrate 505 may have a core or not. In one embodiment, a seed layer 509 is provided on the package substrate 505. The seed layer 509 may be used to plate an MD pad 510. The plating process may be carried out using a mask layer (not shown) on the portion of the seed layer 509 adjacent to the desired location of the MD pad 510. The MD pad 510 may be above the package substrate 505; that is, the MD pad 510 is not embedded in the package substrate 505.

[0048] Next, referring to Figure 5B, a cross-sectional view of the electronic package 500 after the seed layer 509 has been removed is shown according to one embodiment. In one embodiment, the seed layer 509 may be removed by a seed layer etching process, such as a flash etching process.

[0049] Next, referring to Figure 5C, a cross-sectional view of the electronic package 500 after the stress-relaxing dielectric layer 530 has been placed on the MD pad 510 is shown according to one embodiment. In one embodiment, the stress-relaxing dielectric layer 530 may be deposited by a lamination process or any other suitable deposition process. In one embodiment, the stress-relaxing dielectric layer 530 contains a different material from the build-up layer of the package substrate 505. In another embodiment, the stress-relaxing dielectric layer 530 may contain the same material as the build-up layer of the underlying package substrate 505.

[0050] In one embodiment, the stress-relaxing dielectric layer 530 may embed the MD pad 510. For example, the stress-relaxing dielectric layer 530 may be in direct contact with the sidewall surface 515 and the second surface 514 of the MD pad 510. The first surface 513 of the MD pad 510 may be on a package substrate 505 located below it.

[0051] Next, referring to Figure 5D, a cross-sectional view of the electronic package 500 after the stress-relaxing dielectric layer 530 has been recessed is shown according to one embodiment. In one embodiment, the stress-relaxing dielectric layer 530 is recessed by a planarization process or an equivalent process. In one embodiment, recessing the stress-relaxing dielectric layer 530 exposes the second surface 514 of the MD pad 510. That is, the sidewall surface 515 may remain covered by the stress-relaxing dielectric layer 530. In one embodiment, the thickness of the stress-relaxing dielectric layer 530 is substantially equal to the thickness of the MD pad 510.

[0052] Next, referring to Figure 5E, a cross-sectional view of the electronic package 500 after the solder resist layer 520 has been placed on the stress-relaxing dielectric layer 530 is shown according to one embodiment. In one embodiment, the solder resist layer 520 may be deposited in a lamination process. The SRO 522 may be provided through the solder resist layer 520. In one embodiment, the width of the SRO 522 may be greater than the width of the MD pad 510. Thus, a portion of the stress-relaxing dielectric layer 530 may be exposed by the SRO 522. In one embodiment, the sidewalls of the SRO 522 may be tapered or substantially vertical.

[0053] Next, referring to Figure 5F, a cross-sectional view of the electronic package 500 after the surface finish 512 has been provided on the MD pad 510 is shown according to one embodiment. In one embodiment, the surface finish 512 may include any material (or a combination of materials) common to surface finishes for interconnection in microelectronic applications. For example, the surface finish 512 may include ENEPIG or an equivalent. In one embodiment, the thickness of the surface finish 512 may be about 10 μm or less. In a particular embodiment, the surface finish 512 may be about 6 μm or less or about 3 μm or less.

[0054] In one embodiment, the surface finish 512 is provided on the second surface 514 of the MD pad 510. The stress-relaxing dielectric layer 530 protects the sidewall surface 515 and blocks the deposition of the surface finish 512. That is, only the second surface 514 of the MD pad 510 is covered by the surface finish 512. In one embodiment, the width of the surface finish 512 may be greater than the width of the MD pad 510. Thus, portions of the surface finish 512 may come into contact with the top surface of the stress-relaxing dielectric layer 530.

[0055] Next, referring to Figures 6A to 6I, a series of cross-sectional views illustrating the process flow for forming the electronic package 600 are shown according to one embodiment. In one embodiment, the electronic package 600 includes a stress-relaxing dielectric layer 630 on the sidewall surface of the MD pad 610.

[0056] Next, referring to Figure 6A, a cross-sectional view of the electronic package 600 is shown according to one embodiment. In one embodiment, the electronic package 600 includes a package substrate 605. The package substrate 605 includes a core 603 and has dielectric wiring layers 602 (dielectric routing layers) above and below the core 603. Conductive wiring 608 is provided within the wiring layers 602, and through-core vias 641 are provided through the core 603. The package substrate 605 may include a die side 606 and a land side 607. In one embodiment, an MD pad 610 is provided on the land side 607.

[0057] Next, referring to Figure 6B, a cross-sectional view of the electronic package 600 after a protective layer 640 has been formed on the die side 606 of the package substrate 605 is shown according to one embodiment. The protective layer 640 may be formed by a lamination process or an equivalent process.

[0058] Next, referring to Figure 6C, a cross-sectional view of the electronic package 600 after the stress-relaxing dielectric layer 630 has been provided on the land side 607 is shown according to one embodiment. According to one embodiment, the stress-relaxing dielectric layer 630 is formed on the MD pad 610. The stress-relaxing dielectric layer 630 may be made of the same material as the dielectric wiring layer 602. In other embodiments, the stress-relaxing dielectric layer 630 contains a different material from the dielectric wiring layer 602.

[0059] Next, referring to Figure 6D, a cross-sectional view of the electronic package 600 after the stress-relaxing dielectric layer 630 has been recessed is shown according to one embodiment. Recessing the stress-relaxing dielectric layer 630 may expose the surface 614 of the MD pad 610. The sidewall surface of the MD pad 610 may remain covered by the stress-relaxing dielectric layer 630. In one embodiment, the thickness of the stress-relaxing dielectric layer is substantially similar to the thickness of the MD pad 610.

[0060] Next, referring to Figure 6E, a cross-sectional view of the electronic package 600 after the protective layer 640 has been removed from the die side 606 is shown according to one embodiment. The protective layer 640 may be removed by a peeling process or any other suitable process.

[0061] Next, referring to Figure 6F, a cross-sectional view of the electronic package 600 after the solder resist layer 620 has been provided on the die side 606 and the land side 607 is shown according to one embodiment. In one embodiment, the solder resist layer 620 may be deposited by a lamination process or an equivalent process.

[0062] Next, referring to Figure 6G, a cross-sectional view of the electronic package 600 after the SRO622 has been formed through the solder resist layer 620 on the land side 607 is shown according to one embodiment. In one embodiment, the SRO622 may have a width greater than the width of the MD pad 610. Thus, the surface 614 of the MD pad 610 and a portion of the stress relaxation dielectric layer 630 are exposed by the SRO622.

[0063] Next, referring to Figure 6H, a cross-sectional view of the electronic package after the surface finish 612 has been applied to the MD pad 610 is shown according to one embodiment. In one embodiment, the surface finish 612 may comprise any or a selection of materials typical for surface finishes in microelectronic applications, such as ENEPIG or equivalent. In one embodiment, the surface finish 612 covers the surface 614 of the MD pad 610. The portion of the surface finish 612 may also cover a portion of the stress-relaxing dielectric layer 630.

[0064] Next, referring to Figure 6I, a cross-sectional view of an electronic package after a first-level interconnect (FLIS) 651 has been formed on the die side 606 of the package substrate 605 is shown according to one embodiment. The FLI 651 may include a pad having a surface finish 652. A via-through solder resist layer 620 may be coupled to conductive wiring 608 located beneath the FLI 651.

[0065] Next, referring to Figure 7A, a cross-sectional view of the electronic system 790 is shown according to one embodiment. In one embodiment, the electronic system may include a substrate 791, such as a printed circuit board or equivalent. In one embodiment, the substrate 791 is coupled to a package substrate 705 by an interconnect 792, such as a solder ball. The interconnect 792 may pass through a solder resist layer 720 and contact an MD pad 710 on the package substrate 705. The MD pad 710 may have sidewalls that directly contact a stress-relaxing dielectric layer 730. In one embodiment, a die 781 is coupled to the die side of the package substrate 705 by an FLI 782.

[0066] Next, referring to Figure 7B, a cross-sectional view of the electronic system 790 is shown according to one embodiment. The electronic system 790 in Figure 7B may be substantially similar to the electronic system 790 in Figure 7A, except for the interconnect between the package substrate 705 and the circuit board 791. Instead of solder ball interconnects, a socket architecture may be used. The socket architecture may include pins 786 passing through a socket housing 785. The bottom of pins 786 (located at the bottom of the socket housing 785) may be coupled to the substrate by a solder interconnect 792.

[0067] Figure 8 illustrates a computing device 800 according to one implementation of the present invention. The computing device 800 houses a circuit board 802. The circuit board 802 includes, but is not limited to, a processor 804 and at least one communication chip 806, and may include a number of other components. The processor 804 is physically and electrically coupled to the circuit board 802. In some implementations, at least one communication chip 806 is also physically and electrically coupled to the circuit board 802. In further implementations, the communication chip 806 is part of the processor 804.

[0068] These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touchscreen displays, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, Global Positioning System (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (such as hard disk drives, compact discs (CDs), and digital versatile discs (DVDs)).

[0069] The communication chip 806 enables wireless communication for transferring data to and from the computing device 800. The term “wireless” and its derivatives are sometimes used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the devices concerned are wire-free, but in some embodiments they may be wire-free. The communication chip 806 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long-Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth®, their derivatives, and any other wireless protocols designated as 3G, 4G, 5G and beyond. The computing device 800 may include multiple communication chips 806. For example, the first communication chip 806 may be dedicated to shorter-range wireless communication such as Wi-Fi and Bluetooth, and the second communication chip 806 may be dedicated to longer-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, and Ev-DO.

[0070] The processor 804 of the computing device 800 includes an integrated circuit die packaged within the processor 804. In some implementations of the present invention, the integrated circuit die of the processor may be part of an electronic package including a package substrate having MD land-side pads having a stress-relaxation configuration, according to embodiments described herein. The term “processor” may refer to a device or part of a device that processes electronic data from registers and / or memory and converts it into other electronic data that may be stored in registers and / or memory.

[0071] The communication chip 806 also includes an integrated circuit die packaged within the communication chip 806. According to another embodiment of the present invention, the integrated circuit die of the communication chip may be part of an electronic package including a package substrate having MD land-side pads having a stress-relaxation configuration, in accordance with the embodiments described herein.

[0072] The above description of exemplary implementations of the Invention, including those described in the abstract, is not intended to be exhaustive or to limit the Invention to the exact form of disclosure. Specific implementations of the Invention and examples relating to the Invention are described herein for illustrative purposes, but various equivalent modifications are possible within the scope of the Invention, as will be understood by those skilled in the art.

[0073] These modifications may be made to the invention in light of the detailed description above. The terms used in the following claims should not be construed as limiting the invention to any specific implementation disclosed in the specification and claims. Rather, the scope of the invention should be entirely determined by the subsequent claims, which should be interpreted in accordance with established principles of claim interpretation.

[0074] Example 1: An electronic package comprising a package substrate having a die side and a land side, a pad on the land side, a dielectric layer covering the sidewall of the pad, and a surface finish on the exposed surface of the pad.

[0075] Example 2: The electronic package in Example 1, where the dielectric layer is made of a different material than the layers of the package substrate.

[0076] Example 3: An electronic package of Example 1 or 2, where the dielectric layer is solder resist.

[0077] Example 4: An electronic package like Example 3, in which the solder resist does not cover any portion of the top surface of the pads facing outward from the package substrate.

[0078] Example 5: The surface finish extends over the top surface of the dielectric layer, one of the electronic packages from Examples 1-4.

[0079] Example 6: An electronic package from any one of Examples 1-5, further comprising a solder resist on top of a dielectric layer.

[0080] Example 7: An electronic package of Example 6 in which the opening through the solder resist that exposes the top surface of the pad is wider than the pad.

[0081] Example 8: The electronic package in Example 7, where the pad is a metal-defined pad.

[0082] Example 9: An electronic package from any one of Examples 1 to 8, further including a die that is mounted on the die side of the package substrate.

[0083] Example 10: An electronic package from any one of Examples 1-9, in which the die is coupled to a pad by conductive routing through the thickness of the package substrate.

[0084] Example 11: A method for forming an electronic package, comprising forming a pad on the land side of a package substrate, placing a dielectric layer on the pad, and recessing the dielectric layer to expose the surface of the pad, wherein the dielectric layer remains on the side wall surface of the pad.

[0085] Example 12: The method of Example 11, further comprising placing a solder resist on the pad and a dielectric layer, wherein an opening through the dielectric layer exposes the surface of the pad.

[0086] Example 13: The method of Example 12, where the width of the opening through the dielectric layer is wider than the width of the pad.

[0087] Example 14: The method of Example 13, further comprising placing a surface finish on top of the surface of the pad.

[0088] Example 15: Surface finishing is performed by the method of Example 14, extending over the dielectric layer.

[0089] Example 16: The dielectric layer is solder resist, one of the methods from Examples 11-15.

[0090] Example 17: The method of Example 16, further comprising placing a surface finish on top of the surface of the pad.

[0091] Example 18: One of the methods from Examples 11-17, in which the die side of the package substrate is covered with a protective film during the operation of indenting the dielectric layer.

[0092] Example 19: Any one of Examples 11-18, further comprising forming first level interconnects on the die side of the package substrate after exposing the surface of the pad.

[0093] Example 20: A land-side interconnect of a package substrate, comprising: a pad located on the land side of the package substrate, having a first surface connected to a via, a second surface opposite to the first surface, and a sidewall surface connecting the first surface to the second surface; and a dielectric layer located on the land side of the package substrate, in direct contact with the sidewall surface of the pad, wherein the dielectric layer does not contact the second surface of the pad.

[0094] Example 21: Land-side interconnect of Example 20, further including a solder resist layer on top of the dielectric layer.

[0095] Example 22: The land-side interconnect of Example 21, in which an opening through the solder resist layer exposes the second surface of the pad, and the solder resist layer does not come into contact with the second surface of the pad.

[0096] Example 23: A land-side interconnect from any one of Examples 20-22, further including a surface finish on the second surface of the pad.

[0097] Example 24: An electronic system comprising a circuit board, a package substrate coupled to the circuit board, land-side interconnects on the package substrate, and a die coupled to the die side of the package substrate, wherein each land-side interconnect of the land-side interconnect is a pad located on the land side of the package substrate, having a first surface connected to a via, a second surface opposite to the first surface, and a sidewall surface connecting the first surface to the second surface, and a dielectric layer located on the land side of the package substrate and in direct contact with the sidewall surface of the pad, the dielectric layer not in contact with the second surface of the pad.

[0098] Example 25: The electronic system of Example 24, further comprising a solder resist on the dielectric layer, wherein the solder resist does not come into contact with the second surface of the pad.

Claims

1. A package substrate having a die side and a land side, The pad located on the aforementioned land side, A dielectric layer covering the side wall of the pad, comprising a dielectric layer having a top surface at the same level as the top surface of the pad, A surface finish, which is located on the top surface of the pad and extends on the top surface of the dielectric layer, Electronic packaging.

2. The electronic package according to claim 1, wherein the dielectric layer is made of a different material from the layer of the package substrate.

3. The electronic package according to claim 1 or 2, wherein the dielectric layer is a solder resist.

4. The electronic package according to claim 3, wherein the solder resist does not cover any portion of the top surface of the pads that faces outward when viewed from the package substrate.

5. The electronic package according to claim 1 or 2, further comprising a solder resist on the dielectric layer.

6. The electronic package according to claim 5, wherein the opening through the solder resist that exposes the top surface of the pad is wider than the pad.

7. The electronic package according to claim 6, wherein the pad is a metal defining pad.

8. The electronic package according to any one of claims 1 to 7, further comprising a die attached to the die side of the package substrate.

9. The electronic package according to any one of claims 1 to 8, wherein the die is bonded to the pad by conductive wiring through the thickness of the package substrate.

10. A method for forming an electronic package, Forming pads on the land side of the package substrate, Placing a dielectric layer on the aforementioned pad, The dielectric layer is recessed to expose the top surface of the pad, wherein the dielectric layer remains on the side wall surface of the pad and the dielectric layer has a top surface that is at the same level as the top surface of the pad. This includes forming a surface finish that is located on the top surface of the pad and extends on the top surface of the dielectric layer, method.

11. The method according to claim 10, further comprising arranging a solder resist on the pad and the dielectric layer, wherein an opening through the dielectric layer exposes the top surface of the pad.

12. The method according to claim 11, wherein the width of the opening through the dielectric layer is wider than the width of the pad.

13. The method according to claim 10, wherein the dielectric layer is a solder resist.

14. The method according to any one of claims 10 to 13, wherein the die side of the package substrate is covered with a protective film.

15. The method according to any one of claims 10 to 14, further comprising forming a first level interconnect on the die side of the package substrate after exposing the top surface of the pad.

16. The land-side interconnect of the package substrate, A pad located on the land side of the package substrate, having a first surface connected to a via, a second surface opposite to the first surface, and a side wall surface connecting the first surface to the second surface, A dielectric layer that is in direct contact with the side wall surface of the pad, is located on the land side of the package substrate, and does not contact the second surface of the pad, and has a top surface at the same level as the second surface of the pad, A surface finish, which is located on the second surface of the pad and extends over the top surface of the dielectric layer, Land-side interconnect.

17. The land-side interconnect according to claim 16, further comprising a solder resist layer on the dielectric layer.

18. The land-side interconnect according to claim 17, wherein the opening through the solder resist layer exposes the second surface of the pad, and the solder resist layer does not come into contact with the second surface of the pad.

19. Circuit board and A package substrate coupled to the circuit board, The land-side interconnect on the aforementioned package substrate, The package substrate includes a die coupled to the die side, Each of the aforementioned land-side interconnects is: A pad located on the land side of the package substrate, having a first surface connected to a via, a second surface opposite to the first surface, and a side wall surface connecting the first surface to the second surface, A dielectric layer that is in direct contact with the side wall surface of the pad, is located on the land side of the package substrate, and does not contact the second surface of the pad, and has a top surface at the same level as the second surface of the pad, A surface finish, which is located on the second surface of the pad and extends over the top surface of the dielectric layer, Electronic systems.

20. The electronic system according to claim 19, further comprising a solder resist on the dielectric layer, wherein the solder resist does not come into contact with the second surface of the pad.

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