Semiconductor memory element

Abstract

The present invention provides a semiconductor memory element that performs bidirectional driving with improved integration density and operational performance. [Solution] The semiconductor memory element 1 includes a lower peripheral circuit structure DPST, an upper peripheral circuit structure UPST, and a memory cell structure CST that are superimposed on each other in the vertical direction. The lower peripheral circuit structure includes a lower semiconductor substrate PSUBD and a plurality of lower transistors disposed on the substrate, and the upper peripheral circuit structure includes an upper semiconductor substrate PSUBU and a plurality of upper transistors disposed on the substrate. The memory cell structure includes a plurality of word lines WL extending in a first horizontal direction, a plurality of bit lines BL extending in a second horizontal direction different from the first horizontal direction, and a plurality of selectors SLT interposed between the plurality of word lines and the plurality of bit lines to constitute a plurality of memory cells. Each of the plurality of word lines / bit lines is electrically connected to a corresponding transistor among the plurality of lower transistors or the plurality of upper transistors.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device, and more specifically, to a semiconductor memory device that performs bidirectional driving.

Background Art

[0002] As miniaturization, multifunctionality, and high performance of electronic products are required, a large-capacity semiconductor memory device is demanded, and in order to provide a large-capacity semiconductor memory device, an improved integration degree is required. Since a conventional semiconductor memory device includes a memory cell composed of an information storage element and a selector, the integration degree of the semiconductor memory device has been improved, but is still limited. Accordingly, a semiconductor memory device that performs bidirectional driving and has a simple memory cell structure has been proposed.

Summary of the Invention

Problems to be Solved by the Invention

[0003] An object of the present invention is to provide a semiconductor memory device that performs bidirectional driving with an improved integration degree and improved operating performance.

Means for Solving the Problems

[0004] A semiconductor memory element according to one aspect of the present invention made to achieve the above objective includes a lower peripheral circuit structure, an upper peripheral circuit structure, a memory cell structure, and a plurality of vertical through electrodes electrically connecting the lower peripheral circuit structure and the upper peripheral circuit structure, wherein the lower peripheral circuit structure, the upper peripheral circuit structure and the memory cell structure are superimposed on each other in the vertical direction, and the memory cell structure includes a plurality of word lines extended in a first horizontal direction, a plurality of bit lines extended in a second horizontal direction different from the first horizontal direction, and a plurality of selectors interposed between the plurality of word lines and the plurality of bit lines to constitute a plurality of memory cells, and the lower peripheral circuit structure is a lower semiconductor The upper peripheral circuit structure includes a substrate and a plurality of lower transistors arranged on the lower semiconductor substrate, and each of the plurality of word lines is electrically connected to a corresponding upper transistor from the plurality of upper transistors, with at least a portion of the lower transistors overlapping in the vertical direction, and each of the plurality of bit lines is electrically connected to another lower transistor from the plurality of lower transistors, with at least a portion of the lower transistors overlapping in the vertical direction, with the corresponding upper transistor from the plurality of upper transistors.

[0005] To achieve the above objective, a semiconductor memory element according to another aspect of the present invention includes a lower semiconductor substrate, a plurality of lower local word line selection transistors and a plurality of lower local bit line selection transistors, wherein the plurality of lower local word line selection transistors and the plurality of lower local bit line selection transistors are arranged on the lower semiconductor substrate, and an upper peripheral circuit structure on the lower peripheral circuit structure includes an upper semiconductor substrate, a plurality of upper local word line selection transistors and a plurality of upper local bit line selection transistors, wherein the plurality of upper local word line selection transistors and the plurality of upper local bit line selection transistors are arranged on the upper semiconductor substrate, and a plurality of word lines extended in a first horizontal direction, a plurality of bit lines extended in a second horizontal direction different from the first horizontal direction from a vertical level different from the plurality of word lines, and a plurality of memory cells interposed between the plurality of word lines and the plurality of bit lines. A memory cell structure comprising a plurality of selectors constituting a plurality of word lines, a plurality of bit lines, and an interlayer insulating layer covering the plurality of memory cells; a lower wiring structure comprising a lower cover insulating layer and a plurality of lower contact plugs penetrating the lower cover insulating layer and electrically connected to the lower peripheral circuit structure below the lower peripheral circuit structure; an upper wiring structure comprising an upper cover insulating layer and a plurality of upper contact plugs penetrating the upper cover insulating layer and electrically connected to the upper peripheral circuit structure above the memory cell structure; and a plurality of vertical through electrodes electrically connecting the lower peripheral circuit structure and the upper peripheral circuit structure, wherein each of the plurality of word lines is electrically connected to one lower local word line selector transistor from the plurality of lower local word line selector transistors that overlap at least a portion of the upper local word line selector transistors in the vertical direction and to a corresponding upper local word line selector transistor from the plurality of upper local word line selector transistors, and each of the plurality of bit lines,It is electrically connected to one of the multiple lower local bit line selection transistors, at least a portion of which are superimposed in the vertical direction, and to the corresponding upper local bit line selection transistor among the multiple upper local bit line selection transistors.

[0006] A semiconductor memory element according to yet another aspect of the present invention, made to achieve the above objective, comprises a lower peripheral circuit structure including a lower semiconductor substrate, a plurality of lower local word line selection transistors and a plurality of lower local bit line selection transistors disposed on the lower semiconductor substrate, a plurality of lower wiring lines, a plurality of lower wiring contacts electrically connecting the plurality of lower wiring lines to the plurality of lower local word line selection transistors and the plurality of lower local bit line selection transistors, and a lower wiring insulating layer covering the plurality of lower wiring lines and the plurality of lower wiring contacts, and an upper peripheral circuit on the lower peripheral circuit structure including an upper semiconductor substrate, a plurality of upper local word line selection transistors and a plurality of upper local bit line selection transistors disposed on the upper semiconductor substrate, a plurality of upper wiring lines, a plurality of upper wiring contacts electrically connecting the plurality of upper wiring lines to the plurality of upper local word line selection transistors and the plurality of upper local bit line selection transistors, and an upper wiring insulating layer covering the plurality of upper wiring lines and the plurality of upper wiring contacts. A memory cell structure comprising a path structure, a plurality of word lines extending in a first horizontal direction on the upper peripheral circuit structure, a plurality of bit lines extending in a second horizontal direction different from the first horizontal direction on the plurality of word lines, a plurality of selectors interposed between the plurality of word lines and the plurality of bit lines, each including a selection material layer, a first selection electrode layer interposed between the selection material layer and each of the plurality of bit lines, and a second selection electrode layer interposed between each of the plurality of word lines and the selection material layer, a plurality of word line contacts connecting the plurality of word lines and the plurality of upper wiring lines, a plurality of bit line contacts connecting the plurality of bit lines and the plurality of upper wiring lines, and an interlayer insulating layer covering the plurality of word line contacts, the plurality of bit line contacts, the plurality of word lines, the plurality of bit lines, and the plurality of selectors, and a lower wiring structure comprising a lower cover insulating layer and a plurality of lower contact plugs penetrating the lower cover insulating layer and electrically connected to the plurality of lower wiring lines,The memory cell structure includes an upper wiring structure comprising an upper cover insulating layer and a plurality of upper contact plugs penetrating the upper cover insulating layer and electrically connected to the plurality of upper wiring lines, and a plurality of vertical through electrodes penetrating the lower wiring insulating layer, the lower semiconductor substrate, the upper semiconductor substrate, and the upper wiring insulating layer and connecting the plurality of lower wiring lines and the plurality of upper wiring lines, wherein each of the plurality of word lines is electrically connected to one lower local word line selection transistor from the plurality of lower local word line selection transistors which overlap at least a portion in the vertical direction and to a corresponding upper local word line selection transistor from the plurality of upper local word line selection transistors, and each of the plurality of bit lines is electrically connected to one lower local bit line selection transistor from the plurality of lower local bit line selection transistors which overlap at least a portion in the vertical direction and to a corresponding upper local bit line selection transistor from the plurality of upper local bit line selection transistors. [Effects of the Invention]

[0007] In the semiconductor memory element according to the present invention, an upper peripheral circuit structure including a plurality of upper transistors is arranged on a lower peripheral circuit structure including a plurality of lower transistors and superimposed vertically, so the area is reduced or the integration density of semiconductor memory elements within the same area is improved. Furthermore, since the upper and lower transistors connected to a single line, for example, a single word line or a single bit line, are electrically connected via through electrodes, the electrical path between the upper and lower transistors is shortened, and the operating performance of the semiconductor memory element is improved.

[0008] Furthermore, in the semiconductor memory element according to the present invention, power is supplied to multiple upper transistors via multiple upper contact plugs, and power is supplied to multiple lower transistors via multiple lower contact plugs. This simplifies the arrangement of wiring included in the semiconductor memory element, improves the integration density of the semiconductor memory element, and enhances its operating performance. [Brief explanation of the drawing]

[0009] [Figure 1] This is an equivalent circuit diagram illustrating a semiconductor memory element according to one embodiment of the present invention. [Figure 2A] This is a conceptual diagram illustrating a semiconductor memory element based on one embodiment of the present invention. [Figure 2B] This is a conceptual diagram illustrating a semiconductor memory element based on one embodiment of the present invention. [Figure 3] This is a cross-sectional view of a semiconductor memory element according to one embodiment of the present invention. [Figure 4A] This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to one embodiment of the present invention. [Figure 4B] This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to one embodiment of the present invention. [Figure 4C] This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to one embodiment of the present invention. [Figure 4D] This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to one embodiment of the present invention. [Figure 4E] This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to one embodiment of the present invention. [Figure 4F] This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to one embodiment of the present invention. [Figure 5] This is a cross-sectional view of a semiconductor memory element according to one embodiment of the present invention. [Figure 6] This is a cross-sectional view of a semiconductor memory element according to one embodiment of the present invention. [Figure 7] This is a cross-sectional view of a semiconductor memory element according to one embodiment of the present invention. [Figure 8] It is a conceptual diagram for explaining a semiconductor memory device according to an embodiment of the present invention. [Figure 9A] It is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention. [Figure 9B] It is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention. [Figure 10A] It is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention. [Figure 10B] It is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention. [Figure 11A] It is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention. [Figure 11B] It is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention. [Figure 12A] It is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention. [Figure 12B] It is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention.

Mode for Carrying Out the Invention

[0010] FIG. 1 is an equivalent circuit diagram for explaining a semiconductor memory device according to an embodiment of the present invention.

[0011] Referring to FIG. 1, the semiconductor memory device 1 includes a memory cell structure CST, an upper peripheral circuit structure UPST, and a lower peripheral circuit structure DPST stacked in the vertical direction (Z direction). The upper peripheral circuit structure UPST is disposed on the lower peripheral circuit structure DPST. The memory cell structure CST is disposed on the upper peripheral circuit structure UPST, but is not limited thereto. In some embodiments, the memory cell structure CST may be disposed on the lower peripheral circuit structure DPST and the upper peripheral circuit structure UPST. In some embodiments, the memory cell structure CST may be disposed between the lower peripheral circuit structure DPST and the upper peripheral circuit structure UPST. In some embodiments, the memory cell structure CST may include a first memory cell structure CST1 and a second memory cell structure CST2 disposed on the first memory cell structure CST1, as shown in FIGS. 11A to 12B. In some embodiments, the first memory cell structure CST1 may be disposed under the lower peripheral circuit structure DPST, and the second memory cell structure CST2 may be disposed on the upper peripheral circuit structure UPST. For example, the lower peripheral circuit structure DPST and the upper peripheral circuit structure UPST may be interposed between the first memory cell structure CST1 and the second memory cell structure CST2. In some embodiments, the first memory cell structure CST1 may be disposed on the lower peripheral circuit structure DPST, and the second memory cell structure CST2 may be disposed on the upper peripheral circuit structure UPST.

[0012] The lower peripheral circuit structure DPST includes a plurality of lower transistors, and the upper peripheral circuit structure UPST includes a plurality of upper transistors. The plurality of lower transistors and the plurality of upper transistors are driven in opposite directions (reverse directions). The plurality of lower transistors include a lower local word line selection transistor LX-R and a lower local bit line selection transistor LY-R, and the plurality of upper transistors include an upper local word line selection transistor LX-F and an upper local bit line selection transistor LY-F.

[0013] The memory cell structure CST includes multiple word lines WL, multiple bit lines BL, and multiple memory cells MC interposed between the multiple word lines WL and the multiple bit lines BL. Multiple local word line selection transistors LX are connected to the multiple word lines WL, and multiple local bit line selection transistors LY are connected to the multiple bit lines BL. Each of the multiple local word line selection transistors LX includes an upper local word line selection transistor LX-F and a lower local word line selection transistor LX-R, and each of the multiple local bit line selection transistors LY includes an upper local bit line selection transistor LY-F and a lower local bit line selection transistor LY-R.

[0014] The lower peripheral circuit structure DPST and the upper peripheral circuit structure UPST are electrically connected by multiple vertical through-electrode (TSV) connections. For example, the lower local word line selection transistor LX-R and the upper local word line selection transistor LX-F, both connected to one word line WL, are electrically connected by a vertical through-electrode (TSV). For example, the lower local bit line selection transistor LY-R and the upper local bit line selection transistor LY-F, both connected to one bit line BL, are electrically connected via a vertical through-electrode (TSV).

[0015] One word line WL is connected to one lower local word line selection transistor LX-R and one upper local word line selection transistor LX-F, and one bit line BL is connected to one lower local bit line selection transistor LY-R and one upper local bit line selection transistor LY-F. In some embodiments, the lower local word line selection transistor LX-R and upper local word line selection transistor LX-F connected to one word line WL are at least partially superimposed in the vertical direction (Z direction). In some embodiments, the lower local bit line selection transistor LY-R and upper local bit line selection transistor LY-F connected to one bit line BL are at least partially superimposed in the vertical direction (Z direction). The lower local word line selection transistor LX-R and upper local word line selection transistor LX-F provide forward and reverse local word line selection signals to the word line WL, and the lower local bit line selection transistor LY-R and upper local bit line selection transistor LY-F provide forward and reverse local bit line selection signals to the bit line BL.

[0016] Multiple word lines WL extend in a first horizontal direction (X direction) and are separated from each other in a second horizontal direction (Y direction), which is different from the first horizontal direction (X direction). The first horizontal direction (X direction) and the second horizontal direction (Y direction) are orthogonal to each other. In some embodiments, multiple word lines WL are arranged at equal intervals and separated from each other in the second horizontal direction (Y direction). Multiple bit lines BL extend in a second horizontal direction (Y direction) and are separated from each other in the first horizontal direction (X direction). In some embodiments, multiple bit lines BL are arranged at equal intervals and separated from each other in the first horizontal direction (X direction). In some embodiments, multiple bit lines BL are arranged on multiple word lines WL. Multiple memory cells MC are interposed between multiple bit lines BL and multiple word lines WL that intersect in the vertical direction (Z direction). For example, multiple memory cells MC are arranged in a matrix in a planar manner.

[0017] In some embodiments, each of the multiple memory cells MC is composed of a selector (SLT in Figure 3). For example, semiconductor memory element 1 is a Selector-Only Memory (SOM) or Self-Selecting Memory (SSM). In some embodiments, the selector (SLT in Figure 3) includes a first selection electrode layer, a selection material layer, and a second selection electrode layer. The first selection electrode layer is interposed between the bit line BL and the selection material layer, and the second selection electrode layer is interposed between the word line WL and the selection material layer. Each of the multiple memory cells MC stores data by distinguishing between "0" and "1" using a threshold voltage that changes according to bidirectional write operation. Each of the multiple memory cells MC is interposed between the bit line BL and the word line WL and can be driven bidirectionally by lower local word line selection transistors LX-R and upper local word line selection transistors LX-F connected to the word line WL, and lower local bit line selection transistors LY-R and upper local bit line selection transistors LY-F connected to the bit line BL. For example, the lower local word line selection transistor LX-R and the upper local word line selection transistor LX-F, which are connected to the word line WL, are driven in opposite directions to each other, and the lower local bit line selection transistor LY-R and the upper local bit line selection transistor LY-F, which are connected to the bit line BL, are driven in opposite directions to each other.

[0018] In the following, even if coordinate axes are not shown in the drawings, unless otherwise specified, the extension direction of the word line WL is the first horizontal direction (X direction), and the extension direction of the bit line BL is the second horizontal direction (Y direction). Furthermore, the arrangement of the multiple local word line selection transistors LX, including the lower local word line selection transistor LX-R and the upper local word line selection transistor LX-F, respectively, and the multiple local bit line selection transistors LY, including the lower local bit line selection transistor LY-R and the upper local bit line selection transistor LY-F, respectively, as shown in the drawings, indicates only arrangement in the vertical direction (Z direction), and does not limit arrangement in the horizontal direction, for example, the first horizontal direction (X direction) and / or the second horizontal direction (Y direction). For example, Figures 2A and 2B respectively illustrate planar arrangements of multiple local word line selection transistors LX, each including a lower local word line selection transistor LX-R and an upper local word line selection transistor LX-F, and multiple local bit line selection transistors LY, each including a lower local bit line selection transistor LY-R and an upper local bit line selection transistor LY-F. However, for example, the lower local word line selection transistor LX-R, upper local word line selection transistor LX-F, lower local bit line selection transistor LY-R, and upper local bit line selection transistor LY-F shown in Figures 1 and 3 only show arrangements in the vertical direction (Z direction) and do not limit arrangements in the first horizontal direction (X direction) and / or second horizontal direction (Y direction).

[0019] In the semiconductor memory element 1 according to the present invention, for bidirectional driving of each of the multiple memory cells MC, the lower local word line selection transistor LX-R and the upper local word line selection transistor LX-F are connected to the word line WL, and the lower local bit line selection transistor LY-R and the upper local bit line selection transistor LY-F are connected to the bit line BL. The upper peripheral circuit structure UPST, which includes the upper local word line selection transistor LX-F and the upper local bit line selection transistor LY-F, is arranged on the lower peripheral circuit structure DPST, which includes the lower local word line selection transistor LX-R and the lower local bit line selection transistor LY-R, so that the area of ​​the semiconductor memory element 1 is reduced or the integration density within the same area is improved. Furthermore, the lower local word line selection transistor LX-R and the upper local word line selection transistor LX-F, and the lower local bit line selection transistor LY-R and the upper local bit line selection transistor LY-F are electrically connected via multiple vertical through-electrodes TSV, so that the electrical path between them is shortened and the operating performance of the semiconductor memory element 1 is improved.

[0020] Figures 2A and 2B are conceptual diagrams illustrating a semiconductor memory element according to one embodiment of the present invention.

[0021] Referring to both Figures 2A and 2B, the semiconductor memory element 1 includes a region where multiple local word line selection transistors LX are arranged and a region where multiple local bit line selection transistors LY are arranged. Each of the regions where multiple local word line selection transistors LX are arranged and the region where multiple local bit line selection transistors LY are arranged is called a tile. The regions where multiple local word line selection transistors LX are arranged and the region where multiple local bit line selection transistors LY are arranged are arranged alternately along the first horizontal direction (X direction) and the second horizontal direction (Y direction), respectively. In some embodiments, each of the regions where multiple local word line selection transistors LX are arranged in a planar manner has a rectangular shape with a major axis in the first horizontal direction (X direction) and a minor axis in the second horizontal direction (Y direction). For example, each of the regions where multiple local word line selection transistors LX are arranged in a planar manner has a rectangular shape with a major axis in the first horizontal direction (X direction), which is the extension direction of the word line (WL in Figure 1). In some embodiments, each region in which multiple local bit line selection transistors LY are arranged in a planar manner has a rectangular shape with a major axis in the second horizontal direction (Y direction) and a minor axis in the first horizontal direction (X direction). For example, each region in which multiple local bit line selection transistors LY are arranged has a rectangular shape with a major axis in the second horizontal direction (Y direction), which is the extension direction of the bit line (BL in Figure 1).

[0022] Multiple vertical through-electrode (TSV) components are arranged to surround the region where multiple local word line selection transistors (LX) are located and the region where multiple local bit line selection transistors (LY) are located. For example, some of the multiple vertical through-electrode (TSV) components are arranged in a row along the first direction (X direction), and other components are arranged in a row along the second horizontal direction (Y direction).

[0023] Each region where multiple local word line selection transistors LX are located includes a region where an upper local word line selection transistor LX-F is located and a region where a lower local word line selection transistor LX-R is located. The regions where the upper local word line selection transistor LX-F and the lower local word line selection transistor LX-R are located, contained within each region where multiple local word line selection transistors LX are located, overlap each other in the vertical direction (Z direction). Each region where multiple local bit line selection transistors LY are located includes a region where an upper local bit line selection transistor LY-F is located and a region where a lower local bit line selection transistor LY-R is located. The regions where the upper local bit line selection transistor LY-F and the lower local bit line selection transistor LY-R are located, contained within each region where multiple local bit line selection transistors LY are located, overlap each other in the vertical direction (Z direction).

[0024] The semiconductor memory element 1 includes an upper peripheral circuit structure UPST and a lower peripheral circuit structure DPST. The region where the upper local word line selection transistor LX-F and the region where the upper local bit line selection transistor LY-F are located are located in the upper peripheral circuit structure UPST, while the region where the lower local word line selection transistor LX-R and the region where the lower local bit line selection transistor LY-R are located are located in the lower peripheral circuit structure DPST. The upper peripheral circuit structure UPST is located on the lower peripheral circuit structure DPST.

[0025] Figure 3 is a cross-sectional view of a semiconductor memory element according to one embodiment of the present invention.

[0026] Referring to Figure 3, the semiconductor memory element 1 includes a lower peripheral circuit structure DPST, an upper peripheral circuit structure UPST, and a memory cell structure CST, which are stacked sequentially along the vertical direction. A bonding structure BDDI is interposed between the lower peripheral circuit structure DPST and the upper peripheral circuit structure UPST. A lower wiring structure BPST is positioned below the lower peripheral circuit structure DPST, and an upper wiring structure FPST is positioned above the memory cell structure CST. The lower wiring structure BPST, lower peripheral circuit structure DPST, bonding structure BDDI, upper peripheral circuit structure UPST, memory cell structure CST, and upper wiring structure FPST are superimposed on each other in the vertical direction. The lower peripheral circuit structure DPST and the upper peripheral circuit structure UPST are electrically connected by a plurality of vertical through-electrodes (TSVs).

[0027] The lower wiring structure BPST includes a lower semiconductor substrate PSUBD, a lower element isolation film STID, a plurality of lower transistors, a plurality of lower wiring lines PMLD and a plurality of lower wiring contacts PMCD electrically connected to the plurality of lower transistors, and a lower wiring insulating layer IMDD covering the plurality of lower transistors, the plurality of lower wiring lines PMLD and the plurality of lower wiring contacts PMCD. The plurality of lower transistors include lower local word line selection transistors LX-R and lower local bit line selection transistors LY-R. The lower element isolation film STID is embedded within the lower semiconductor substrate PSUBD. In some embodiments, the lower element isolation film STID is embedded within the lower semiconductor substrate PSUBD so as to extend from the lower surface of the lower semiconductor substrate PSUBD into the lower semiconductor substrate PSUBD. Each of the lower local word line selection transistors LX-R and lower local bit line selection transistors LY-R is located in the portion of the lower semiconductor substrate PSUBD limited by the lower element isolation film STID. In some embodiments, each of the lower local word line selection transistors LX-R and lower local bit line selection transistors LY-R is located below the lower semiconductor substrate PSUBD.

[0028] Each of the lower local word line selection transistors LX-R and LY-R includes a lower gate electrode PGLD, a lower gate dielectric film PGoxD, and a lower source-drain region SDD. Multiple lower wiring contacts PMCD are interposed between the lower local word line selection transistors LX-R and LY-R and multiple lower wiring line PMLDs. Figure 3 shows, but is illustrative, how multiple lower wiring contacts PMCD connect multiple lower wiring line PMLDs and multiple lower source-drain regions SDD. For example, multiple lower wiring contacts PMCD connect multiple lower wiring line PMLDs and multiple lower gate electrode PGLDs. The lower wiring insulating layer IMDD covers the underside of the lower semiconductor substrate PSUBD and covers multiple lower gate electrode PGLDs, multiple lower gate dielectric films PGoxD, multiple lower wiring contacts PMCDs, and multiple lower wiring line PMLDs. The lower source-drain region SDD is formed by injecting impurities into a portion of the underside of the lower semiconductor substrate PSUBD. For example, if the lower semiconductor substrate PSUBD has a first conductivity type, the lower source-drain region SDD has a second conductivity type different from the first conductivity type. In some embodiments, the first conductivity type is p-type and the second conductivity type is n-type, but this is not limited to this. For example, the first conductivity type is n-type and the second conductivity type is p-type.

[0029] The upper peripheral circuit structure UPST includes an upper semiconductor substrate PSUBU, an upper element isolation film STIU, a plurality of upper transistors, a plurality of upper wiring lines PMLU and a plurality of upper wiring contacts PMCU electrically connected to the plurality of upper transistors, and an upper wiring insulating layer IMDU covering the plurality of upper transistors, the plurality of upper wiring lines PMLU and the plurality of upper wiring contacts PMCU. The plurality of upper transistors include upper local word line selection transistors LX-F and upper local bit line selection transistors LY-F. The upper element isolation film STIU is embedded within the upper semiconductor substrate PSUBU. In some embodiments, the upper element isolation film STIU is embedded within the upper semiconductor substrate PSUBU so as to extend from the upper surface of the upper semiconductor substrate PSUBU into the upper semiconductor substrate PSUBU. Each of the upper local word line selection transistors LX-F and upper local bit line selection transistors LY-F is located in the portion of the upper semiconductor substrate PSUBU limited by the upper element isolation film STIU. In some embodiments, the upper local word line selection transistor LX-F and the upper local bit line selection transistor LY-F are located on top of the upper semiconductor substrate PSUBU.

[0030] Each of the upper local word line selection transistors LX-F and LY-F includes an upper gate electrode PGLU, an upper gate dielectric film PGoxU, and an upper source-drain region SDU. Multiple upper wiring contacts PMCU are interposed between the upper local word line selection transistors LX-F and LY-F and multiple upper wiring line PMLUs. Figure 3 shows, but is illustrative, how multiple upper wiring contacts PMCU connect multiple upper wiring line PMLUs and multiple upper source-drain region SDUs. For example, multiple upper wiring contacts PMCU connect multiple upper wiring line PMLUs and multiple upper gate electrode PGLUs. The upper wiring insulating layer IMDU covers the upper surface of the upper semiconductor substrate PSUBU and covers multiple upper gate electrode PGLUs, multiple upper gate dielectric films PGoxU, multiple upper wiring contacts PMCUs, and multiple upper wiring line PMLUs. The upper source-drain region SDU is formed by impregnating a portion of the upper side of the upper semiconductor substrate PSUBU with impurities. For example, if the upper semiconductor substrate PSUBU has a first conductivity type, the upper source-drain region SDU has a second conductivity type that is different from the first conductivity type.

[0031] Each of the lower semiconductor substrate PSUBD and the upper semiconductor substrate PSUBU may contain a semiconductor material such as a Group IV semiconductor material, a Group III-V semiconductor material, or a Group II-VI semiconductor material, or a Group II-VI oxide semiconductor material. Group IV semiconductor materials include, for example, silicon (Si), germanium (Ge), or silicon-germanium (Si-Ge). Group III-V semiconductor materials include, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimony (InSb), or indium gallium arsenide (InGaAs). Group II-VI semiconductor materials include, for example, zinc tellurium (ZnTe) or cadmium sulfide (CdS). Each of the lower semiconductor substrate PSUBD and the upper semiconductor substrate PSUBU may be provided as a bulk wafer or an epitaxial layer. In other embodiments, the lower semiconductor substrate PSUBD and the upper semiconductor substrate PSUBU may each include an SOI (silicon-on-insulator) substrate or a GeOI (germanium-on-insulator) substrate.

[0032] The lower gate dielectric film PGoxD and the upper gate dielectric film PGoxU are each composed of a silicon oxide film, a high dielectric film, or a combination thereof. In some embodiments, each of the lower gate dielectric film PGoxD and the upper gate dielectric film PGoxU consists of a laminated structure of an interface layer and a high dielectric film. The interface layer is composed of a low dielectric material with a dielectric constant of about 9 or less. For example, the interface layer is composed of an oxide, nitride, or oxynitride. The high dielectric film is composed of a metal oxide or metal oxynitride. The high dielectric film is composed of a material with a dielectric constant even greater than that of the silicon oxide film. For example, the high dielectric film has a dielectric constant of about 10 to about 25. The high dielectric film has a thickness of about 10 to about 40 angstroms, but is not limited thereto. In some embodiments, the interface layer may be omitted. For example, each of the lower gate dielectric film PGoxD and the upper gate dielectric film PGoxU may be composed of HfO2, Al2O3, HfAlO3, Ta2O3, or TiO2.

[0033] Each of the lower gate electrode PGLD and upper gate electrode PGLU includes a work function-adjusting metal-containing layer and a gap-fill metal-containing layer that fills the space above the work function-adjusting metal-containing layer. The work function-adjusting metal-containing layer contains at least one metal selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. In some embodiments, each of the lower gate electrode PGLD and upper gate electrode PGLU has a structure in which a metal nitride layer, a metal layer, a conductive gap-fill layer, and a gap-fill metal film are sequentially laminated. The metal nitride layer and the metal layer contain at least one metal selected from Ti, Ta, W, Ru, Nb, Mo, or Hf. The gap-fill metal film is composed of a W film or an Al film. In some embodiments, the lower gate electrode PGLD and the upper gate electrode PGLU each include, but are not limited to, a TiAlC / TiN / W stacked structure, a TiN / TaN / TiAlC / TiN / W stacked structure, or a TiN / TaN / TiN / TiAlC / TiN / W stacked structure.

[0034] Each of the multiple lower wiring contacts PMCD, multiple lower wiring lines PMLD, multiple upper wiring lines PMLU, and multiple upper wiring contacts PMCU contains a conductive material such as copper (Cu), aluminum (Al), tungsten (W), silver (Ag), gold (Au), or a combination thereof. Each of the lower wiring insulating layer IMDD and upper wiring insulating layer IMDU contains an insulating material including silicon oxide, silicon nitride, low-dielectric (low-k) material, or a combination thereof. Low-dielectric material is a material having a lower dielectric constant than silicon oxide and includes, for example, PSG (phospho silicate glass), BPSG (borophos phosilicate glass), FSG (fluoro silicate glass), OSG (organo silicate glass), SOG (spin-on-glass), SOP (spin-on-polymer), or a combination thereof. In some embodiments, the lower wiring insulation layer IMDD and the upper wiring insulation layer IMDU each contain an Ultra Low k (ULK) material having an ultra low dielectric constant of about 2.2 to 2.4. The ULK material includes SiOC or SiCOH.

[0035] In some embodiments, the lower local word line selection transistor LX-R and the upper local word line selection transistor LX-F connected to a word line WL overlap each other vertically, but are not limited to this. For example, the lower local word line selection transistor LX-R and the upper local word line selection transistor LX-F connected to a word line WL overlap each other vertically, at least in part. In some embodiments, the lower local bit line selection transistor LY-R and the upper local bit line selection transistor LY-F connected to a bit line BL overlap each other vertically, but are not limited to this. For example, the lower local bit line selection transistor LY-R and the upper local bit line selection transistor LY-F connected to a bit line BL overlap each other vertically, at least in part.

[0036] The bonding structure BDDI is interposed between the upper surface of the lower semiconductor substrate PSUBD and the lower surface of the upper semiconductor substrate PSUBU. The bonding structure BDDI contains an insulating material. In some embodiments, the bonding structure BDDI is constructed by bonding a lower bonding insulating layer covering the upper side of the lower peripheral circuit structure DPST and an upper bonding insulating layer covering the lower side of the upper peripheral circuit structure UPST to each other by forming covalent bonds. The bonding structure BDDI contains silicon oxide or silicon carbonitride (SiCN). For example, each of the lower bonding insulating layer and the upper bonding insulating layer contains silicon oxide or silicon carbonitride (SiCN). Multiple vertical through-electrodes (TSVs) penetrate the bonding structure BDDI and electrically connect the lower peripheral circuit structure DPST and the upper peripheral circuit structure UPST.

[0037] In some embodiments, the lower peripheral circuit structure DPST and the upper peripheral circuit structure UPST are bonded to each other and electrically connected in a metal-oxide hybrid bonding manner. For example, the bonding structure BDDI consists of a plurality of bonding pads and a bonding insulating layer covering the plurality of bonding pads. The plurality of bonding pads electrically connect portions of a plurality of vertical through-electrode TSVs that penetrate at least a portion of the lower peripheral circuit structure DPST to portions of a plurality of vertical through-electrode TSVs that penetrate at least a portion of the upper peripheral circuit structure UPST, thereby electrically connecting the lower peripheral circuit structure DPST and the upper peripheral circuit structure UPST. The bonding insulating layer is formed by bonding a lower bonding insulating layer covering the lower peripheral circuit structure DPST and an upper bonding insulating layer covering the underside of the upper peripheral circuit structure UPST to each other, forming a covalent bond. For example, the bonding insulating layer includes silicon oxide or silicon carbonitride (SiCN). Each of the plurality of bonding pads is formed by bonding a lower bonding pad, which is covered by the lower bonding insulating layer, and an upper bonding pad, which is covered by the upper bonding insulating layer. For example, a lower bonding pad and an upper bonding pad that correspond to each other expand due to heat and come into contact with each other, and then become a diffusion-bonded bonding pad that forms a single unit through the diffusion of the metal atoms it contains.

[0038] In some embodiments, the upper local word line selection transistor LX-F and the upper local bit line selection transistor LY-F, and the lower local word line selection transistor LX-R and the lower local bit line selection transistor LY-R are arranged on opposite sides of the upper semiconductor substrate PSUBU and the lower semiconductor substrate PSUBD. For example, the upper peripheral circuit structure UPST has a face-up structure in which the upper local word line selection transistor LX-F and the upper local bit line selection transistor LY-F are arranged on the upper side of the upper semiconductor substrate PSUBU facing the memory cell structure CST, and the lower peripheral circuit structure DPST has a face-down structure in which the lower local word line selection transistor LX-R and the lower local bit line selection transistor LY-R are arranged on the lower side of the lower semiconductor substrate PSUBD facing the lower wiring structure BPST on the opposite side of the memory cell structure CST.

[0039] The memory cell structure CST includes a plurality of word lines WL extending in a first horizontal direction, a plurality of bit lines BL extending in a second horizontal direction, a plurality of selector SLTs interposed between the plurality of word lines WL and the plurality of bit lines BL, and an interlayer insulating layer ILD covering the plurality of word lines, the plurality of bit lines, and the plurality of selector SLTs. The plurality of selector SLTs constitute a plurality of memory cells MC. Each of the plurality of word lines WL is made of a conductive material. For example, each of the plurality of word lines WL includes doped polysilicon, metal, conductive metal nitride, or a combination thereof. Each of the plurality of bit lines BL is made of a conductive material. For example, each of the plurality of bit lines BL includes doped polysilicon, metal, conductive metal nitride, or a combination thereof. The interlayer insulating layer ILD is made of silicon oxide or an insulating material with a dielectric constant lower than silicon oxide. In some embodiments, the interlayer insulating layer ILD is made of TEOS (tetraethyl orthosilicate) or ULK (ultra low K) material.

[0040] In some embodiments, the selector SLT includes a first select electrode layer EL1, a select material layer SML, and a second select electrode layer EL2. The first select electrode layer EL1 is interposed between the bit line BL and the select material layer SML, and the second select electrode layer EL2 is interposed between the word line WL and the select material layer SML.

[0041] The first selective electrode layer EL1 and the second selective electrode layer EL2 each contain a conductive material. For example, the first selective electrode layer EL1 and the second selective electrode layer EL2 each consist of carbon or a carbon-containing conductive material. The selective material layer SML contains a material having ovonic threshold switching (OTS) properties. The selective material layer SML contains a chalcogenide material. For example, the selective material layer SML includes two-component materials such as GeSe, GeS, AsSe, AsTe, AsS, SiTe, SiSe, SiS, GeAs, SiAs, SnSe, and SnTe; three-component materials such as GeAsTe, GeAsSe, AlAsTe, AlAsSe, SiAsSe, SiAsTe, GeSeTe, GeSeSb, GaAsSe, GaAsTe, InAsSe, InAsTe, SnAsSe, and SnAsTe; and GeSiAsTe and GeSi AsSe, GeSiSeTe, GeSeTeSb, GeSiSeSb, GeSiTeSb, GeSeTeBi, GeSiSeBi, GeSiTeBi, GeAsSeSb, GeAsTeSb, GeAsTeBi, GeAsS eBi, GeAsSeIn, GeAsSeGa, GeAsSeAl, GeAsSeTl, GeAsSeSn, GeAsSeZn, GeAsTeIn, GeAsTeGa, GeAsTeAl, GeAsTeTl, GeAsTe Four-component materials such as Sn, GeAsTeZn, GeSiAsSeTe, GeAsSeTeS, GeSiAsSeS, GeSiAsTeS, GeSiSeTeS, GeSiAsSeP, GeSiAsTeP, GeAsSeTe P, GeSiAsSeIn, GeSiAsSeGa, GeSiAsSeAl, GeSiAsSeTl, GeSiAsSeZn, GeSiAsSeSn, GeSiAsTeIn, GeSiAsTeGa, GeSiAsTeAl , GeSiAsTeTl, GeSiAsTeZn, GeSiAsTeSn, GeAsSeTeIn, GeAsSeTeGa, GeAsSeTeAl, GeAsSeTeTl, GeAsSeTeZn, GeAsSeTeSn, GeAsSeSIn, GeAsSeSGa, GeAsSeSAl, GeAsSeSTl, GeAsSeSZn, GeAsSeSSn, GeAsTeSIn, GeAsTeSGa, GeAsTeSAl, GeAsTeSTl,GeAsTeSZn, GeAsTeSSn, GeAsSeInGa, GeAsSeInAl, GeAsSeInTl, GeAsSeInZn, GeAsSeInSn, GeAsSeGaAl, GeAsSeGaTl, GeAsSeGaZn, GeAsSeGa Five-component materials such as Sn, GeAsSeAlTl, GeAsSeAlZn, GeAsSEAlSn, GeAsSeTlZn, GeAsSeTlSn, GeAsSeZnSn, and GeSiAsSeTeS, GeSiAsSeTeIn, GeSiAsSeTeGa , GeSiAsSeTeAl, GeSiAsSeTeTl, GeSiAsSeTeZn, GeSiAsSeTeSn, GeSiAsSeTeP, GeSiAsSeSIn, GeSiAsSeSGa, GeSiAsSeSAl, GeSiAsSeSTl, GeS iAsSeSZn, GeSiAsSeSSn, GeAsSeTeSIn, GeAsSeTeSGa, GeAsSeTeSAl, GeAsSeTeSTl, GeAsSeTeSZn, GeAsSeTeSSn, GeAsSeTePIn, GeAsSeTePGa, GeAsSeTePAl, GeAsSeTePTl, GeAsSeTePZn, GeAsSeTePSn, GeSiAsSeInGa, GeSiAsSeInAl, GeSiAsSeInTl, GeSiAsSeInZn, GeSiAsSeInSn, GeS iAsSeGaAl, GeSiAsSeGaTl, GeSiAsSeGaZn, GeSiAsSeGaSn, GeSiAsSeAlSn, GeAsSeTeInGa, GeAsSeTeInAl, GeAsSeTeInTl, GeAsSeTeInZn, GeA The layers consist of a single or multilayer structure made of a substance selected from among the six-component systems such as sSeTeInSn, GeAsSeTeGaAl, GeAsSeTeGaTl, GeAsSeTeGaZn, GeAsSeTeGaSn, GeAsSeTeAlSn, GeAsSeSInGa, GeAsSeSInAl, GeAsSeSInTl, GeAsSeSInZn, GeAsSeSInSn, GeAsSeSGaAl, GeAsSeSGaTl, GeAsSeSGaZn, GeAsSeSGaSn, and GeAsSeSAlSn. In some embodiments, the selected substance layer SML consists of at least one substance selected from the two-component to six-component systems exemplified above, and B,It contains at least one additional element selected from C, N, and O.

[0042] If the selector SLT is made of a material with OTS characteristics, when a voltage above a threshold voltage (Vth) is applied across the selector SLT, the resistance or threshold voltage in the selector SLT drops sharply due to threshold switching, resulting in a turn-on state where current flows. In this turn-on state, if a current below a specific threshold (Ihold) flows through the selector SLT, the resistance or threshold voltage in the selector SLT increases sharply, resulting in a turn-off state where almost no current flows through the selector SLT. The turn-on and turn-off states correspond to other logic states (SET state or RESET state).

[0043] The memory cell structure CST includes a word line contact WLC that electrically connects a word line WL to an upper peripheral circuit structure UPST, and a bit line contact BLC that electrically connects a bit line BL to an upper peripheral circuit structure UPST. Figure 3 shows a word line contact WLC connected to one of several word lines WL and a bit line contact BLC connected to one of several bit lines BL, but this is merely an example for illustrative purposes and is not limited thereto. For example, the memory cell structure CST includes multiple word line contacts WLC connected to multiple word lines WL and multiple bit line contacts BLC connected to multiple bit lines BL. In some embodiments, the word line contact WLC penetrates the interlayer insulation layer ILD and electrically connects the word line WL to the upper wiring line PMLU. In some embodiments, the bit line contact BLC penetrates the interlayer insulation layer ILD and electrically connects the bit line BL to the upper wiring line PMLU.

[0044] The upper wiring structure FPST includes a plurality of upper contact plugs CTA and an upper cover insulating layer CDU that covers the plurality of upper contact plugs CTA. The plurality of upper contact plugs CTA penetrate the upper cover insulating layer CDU and the interlayer insulating layer ILD and are electrically connected to the upper peripheral circuit structure UPST. The plurality of upper contact plugs CTA are electrically connected to a plurality of upper wiring lines PMLU. For example, the plurality of upper contact plugs CTA are electrically connected to the upper local word line selection transistor LX-F and the upper local bit line selection transistor LY-F, and supply power to the upper local word line selection transistor LX-F and the upper local bit line selection transistor LY-F.

[0045] The lower wiring structure BPST includes a plurality of lower contact plugs CTB and a lower cover insulating layer CDD that covers the plurality of lower contact plugs CTB. The plurality of lower contact plugs CTB penetrate the lower cover insulating layer CDD and are electrically connected to the lower peripheral circuit structure DPST. The plurality of lower contact plugs CTB are electrically connected to a plurality of lower wiring lines PMLD. For example, the plurality of lower contact plugs CTB are electrically connected to the lower local word line selection transistor LX-R and the lower local bit line selection transistor LY-R, and supply power to the lower local word line selection transistor LX-R and the lower local bit line selection transistor LY-R.

[0046] Each of the upper contact plug CTA and lower contact plug CTB consists of a metal layer and a conductive metal nitride layer covering the metal layer. For example, the metal layer is W or Al, and the conductive metal nitride layer is TiN or TaN. Each of the lower cover insulating layer CDD and upper cover insulating layer CDU contains an insulating material including silicon oxide, silicon nitride, low-dielectric (low-k) material, ULK (ultra low K) material, or a combination thereof. The upper contact plug CTA has a tapered shape in which the horizontal width decreases from the upper wiring structure FPST towards the upper peripheral circuit structure UPST. The lower contact plug CTB has a tapered shape in which the horizontal width decreases from the lower wiring structure BPST towards the lower peripheral circuit structure DPST.

[0047] Multiple vertical through-electrode (TSV) connections electrically link the upper peripheral circuit structure (UPST) and the lower peripheral circuit structure (DPST). For example, multiple vertical through-electrode (TSV) connections electrically link the lower local word line selection transistor (LX-R) and the upper local word line selection transistor (LX-F), and the lower local bit line selection transistor (LY-R) and the upper local bit line selection transistor (LY-F). In some embodiments, multiple vertical through-electrode (TSV) connections electrically link multiple lower wiring lines (PMLD) and multiple upper wiring lines (PMLU). For example, multiple vertical through-electrode (TSV) connections penetrate the lower wiring insulation layer (IMDD), the lower semiconductor substrate (PSUBD), the bonding structure (BDDI), the upper semiconductor substrate (PSUBU), and the upper wiring insulation layer (IMDU), electrically linking multiple lower wiring lines (PMLD) and multiple upper wiring lines (PMLU).

[0048] Each of the multiple vertical through-electrode (TSV) consists of a conductive plug and a conductive barrier film covering the surface of the conductive plug. For example, the conductive plug contains Cu or W. In some embodiments, the conductive plug is composed of, but is not limited to, Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W, or a W alloy. In some embodiments, the conductive barrier film contains at least one material selected from Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or NiB. In some embodiments, a via insulating film is placed between each of the multiple vertical through-electrode (TSV) and the lower semiconductor substrate PSUBD and the upper semiconductor substrate PSUBU. For example, the via insulating film consists of an oxide film, a nitride film, a carbide film, a polymer, or a combination thereof. Each of the multiple vertical through-electrode (TSV) has a tapered shape in which the horizontal width decreases from the lower peripheral circuit structure DPST to the upper peripheral circuit structure UPST.

[0049] In the semiconductor memory element 1 according to the present invention, the upper peripheral circuit structure UPST, which includes the upper local word line selection transistor LX-F and the upper local bit line selection transistor LY-F, is arranged on the lower peripheral circuit structure DPST, which includes the lower local word line selection transistor LX-R and the lower local bit line selection transistor LY-R, and is superimposed vertically. As a result, the area of ​​the semiconductor memory element 1 is reduced or the integration density within the same area is improved. Furthermore, the lower local word line selection transistor LX-R and the upper local word line selection transistor LX-F, and the lower local bit line selection transistor LY-R and the upper local bit line selection transistor LY-F are electrically connected via multiple vertical through-electrodes (TSVs), shortening the electrical paths between them and improving the operational performance of the semiconductor memory element 1.

[0050] Furthermore, in the semiconductor memory element 1 according to the present invention, power is supplied to the upper peripheral circuit structure UPST, which includes the upper local word line selection transistor LX-F and the upper local bit line selection transistor LY-F, via a plurality of upper contact plugs CTA included in the upper wiring structure FPST, and power is supplied to the lower peripheral circuit structure DPST, which includes the lower local word line selection transistor LX-R and the lower local bit line selection transistor LY-R, via a plurality of lower contact plugs CTB included in the lower wiring structure BPST. As a result, the arrangement of the wiring included in the semiconductor memory element 1 is simplified, the integration density of the semiconductor memory element 1 is improved, and the operating performance is improved.

[0051] Figures 4A to 4F are cross-sectional views illustrating a method for manufacturing a semiconductor memory element according to one embodiment of the present invention.

[0052] Referring to Figure 4A, after forming the upper peripheral circuit structure UPST, a memory cell structure CST is formed on the upper peripheral circuit structure UPST. For example, after forming the upper element isolation film STIU, the upper local word line selection transistor LX-F, and the upper local bit line selection transistor LY-F on the upper semiconductor substrate PSUBU, a plurality of upper wiring lines PMLU and a plurality of upper wiring contacts PMCU are formed that are electrically connected to the upper local word line selection transistor LX-F and the upper local bit line selection transistor LY-F, and an upper wiring insulating layer IMDU is formed that covers the plurality of upper wiring lines PMLU and the plurality of upper wiring contacts PMCU, thereby forming the upper peripheral circuit structure UPST.

[0053] For example, a memory cell structure CST is formed by creating a plurality of word lines WL extending in a first horizontal direction, a plurality of bit lines BL extending in a second horizontal direction, a plurality of selector SLTs interposed between the plurality of word lines WL and the plurality of bit lines BL, a plurality of word lines, a plurality of bit lines, and an interlayer insulating layer ILD covering the plurality of selector SLTs, a plurality of word line contacts WLC penetrating the interlayer insulating layer ILD and electrically connecting the plurality of word lines WL and the plurality of upper wiring lines PMLU, and a plurality of bit line contacts BLC penetrating the interlayer insulating layer ILD and electrically connecting the plurality of bit lines BL and the plurality of upper wiring lines PMLU.

[0054] Referring to Figure 4B, after forming the lower element isolation film STID, the lower local word line selection transistor LX-R, and the lower local bit line selection transistor LY-R on the lower semiconductor substrate PSUBD, a plurality of lower wiring contacts PMCD, which are electrically connected to the lower local word line selection transistor LX-R and the lower local bit line selection transistor LY-R, and a lower wiring insulating layer IMDD covering the plurality of lower wiring contacts PMCD are formed. The result in Figure 4B is referred to as a preliminary lower wiring structure.

[0055] Referring to Figure 4C, the result of Figure 4A is inverted vertically so that the memory cell structure CST is on the bottom and the upper peripheral circuit structure UPST is on the top, and then the preliminary lower wiring structure, which is the result of Figure 4B, is attached onto the upper peripheral circuit structure UPST. The preliminary lower wiring structure is attached onto the upper peripheral circuit structure UPST so that a bonding structure BDDI is interposed between the upper semiconductor substrate PSUBU and the lower semiconductor substrate PSUBD. In some embodiments, the preliminary lower wiring structure is attached onto the upper peripheral circuit structure UPST so that the upper local word line selection transistor LX-F and the upper local bit line selection transistor LY-F, and the lower local word line selection transistor LX-R and the lower local bit line selection transistor LY-R are located on opposite sides of the upper semiconductor substrate PSUBU and the lower semiconductor substrate PSUBD.

[0056] Referring to Figure 4D, multiple vertical through-electrodes (TSVs) are formed that penetrate the lower wiring insulation layer IMDD, the lower semiconductor substrate PSUBD, the bonding structure BDDI, the upper semiconductor substrate PSUBU, and the upper wiring insulation layer IMDU, and are connected to multiple upper wiring lines PMLU.

[0057] Referring to Figure 4E, multiple lower wiring lines PMLD are formed, which are connected to multiple lower wiring contacts PMCD, forming a lower peripheral circuit structure DPST. In some embodiments, an insulating material layer is formed to cover the multiple lower wiring lines PMLD, and the lower wiring insulating layer IMDD, which includes the insulating material layer, covers the multiple lower wiring contacts PMCD and the multiple lower wiring lines PMLD.

[0058] A lower wiring structure BPST is formed on the lower peripheral circuit structure DPST, including multiple lower contact plugs CTB and a lower cover insulating layer CDD that covers the multiple lower contact plugs CTB. The multiple lower contact plugs CTB penetrate the lower cover insulating layer CDD and are connected to multiple lower wiring lines PMLD.

[0059] Referring to Figure 4F, the result of Figure 4E is inverted vertically so that the lower wiring structure BPST is on the bottom and the memory cell structure CST is on the top.

[0060] Subsequently, as shown in Figure 3, an upper wiring structure FPST is formed on the memory cell structure CST, which includes a plurality of upper contact plugs CTA and an upper cover insulating layer CDU covering the plurality of upper contact plugs CTA, thereby forming a semiconductor memory element 1. The plurality of upper contact plugs CTA penetrate the upper cover insulating layer CDU and the interlayer insulating layer ILD, and are connected to a plurality of upper wiring lines PMLU.

[0061] Figure 5 is a cross-sectional view of a semiconductor memory element according to one embodiment of the present invention.

[0062] Referring to Figure 5, the semiconductor memory element 1a includes a lower peripheral circuit structure DPST, an upper peripheral circuit structure UPST, and a memory cell structure CST, which are stacked sequentially along the vertical direction. A bonding structure BDDI is interposed between the lower peripheral circuit structure DPST and the upper peripheral circuit structure UPST. For example, the lower surface of the bonding structure BDDI covers the upper surface of the lower wiring line PMLD located at the uppermost end of the multiple lower wiring lines PMLD and the upper surface of the lower wiring insulating layer IMDD, while the upper surface of the bonding structure BDDI covers the lower surface of the upper semiconductor substrate PSUBU. A lower wiring structure BPST is positioned below the lower peripheral circuit structure DPST, and an upper wiring structure FPST is positioned above the memory cell structure CST. The lower wiring structure BPST, lower peripheral circuit structure DPST, bonding structure BDDI, upper peripheral circuit structure UPST, memory cell structure CST, and upper wiring structure FPST are superimposed on each other in the vertical direction. The lower peripheral circuit structure DPST and the upper peripheral circuit structure UPST are electrically connected by multiple vertical through-electrodes TSVs.

[0063] The upper local word line selection transistor LX-F and the upper local bit line selection transistor LY-F, and the lower local word line selection transistor LX-R and the lower local bit line selection transistor LY-R are positioned on the side of the upper semiconductor substrate PSUBU and the lower semiconductor substrate PSUBD that faces the respective memory cell structure CST. For example, the upper peripheral circuit structure UPST has a face-up structure in which the upper local word line selection transistor LX-F and the upper local bit line selection transistor LY-F are positioned on the upper side of the upper semiconductor substrate PSUBU facing the memory cell structure CST, and the lower peripheral circuit structure DPST has a face-up structure in which the lower local word line selection transistor LX-R and the lower local bit line selection transistor LY-R are positioned on the upper side of the lower semiconductor substrate PSUBD facing the memory cell structure CST.

[0064] Multiple upper contact plugs CTA penetrate the upper cover insulating layer CDU and the interlayer insulating layer ILD, and are electrically connected to multiple upper wiring lines PMLU. Multiple lower contact plugs CTB penetrate the lower cover insulating layer CDD, the lower semiconductor substrate PSUBD, and the lower wiring insulating layer IMDD, and are electrically connected to multiple lower wiring lines PMLD. Multiple vertical through electrodes TSV penetrate the bonding structure BDDI, the upper semiconductor substrate PSUBU, and the upper wiring insulating layer IMDU, and electrically connect multiple lower wiring lines PMLD and multiple upper wiring lines PMLU.

[0065] Figures 6 and 7 are cross-sectional views of a semiconductor memory element according to one embodiment of the present invention.

[0066] Referring to Figure 6, the semiconductor memory element 2 includes a lower peripheral circuit structure DPST, a memory cell structure CST, and an upper peripheral circuit structure UPST, which are stacked sequentially along the vertical direction. A bonding structure BDDI is interposed between the memory cell structure CST and the upper peripheral circuit structure UPST. For example, the lower surface of the bonding structure BDDI covers the upper surfaces of multiple bit lines BL and the upper surface of the interlayer insulating layer ILD, and the upper surface of the bonding structure BDDI covers the lower surface of the upper semiconductor substrate PSUBU. A lower wiring structure BPST is positioned below the lower peripheral circuit structure DPST, and an upper wiring structure FPST is positioned above the upper peripheral circuit structure UPST. The lower wiring structure BPST, lower peripheral circuit structure DPST, memory cell structure CST, bonding structure BDDI, upper peripheral circuit structure UPST, and upper wiring structure FPST are superimposed on each other in the vertical direction. The lower peripheral circuit structure DPST and the upper peripheral circuit structure UPST are electrically connected by multiple vertical through-electrodes TSVs.

[0067] The upper local word line selection transistor LX-F and the upper local bit line selection transistor LY-F, and the lower local word line selection transistor LX-R and the lower local bit line selection transistor LY-R are positioned on the side of the upper semiconductor substrate PSUBU and the lower semiconductor substrate PSUBD that faces the respective memory cell structure CST. For example, the upper peripheral circuit structure UPST has a face-up structure in which the upper local word line selection transistor LX-F and the upper local bit line selection transistor LY-F are positioned on the upper side of the upper semiconductor substrate PSUBU facing the memory cell structure CST, and the lower peripheral circuit structure DPST has a face-up structure in which the lower local word line selection transistor LX-R and the lower local bit line selection transistor LY-R are positioned on the upper side of the lower semiconductor substrate PSUBD facing the memory cell structure CST.

[0068] Multiple upper contact plugs CTA penetrate the upper cover insulation layer CDU and are electrically connected to multiple upper wiring lines PMLU. Multiple lower contact plugs CTB penetrate the lower cover insulation layer CDD, the lower semiconductor substrate PSUBD, and the lower wiring insulation layer IMDD and are electrically connected to multiple lower wiring lines PMLD. Multiple vertical through electrodes TSV penetrate the upper wiring insulation layer IMDU, the upper semiconductor substrate PSUBU, the bonding structure BDDI, and the interlayer insulation layer ILD and electrically connect multiple lower wiring lines PMLD to multiple upper wiring lines PMLU.

[0069] Referring to Figure 7, the semiconductor memory element 2a includes a lower peripheral circuit structure DPST, a memory cell structure CST, and an upper peripheral circuit structure UPST, which are stacked sequentially along the vertical direction. A bonding structure BDDI is interposed between the memory cell structure CST and the upper peripheral circuit structure UPST. For example, the lower surface of the bonding structure BDDI covers the upper surfaces of multiple bit lines BL and the upper surface of the interlayer insulating layer ILD, and the upper surface of the bonding structure BDDI covers the lower surface of the upper wiring line PMLU located at the lowest end of the multiple upper wiring lines PMLU and the lower surface of the upper wiring insulating layer IMDU. A lower wiring structure BPST is positioned below the lower peripheral circuit structure DPST, and an upper wiring structure FPST is positioned on top of the upper peripheral circuit structure UPST. The lower wiring structure BPST, lower peripheral circuit structure DPST, memory cell structure CST, bonding structure BDDI, upper peripheral circuit structure UPST, and upper wiring structure FPST are superimposed on each other in the vertical direction. The lower peripheral circuit structure DPST and the upper peripheral circuit structure UPST are electrically connected by multiple vertical through-electrodes TSVs.

[0070] The upper local word line selection transistor LX-F and the upper local bit line selection transistor LY-F, and the lower local word line selection transistor LX-R and the lower local bit line selection transistor LY-R are arranged on opposite sides of the upper semiconductor substrate PSUBU and the lower semiconductor substrate PSUBD. For example, the upper peripheral circuit structure UPST has a face-down structure in which the upper local word line selection transistor LX-F and the upper local bit line selection transistor LY-F are positioned below the upper semiconductor substrate PSUBU facing the memory cell structure CST, and the lower peripheral circuit structure DPST has a face-up structure in which the lower local word line selection transistor LX-R and the lower local bit line selection transistor LY-R are positioned above the lower semiconductor substrate PSUBD facing the memory cell structure CST.

[0071] Multiple upper contact plugs CTA penetrate the upper cover insulating layer CDU, the upper semiconductor substrate PSUBU, and the upper wiring insulating layer IMDU, and are electrically connected to multiple upper wiring lines PMLU. Multiple lower contact plugs CTB penetrate the lower cover insulating layer CDD, the lower semiconductor substrate PSUBD, and the lower wiring insulating layer IMDD, and are electrically connected to multiple lower wiring lines PMLD. Multiple vertical through electrodes TSV penetrate the bonding structure BDDI and the interlayer insulating layer ILD, and electrically connect multiple lower wiring lines PMLD and multiple upper wiring lines PMLU.

[0072] Figure 8 is a conceptual diagram illustrating a semiconductor memory element according to one embodiment of the present invention.

[0073] Referring to Figure 8, the semiconductor memory element 3 includes regions where multiple first local word line selection transistors LX1 are arranged, regions where multiple second local word line selection transistors LX2 are arranged, regions where multiple first local bit line selection transistors LY1 are arranged, and regions where multiple second local bit line selection transistors LY2 are arranged. Each of the regions where multiple first local word line selection transistors LX1 are arranged, regions where multiple second local word line selection transistors LX2 are arranged, regions where multiple first local bit line selection transistors LY1 are arranged, and regions where multiple second local bit line selection transistors LY2 are arranged is called a tile. One of the regions where the first local word line selection transistor LX1 is located and the region where the second local word line selection transistor LX2 is located, and one of the regions where the first local bit line selection transistor LY1 is located and the region where the second local bit line selection transistor LY2 is located, are arranged alternately along the first horizontal direction (X direction) and the second horizontal direction (Y direction), respectively. However, the regions where multiple first local word line selection transistors LX1 are located and the regions where multiple second local word line selection transistors LX2 are located are arranged alternately along the first horizontal direction (X direction), and the regions where multiple first local bit line selection transistors LY1 are located and the regions where multiple second local bit line selection transistors LY2 are located are arranged alternately along the second horizontal direction (Y direction). In some embodiments, each of the regions where multiple first local word line selection transistors LX1 are located and the regions where multiple second local word line selection transistors LX2 are located have a rectangular shape with a major axis in the first horizontal direction (X direction) and a minor axis in the second horizontal direction (Y direction). In some embodiments, each of the regions where a plurality of first local bit line selection transistors LY1 are arranged in a planar manner and the region where a plurality of second local bit line selection transistors LY2 are arranged has a rectangular shape with a major axis in the second horizontal direction (Y direction) and a minor axis in the first horizontal direction (X direction).

[0074] Multiple vertical through-electrode TSVs are arranged to surround the region where multiple first local word line selection transistors LX1 are located, the region where multiple second local word line selection transistors LX2 are located, the region where multiple first local bit line selection transistors LY1 are located, and the region where multiple second local bit line selection transistors LY2 are located.

[0075] Each region where multiple first local word line selection transistors LX1 are arranged is provided with a first lower local word line selection transistor LX1-R and a first upper local word line selection transistor LX1-F located on the first lower local word line selection transistor LX1-R, as shown in Figure 9A. Each region where multiple second local word line selection transistors LX2 are arranged is provided with a second lower local word line selection transistor LX2-R and a second upper local word line selection transistor LX2-F located on the second lower local word line selection transistor LX2-R, as shown in Figure 9A. Each region where multiple first local bit line selection transistors LY1 are arranged is provided with a first lower local bit line selection transistor LY1-R and a first upper local bit line selection transistor LY1-F located on the first lower local bit line selection transistor LY1-R, as shown in Figure 9B. In each region where multiple second local bit line selection transistors LY2 are arranged, a second lower local bit line selection transistor LY2-R and a second upper local bit line selection transistor LY2-F, located on the second lower local bit line selection transistor LY2-R, are arranged, as shown in Figure 9B.

[0076] Figures 9A and 9B are cross-sectional views of a semiconductor memory element according to one embodiment of the present invention.

[0077] Referring to both Figures 9A and 9B, the semiconductor memory element 3 includes a lower peripheral circuit structure DPST, an upper peripheral circuit structure UPST, and a memory cell structure CSTA, which are stacked sequentially along the vertical direction. A bonding structure BDDI is interposed between the lower peripheral circuit structure DPST and the upper peripheral circuit structure UPST. A lower wiring structure BPST is positioned below the lower peripheral circuit structure DPST, and an upper wiring structure FPST is positioned on top of the memory cell structure CSTA. The lower wiring structure BPST, the lower peripheral circuit structure DPST, the bonding structure BDDI, the upper peripheral circuit structure UPST, the memory cell structure CSTA, and the upper wiring structure FPST are superimposed on each other in the vertical direction. The lower peripheral circuit structure DPST and the upper peripheral circuit structure UPST are electrically connected by a plurality of vertical through-electrodes TSVs. The upper peripheral circuit structure UPST has a face-up structure, and the lower peripheral circuit structure DPST has a face-down structure.

[0078] The memory cell structure CSTA includes a plurality of first word lines WL1, a plurality of second word lines WL2, and a plurality of third word lines WL3 extending in a first horizontal direction, and a plurality of first bit lines BL1 and a plurality of second bit lines BL2 extending in a second horizontal direction. The plurality of first word lines WL1, a plurality of second word lines WL2, and a plurality of third word lines WL3 are located at different vertical levels from each other, and the plurality of first bit lines BL1 and a plurality of second bit lines BL2 are located at different vertical levels from each other. In some embodiments, for example, the plurality of first bit lines BL1 are located vertically between the plurality of first word lines WL1 and a plurality of second word lines WL2, and the plurality of second bit lines BL2 are located vertically between the plurality of second word lines WL2 and a plurality of third word lines WL3. For example, the plurality of first word lines WL1, a plurality of first bit lines BL1, a plurality of second word lines WL2, a plurality of second bit lines BL2, and a plurality of third word lines WL3 are arranged sequentially along the vertical direction.

[0079] The memory cell structure CSTA includes multiple first selectors SLT1 interposed between multiple first word lines WL1 and multiple first bit lines BL1, multiple second selectors SLT2 interposed between multiple first bit lines BL1 and multiple second word lines WL2, multiple third selectors SLT3 interposed between multiple second word lines WL2 and multiple second bit lines BL2, multiple fourth selectors SLT4 interposed between multiple second bit lines BL2 and multiple third word lines WL3, and an interlayer insulating layer ILD covering multiple first word lines WL1, multiple second word lines WL2, multiple third word lines WL3, multiple first bit lines BL1, multiple second bit lines BL2, multiple first selectors SLT1, multiple second selectors SLT2, multiple third selectors SLT3, and multiple fourth selectors SLT4. The multiple first selectors SLT1, multiple second selectors SLT2, multiple third selectors SLT3, and multiple fourth selectors SLT4 constitute multiple memory cells MC.

[0080] Each of the multiple first word lines WL1, multiple second word lines WL2, and multiple third word lines WL3 is substantially the same as the multiple word lines WL shown in Figure 3; the multiple first bit lines BL1 and multiple second bit lines BL2 are substantially the same as the multiple bit lines BL shown in Figure 3; and the multiple first selectors SLT1, multiple second selectors SLT2, multiple third selectors SLT3, and multiple fourth selectors SLT4 are substantially the same as the multiple selectors SLT shown in Figure 3; therefore, redundant explanations are omitted.

[0081] The memory cell structure CSTA includes a first word line contact WLC1 that electrically connects the first word line WL1 to the upper peripheral circuit structure UPST, a second word line contact WLC2 that electrically connects the second word line WL2 to the upper peripheral circuit structure UPST, and a third word line contact WLC3 that electrically connects the third word line WL3 to the first word line WL1. The memory cell structure CSTA also includes a first bit line contact BLC1 that electrically connects the first bit line BL1 to the upper peripheral circuit structure UPST, and a second bit line contact BLC2 that electrically connects the second bit line BL2 to the upper peripheral circuit structure UPST. In some embodiments, the first word line contact WLC1 and the second word line contact WLC2 each penetrate the interlayer insulation layer ILD and electrically connect the first word line WL1 and the second word line WL2 to the upper wiring line PMLU, and the third word line contact WLC3 penetrates the interlayer insulation layer ILD and electrically connects the third word line WL3 to the first word line WL1. In some embodiments, the first bit line contact BLC1 and the second bit line contact BLC2 each penetrate the interlayer insulation layer ILD and electrically connect the first bit line BL1 and the second bit line BL2 to the upper wiring line PMLU.

[0082] The lower peripheral circuit structure DPST includes a plurality of lower transistors, and the upper peripheral circuit structure UPST includes a plurality of upper transistors. The plurality of lower transistors include a first lower local word line selection transistor LX1-R, a second lower local word line selection transistor LX2-R, a first lower local bit line selection transistor LY1-R, and a second lower local bit line selection transistor LY2-R, and the plurality of upper transistors include a first upper local word line selection transistor LX1-F, a second upper local word line selection transistor LX2-F, a first upper local bit line selection transistor LY1-F, and a second upper local bit line selection transistor LY2-F. Each of the first word line WL1, the second word line WL2, and the third word line WL3 is electrically connected to the first lower local word line selection transistor LX1-R and the first upper local word line selection transistor LX1-F, or to the second lower local word line selection transistor LX2-R and the second upper local word line selection transistor LX2-F. The first bit line BL1 and the second bit line BL2 are electrically connected to either the first lower local bit line selection transistor LY1-R and the first upper local word line selection transistor LX1-F, or to the second lower local bit line selection transistor LY2-R and the second upper local bit line selection transistor LY2-F.

[0083] The first lower local word line selection transistor LX1-R and the first upper local word line selection transistor LX1-F, connected to any one of the first word line WL1, the second word line WL2, and the third word line WL3, overlap at least partially in the vertical direction. The second lower local word line selection transistor LX2-R and the second upper local word line selection transistor LX2-F, connected to any one of the first word line WL1, the second word line WL2, and the third word line WL3, overlap at least partially in the vertical direction. The first lower local bit line selection transistor LY1-R and the first upper local word line selection transistor LX1-F, connected to any one of the first bit line BL1 and the second bit line BL2, overlap at least partially in the vertical direction. The second lower local bit line selection transistor LY2-R and the second upper local bit line selection transistor LY2-F, connected to any one of the first bit line BL1 and the second bit line BL2, overlap at least partially in the vertical direction.

[0084] Figures 10A and 10B are cross-sectional views of a semiconductor memory element according to one embodiment of the present invention.

[0085] Referring to both Figures 10A and 10B, the semiconductor memory element 4 includes a lower peripheral circuit structure DPST, an upper peripheral circuit structure UPST, and a memory cell structure CSTA, which are stacked sequentially along the vertical direction. A bonding structure BDDI is interposed between the lower peripheral circuit structure DPST and the upper peripheral circuit structure UPST. A lower wiring structure BPST is positioned below the lower peripheral circuit structure DPST, and an upper wiring structure FPST is positioned above the memory cell structure CSTA. The lower wiring structure BPST, lower peripheral circuit structure DPST, bonding structure BDDI, upper peripheral circuit structure UPST, memory cell structure CSTA, and upper wiring structure FPST are superimposed on each other in the vertical direction. The lower peripheral circuit structure DPST and the upper peripheral circuit structure UPST are electrically connected by a plurality of vertical through-electrodes TSVs. The upper peripheral circuit structure UPST has a face-up structure, and the lower peripheral circuit structure DPST also has a face-up structure.

[0086] In some embodiments, with reference to Figures 6 and 7, the upper peripheral circuit structure UPST included in the semiconductor memory element 4 may be modified to be placed on the memory cell structure CSTA. For example, the upper peripheral circuit structure UPST placed on the memory cell structure CSTA may have a face-up structure, similar to the upper peripheral circuit structure UPST shown in Figure 6. For example, the upper peripheral circuit structure UPST placed on the memory cell structure CSTA may have a face-down structure, similar to the upper peripheral circuit structure UPST shown in Figure 7.

[0087] Figures 11A and 11B are cross-sectional views of a semiconductor memory element according to one embodiment of the present invention.

[0088] Referring to both Figures 11A and 11B, the semiconductor memory element 5 includes a first memory cell structure CST1, a lower peripheral circuit structure DPST, an upper peripheral circuit structure UPST, and a second memory cell structure CST2, which are stacked sequentially along the vertical direction. A bonding structure BDDI is interposed between the lower peripheral circuit structure DPST and the upper peripheral circuit structure UPST. A lower wiring structure BPST is positioned below the first memory cell structure CST1, and an upper wiring structure FPST is positioned above the second memory cell structure CST2. The lower wiring structure BPST, the first memory cell structure CST1, the lower peripheral circuit structure DPST, the bonding structure BDDI, the upper peripheral circuit structure UPST, the second memory cell structure CST2, and the upper wiring structure FPST are superimposed on each other in the vertical direction. The lower peripheral circuit structure DPST and the upper peripheral circuit structure UPST are electrically connected by a plurality of vertical through-electrodes TSVs. The upper peripheral circuit structure UPST has a face-up structure, and the lower peripheral circuit structure DPST has a face-down structure.

[0089] The first memory cell structure CST1 and the second memory cell structure CST2 have substantially identical structures, but are inverted versions of each other. For example, the first memory cell structure CST1 has a structure that is inverted from the memory cell structure CSTA shown in Figures 9A and 9B, and the second memory cell structure CST2 has a substantially identical structure to the memory cell structure CSTA shown in Figures 9A and 9B. The semiconductor memory element 5 shown in Figures 11A and 11B has the same structure as the semiconductor memory element 3 shown in Figures 9A and 9B, where the first memory cell structure CST1 is inserted between the lower wiring structure BPST and the lower peripheral circuit structure DPST, and the second memory cell structure CST2 has the same structure as the memory cell structure CSTA, so a redundant explanation is omitted. The first memory cell structure CST1 and the second memory cell structure CST2 each share the lower peripheral circuit structure DPST and the upper peripheral circuit structure UPST. The lower peripheral circuit structure DPST and the upper peripheral circuit structure UPST, as well as the first memory cell structure CST1 and the second memory cell structure CST2, have a mirror-symmetric structure in the vertical direction (Z direction) with respect to the bonding structure BDDI.

[0090] Multiple upper contact plugs CTA penetrate the upper cover insulating layer CDU and the interlayer insulating layer ILD of the second memory cell structure CST2, and are electrically connected to multiple upper wiring lines PMLU. Multiple lower contact plugs CTB penetrate the lower cover insulating layer CDD and the interlayer insulating layer ILD of the first memory cell structure CST1, and are electrically connected to multiple lower wiring lines PMLD. Multiple vertical through-electrodes TSV penetrate the upper wiring insulating layer IMDU, the upper semiconductor substrate PSUBU, the bonding structure BDDI, and the lower semiconductor substrate PSUBD and the lower wiring insulating layer IMDD, and electrically connect multiple lower wiring lines PMLD to multiple upper wiring lines PMLU.

[0091] In some embodiments, with reference to Figures 6 and 7, the upper peripheral circuit structure UPST included in the semiconductor memory element 5 may be modified to be placed on the second memory cell structure CST2. For example, the upper peripheral circuit structure UPST placed on the second memory cell structure CST2 may have a face-up structure, similar to the upper peripheral circuit structure UPST shown in Figure 6. For example, the upper peripheral circuit structure UPST placed on the second memory cell structure CST2 may have a face-down structure, similar to the upper peripheral circuit structure UPST shown in Figure 7. In addition, in some embodiments, it is also possible to modify the semiconductor memory element 5 by inverting the first memory cell structure CST1 or the second memory cell structure CST2.

[0092] Figures 12A and 12B are cross-sectional views of a semiconductor memory element according to one embodiment of the present invention.

[0093] Referring to both Figures 12A and 12B, the semiconductor memory element 6 includes a lower peripheral circuit structure DPST, a first memory cell structure CST1, an upper peripheral circuit structure UPST, and a second memory cell structure CST2, which are stacked sequentially along the vertical direction. A bonding structure BDDI is interposed between the first memory cell structure CST1 and the upper peripheral circuit structure UPST. A lower wiring structure BPST is positioned below the lower peripheral circuit structure DPST, and an upper wiring structure FPST is positioned above the second memory cell structure CST2. The lower wiring structure BPST, lower peripheral circuit structure DPST, first memory cell structure CST1, bonding structure BDDI, upper peripheral circuit structure UPST, second memory cell structure CST2, and upper wiring structure FPST are superimposed on each other in the vertical direction. The lower peripheral circuit structure DPST and the upper peripheral circuit structure UPST are electrically connected via a plurality of vertical through-electrodes TSV and the first memory cell structure CST1. The upper peripheral circuit structure UPST has a face-up structure, and the lower peripheral circuit structure DPST also has a face-up structure.

[0094] The first memory cell structure CST1 and the second memory cell structure CST2 have substantially the same structure. For example, each of the first memory cell structure CST1 and the second memory cell structure CST2 has substantially the same structure as the memory cell structure CSTA shown in Figures 10A and 10B. The semiconductor memory element 6 shown in Figures 12A and 12B has the same structure as the semiconductor memory element 4 shown in Figures 10A and 10B, where the first memory cell structure CST1 is inserted between the lower peripheral circuit structure DPST and the upper peripheral circuit structure UPST, and the second memory cell structure CST2 has the same structure as the memory cell structure CSTA, so a redundant explanation is omitted. Each of the first memory cell structure CST1 and the second memory cell structure CST2 shares the lower peripheral circuit structure DPST and the upper peripheral circuit structure UPST.

[0095] Multiple upper contact plugs CTA penetrate the upper cover insulating layer CDU and the interlayer insulating layer ILD of the second memory cell structure CST2, and are electrically connected to multiple upper wiring lines PMLU. Multiple lower contact plugs CTB penetrate the lower cover insulating layer CDD, the lower semiconductor substrate PSUBD, and the lower wiring insulating layer IMDD, and are electrically connected to multiple lower wiring lines PMLD. The first memory cell structure CST1 further includes multiple through-electrode pads TSPD positioned on multiple third word lines WL3, which are located at the uppermost end of multiple first word lines WL1, multiple second word lines WL2, and multiple third word lines WL3. Multiple through-electrode pads TSPD are electrically connected to multiple third word lines WL3. The interlayer insulating layer ILD included in the first memory cell structure CST1 covers the multiple through-electrode pads TSPD. The lower surface of the bonding structure BDDI is in contact with the upper surface of the interlayer insulating layer ILD included in the first memory cell structure CST1 and the upper surfaces of the multiple through-electrode pads TSPD. Multiple vertical through-electrode (TSV) elements penetrate the upper wiring insulation layer (IMDU), the upper semiconductor substrate (PSUBU), and the bonding structure (BDDI), and are electrically connected to multiple through-electrode pads (TSPD). Multiple upper wiring lines (PMLU) are electrically connected to multiple lower wiring lines (PMLD) via multiple vertical through-electrode (TSV), multiple through-electrode pads (TSPD), and multiple memory cells (MC) included in the first memory cell structure (CST1). In some embodiments, the first memory cell structure (CST1) may further include multiple served vertical through-electrodes that penetrate the interlayer insulation layer (ILD) and electrically connect multiple through-electrode pads (TSPD) and multiple lower wiring lines (PMLD). For example, multiple upper wiring lines (PMLU) are electrically connected to multiple lower wiring lines (PMLD) via multiple vertical through-electrode (TSV), multiple through-electrode pads (TSPD), and multiple served vertical through-electrodes.

[0096] In some embodiments, the upper peripheral circuit structure UPST included in the semiconductor memory element 6 may be modified to be placed on the second memory cell structure CST2. For example, the upper peripheral circuit structure UPST placed on the second memory cell structure CST2 may have a face-up structure, similar to the upper peripheral circuit structure UPST shown in Figure 6. For example, the upper peripheral circuit structure UPST placed on the second memory cell structure CST2 may have a face-down structure, similar to the upper peripheral circuit structure UPST shown in Figure 7. In addition, in some embodiments, it is also possible to modify the semiconductor memory element 6 by inverting the first memory cell structure CST1 or the second memory cell structure CST2.

[0097] Although the present invention has been described in detail above with respect to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications and alterations are possible by those with ordinary skill in the art within the technical spirit and scope of the present invention. [Explanation of symbols]

[0098] 1, 1a, 2, 2a, 3, 4, 5, 6 Semiconductor memory elements CST, CSTA memory cell structure CST1 First Memory Cell Structure CST2 Second Memory Cell Structure DPST Lower Peripheral Circuit Structure UPST Upper Peripheral Circuitry Structure BDDI bonding structure FPST Upper Wiring Structure BPST Lower Wiring Structure WL Wardline BL Bitline MC memory cell SLT Selector EL1 First Select Electrode Layer SML Selective Material Layer EL2 Second Selective Electrode Layer TSV vertical through electrode ILD (Interlayer Insulation Layer) PSUBD Lower Semiconductor Substrate PSUBU Upper Semiconductor Substrate STID lower element isolation membrane STIU upper element isolation membrane PMLD lower wiring line PMLU Upper Wiring Line PMCD Lower Wiring Contacts PMCU Upper Wiring Contacts IMDD lower wiring insulation layer IMDU upper wiring insulation layer PGLD Lower Food Service PGLU Upper Terminal PGoxD lower gate dielectric film PGoxU upper gate dielectric film SDD Lower Source-Drain Region SDU Upper Source-Drain Region WLC Wordline Contact BLC Bitline Contact CDU upper cover insulation layer CDD lower cover insulating layer CTA Upper Contact Plug CTB Lower Contact Plug LX-R Lower Local Wordline Selection Transistor LY-R Lower Local Bitline Selection Transistor LX-F Upper Local Word Line Selection Transistor LY-F Upper Local Bitline Selection Transistor

Claims

1. Lower peripheral circuit structure, Upper peripheral circuit structure, Memory cell structure, The lower peripheral circuit structure and the upper peripheral circuit structure are electrically connected by a plurality of vertical through electrodes, The lower peripheral circuit structure, the upper peripheral circuit structure, and the memory cell structure are superimposed on each other in the vertical direction. The memory cell structure includes a plurality of word lines extended in a first horizontal direction, a plurality of bit lines extended in a second horizontal direction different from the first horizontal direction, and a plurality of selectors interposed between the plurality of word lines and the plurality of bit lines, which constitute a plurality of memory cells. The lower peripheral circuit structure includes a lower semiconductor substrate and a plurality of lower transistors arranged on the lower semiconductor substrate. The upper peripheral circuit structure includes an upper semiconductor substrate and a plurality of upper transistors arranged on the upper semiconductor substrate. Each of the plurality of word lines is electrically connected to one of the plurality of lower transistors, which overlaps at least a portion of the vertical direction, and to a corresponding upper transistor among the plurality of upper transistors. A semiconductor memory element characterized in that each of the plurality of bit lines is electrically connected to one other lower transistor of the plurality of lower transistors, at least a portion of which is superimposed in the vertical direction, and to a corresponding other upper transistor of the plurality of upper transistors.

2. On the upper peripheral circuit structure, an upper wiring structure including an upper cover insulating layer and a plurality of upper contact plugs that penetrate the upper cover insulating layer and are electrically connected to the upper peripheral circuit structure, The semiconductor memory element according to claim 1, further comprising, below the lower peripheral circuit structure, a lower wiring structure including a lower cover insulating layer and a plurality of lower contact plugs that penetrate the lower cover insulating layer and are electrically connected to the lower peripheral circuit structure.

3. The lower peripheral circuit structure includes the lower semiconductor substrate, the plurality of lower transistors arranged on the lower semiconductor substrate, the plurality of lower wiring lines, the plurality of lower wiring contacts electrically connecting the plurality of lower wiring lines and the plurality of lower transistors, and the upper wiring insulating layer covering the plurality of lower transistors, the plurality of lower wiring lines and the plurality of lower wiring contacts. The upper peripheral circuit structure includes the upper semiconductor substrate, the plurality of upper transistors arranged on the upper semiconductor substrate, the plurality of upper wiring lines, the plurality of upper wiring contacts that electrically connect the plurality of upper wiring lines and the plurality of upper transistors, and a lower wiring insulating layer that covers the plurality of upper transistors, the plurality of upper wiring lines and the plurality of upper wiring contacts. The plurality of vertical through electrodes connect the plurality of lower wiring lines and the plurality of upper wiring lines, The plurality of upper contact plugs are connected to the plurality of upper wiring lines, The semiconductor memory element according to claim 2, characterized in that the plurality of lower contact plugs are connected to the plurality of lower wiring lines.

4. The bonding structure, which is interposed between the lower peripheral circuit structure and the upper peripheral circuit structure, further includes an insulating material, The semiconductor memory element according to claim 1, characterized in that the plurality of vertical through electrodes extend through the bonding structure.

5. The semiconductor memory element according to claim 1, characterized in that each of the plurality of selectors includes a selection material layer, a first selection electrode layer interposed between the selection material layer and each of the plurality of bit lines, and a second selection electrode layer interposed between each of the plurality of word lines and the selection material layer.

6. A lower peripheral circuit structure comprising a lower semiconductor substrate, a plurality of lower local word line selection transistors and a plurality of lower local bit line selection transistors, wherein the plurality of lower local word line selection transistors and the plurality of lower local bit line selection transistors are arranged on the lower semiconductor substrate, The lower peripheral circuit structure includes an upper semiconductor substrate, a plurality of upper local word line selection transistors, and a plurality of upper local bit line selection transistors, wherein the plurality of upper local word line selection transistors and the plurality of upper local bit line selection transistors are arranged on the upper semiconductor substrate, On the upper peripheral circuit structure, a memory cell structure including a plurality of word lines extended in a first horizontal direction, a plurality of bit lines extended in a second horizontal direction different from the first horizontal direction from a vertical level different from the plurality of word lines, a plurality of selectors interposed between the plurality of word lines and the plurality of bit lines and constituting a plurality of memory cells, and an interlayer insulating layer covering the plurality of word lines, the plurality of bit lines, and the plurality of memory cells, Below the lower peripheral circuit structure, a lower wiring structure including a lower cover insulating layer and a plurality of lower contact plugs that penetrate the lower cover insulating layer and are electrically connected to the lower peripheral circuit structure, On the memory cell structure, an upper wiring structure including an upper cover insulating layer and a plurality of upper contact plugs that penetrate the upper cover insulating layer and are electrically connected to the upper peripheral circuit structure, The lower peripheral circuit structure and the upper peripheral circuit structure are electrically connected by a plurality of vertical through electrodes, Each of the plurality of word lines is electrically connected to one of the plurality of lower local word line selection transistors, which overlaps at least a portion of the lower local word line selection transistors in the vertical direction, and to a corresponding upper local word line selection transistor from the plurality of upper local word line selection transistors. A semiconductor memory element characterized in that each of the plurality of bit lines is electrically connected to one lower local bit line selection transistor from the plurality of lower local bit line selection transistors, at least a portion of which are superimposed in the vertical direction, and to a corresponding upper local bit line selection transistor from the plurality of upper local bit line selection transistors.

7. The lower peripheral circuit structure includes the lower semiconductor substrate, the plurality of lower local word line selection transistors and the plurality of lower local bit line selection transistors arranged on the lower semiconductor substrate, the plurality of lower wiring lines, the plurality of lower wiring contacts that electrically connect the plurality of lower wiring lines, the plurality of lower local word line selection transistors and the plurality of lower local bit line selection transistors, and the lower wiring insulating layer that covers the plurality of lower wiring lines and the plurality of lower wiring contacts. The upper peripheral circuit structure includes the upper semiconductor substrate, the plurality of upper local word line selection transistors and the plurality of upper local bit line selection transistors arranged on the upper semiconductor substrate, the plurality of upper wiring lines, the plurality of upper wiring contacts that electrically connect the plurality of upper wiring lines, the plurality of upper local word line selection transistors and the plurality of upper local bit line selection transistors, and the upper wiring insulating layer that covers the plurality of upper wiring lines and the plurality of upper wiring contacts. The plurality of lower contact plugs are connected to the plurality of lower wiring lines, The semiconductor memory element according to claim 6, characterized in that the plurality of upper contact plugs are connected to the plurality of upper wiring lines.

8. The plurality of vertical through electrodes connect the plurality of lower wiring lines and the plurality of upper wiring lines, The semiconductor memory element according to claim 7, characterized in that each of the plurality of vertical through electrodes electrically connects each of the plurality of word lines to one lower local word line selection transistor from the plurality of lower local word line selection transistors and a corresponding upper local word line selection transistor from the plurality of upper local word line selection transistors, or electrically connects each of the plurality of bit lines to one lower local bit line selection transistor from the plurality of lower local bit line selection transistors and a corresponding upper local bit line selection transistor from the plurality of upper local bit line selection transistors.

9. Each of the plurality of vertical through electrodes penetrates the lower wiring insulating layer, the lower semiconductor substrate, the upper semiconductor substrate, and the upper wiring insulating layer from the plurality of lower wiring lines to the plurality of upper wiring lines, and has a tapered shape in which the horizontal width decreases. Each of the plurality of upper contact plugs has a tapered shape that penetrates the upper cover insulating layer and the interlayer insulating layer and extends to the plurality of upper wiring lines with decreasing horizontal width. The semiconductor memory element according to claim 7, characterized in that each of the plurality of lower contact plugs has a tapered shape that penetrates the lower cover insulating layer and extends to the plurality of lower wiring lines with decreasing horizontal width.

10. A lower peripheral circuit structure comprising a lower semiconductor substrate, a plurality of lower local word line selection transistors and a plurality of lower local bit line selection transistors arranged on the lower semiconductor substrate, a plurality of lower wiring lines, a plurality of lower wiring contacts electrically connecting the plurality of lower wiring lines, the plurality of lower local word line selection transistors, and the plurality of lower local bit line selection transistors, and a lower wiring insulating layer covering the plurality of lower wiring lines and the plurality of lower wiring contacts, The upper peripheral circuit structure includes an upper semiconductor substrate, a plurality of upper local word line selection transistors and a plurality of upper local bit line selection transistors arranged on the upper semiconductor substrate, a plurality of upper wiring lines, a plurality of upper wiring contacts electrically connecting the plurality of upper wiring lines, the plurality of upper local word line selection transistors and the plurality of upper local bit line selection transistors, and an upper wiring insulating layer covering the plurality of upper wiring lines and the plurality of upper wiring contacts. A memory cell structure comprising, on the upper peripheral circuit structure, a plurality of word lines extended in a first horizontal direction, a plurality of bit lines extended in a second horizontal direction different from the first horizontal direction on the plurality of word lines, a plurality of selectors interposed between the plurality of word lines and the plurality of bit lines, each including a selection material layer, a first selection electrode layer interposed between the selection material layer and each of the plurality of bit lines, and a second selection electrode layer interposed between each of the plurality of word lines and the selection material layer, a plurality of word line contacts connecting the plurality of word lines and the plurality of upper wiring lines, a plurality of bit line contacts connecting the plurality of bit lines and the plurality of upper wiring lines, and an interlayer insulating layer covering the plurality of word line contacts, the plurality of bit line contacts, the plurality of word lines, the plurality of bit lines, and the plurality of selectors, Below the lower peripheral circuit structure, a lower wiring structure including a lower cover insulating layer and a plurality of lower contact plugs that penetrate the lower cover insulating layer and are electrically connected to the plurality of lower wiring lines, On the memory cell structure, an upper wiring structure including an upper cover insulating layer and a plurality of upper contact plugs that penetrate the upper cover insulating layer and are electrically connected to the plurality of upper wiring lines, The lower wiring insulating layer, the lower semiconductor substrate, the upper semiconductor substrate, and a plurality of vertical through electrodes that penetrate the upper wiring insulating layer and connect the plurality of lower wiring lines and the plurality of upper wiring lines are included, Each of the plurality of word lines is electrically connected to one of the plurality of lower local word line selection transistors, which overlaps at least a portion of the plurality of lower local word line selection transistors in the vertical direction, and to a corresponding upper local word line selection transistor from the plurality of upper local word line selection transistors. A semiconductor memory element characterized in that each of the plurality of bit lines is electrically connected to one of the plurality of lower local bit line selection transistors, at least a portion of which overlap in the vertical direction, and to a corresponding upper local bit line selection transistor from the plurality of upper local bit line selection transistors.

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