Light source device and distance measuring device

Abstract

The present invention provides a light source device that can improve the uniformity of light emission in multiple semiconductor light-emitting elements. [Solution] The light source device comprises a plurality of semiconductor light-emitting elements, each having a first reflector, a first semiconductor resonator including a first active layer, a second reflector, and a first electrode in this order on the first surface side of the semiconductor substrate, and a second electrode on the second surface opposite to the first surface of the semiconductor substrate. The power supply pad is for supplying power to the plurality of semiconductor light-emitting elements. Wiring connects each of the plurality of semiconductor light-emitting elements to the power supply pad. The plurality of semiconductor light-emitting elements are divided into a plurality of groups, each having at least one semiconductor light-emitting element, according to the distance from the power supply pad. The plurality of semiconductor light-emitting elements are configured such that the resistance between the first electrode and the second electrode is larger for semiconductor light-emitting elements in groups that are closer to the power supply pad.

Description

[Technical Field]

[0001] This invention relates to a light source device and a distance measuring device. [Background technology]

[0002] Conventionally, Time of Flight (ToF) LiDAR (Light Detection and Ranging) systems have been known as distance measuring devices for measuring the distance to an object. For LiDAR systems, VCSELs (Vertical Cavity Surface Emitting Lasers) are preferred as light sources due to their advantages, such as low wavelength dependence with respect to temperature.

[0003] Light sources for LiDAR systems are sometimes configured to support flash driving, where multiple semiconductor light-emitting elements are arranged in an array and the entire surface is illuminated simultaneously, because higher power results in a longer measuring distance. Furthermore, light sources for LiDAR systems may also be configured to support sequential driving, where one or several rows are illuminated sequentially. For example, Patent Document 1 describes an example where the number of semiconductor light-emitting elements is between 100 and 1000, and states that increasing the number of semiconductor light-emitting elements increases the output.

[0004] In LiDAR systems, increasing the output of the semiconductor light-emitting element also increases power consumption. Therefore, measures are taken to reduce power consumption by lowering the element resistance. For example, Patent Document 2 discloses an example of lowering element resistance by increasing the doping concentration of the upper reflector, which is the current path within the semiconductor light-emitting element. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2021-136307 [Patent Document 2] Japanese Patent Publication No. 2021-136319 [Overview of the project] [Problems that the invention aims to solve]

[0006] However, when a light source device having multiple semiconductor light-emitting elements was configured using the above-mentioned conventional technology, the light emission from each semiconductor light-emitting element was sometimes not uniform.

[0007] Therefore, the object of the present invention is to provide a light source device that can improve the uniformity of light emission in multiple semiconductor light-emitting elements. [Means for solving the problem]

[0008] According to one disclosure of this specification, a light source device is provided comprising: a plurality of semiconductor light-emitting elements, each having, in this order, a first reflector, a first semiconductor resonator including a first active layer, a second reflector, and a first electrode on the side of a first surface of a semiconductor substrate, and a second electrode on the second surface of the semiconductor substrate opposite to the first surface; a power supply pad for supplying power to the plurality of semiconductor light-emitting elements; and wiring connecting each of the plurality of semiconductor light-emitting elements to the power supply pad, wherein the plurality of semiconductor light-emitting elements are divided into a plurality of groups, each having at least one of the semiconductor light-emitting elements, according to the distance from the power supply pad, and the resistance between the first electrode and the second electrode is larger for semiconductor light-emitting elements in groups that are closer to the power supply pad. [Effects of the Invention]

[0009] According to the present invention, a light source device can be realized that can improve the uniformity of light emission in multiple semiconductor light-emitting elements. [Brief explanation of the drawing]

[0010] [Figure 1] This is a plan view showing an example configuration of a VCSEL array according to the first embodiment. [Figure 2]It is a cross-sectional view showing a configuration example of a VCSEL according to the first embodiment. [Figure 3] It is a diagram showing an example of the material of a semiconductor layer added to the VCSEL according to the first embodiment and the increase rate of the resistance value due to the addition of the semiconductor layer. [Figure 4] It is a plan view showing a configuration example of a VCSEL array according to a comparative example. [Figure 5] It is a diagram showing the current distribution in each VCSEL array according to the first and second embodiments. [Figure 6] It is a cross-sectional view showing a configuration example of an epitaxial wafer according to the first embodiment. [Figure 7] It is a cross-sectional view showing the manufacturing process of a VCSEL array according to the first embodiment. [Figure 8] It is a cross-sectional view showing the manufacturing process of a VCSEL array according to the first embodiment. [Figure 9] It is a cross-sectional view showing a configuration example of an epitaxial wafer according to the second embodiment. [Figure 10] It is a cross-sectional view showing a configuration example of a VCSEL according to the second embodiment. [Figure 11] It is a plan view showing a configuration example of a VCSEL array according to the third embodiment. [Figure 12] It is a cross-sectional view showing a configuration example of a VCSEL according to the third embodiment. [Figure 13] It is a diagram showing the relationship between the width of an insulating opening and the multiple of resistance according to the third embodiment. [Figure 14] It is a diagram showing the current distribution in each VCSEL array according to the third and fourth embodiments. [Figure 15] It is a plan view showing a configuration example of a VCSEL array according to the fourth embodiment. [Figure 16] It is a diagram showing the relationship between the width of an insulating opening and the resistance value according to the fourth embodiment. [Figure 17] It is a diagram showing the relationship between the current density and the pulse generation timing according to the fifth embodiment. [Figure 18] It is a diagram showing the relationship between the current density and the pulse delay time according to the fifth embodiment. [Figure 19] This is a plan view showing an example configuration of a VCSEL array according to the fifth embodiment. [Figure 20] This is a cross-sectional view showing an example configuration of a high peak-value VCSEL according to the fifth embodiment. [Figure 21] This is a plan view showing an example configuration of a VCSEL array according to the sixth embodiment. [Figure 22] This is a cross-sectional view showing an example configuration of a VCSEL according to the sixth embodiment. [Figure 23] This figure shows the relationship between the area of ​​the non-oxidizing region and the resistance value according to the sixth embodiment. [Figure 24] This is a plan view showing an example configuration of a VCSEL array according to the seventh embodiment. [Figure 25] This figure shows the relationship between the width of the non-oxidizing region and the resistance value according to the 8th embodiment. [Figure 26] This figure shows the current distribution in each VCSEL array according to the 8th embodiment. [Figure 27] This is a plan view showing an example configuration of a VCSEL array according to the 9th embodiment. [Figure 28] This is a cross-sectional view showing an example of the configuration of a VCSEL according to the 9th embodiment. [Figure 29] This is a cross-sectional view showing an example configuration of a VCSEL array according to the 10th embodiment. [Figure 30] This is a block diagram showing an example configuration of a distance measuring device according to the 11th embodiment. [Modes for carrying out the invention]

[0011] [First Embodiment] A VCSEL array (light source device) 100 according to the first embodiment will be described. The VCSEL array 100 is a semiconductor laser comprising a plurality of VCSELs 1 arranged in an array, with each VCSEL 1 emitting laser light. Here, "array" refers to a state in which a plurality of VCSELs 1 are arranged in two dimensions according to a predetermined pattern.

[0012] In the following explanation, the first direction (row direction) when arranging multiple VCSEL1s in an array is referred to as the X direction. The second direction (column direction) when arranging multiple VCSEL1s in an array is referred to as the Y direction. The direction intersecting the X and Y directions is referred to as the Z direction. The X, Y, and Z directions are typically orthogonal to each other.

[0013] The VCSEL array 100 comprises, for example, multiple VCSELs 1 as semiconductor light-emitting elements, multiple anode wirings 101 as wiring, and multiple anode power supply pads 102 as power supply pads, as shown in Figure 1. In Figure 1, four VCSELs on one side in the Y direction and three on the other side in the Y direction are shown.

[0014] Each of the multiple VCSEL1s is a vertical-cavity surface-emitting laser with a distributed Bragg reflector (DBR). The multiple VCSEL1s are arranged in an array across multiple rows and columns. For example, 20 VCSEL1s are arranged in a single row along the Y direction, and 20 of these Y-direction arrays are arranged along the X direction. This results in a total of 400 (20 x 20) VCSEL1s arranged in an array, forming a rectangular shape when viewed from the Z direction.

[0015] The multiple anode wires 101 are wires that connect each of the multiple VCSELs 1 to the anode power supply pad 102. Each of the multiple anode wires 101 extends along the Y direction and is arranged in a line along the X direction. One anode wire 101 is electrically connected to 20 VCSELs 1 along the Y direction. In other words, the 20 VCSELs 1 along the Y direction are connected in parallel to one anode wire 101. And 20 such anode wires 101 are arranged in a line along the X direction. In this way, the multiple anode wires 101 are configured as sequential anode wires. Each anode wire 101 supplies current to the 20 VCSELs 1 connected in parallel.

[0016] The anode power supply pad 102 is a part for connecting the Au wire (not shown). The anode power supply pad 102 is a power supply pad for supplying power to multiple VCSELs 1 and is provided at one end of the anode wiring 101 in the Y direction. The anode power supply pad 102 has the role of supplying current supplied from the outside via the Au wire to the anode wiring 101.

[0017] As described above, the VCSEL array 100 can emit light from 400 VCSELs 1 by supplying current from an external source via Au wires to 20 anode power supply pads 102. Furthermore, by sequentially supplying current from an external source to the 20 anode power supply pads 102, sequential drive can be performed in which each row emits light at a different timing.

[0018] Here, the plurality of VCSEL1 according to the first embodiment are composed of a VCSEL1A as a semiconductor light-emitting element and a VCSEL1B as a semiconductor light-emitting element. In the following description, when there is no need to distinguish between VCSEL1A and VCSEL1B, they may simply be referred to as "VCSEL1".

[0019] As shown in Figure 2(b), VCSEL1B comprises an n-type GaAs substrate 10 as a semiconductor substrate, a first DBR 20 as a first reflector, a semiconductor resonator 30 as a first semiconductor resonator, and a second DBR 40 as a second reflector. Furthermore, VCSEL1B comprises an insulating film 50, an upper ring electrode 60 as a first electrode, and a back electrode 70 as a second electrode. The first DBR 20, the semiconductor resonator 30, the second DBR 40, and the upper ring electrode 60 are stacked in this order on the first surface of the n-type GaAs substrate 10. The back electrode 70 is provided on the second surface of the n-type GaAs substrate 10, opposite to the first surface. In Figure 2(b), these components of VCSEL1B are in direct contact, but other components may be provided between them. Also, the above description is a description of the structure and does not limit the manufacturing order of each component. Note that Figure 2(b) is a cross-sectional view taken along the line V2-V2 in Figure 1.

[0020] The n-type GaAs substrate 10 is a substrate made of an n-type GaAs single crystal. The n-type GaAs substrate 10 has a first surface on which various components are laminated, and a second surface located on the opposite side of the first surface in the Z direction.

[0021] The first DBR20 is provided on the first surface of the n-type GaAs substrate 10. The first DBR20 has an optical film thickness of 1 / 4λc Al 0.1 GaAs layer and Al 0.9 It is constructed by stacking 35 pairs of GaAs layers, with each pair representing one layer. Here, λc is the central wavelength of the high-reflection band of the second DBR40, for example, 940 nm.

[0022] The semiconductor resonator 30 is placed on the first DBR 20 and consists of an n-type AlGaAs layer, a first active layer, and a p-type layer, starting from the first DBR 20 side. The first active layer is an undoped layer and contains three quantum well layers 31. Each of the three quantum well layers 31 consists of an 8 nm thick InGaAs well layer and a 10 nm thick AlGaAs barrier layer sandwiching it.

[0023] The second DBR40 is mounted on top of the semiconductor resonator 30 and has an optical film thickness of 1 / 4λc Al 0.1 GaAs layer and Al 0.9 The DBR is constructed by stacking 20 pairs of GaAs layers, with each pair forming one. A current-constricting layer 41 with a thickness of 30 nm is provided inside the second DBR 40. During the manufacturing process, this current-constricting layer 41 is partially oxidized from the mesa lateral direction (X direction, Y direction) by exposure to a water vapor atmosphere. The current-constricting layer 41 is divided into an oxidized region of a predetermined width from the mesa sidewall and a non-oxidized region near the center of the mesa. Since the current injected into VCSEL1B flows only through the non-oxidized region, only the central part of VCSEL1B oscillates. The upper ring electrode 60 is electrically in contact with the second DBR 40. The uppermost layer of the second DBR 40 is Al 0.1 A portion of the GaAs layer has a thickness of 50 nm and a carrier concentration of 1 × 10⁻¹⁶. 19 cm -3 The GaAs contact layer has been replaced. As a result, the second DBR 40 improves the electrical contact with the upper ring electrode 60. Note that the semiconductor resonator 30 and the second DBR 40, which are layers above the first DBR 20, have a portion of their surface removed during the manufacturing process, and the remaining portion is configured in a mesa shape.

[0024] The insulating film 50 covers the semiconductor resonator 30 and the second DBR 40, which are configured in a mesa shape, and suppresses their deterioration.

[0025] The upper ring electrode 60 is mounted on the second DBR 40 and is electrically connected to the anode wiring 101. The upper ring electrode 60 has an annular conductive pattern, and the central opening serves as a circular window for light extraction. The upper ring electrode 60 makes ohmic contact with the second DBR 40 through a portion of the insulating film 50 that has been partially removed.

[0026] The back electrode 70 is conductive and is provided on the second surface of the n-type GaAs substrate 10. The back electrode 70 is in ohmic contact with the n-type GaAs substrate 10.

[0027] In the VCSEL1B configured in this way, when current is applied to the upper ring electrode 60 via the anode wiring 101, current flows through the upper ring electrode 60 to the semiconductor resonator 30, thereby generating light in the semiconductor resonator 30. The light generated in the semiconductor resonator 30 then resonates between the first DBR20 and the second DBR40, causing laser oscillation, and the oscillating laser light is emitted from the central opening of the upper ring electrode 60 along the Z direction.

[0028] Next, VCSEL1A will be described. VCSEL1A differs from VCSEL1B in that it includes a semiconductor layer 80, but otherwise has the same configuration as VCSEL1B. That is, as shown in Figure 2(a), VCSEL1A comprises an n-type GaAs substrate 10, a first DBR 20, a semiconductor resonator 30, a second DBR 40, an insulating film 50, an upper ring electrode 60, a back electrode 70, and a semiconductor layer 80. The first DBR 20, the semiconductor resonator 30, the second DBR 40, the semiconductor layer 80, and the upper ring electrode 60 are stacked in this order on the first surface of the n-type GaAs substrate 10. The back electrode 70 is provided on the second surface of the n-type GaAs substrate 10, opposite to the first surface. Note that Figure 2(a) is a cross-sectional view taken along line V1-V1 in Figure 1. Since the n-type GaAs substrate 10, the first DBR 20, the semiconductor resonator 30, the second DBR 40, the insulating film 50, the upper ring electrode 60, and the back electrode 70 have the same configuration as the VCSEL1B described above, a detailed explanation is omitted.

[0029] The semiconductor layer 80 is for setting the resistance value (device resistance value) between the upper ring electrode 60 and the back electrode 70 of the VCSEL 1A to a value different from the resistance value between the upper ring electrode 60 and the back electrode 70 of the VCSEL 1B. The semiconductor layer 80 is provided between the upper ring electrode 60 and the second DBR 40. In other words, the semiconductor layer 80 is laminated on the opposite side of the semiconductor resonator 30 of the second DBR 40 in the Z direction. By having the semiconductor layer 80, the VCSEL 1A has a larger series resistance component between the upper ring electrode 60 and the second DBR 40 than the VCSEL 1B. That is, the VCSEL 1A is formed such that the distance between the upper ring electrode 60 and the back electrode 70 is longer than that of the VCSEL 1B, and due to this longer distance, the resistance value between the upper ring electrode 60 and the back electrode 70 is larger than that of the VCSEL 1B. The resistance value of the VCSEL 1A can be changed by changing the material, composition, and film thickness of the semiconductor layer 80.

[0030] As described above, the VCSEL 1A has the semiconductor layer 80 between the upper ring electrode 60 and the second DBR 40, while the VCSEL 1B does not have the semiconductor layer 80 between the upper ring electrode 60 and the second DBR 40. In other words, the VCSEL 1A has a predetermined thickness where the film thickness of the semiconductor layer 80 is greater than 0, while the VCSEL 1B has a film thickness of 0 for the semiconductor layer 80. As a result, the resistance values between the upper ring electrode 60 and the back electrode 70 of the VCSEL 1A and the VCSEL 1B are different from each other. Let the first resistance value between the upper ring electrode 60 and the back electrode 70 of the VCSEL 1A be R1, and the second resistance value between the upper ring electrode 60 and the back electrode 70 of the VCSEL 1B be R2. Then, R1 > R2. That is, the VCSEL 1A has a larger resistance value than the VCSEL 1B.

[0031] FIG. 3 is a diagram showing material examples of the semiconductor layer 80 and their various electrical characteristics. In the figure, the increase rate of the device resistance value indicates the increase rate of the resistance value per 1 μm thickness. The doping concentration in each material is 1×10 17 cm -3This is assumed. By placing a semiconductor layer 80 on top of the second DBR40, the resistance of VCSEL1A can be increased. The semiconductor layer 80 has a carrier concentration of 1 × 10⁻¹⁰ 17 cm -3 AlInP is layered to a thickness of 0.38 μm, and on top of that, a layer with a thickness of 50 nm and a carrier concentration of 1 × 10⁻¹⁶ is applied. 19 cm -3 The device has a two-layer structure with a GaAs contact layer. The thickness of the semiconductor layer 80 is preferably selected from an integer multiple of λc / 2 in order to suppress the optical effects caused by the addition of this layer. In the first embodiment, the thickness of the AlInP layer is set to 403 nm, so the optical thickness of the semiconductor layer 80 is set to 3 × λc / 2. With this configuration, the resistance value of VCSEL1A can be made 1.33 times that of VCSEL1B.

[0032] In the VCSEL array 100, the arrangement of two types of VCSELs 1A and 1B with different resistance values ​​is designed to ensure that the current injected into each VCSEL 1A and 1B is more uniform. Here, the multiple VCSELs 1 are divided into multiple groups according to the wiring resistance to the anode power supply pad 102. For example, the multiple VCSELs 1 can be divided into multiple groups according to the distance to the anode power supply pad 102. The multiple groups may consist of, for example, a first group and a second group. The first group may consist of VCSELs 1 that are closer to the anode power supply pad 102 than the second group. The second group may consist of VCSELs 1 that are further away from the anode power supply pad 102 than the first group. Here, the VCSELs 1 in the first group and the VCSELs 1 in the second group have different resistance values. That is, the VCSELs 1 in the second group have lower resistance values ​​than the VCSELs 1 in the first group. In other words, the VCSELs 1 in the first group have higher resistance values ​​than the VCSELs 1 in the second group. Thus, the VCSELs in groups with shorter distances from the anode power supply pad 102 are configured to have higher resistance values. For example, the VCSELs in groups with lower wiring resistance to the anode power supply pad 102 are configured to have higher resistance values. Specifically, the first group of VCSELs, which are short distances from the anode power supply pad 102, are configured as VCSEL1A, and the second group of VCSELs, which are long distances from the anode power supply pad 102, are configured as VCSEL1B. More specifically, as shown in Figure 1, in the 20 VCSELs along the Y direction, the first group of VCSELs, from the 1st to the 6th VCSELs closest to the anode power supply pad 102, are configured as VCSEL1A. The remaining second group of VCSELs, from the 6th to the 20th VCSELs, are configured as VCSEL1B.

[0033] Figure 4 is a plan view showing an example configuration of a VCSEL array 900 related to a comparative example. As shown in Figure 4, the VCSEL array 900 related to the comparative example is composed of 400 VCSELs, all of which are made of one type of VCSEL1B and arranged in an array. In the VCSEL array 900 related to the comparative example, when the spacing between VCSEL1Bs is narrowed and they are arranged at high density for reasons such as reducing chip costs, it is difficult to make the wiring for supplying power to each VCSEL1B thicker. As a result, VCSEL1Bs located far from the anode power supply pad 102 and with long current paths experience a larger voltage drop due to wiring resistance compared to VCSEL1Bs located close to the anode power supply pad 102. This reduces the voltage applied between the anode and cathode of the VCSEL1B, resulting in a smaller amount of injected current. This leads to uneven current injection into each VCSEL1B of the VCSEL array 900, causing various adverse effects. For example, the power input increases in order to supply a predetermined current to the VCSEL1B with the minimum current, and variations occur in the light intensity of each VCSEL1B within the VCSEL array 900. As a result, in distance measurement applications, the signal in dark areas becomes weaker, which reduces the signal-to-noise ratio in the light-receiving unit, causing variations in distance measurement accuracy. In illumination applications, various adverse effects occur, such as affecting the uniformity of illumination within the surface.

[0034] In contrast, the VCSEL array 100 according to the first embodiment places the first group of VCSELs 1A, which have high resistance values, closer to the anode power supply pad 102 than the second group of VCSELs 1B, which have low resistance values. In other words, the current path from the anode power supply pad 102 to the high-resistance VCSEL 1A is shorter than the current path from the anode power supply pad 102 to the low-resistance VCSEL 1B. This configuration allows the resistance values ​​of each VCSEL 1A and 1B, including the resistance value of the anode wiring 101, to be closer to each other. As a result, even if a voltage drop occurs due to wiring resistance, the current injected into each VCSEL 1A and 1B can be made more uniform, and the spread of the current distribution can be suppressed. Here, the current distribution refers to the distribution of current values ​​of the current injected into each VCSEL in the VCSEL array. Since the spread of the current distribution can be suppressed, the variation in the light intensity of each VCSEL 1A and 1B is suppressed, thereby improving the uniformity of light emission in each VCSEL 1A and 1B. The uniformity of light emission from each VCSEL1A and 1B suppresses variations in the lifespan of each VCSEL1A and 1B. Furthermore, the suppression of the current distribution reduces the power input to the VCSEL array 100. Thus, the effect of reducing the power input due to suppressing the current distribution is greater than the effect of increasing the power input due to raising some of the resistors. Moreover, regarding the heat generated by the VCSEL array 100, the amount of heat generated is proportional to the product of the resistance to the power of 1 and the current value to the power of 2. Therefore, from the perspective of heat generation, the effect of reducing the current value due to suppressing the current distribution is also significant.

[0035] Figure 5 shows the current distribution in each VCSEL array. In Figure 5, the vertical axis represents the current value, and the horizontal axis represents the nth VCSEL in one array (20 VCSELs in one row) counted from the one closest to the anode power supply pad 102. In Figure 5, L2 is the current distribution of one array in the VCSEL array 100 according to the first embodiment. Figure 5 also shows the current distribution L1 of one array in the VCSEL array 900 according to a comparative example.

[0036] In the comparative example VCSEL array 900, the ratio of the maximum (MAX) to the minimum (MIN) current values ​​flowing through each VCSEL 1B in one array is 0.63 (L1 in Figure 5). Furthermore, in the VCSEL array 900, when the minimum current value required for one VCSEL 1B is set to 0.06A, the estimated current value required for one array, taking into account the variation in current values, is 1.44A, and the input power is 7.29W. In contrast, in the VCSEL array 100 according to the first embodiment, the ratio of the maximum to the minimum current values ​​flowing through each VCSEL 1A, 1B in one array is 0.76 (L2 in Figure 5). Furthermore, in the VCSEL array 100, when the minimum current value required for one VCSEL 1A, 1B is set to 0.06A, the estimated current value required for one array, taking into account the variation in current values, is 1.33A, and the input power is 6.70W. Thus, compared to the comparative example VCSEL array 900, the VCSEL array 100 has a ratio of maximum to minimum current values ​​that is close to 1.0, thus suppressing the spread of the current distribution. Furthermore, compared to the comparative example VCSEL array 900, the VCSEL array 100 can reduce the current value required per array, thereby suppressing the input power.

[0037] Next, a method for manufacturing a VCSEL array 100 containing two types of VCSELs 1A and 1B will be described. Figure 6 is a cross-sectional view showing an example of the configuration of an epitaxial wafer including the epitaxially grown portion. As shown in Figure 6, first, the first DBR 20, semiconductor resonator 30, second DBR 40, AlInP resistive layer 181 constituting the semiconductor layer 80, and second p-type GaAs contact layer 182 are sequentially epitaxially grown on the n-type GaAs substrate 10. The uppermost layer of the second DBR 40 is the first p-type GaAs contact layer 180.

[0038] Next, the manufacturing process will be explained using Figures 7 and 8. Figures 7 and 8 show cross-sections of the two VCSEL1A and VCSEL1B, extracted from the portion of Figure 1 where VCSEL1A and VCSEL1B are adjacent to each other in the Y direction. However, the same manufacturing process can be applied to other portions as well.

[0039] First, a SiOx layer 183, which will serve as a hard mask during dry etching, is deposited on the second p-type GaAs contact layer 182 by plasma CVD (Figure 7(a)).

[0040] Next, the SiOx layer 183 is patterned using photolithography and wet etching techniques. This pattern serves as the hard mask during dry etching (Figure 7(b)).

[0041] Next, a mesa structure is formed by dry etching technology. During the formation of the mesa structure, the second DBR 40, which includes the second p-type GaAs contact layer 182, the AlInP resistive layer 181, and the first p-type GaAs contact layer 180, is etched. Furthermore, the semiconductor resonator 30 is etched, and a portion of the first DBR 20 is also etched. If high-density arrangement of VCSELs 1 is desired, it is preferable to make the sidewall angle of the mesa structure as close to perpendicular to the n-type GaAs substrate 10 as possible. On the other hand, if the film formed on the sidewall of the mesa structure, such as the insulating film 50 or anode wiring 101, is adversely affected by step breaks due to the mesa step, it is preferable for the sidewall angle to be smaller than perpendicular. Therefore, the sidewall angle is appropriately selected by changing the etching conditions according to the required specifications and performance.

[0042] Next, heat treatment is performed in a water vapor atmosphere to selectively oxidize a portion of the second DBR 40 from the mesa sidewall, forming a current-constricted layer 41 (Figure 7(c)).

[0043] Next, a resist R with resist openings is formed on top of VCSEL1B using photolithography technology, selectively exposing the SiOx layer 183 on top of VCSEL1B (Figure 7(d)).

[0044] Next, the SiOx layer 183 in the region with resist openings is selectively etched by wet etching using buffered hydrofluoric acid. Furthermore, the second p-type GaAs contact layer 182 is selectively etched with a citrate-based etchant, and then the AlInP resistive layer 181 is selectively etched with a hydrochloric acid-based etchant (Figure 7(e)). After that, the resist pattern is removed (Figure 7(f)).

[0045] Next, a resist R with resist openings is formed on top of VCSEL1A using photolithography technology, selectively exposing the SiOx layer 183 on top of VCSEL1A (Figure 8(g)).

[0046] Next, the SiOx layer 183 in the region with resist openings is selectively etched by wet etching using buffered hydrofluoric acid (Figure 8(h)), and then the resist pattern is removed (Figure 8(i)).

[0047] Next, an insulating film 50 is deposited to cover the mesa structure, and openings are formed in the insulating film 50 using photolithography and etching techniques. The upper ring electrode 60 and anode wiring 101 are formed using photolithography, vacuum deposition, and lift-off techniques, and the output port is formed. Next, after polishing the back surface of the n-type GaAs substrate 10, a back surface electrode 70 is formed on the back side of the n-type GaAs substrate 10 (Figure 8(j)).

[0048] By proceeding with the above process, two types of VCSELs can be manufactured: VCSEL1A, which has a semiconductor layer 80 including an AlInP resistive layer 181, and VCSEL1B, which does not have a semiconductor layer 80.

[0049] In this embodiment, an example was described in which VCSEL1B does not have a semiconductor layer 80. However, the embodiment is not limited to this, and the current distribution can be improved compared to the comparative example by changing the resistance value of the two types of VCSELs, VCSEL1A and VCSEL1B. Specifically, VCSEL1B may have a thinner semiconductor layer 80 than VCSEL1A. The same applies to the following embodiments.

[0050] Furthermore, although this embodiment describes an example in which the power supply pad 102 is provided at one end of the anode wiring 101 in the Y direction, it is not limited to this, and the power supply pad 102 may be provided at both ends of the anode wiring 101 in the Y direction. In that case as well, the arrangement of VCSEL1A and VCSEL1B will be the same as with respect to the power supply pad 102. Specifically, VCSEL1A may be placed on the side closer to the power supply pad 102, and VCSEL1B may be placed on the side farther from the power supply pad 102 (center of the array). The same applies to the following embodiments.

[0051] [Second Embodiment] Next, a VCSEL array 100A (not shown) according to the second embodiment will be described. The VCSEL array 100A according to the second embodiment is composed of three types of VCSELs 1A, 1Aa, and 1B, each with different resistance values.

[0052] VCSEL1A, VCSEL1Aa, and VCSEL1B have different resistance values ​​between the upper ring electrode 60 and the back electrode 70. Let R1 be the first resistance value between the upper ring electrode 60 and the back electrode 70 of VCSEL1A, and R2 be the second resistance value between the upper ring electrode 60 and the back electrode 70 of VCSEL1B. Then, let R3 be the third resistance value between the upper ring electrode 60 and the back electrode 70 of VCSEL1Aa. In this case, R1 > R3 > R2. That is, the resistance value of VCSEL1Aa is smaller than the resistance value of VCSEL1A and larger than the resistance value of VCSEL1B.

[0053] In VCSEL1Aa, the semiconductor layer 80 is constructed from the side closest to the second DBR40, with a thickness of 0.25 μm and a carrier concentration of 1 × 10⁻¹⁶. 17 cm -3 The AlInP layer has a thickness of 50 nm and a carrier concentration of 1 × 10⁻¹⁶. 19 cm -3The semiconductor layer 80 has a two-layer structure consisting of a GaAs contact layer and another layer. The optical thickness of the semiconductor layer 80 is λc. With this configuration, the resistance of VCSEL1Aa is 1.2 times that of VCSEL1B. In VCSEL1A, the semiconductor layer 80 has a four-layer structure, with the same AlInP layer and GaAs contact layer as the semiconductor layer 80 of VCSEL1Aa being stacked twice, starting from the side closer to the second DBR40. The optical thickness of the semiconductor layer 80 is 2 × λc. With this configuration, the resistance of VCSEL1A is 1.4 times that of VCSEL1B.

[0054] Multiple VCSELs 1 are divided into three groups (Groups 1 to 3) according to their distance from the anode power supply pad 102. Group 3 is located between Group 1 and Group 2. Group 3 consists of VCSELs 1Aa whose resistance is smaller than VCSEL 1A of Group 1 and larger than VCSEL 1B of Group 2. In this way, the VCSEL array 100A is configured such that the resistance of the VCSELs increases as the distance from the anode power supply pad 102 decreases. That is, they are arranged in descending order of resistance from the anode power supply pad 102, in the order of Group 1 VCSEL 1A, Group 3 VCSEL 1Aa, and Group 2 VCSEL 1B. Specifically, in the 20 VCSELs along the Y direction, the first to fourth VCSELs of Group 1, which are closest to the anode power supply pad 102, consist of VCSEL 1A, which has the highest resistance. Furthermore, the 5th to 9th VCSELs in the third group are composed of VCSEL1Aa, which has the next highest resistance value, and the 10th to 20th VCSELs in the second group are composed of VCSEL1B, which has the lowest resistance value.

[0055] In the VCSEL array 100A, the ratio of the maximum to minimum current values ​​flowing through each VCSEL 1A, 1Aa, and 1B is 0.86 (L3 in Figure 5). Thus, the VCSEL array 100A according to the second embodiment can suppress the spread of current distribution more effectively than the VCSEL array 100 according to the first embodiment (L2 in Figure 5). Furthermore, in the VCSEL array 100A according to the second embodiment, when the minimum current value required for each VCSEL is 0.06A, the input power is 6.35W. As a result, the VCSEL array 100A can use less input power compared to the VCSEL array 100 according to the first embodiment, which is composed of two types of VCSELs (6.70W).

[0056] Next, a method for manufacturing a VCSEL array 100A containing three types of VCSELs 1A, 1Aa, and 1B according to the second embodiment will be described. In the second embodiment, compared to the case in which two types of VCSELs 1A and 1B according to the first embodiment are manufactured, the semiconductor layer 80 is configured as four layers during the epitaxial growth stage. Figure 9 is a cross-sectional view showing an example of the configuration of an epitaxial wafer including the epitaxial growth portion.

[0057] As shown in Figure 9, the semiconductor layer 80 is epitaxially grown in the following order: AlInP resistive layer 181, second p-type GaAs contact layer 182, AlInP resistive layer 183a, and third p-type GaAs contact layer 184.

[0058] As shown in Figure 10, for VCSEL1B, the third p-type GaAs contact layer 184, AlInP resistive layer 183a, second p-type GaAs contact layer 182, and AlInP resistive layer 181 are removed by etching. In other words, for VCSEL1B, the entire semiconductor layer 80 is removed. For VCSEL1Aa, the third p-type GaAs contact layer 184 and AlInP resistive layer 183a are removed by etching, leaving the second p-type GaAs contact layer 182 and AlInP resistive layer 181. In other words, for VCSEL1Aa, a portion of the semiconductor layer 80 is removed. For VCSEL1A, all the layers constituting the semiconductor layer 80 are left. This makes it possible to manufacture three types of VCSELs, 1A, and 1B, with different resistance values. In the second embodiment, VCSEL1A,1Aa,1B are not arranged side by side as shown in Figure 10, but for the sake of explaining the cross-sectional configuration, three types of resistor VCSELs are shown side by side in Figure 10.

[0059] [Third Embodiment] Next, the VCSEL array 100B according to the third embodiment will be described. Figure 11 is a plan view showing an example of the configuration of the VCSEL array 100B according to the third embodiment. The VCSEL array 100B according to the third embodiment includes VCSEL2A and 2B, which are different from the VCSEL1A and 1B according to the first embodiment. The VCSEL2A and 2B will be described in detail below. In the following description, the same reference numerals are used for components that are the same as those in the VCSEL1A and 1B according to the first embodiment, and their detailed descriptions are omitted.

[0060] The VCSEL array 100B comprises, for example, a plurality of VCSELs 2, an anode wiring 101, and an anode power supply pad 102, as shown in Figure 11. In Figure 11, four VCSELs on one side in the Y direction and three on the other side in the Y direction are shown among the plurality of VCSELs 2 connected to each anode wiring 101.

[0061] Twenty VCSEL2s are arranged in a single row along the Y direction, and these Y-direction rows of 20 are then arranged in a single row of 20 along the X direction. As a result, a total of 400 (20 x 20) VCSEL2s are arranged in an array, forming a rectangular shape when viewed from the Z direction.

[0062] Each anode wire 101 extends along the Y direction and multiple wires are arranged in a row along the X direction. One anode wire 101 is electrically connected to 20 VCSELs 2 along the Y direction. Twenty such anode wires 101 are arranged in a row along the X direction. Each anode wire 101 carries current through 20 VCSELs 2 connected in parallel.

[0063] The VCSEL array 100B configured in this way can emit light from 400 VCSELs 2 by supplying current from an external source via Au wires to 20 anode power supply pads 102. Furthermore, by sequentially supplying current from an external source to the 20 anode power supply pads 102, sequential drive can be performed in which each row emits light at a different timing.

[0064] Here, the VCSEL array 100B according to the third embodiment is configured to include a plurality of VCSEL2s, namely VCSEL2A and VCSEL2B. In the following description, when there is no need to distinguish between VCSEL2A and VCSEL2B, they may simply be referred to as "VCSEL2".

[0065] As shown in Figure 12, the VCSEL2A comprises an n-type GaAs substrate 10, a first DBR 20, a semiconductor resonator 30, a second DBR 40, an insulating film 50, an upper ring electrode 60, and a back electrode 70. The VCSEL2A further comprises an ITO (Indium Tin Oxide) layer 90 as a transparent conductive film. The first DBR 20, the semiconductor resonator 30, the second DBR 40, the insulating film 50, the ITO layer 90, and the upper ring electrode 60 are laminated in this order on the first surface of the n-type GaAs substrate 10. The back electrode 70 is provided on the second surface of the n-type GaAs substrate 10, opposite to the first surface. Note that Figure 12 is a cross-sectional view taken along V1-V1 of Figure 11. In Figure 12, these components of the VCSEL2A are in direct contact, but other components may be provided between them. Furthermore, the above description is a description of the structure and does not limit the order in which each component is manufactured.

[0066] The semiconductor resonator 30 and the second DBR 40 are processed into a mesa shape, and an insulating film 50 is provided on the sides and top surface of this mesa. Furthermore, an ITO layer 90 is formed on top of the insulating film 50. In other words, the ITO layer 90 covers the mesa-shaped semiconductor resonator 30 and the second DBR 40 from above the insulating film 50.

[0067] The upper surface of the second DBR 40 has a portion of the insulating film 50 partially removed in the center, and the ITO layer 90 is in contact with the upper surface of the second DBR 40 in the removed portion. The portion where the insulating film 50 has been removed is called an "insulating opening". The shape of this insulating opening is, for example, a square, and the width of the insulating opening is represented by d2 (see Figure 12). The ITO layer 90 is provided between the upper ring electrode 60 and the second DBR 40 and is in contact with the upper surface of the second DBR 40 at the insulating opening. In addition, the upper ring electrode 60 is electrically in contact with a portion of the ITO layer 90. The optical thickness of the ITO layer 90 is λc / 2.

[0068] The second DBR40 has a top layer with a thickness of 50 nm and a carrier concentration of 1 × 10⁻¹⁶ 19 cm -3It has a GaAs contact layer (not shown), which improves electrical contact with the ITO layer 90.

[0069] In the third embodiment, the resistance value is changed by changing the contact area between the GaAs contact layer of the second DBR40 and the ITO layer 90. Specifically, the contact area is changed by changing the width d2 of the insulating opening, thereby adjusting the amount of current flowing into the second DBR40. For example, by relatively reducing the width d2 of the insulating opening, the contact area is reduced, thereby increasing the resistance value and decreasing the amount of current flowing into the second DBR40. On the other hand, by relatively increasing the width d2 of the insulating opening, the contact area is increased, thereby lowering the resistance value and increasing the amount of current flowing into the second DBR40.

[0070] Figure 13 shows the relationship between the insulating aperture width d2 and the resistance value (calculated and measured values). The horizontal axis of Figure 13 represents the insulating aperture width d2, and the vertical axis represents the relative resistance value when the resistance value for an insulating aperture width d2 of 10.6 μm is set to 1.0. As shown in Figure 13, when d2 = 7.5 μm, the resistance value changes by 1.15 times, and when d2 = 20 μm, the resistance value changes by 0.93 times. Furthermore, Figure 13 confirms that the measured values ​​are in line with the calculation results. Note that if the insulating aperture is located inside the non-oxidizing region, it may adversely affect the light emitted from VCSEL2A. If this is a problem, it is desirable to set the insulating aperture width d2 to be larger than the non-oxidizing region width d1. Note that VCSEL2B is configured similarly to VCSEL2A except for the difference in insulating aperture width d2.

[0071] By adjusting the width d2 of the insulating opening in VCSEL2A, the contact area between the ITO layer 90 and the second DBR 40 in VCSEL2A is made smaller than the contact area between the ITO layer 90 and the second DBR 40 in VCSEL2B. As a result, if the first resistance value between the upper ring electrode 60 and the back electrode 70 of VCSEL2A is R1, and the second resistance value between the upper ring electrode 60 and the back electrode 70 of VCSEL2B is R2, then R1 > R2. That is, VCSEL2A has a higher resistance value than VCSEL2B. For example, based on Figure 13, the width d2 of the insulating opening in VCSEL2A is set to 10.6 μm, and the width d2 of the insulating opening in VCSEL2B is set to 16.8 μm. In this case, the width d1 of the non-oxidizing region of the current constriction layer 41 is 10.6 μm. With this design, the resistance value of VCSEL2A is approximately 1.07 times that of VCSEL2B.

[0072] In the VCSEL array 100B, the arrangement of two types of VCSELs 2A and 2B with different resistance values ​​is designed to ensure that the current injected into each VCSEL 2A and 2B is more uniform. Here, the multiple VCSELs 2 are divided into two groups (first and second groups) according to their distance from the anode power supply pad 102. The VCSEL array 100B is configured such that the resistance value of the VCSELs in the group that is closer to the anode power supply pad 102 is higher. Specifically, the first group of VCSELs, which are closer to the anode power supply pad 102, are composed of VCSEL 2A, and the second group of VCSELs, which are further from the anode power supply pad 102, are composed of VCSEL 2B. More specifically, as shown in Figure 11, in the 20 VCSELs along the Y direction, the first to fifth VCSELs in the first group, which are closer to the anode power supply pad 102, are composed of VCSEL 2A with a higher resistance value. Then, the remaining 6th to 20th VCSELs in the second group are made up of VCSEL2B with low resistance values.

[0073] Figure 14 shows the current distribution in each VCSEL array. In Figure 14, the vertical axis represents the current value, and the horizontal axis represents the nth VCSEL in an array, counting from the one closest to the anode power supply pad 102. In Figure 14, L5 is the current distribution of one array in the VCSEL array 100B according to the third embodiment. Figure 14 also shows the current distribution L4 of one array in a VCSEL array according to a comparative example. In the VCSEL array according to the comparative example, all VCSELs (400 units) are composed of one type of VCSEL 2B and arranged in an array.

[0074] In the comparative example VCSEL array, the ratio of the maximum (MAX) to the minimum (MIN) current value flowing through each VCSEL2B is 0.80 (L4 in Figure 14). In contrast, in the VCSEL array 100B according to the third embodiment, the ratio of the maximum to the minimum current value flowing through each VCSEL2A,2B is 0.86 (L5 in Figure 14). As a result, the VCSEL array 100B has a ratio of the maximum to the minimum current value that is closer to 1.0 compared to the comparative example VCSEL array 900, thus suppressing the spread of the current distribution. Furthermore, in the comparative example VCSEL array, the minimum current density injected into each VCSEL2B is 20 kA / cm². 2 When the amount of current injected into one array is adjusted as described above, the input power is 90.4 mW (0.49 A). In the VCSEL array 100B of the third embodiment, the minimum current density injected into each VCSEL 2A, 2B is 20 kA / cm². 2 As described above, when the amount of current injected into one array is adjusted, the input power is 90.2 mW (0.48 A). From this, it can be seen that the VCSEL array 100B of the third embodiment can also reduce the power supplied to the array.

[0075] The VCSEL array 100B has the characteristic of being able to realize multiple types of VCSELs 2 simultaneously by only changing the width d2 of the insulating aperture on the photomask, without increasing the number of epitaxial layers, etc., as in the first embodiment. Therefore, the VCSEL array 100B can use more than two types of insulating aperture width d2. On the other hand, compared to the VCSEL array 100 of the first embodiment, the VCSEL array 100B has a limited range of changeable insulating aperture width d2, so the amount of change in resistance value is smaller.

[0076] [Fourth Embodiment] Next, the VCSEL array 100C according to the fourth embodiment will be described. The VCSEL array 100C according to the fourth embodiment is composed of six types of VCSELs 2A, 2Aa1, 2Aa2, 2Aa3, 2Aa4, and 2B, each with different resistance values. When the current value changes abruptly at the boundary between VCSEL2A and VCSEL2B, as in the current value change of the VCSEL array 100B according to the third embodiment (L5 in Figure 14), the current distribution can be made smoother by finely setting the resistance value of each VCSEL2. Figure 15 is a plan view showing an example of the configuration of the VCSEL array 100C according to the fourth embodiment. The multiple VCSELs 2 include six types of VCSELs 2 with different resistance values, and are divided into six groups (groups 1 to 6) according to the distance from the anode power supply pad 102. The VCSEL array 100C is configured such that the resistance value of the VCSELs is higher for VCSELs in groups that are closer to the anode power supply pad 102. Specifically, starting from the one closest to the anode power supply pad 102, the array consists of VCSEL2A of the first group, VCSEL2Aa1 of the second group, and VCSEL2Aa2 of the third group, one by one. Following VCSEL2Aa2 of the third group, there are VCSEL2Aa3 of the fourth group and VCSEL2Aa4 of the fifth group (not shown), and the 6th to 20th are composed of VCSEL2B of the sixth group.

[0077] In the VCSEL array 100C according to the fourth embodiment, the width d2 of the insulating opening follows the relationship VCSEL2B>VCSEL2Aa4>VCSEL2Aa3>VCSEL2Aa2>VCSEL2Aa1>VCSEL2A, as shown in Figure 16. That is, the width d2 of the insulating opening becomes smaller the closer it is to the anode power supply pad 102. As a result, the resistance values ​​follow the relationship VCSEL2A>VCSEL2Aa1>VCSEL2Aa2>VCSEL2Aa3>VCSEL2Aa4>VCSEL2B, and the resistance values ​​of the VCSELs in the group closer to the anode power supply pad 102 become larger. This makes it possible to change the resistance value of each VCSEL2 in a stepwise and fine manner. As a result, the VCSEL array 100C can reduce the ratio of the maximum and minimum current values ​​of the current flowing through each VCSEL2 and further suppress the spread of the current distribution (L6 in Figure 14) compared to the VCSEL array 100B (L5 in Figure 14).

[0078] [Fifth Embodiment] Next, the VCSEL array 100D according to the fifth embodiment will be described. The VCSEL array 100D has short, high peak pulse characteristics suitable for LiDAR. Japanese Patent Application Publication No. 2022-176886 describes a configuration using a saturable absorption layer, etc. (hereinafter also referred to as "high peak VCSEL"). By combining this high peak VCSEL configuration with a configuration that makes the current value more uniform, the problems specific to high peak VCSELs can be solved.

[0079] As described in Japanese Patent Publication No. 2022-176886, high peak-value VCSELs have the characteristic of being able to output optical pulses with a pulse width of several hundred ps and a high peak value at the start of oscillation, which is effective in improving the ranging distance and ranging accuracy of LiDAR systems.

[0080] On the other hand, high peak-value VCSELs have a unique characteristic in that the timing of pulse generation at the start of oscillation changes depending on the current density. Figure 17 shows the relationship between current density and pulse generation timing. In Figure 17, the vertical axis represents light intensity and the horizontal axis represents time. Figure 18 shows the relationship between current density and pulse delay time. In Figure 18, the vertical axis represents pulse delay time and the horizontal axis represents current density. As shown in Figures 17 and 18, current densities of 21-29 kA / cm² 2 This results in a pulse generation timing delay of 1.27 ns.

[0081] Therefore, when multiple high-peak-value VCSELs are arranged in an array, if the current injected into each high-peak-value VCSEL is non-uniform, the emission timing of each high-peak-value VCSEL will differ. As a result, the time variation of the light intensity of the entire array will be wider than the pulse width of the high-peak-value VCSELs, leading to a problem where the advantages of the LiDAR system are reduced.

[0082] Therefore, by making the current more uniform, it is possible to suppress the shift in the oscillation start timing within the VCSEL array when high peak-value VCSELs are arranged in an array. In addition, it is possible to suppress the increase in the optical pulse width when the light from each VCSEL is combined by an optical system, etc.

[0083] Figure 20 is a cross-sectional view showing an example of the configuration of a high-peak value VCSEL3A according to the fifth embodiment, and is, for example, the V1-V1 cross-sectional view in Figure 19. In the high-peak value VCSEL3A according to the fifth embodiment, the same reference numerals are used for the same components as in the VCSEL2A according to the fourth embodiment, and their detailed descriptions are omitted. The high-peak value VCSEL3A differs from the VCSEL2A in that the barrier layer (inhibition layer) sandwiching the quantum well layer 31 is made of a GaAs layer. Furthermore, the high-peak value VCSEL3A differs from the VCSEL2A in that it has a spacer layer 110 including a saturable absorption layer 111. The spacer layer 110 is provided inside the first DBR 20 (inside the first reflector). With this configuration, the high-peak value VCSEL3A can emit light pulses with short and high peak values. In the fifth embodiment, the width d2 of the insulating aperture of the high-peak value VCSEL3A is 10.4 μm, and the width d2 of the insulating aperture of the high-peak value VCSEL3B is 16.8 μm. As a result, the high-peak value VCSEL3A has a higher resistance value than the high-peak value VCSEL3B.

[0084] Figure 19 is a plan view showing an example configuration of a VCSEL array 100D according to the fifth embodiment. The multiple VCSELs 3 are divided into two groups (first and second groups) according to their distance from the anode power supply pad 102. The VCSEL array 100D is configured such that the resistance value of the VCSELs increases as the distance from the anode power supply pad 102 decreases. Specifically, the first group of VCSELs, which are closer to the anode power supply pad 102, are configured with high peak value VCSEL3A, and the second group of VCSELs, which are further from the anode power supply pad 102, are configured with high peak value VCSEL3B. More specifically, the first to fifth VCSELs of the first group, which are closer to the anode power supply pad 102, are configured with high peak value VCSEL3A, and the remaining sixth to twentieth VCSELs of the second group are configured with high peak value VCSEL3B.

[0085] This configuration allows for more uniform current injection into the high-peak-value VCSELs 3A and 3B, suppressing timing discrepancies in their emission. Arraying enables increased optical output and allows for the proper use of pulses with high peak values ​​of several hundred ps generated by the high-peak-value VCSELs 3A and 3B. Here, the minimum current density is 20 kA / cm². 2 The current value injected into one array is adjusted to achieve the above result. In this case, in the comparative example where one array is composed entirely of the same high peak value VCSEL3B, the maximum current density is 25.1 kA / cm². 2 As a result, the pulse delay time difference in one array is 1.07 ns. In contrast, in the VCSEL array 100D according to the fifth embodiment, one array is composed of high peak value VCSELs 3A and 3B, so the maximum current density is 23.3 kA / cm². 2 As a result, the pulse delay time difference in one array can be suppressed to 0.76 ns.

[0086] [Sixth Embodiment] Next, the VCSEL array 100E according to the sixth embodiment will be described. Figure 21 is a plan view showing an example of the configuration of the VCSEL array 100E according to the sixth embodiment. The VCSEL array 100E according to the sixth embodiment includes VCSELs 4A and 4B, which are different from the VCSELs 1A, etc., of the first to fifth embodiments. The VCSELs 4A and 4B will be described in detail below. In the following description, the same reference numerals are used for components that are the same as those in the VCSELs 1A, etc., of the first to fifth embodiments, and their detailed descriptions will be omitted.

[0087] The VCSEL array 100E comprises, for example, a plurality of VCSELs 4, an anode wiring 101, and an anode power supply pad 102, as shown in Figure 21. In Figure 21, four VCSELs on one side in the Y direction and three on the other side in the Y direction are shown, among the plurality of VCSELs 4 connected to each anode wiring 101.

[0088] Twenty VCSEL4s are arranged in a single row along the Y direction, and these Y-direction rows of 20 are then arranged in a single row of 20 along the X direction. As a result, a total of 400 (20 x 20) VCSEL4s are arranged in an array, forming a rectangular shape when viewed from the Z direction.

[0089] Each anode wire 101 extends along the Y direction and multiple wires are arranged in a row along the X direction. One anode wire 101 is electrically connected to 20 VCSELs 4 along the Y direction. Twenty such anode wires 101 are arranged in a row along the X direction. Each anode wire 101 carries current through 20 VCSELs 4 connected in parallel.

[0090] The VCSEL array 100B configured in this way can emit light from 400 VCSELs 4 by supplying current from an external source via Au wires to 20 anode power supply pads 102. Furthermore, by sequentially supplying current from an external source to the 20 anode power supply pads 102, sequential drive can be performed in which each row emits light at a different timing.

[0091] Here, the VCSEL array 100E according to the sixth embodiment is configured to include a plurality of VCSEL4s, namely VCSEL4A and VCSEL4B. In the following description, when there is no need to distinguish between VCSEL4A and VCSEL4B, they may simply be referred to as "VCSEL4".

[0092] As shown in Figure 22(b), the VCSEL4B comprises an n-type GaAs substrate 10, a first DBR 20, a semiconductor resonator 30, a second DBR 40, an insulating film 50, an upper ring electrode 60, and a back electrode 70. The first DBR 20, the semiconductor resonator 30, the second DBR 40, and the upper ring electrode 60 are stacked in this order on the first surface of the n-type GaAs substrate 10. The back electrode 70 is provided on the second surface of the n-type GaAs substrate 10, opposite to the first surface. In the VCSEL4B, the semiconductor resonator 30 and the second DBR 40 are processed into a mesa shape. Although these components are in direct contact in Figure 22(b), other components may be provided between them. Furthermore, the above description is a description of the structure and does not limit the order in which each component is manufactured. Note that Figure 22(b) is a cross-sectional view taken along the line V2-V2 in Figure 21.

[0093] Next, VCSEL4A will be described. VCSEL4A is configured similarly to VCSEL4B described above. That is, as shown in Figure 22(a), VCSEL4A comprises an n-type GaAs substrate 10, a first DBR 20, a semiconductor resonator 30, a second DBR 40, an insulating film 50, an upper ring electrode 60, and a back electrode 70. The first DBR 20, the semiconductor resonator 30, the second DBR 40, and the upper ring electrode 60 are stacked in this order on the first surface of the n-type GaAs substrate 10. The back electrode 70 is provided on the second surface of the n-type GaAs substrate 10, opposite to the first surface. In VCSEL4A, the semiconductor resonator 30 and the second DBR 40 are processed in a mesa shape. Note that Figure 22(a) is a cross-sectional view taken along V1-V1 in Figure 21.

[0094] Furthermore, the mesa size of VCSEL4A is smaller than that of VCSEL4B. That is, the mesa width d2 of VCSEL4A is narrower than the mesa width d4 of VCSEL4B. As a result, as shown in Figure 22(a), the width d1 of the non-oxidized region of the current-constricting layer 41 of VCSEL4A is narrower than the width d3 of the non-oxidized region of the current-constricting layer 41 of VCSEL4B. This is because if oxidation is performed in the same way on the same wafer, the oxidation distance from the mesa edge will be approximately the same. Since the current path within the mesa is narrowed by the non-oxidized region of the current-constricting layer 41, the current path can be made narrower by making the non-oxidized region of VCSEL4A smaller than that of VCSEL4B, and the resistance value of VCSEL4A can be made higher than that of VCSEL4B.

[0095] Figure 23 shows the relationship between the area of ​​the non-oxidized region of the current-constricting layer 41 and its resistance. In Figure 23, the horizontal axis represents the area of ​​the non-oxidized region of the current-constricting layer 41, and the vertical axis represents the area of ​​the non-oxidized region of the current-constricting layer 41 being 300 μm². 2 This shows the relative resistance value when the resistance value in this case is set to 1.0. The width d3 of the non-oxidized region of VCSEL4B is 17.3 μm, meaning the non-oxidized region area is approximately 300 μm. 2 Assuming the width d1 of the non-oxidized region of VCSEL4A is 15.1 μm, that is, the area of ​​the non-oxidized region is approximately 227 μm. 2 In this case, the resistance of VCSEL4A will be 1.27 times the resistance of VCSEL4B.

[0096] Multiple VCSELs 4 are divided into two groups (first and second groups) according to their distance from the anode power supply pad 102. The VCSEL array 100E is configured such that the resistance value of the VCSELs in the group that is closer to the anode power supply pad 102 is higher. Specifically, the first group of VCSELs, which are closer to the anode power supply pad 102, are made up of VCSEL 4A, and the second group of VCSELs, which are further away from the anode power supply pad 102, are made up of VCSEL 4B. More specifically, as shown in Figure 21, the first group of VCSELs, from the 1st to the 7th VCSELs, which are closer to the anode power supply pad 102, are made up of VCSEL 4A with a higher resistance value. The remaining second group of VCSELs, from the 8th to the 20th VCSELs, are made up of VCSEL 4B with a lower resistance value.

[0097] With this configuration, the current distribution of the VCSEL array 100E becomes the same as L3 shown in Figure 5. Compared to the case where the array is configured with only one type of VCSEL 4B as in the comparative example (L1 shown in Figure 5), the spread of the current distribution of the VCSEL array 100E can be suppressed. Furthermore, by suppressing the spread of the current distribution, the amount of current required for the VCSEL array 100E can be reduced, and the input power can also be reduced.

[0098] [Seventh Embodiment] Next, the VCSEL array 100F according to the seventh embodiment will be described. As shown in Figure 24, the VCSEL array 100F according to the seventh embodiment is composed of three types of VCSELs 4A, 4Aa, and 4B, each with different resistance values.

[0099] In the seventh embodiment, the width of the non-oxidized region of VCSEL4B is 17.3 μm, and the area of ​​the non-oxidized region is 300 μm. 2 Furthermore, the width of the non-oxidized region of VCSEL4A is 14.2 μm, and the area of ​​that non-oxidized region is 203 μm. 2 Furthermore, the width of the non-oxidized region of VCSEL4Aa is 15.8 μm, and the area of ​​that non-oxidized region is 250 μm. 2Therefore, the resistance of VCSEL4A becomes 1.40 times that of VCSEL4B, and the resistance of VCSEL4Aa becomes 1.17 times that of VCSEL4B.

[0100] Multiple VCSELs 4 are divided into three groups (1st to 3rd groups) according to their distance from the anode power supply pad 102. The VCSEL array 100F is configured such that the resistance value of the VCSELs in the group that is closer to the anode power supply pad 102 is higher. Specifically, as shown in Figure 24, the 1st to 4th VCSELs in the 1st group, which are closest to the anode power supply pad 102, are composed of VCSEL 4A, which has the highest resistance value. The 5th to 9th VCSELs in the 3rd group are composed of VCSEL 4Aa, which has the next highest resistance value, and the 10th to 20th VCSELs in the 2nd group are composed of VCSEL 4B, which has the lowest resistance value.

[0101] In this case, the current distribution of the VCSEL array 100F according to the seventh embodiment will have a similar trend to L3 (see Figure 5). Compared to the case where the array is configured with one type of VCSEL 4B, as in the comparative example (current distribution L1 in Figure 5), the spread of the current distribution of the VCSEL array 100F can be suppressed. Furthermore, by suppressing the spread of the current distribution, the amount of current required for the VCSEL array 100F is reduced, and the input power is also reduced. Thus, in the VCSEL array 100F, by increasing the variety of VCSEL resistance values ​​and appropriately setting the multiplier and arrangement of each resistance value, the spread of the current distribution can be suppressed and the input power can be reduced.

[0102] [Eighth Embodiment] Next, the VCSEL array 100G (not shown) according to the eighth embodiment will be described. The VCSEL array 100G according to the eighth embodiment has a configuration that further sets the width of the non-oxidized region of the VCSEL 4 in multiple stages and changes the resistance value of the VCSEL 4 in steps. Figure 25 is a diagram showing the relationship between the non-oxidized region and the resistance value of each VCSEL 4. Multiple VCSEL 4 are divided into 14 groups (groups 1 to 14) according to the distance from the anode power supply pad 102. The VCSEL array 100G is configured such that the resistance value of the VCSELs increases as the distance from the anode power supply pad 102 decreases. Specifically, as shown in Figure 25, 14 types of VCSEL 4 are arranged in groups such that the resistance value of the VCSEL 4 gradually increases as it approaches the anode power supply pad 102. For example, the maximum resistance multiplier of the VCSEL array 100G is 1.53 times, and the width of its non-oxidized region is 13.5 μm.

[0103] Figure 26 shows the current distribution in the VCSEL array 100G. In Figure 26, L8 is the current distribution of one array in the VCSEL array 100G according to the eighth embodiment. Figure 26 also shows the current distribution L7 of one array in the VCSEL array of the comparative example. In the VCSEL array of the comparative example, all VCSELs (400 in total) are composed of one type of VCSEL4 and arranged in an array. As shown in Figure 26, the ratio of the maximum and minimum current values ​​flowing through each VCSEL4 in the VCSEL array 100G is 0.97 (L8 in Figure 26), which shows that the spread of the current distribution can be suppressed compared to the VCSEL array of the comparative example (L7 in Figure 26).

[0104] Furthermore, with the VCSEL array 100G, multiple types can be manufactured simultaneously simply by changing the width of the mesa of the VCSEL4 on the photomask during the manufacturing process. Also, compared to the change in resistance value of the VCSEL array 100B of the third embodiment, the change in resistance value of the VCSEL array 100G can be made larger. In the VCSEL array 100G, by appropriately increasing the number of resistance values ​​compared to the example shown in Figure 25, it is also possible to bring the ratio of the maximum to minimum current value closer to 1.

[0105] Furthermore, since the VCSEL array 100G changes the width of the non-oxidation region, the oscillation mode, FFP (Far Field Pattern), and current density distribution may affect the intended operating conditions. In such cases, it is preferable to employ methods such as minimizing the change in the non-oxidation region by combining it with other embodiments. In that case, instead of defining the resistance value by the length of the current path from the anode power supply pad 102, it is conceivable to define the resistance value of the VCSELs based on the current value actually applied to the VCSELs. Specifically, by placing VCSELs with high resistance values ​​in areas with high current values, the current distribution of the entire array can be made smoother.

[0106] [Ninth Embodiment] Next, the VCSEL array 100H according to the ninth embodiment will be described. Figure 27 is a plan view showing an example of the configuration of the VCSEL array 100H according to the ninth embodiment. The VCSEL array 100H according to the ninth embodiment includes VCSELs 5A and 5B, which are different from the VCSELs 1A, etc., of the first to eighth embodiments. The VCSELs 5A and 5B will be described in detail below. In the following description, the same reference numerals are used for components that are the same as those in the VCSELs 1A, etc., of the first to eighth embodiments, and their detailed descriptions will be omitted.

[0107] The VCSEL array 100H comprises, for example, a plurality of VCSELs 5, an anode wiring 101, and an anode power supply pad 102, as shown in Figure 27. In Figure 27, four VCSELs on one side in the Y direction and three on the other side in the Y direction are shown, out of the plurality of VCSELs 5 connected to each anode wiring 101.

[0108] Twenty VCSEL5s are arranged in a single row along the Y direction, and these Y-direction arrays of 20 are then arranged in 20 separate rows along the X direction. This results in a total of 400 (20x20) VCSEL5s arranged in an array, which, when viewed from the Z direction, forms a rectangular shape overall.

[0109] Each anode wire 101 extends along the Y direction and multiple wires are arranged in a row along the X direction. One anode wire 101 is electrically connected to 20 VCSELs 5 along the Y direction. Twenty such anode wires 101 are arranged in a row along the X direction. Each anode wire 101 carries current through 20 VCSELs 5 connected in parallel.

[0110] The VCSEL array 100H configured in this way can emit light from 400 VCSELs 5 by supplying current from an external source via Au wires to 20 anode power supply pads 102. Furthermore, by sequentially supplying current from an external source to the 20 anode power supply pads 102, sequential drive can be performed in which each row emits light at a different timing.

[0111] Here, the VCSEL array 100H according to the ninth embodiment is configured to include a plurality of VCSEL5s, namely VCSEL5A and VCSEL5B. In the following description, when there is no need to distinguish between VCSEL5A and VCSEL5B, they may simply be referred to as "VCSEL5".

[0112] As shown in Figure 28(b), the VCSEL5B comprises an n-type GaAs substrate 10, a first DBR 20, a semiconductor resonator 30, a second DBR 40, an insulating film 50, an upper ring electrode 60, and a back electrode 70. The first DBR 20, the semiconductor resonator 30, the second DBR 40, and the upper ring electrode 60 are stacked in this order on the first surface of the n-type GaAs substrate 10. The back electrode 70 is provided on the second surface of the n-type GaAs substrate 10, opposite to the first surface. Although these components are in direct contact in Figure 28(b), other components may be provided between them. Furthermore, the above description is a description of the structure and does not limit the manufacturing order of each component. Figure 28(b) is a cross-sectional view taken along line V2-V2 in Figure 27.

[0113] Next, VCSEL5A will be described. VCSEL5A differs from VCSEL5B in that it has a proton injection region 120, but otherwise has the same configuration as VCSEL5B. That is, as shown in Figure 28(a), VCSEL5A comprises an n-type GaAs substrate 10, a first DBR 20, a semiconductor resonator 30, a second DBR 40, an insulating film 50, an upper ring electrode 60, and a back electrode 70. The first DBR 20, the semiconductor resonator 30, the second DBR 40, and the upper ring electrode 60 are stacked in this order on the first surface of the n-type GaAs substrate 10. The back electrode 70 of VCSEL5A is provided on the second surface of the n-type GaAs substrate 10, opposite to the first surface. Note that Figure 28(a) is a cross-sectional view taken along V1-V1 in Figure 27.

[0114] In the ninth embodiment, a proton injection region 120 is provided as a means for changing the resistance value. The proton injection region 120 is provided in a part of the second DBR 40 of VCSEL5A. As a result, VCSEL5A can lower the carrier density in the second DBR 40 in the current path flowing from the upper ring electrode 60 to the current constriction layer 41, and thus can increase the resistance value compared to VCSEL5B.

[0115] A specific method for forming the proton injection region 120 can be, for example, the method disclosed in Japanese Patent Application Publication No. 2021-136319. Here, as described in the third embodiment, in a VCSEL2 having an ITO layer 90 on top, the current path is concentrated towards the mesa center, so if a proton injection region 120 is provided for such a configuration, the resistance value can be efficiently increased. In the ninth embodiment, since injecting protons into the proton injection region 120 also changes the light absorption rate of the second DBR 40, the extraction efficiency changes. For this reason, if you want to suppress the spreading of the light intensity distribution within the array, it is desirable to design the arrangement of VCSELs within the array considering not only the current distribution but also the light intensity distribution.

[0116] Thus, VCSEL5A has a proton injection region 120 within the second DBR 40, while VCSEL5B does not. Due to this configuration, the resistance values ​​between the upper ring electrode 60 and the back electrode 70 of VCSEL5A and VCSEL5B are different. If the resistance value between the upper ring electrode 60 and the back electrode 70 of VCSEL5A is R1, and the resistance value between the upper ring electrode 60 and the back electrode 70 of VCSEL5B is R2, then R1 > R2. In other words, VCSEL5A has a proton injection region 120, so its resistance value is greater than that of VCSEL5B.

[0117] Multiple VCSELs 5 are divided into two groups (first and second groups) according to their distance from the anode power supply pad 102. The VCSEL array 100H is configured such that the resistance value of the VCSELs in the group that is closer to the anode power supply pad 102 is higher. Specifically, the first group of VCSELs, which are closer to the anode power supply pad 102, are composed of VCSEL 5A, and the second group of VCSELs, which are further away from the anode power supply pad 102, are composed of VCSEL 5B. More specifically, as shown in Figure 27, the first five VCSELs in the first group, which are closer to the anode power supply pad 102, are composed of VCSEL 5A with high resistance values. The remaining 6th to 20th VCSELs in the second group are composed of VCSEL 5B with low resistance values. By arranging the two types of VCSELs 5A and 5B with different resistance values ​​in the VCSEL array 100H, the current injected into each VCSEL 5A and 5B can be made more uniform.

[0118] [Tenth Embodiment] Next, an example of applying the VCSEL array 100 to the SWIR (Short Wavelength Infrared Region) band will be described. Figure 29 is a cross-sectional view showing an example configuration of the VCSEL array 100M according to the 10th embodiment.

[0119] The VCSEL array 100M comprises the VCSEL array 100 of the first embodiment and a VCSEL chip 200, with the VCSEL chip 200 bonded onto the VCSEL array 100.

[0120] The VCSEL chip 200 oscillates via photoexcitation and, as shown in Figure 29, comprises a lower reflector 201 as a third reflector and a semiconductor resonator 202 as a second semiconductor resonator including a second active layer. Furthermore, the VCSEL chip 200 comprises an upper reflector 203 as a fourth reflector, an InP substrate 206, and an AR (Anti-Reflection) coating 207. The VCSEL chip 200 is constructed by stacking the lower reflector 201, semiconductor resonator 202, upper reflector 203, InP substrate 206, and AR coating 207 in this order on top of the VCSEL array 100. The lower reflector 201 is composed of seven pairs of alternating stacked layers of SiO2 and TiO2 with an optical film thickness of 1 / 4λc. The semiconductor resonator 202 includes an InGaAsP light absorption layer 204 and five quantum well layers 205 composed of 8 nm thick InGaAs (only one layer is shown in the figure). The quantum well layer 205 is excited by light of the first wavelength emitted from the VCSEL array 100. The upper reflector 203 is composed of alternating layers of InP / InGaAsP with an optical film thickness of 1 / 4λc. The upper reflector 203 is configured to have a lower reflectivity than the lower reflector 201. Therefore, the light of the second wavelength oscillated by the VCSEL chip 200 is extracted through the InP substrate 206. The AR coating 207 prevents reflection. Note that the light of the second wavelength is different in wavelength from the light of the first wavelength.

[0121] The VCSEL array 100 emits, for example, light with a wavelength of 940 nm to the VCSEL chip 200. The VCSEL chip 200 absorbs this light by the InGaAsP light absorption layer 204 in the semiconductor resonator 202 after it passes through the lower reflector 201. The absorbed light generates electrons and holes, which enter the quantum well layer 205, and gain is generated when the density exceeds the transparent carrier density. In this way, the VCSEL array 100M generates laser oscillation in the VCSEL chip 200 and emits laser light in the 1550 nm wavelength band.

[0122] In the VCSEL array 100M, the portion that emits light at a wavelength of 1550 nm can be selected by selecting the energized anode wiring 101 from among the multiple anode wirings 101 that constitute the VCSEL array 100. Furthermore, by suppressing the spread of the current distribution of the VCSEL array 100, the spread of the emission intensity distribution of the VCSELs 1A and 1B that constitute the VCSEL array 100 can be suppressed, while minimizing the space required for wiring between VCSELs 1A and 1B. As a result, the VCSEL array 100M can reduce the chip size. Reducing the chip size leads not only to a reduction in chip cost, but also to a reduction in the size and cost of optical systems, including lenses.

[0123] The VCSEL chip 200, which is excited by light with a wavelength of 940 nm, was a VCSEL in the 1550 nm wavelength band, but it is not limited to this. For example, it could be an LED or VCSEL array that is excited by light with a wavelength of 940 nm and emits light in the 1900 nm wavelength band.

[0124] Furthermore, although the example shown uses the VCSEL array 100 described in the first embodiment as the excited VCSEL array, similar effects can be achieved with the configurations described in the second to tenth embodiments. In all cases, the wiring space is minimized, resulting in a smaller VCSEL chip size.

[0125] [Embodiment No. 11] Next, a distance measuring device 300 according to the 11th embodiment will be described. The distance measuring device 300 is a LiDAR that uses, for example, the VCSEL array 100 according to the first embodiment as the light source.

[0126] As shown in Figure 30, the distance measuring device 300 comprises an overall control unit 310, a surface-emitting laser array driver 320, a surface-emitting laser array 330, a light-emitting optical system 340, a light-receiving optical system 350, a light-receiving image sensor 360, and a distance data processing unit 370.

[0127] The overall control unit 310 is composed of an information processing device including a microcomputer and logic circuits, and functions as a central processing unit that controls the operation of the distance measuring device 300, including the operation control of each part and various calculation processing.

[0128] The surface-emitting laser array driver 320 is a drive unit that receives a drive signal from the overall control unit 310, generates a drive current for the surface-emitting laser array 330 to oscillate, and outputs the drive current to the surface-emitting laser array 330.

[0129] The surface-emitting laser array 330 is configured by mounting the VCSEL array described in the first to tenth embodiments into a package.

[0130] The light-emitting optical system 340 is an optical system that emits laser light generated by the surface-emitting laser array 330 towards the range to be measured.

[0131] The light-receiving optical system 350 is an optical system that guides the laser light reflected by the object OJ included in the distance measurement range to the light-receiving image sensor 360. Although the light-emitting optical system 340 and the light-receiving optical system 350 are represented as a single convex lens-shaped component in Figure 30, they are not composed of only a single convex lens system, but are composed of a lens group made up of multiple lenses.

[0132] The light-receiving image sensor 360 is, for example, a light-receiving device in which CMOS (Complementary Metal-Oxide Semiconductor) optical sensors are arranged in an array. Alternatively, the light-receiving image sensor 360 may be a light-receiving device in which SPAD (Single Photon Avalanche Diode) optical sensors are arranged in an array.

[0133] The distance data processing unit 370 functions as a distance information acquisition unit that generates information regarding the distance to the object OJ within the distance measurement range based on the signal from the light-receiving image sensor 360 and outputs the generated information. For example, the distance data processing unit 370 acquires information regarding the distance to the object OJ based on the time difference between the timing of light emission from the surface-emitting laser array 330 and the timing of light reception by the light-receiving image sensor 360. The distance data processing unit 370 only needs to be electrically connected to the light-receiving image sensor 360 and may be located in the same package as the light-receiving image sensor 360 or in a separate package from the light-receiving image sensor 360.

[0134] Next, the operation of the distance measuring device 300 will be described. First, a drive signal is output from the overall control unit 310 to the surface-emitting laser array driver 320. Upon receiving this drive signal, the surface-emitting laser array driver 320 outputs a predetermined drive current to the surface-emitting laser array 330, causing the surface-emitting laser array 330 to oscillate. The laser light generated by the surface-emitting laser array 330 is emitted towards the object to be measured OJ through the light-emitting optical system 340, and the light reflected by the object to be measured OJ is incident on the light-receiving image sensor 360 through the light-receiving optical system 350. The light-receiving image sensor 360 converts the optical signal of the incident light into an electrical signal and outputs the converted electrical signal to the distance data processing unit 370. The distance data processing unit 370 calculates distance information based on the time difference between the timing of light emission from the surface-emitting laser array 330 and the timing of light reception by the light-receiving image sensor 360, and generates 3D information based on this distance information. The distance data processing unit 370 outputs the generated 3D information to the overall control unit 310.

[0135] The rangefinder 300 can be applied in the automotive sector to control systems that prevent collisions with other vehicles and to control systems that automatically follow other vehicles. Furthermore, the rangefinder 300 can be used in mobile objects (mobile devices) such as ships, aircraft, or industrial robots, as well as in mobile object detection systems. In addition, the rangefinder 300 can be applied to a wide range of devices that utilize three-dimensional recognition of objects, including distance information.

[0136] Furthermore, by using three-dimensional information including depth, the distance measuring device 300 can display virtual objects on top of the real world without any sense of incongruity in an image capture device, image processing device, and display device. In addition, the distance measuring device 300 can also be applied to devices that store three-dimensional information together with image information and add functions to correct blurring and other issues in captured images after shooting.

[0137] [Modified Embodiment] The present invention is not limited to the embodiments described above and can be modified in various ways. For example, an example in which a part of the configuration of one embodiment is added to another embodiment, or in which a part of the configuration of another embodiment is replaced, is also an embodiment of the present invention.

[0138] For example, a semiconductor layer 80 and a proton injection region 120 may be provided in addition to VCSEL2A which has an ITO layer 90, or a semiconductor layer 80 and a proton injection region 120 may be provided in addition to high peak value VCSEL3A. Also, a semiconductor layer 80 and a proton injection region 120 may be provided in VCSEL4A which has a different width of the non-oxidation region of the current constriction layer 41, or a semiconductor layer 80 may be provided in addition to VCSEL5A which has a proton injection region 120. In this way, means for changing the resistance value may be combined as appropriate. This makes it possible to increase the types of resistances of VCSELs in the VCSEL array and further suppress the spread of the current distribution.

[0139] Furthermore, a semiconductor layer 80 may be provided for VCSELs 3A and 3B with different widths of the non-oxidation region of the current-constricting layer 41, or for the high-peak value VCSEL 3A. This increases the variety of resistances of the VCSELs in the VCSEL array, further suppressing the spread of the current distribution.

[0140] Furthermore, multiple VCSELs may be configured to include at least two types of VCSELs from among VCSEL1A, VCSEL2A, VCSEL3A, VCSEL4A, and VCSEL5A.

[0141] Furthermore, while an example was shown in which VCSEL1A has a semiconductor layer 80 between the upper ring electrode 60 and the second DBR 40, and VCSEL1B does not have a semiconductor layer 80 between the upper ring electrode 60 and the second DBR 40, the examples are not limited to this. For example, VCSEL1A and VCSEL1B may each have a semiconductor layer 80 between the upper ring electrode 60 and the second DBR 40, and the thickness of the semiconductor layer 80 of VCSEL1A may be thicker than the thickness of the semiconductor layer 80 of VCSEL1B.

[0142] Furthermore, while we described an example where a VCSEL array consists of 400 VCSELs, the number of VCSELs is not limited to this and may be any other number.

[0143] Furthermore, although each embodiment describes a sequential anode wiring configuration in which each array emits light simultaneously in a single row, it is not limited to this, and can be similarly applied to configurations where each array emits light simultaneously in two, three, or four or more rows. It can also be similarly applied to a flash-type anode wiring configuration in which the entire surface emits light simultaneously. Specifically, for example, if there are 20 arrays in the Y direction and 20 in the X direction, and the anode wiring is uniformly connected to all of them, the amount of current injected into the center of the VCSEL array tends to be smaller than that into the outer parts. Even in such a configuration, if the resistance value of the VCSEL closer to the anode power supply pad 102 in the current path is R1, and the resistance value of the VCSEL further away is R2, then the first to tenth embodiments can be applied individually or in combination as appropriate so that R1 > R2. This can suppress the spread of the current distribution across the entire array. Furthermore, by increasing the types of resistors and appropriately arranging the VCSELs, the spread of the current distribution can be further suppressed.

[0144] Furthermore, while the current-constricted structure was described using an oxidized constricted layer formed by selectively oxidizing a portion of the semiconductor layer as an example, it is not limited to this. The current-constricted structure may also be formed by other methods, such as ion implantation.

[0145] Furthermore, while an example has been described in which a proton implantation region 120 is present in a second DBR 40 which is a P-type semiconductor, the invention is not limited to this. For example, instead of protons, donor impurities with a hole compensation effect may be ion-implanted. Also, if the second DBR 40 is an N-type semiconductor, acceptor impurities with an electron compensation effect may be ion-implanted instead of protons.

[0146] Furthermore, while the VCSEL4A and 4B examples described show both the semiconductor resonator 30 and the second DBR40 being processed into a mesa shape, the invention is not limited to this example; at least the second DBR40 must be processed into a mesa shape.

[0147] The above-disclosed embodiment includes the following configuration. (Composition 1) Each of a plurality of semiconductor light-emitting elements has, in this order, a first reflector, a first semiconductor resonator including a first active layer, a second reflector, and a first electrode on the first surface side of the semiconductor substrate, and a second electrode on the second surface of the semiconductor substrate opposite to the first surface. A power supply pad for supplying power to the plurality of semiconductor light-emitting elements, The system includes wiring that connects each of the plurality of semiconductor light-emitting elements to the power supply pad, The plurality of semiconductor light-emitting elements are divided into a plurality of groups, each having at least one of the semiconductor light-emitting elements, depending on the distance from the power supply pad. The semiconductor light-emitting element in the group with a shorter distance from the power supply pad is configured to have a larger resistance value between the first electrode and the second electrode. A light source device characterized by the following features. (Configuration 2) Each of a plurality of semiconductor light-emitting elements has, in this order, a first reflector, a first semiconductor resonator including a first active layer, a second reflector, and a first electrode on the first surface side of the semiconductor substrate, and a second electrode on the second surface of the semiconductor substrate opposite to the first surface. A power supply pad for supplying power to the plurality of semiconductor light-emitting elements, The system includes wiring that connects each of the plurality of semiconductor light-emitting elements to the power supply pad, The plurality of semiconductor light-emitting elements are divided into a plurality of groups, each having at least one of the semiconductor light-emitting elements, according to the length of the current path between them and the power supply pad. The semiconductor light-emitting element in the group with a shorter current path length between it and the power supply pad is configured to have a larger resistance value between the first electrode and the second electrode. A light source device characterized by the following features. (Composition 3) The plurality of groups includes a first group and a second group having semiconductor light-emitting elements whose resistance value is smaller than that of the first group. A light source device according to configuration 1 or 2, characterized by the above. (Composition 4) The plurality of groups include the first group, the second group, and the third group having semiconductor light-emitting elements whose resistance value is smaller than that of the first group and larger than that of the second group. The third group is positioned between the first group and the second group. The light source device according to configuration 3, characterized by the above. (Composition 5) The plurality of semiconductor light-emitting devices have a transparent conductive film between the first electrode and the second reflector. A light source device according to any one of configurations 1 to 4, characterized by the above. (Composition 6) The plurality of semiconductor light-emitting elements have a saturable absorption layer within the first reflector. A light source device according to any one of configurations 1 to 5, characterized by the above. (Composition 7) The semiconductor light-emitting element of the first group is formed in such a way that the distance between the first electrode and the second electrode is longer than that of the second semiconductor light-emitting element of the first group, and because the distance is longer than that of the semiconductor light-emitting element of the second group, the resistance between the first electrode and the second electrode is greater than that of the semiconductor light-emitting element of the second group. A light source device according to configuration 3 or 4, characterized by the above. (Composition 8) The contact area between the transparent conductive film and the second reflector in the semiconductor light-emitting element of the first group of the aforementioned multiple groups is smaller than the contact area between the transparent conductive film and the second reflector in the semiconductor light-emitting element of the second group of the aforementioned multiple groups. The light source device according to configuration 5, characterized in that it is a light source device. (Composition 9) At least the second reflector of the plurality of semiconductor light-emitting elements is processed into a mesa shape, and the width of the mesa of the first group of semiconductor light-emitting elements is narrower than the width of the mesa of the second group of semiconductor light-emitting elements. A light source device according to any one of configurations 3, 4, 7, or 8, characterized by the above. (Composition 10) The semiconductor light-emitting element of the first group has a proton injection region within the second reflector, and as a result of having the proton injection region, the resistance between the first electrode and the second electrode is larger than that of the semiconductor light-emitting element of the second group. A light source device according to any one of configurations 3, 4, 7, or 8, characterized by the above. (Composition 11) On the side of the second reflector opposite to the first semiconductor resonator, there is a third reflector, a second semiconductor resonator including a second active layer, and a fourth reflector, in this order. The second active layer is excited by light of a first wavelength emitted from the plurality of semiconductor light-emitting elements and emits light of a second wavelength different from the first wavelength. A light source device according to any one of configurations 1 to 10, characterized by the above. (Composition 12) Each of a plurality of semiconductor light-emitting elements has, in this order, a first reflector, a first semiconductor resonator including a first active layer, a second reflector, and a first electrode on the first surface side of the semiconductor substrate, and a second electrode on the second surface of the semiconductor substrate opposite to the first surface. A power supply pad for supplying power to the plurality of semiconductor light-emitting elements, The system includes wiring that connects each of the plurality of semiconductor light-emitting elements to the power supply pad, The plurality of semiconductor light-emitting elements are divided into a plurality of groups, each having at least one of the semiconductor light-emitting elements, according to the wiring resistance between them and the power supply pad. The semiconductor light-emitting element in the group with the lowest wiring resistance between it and the power supply pad is configured to have a larger resistance value between the first electrode and the second electrode. A light source device characterized by the following features. (Composition 13) The plurality of semiconductor light-emitting elements have a saturable absorption layer within the first reflector. The light source device according to configuration 5, characterized in that it is a light source device. (Composition 14) The plurality of groups comprises a first group and a second group having semiconductor light-emitting elements whose resistance value is smaller than that of the first group. The semiconductor light-emitting element of the first group is formed in such a way that the distance between the first electrode and the second electrode is longer than that of the second semiconductor light-emitting element of the first group, and because the distance is longer than that of the semiconductor light-emitting element of the second group, the resistance between the first electrode and the second electrode is greater than that of the semiconductor light-emitting element of the second group. A light source device according to configuration 13, characterized by the features described above. (Composition 15) In the first group of semiconductor light-emitting elements, the contact area between the transparent conductive film and the second reflector is smaller than the contact area between the transparent conductive film and the second reflector in the second group of semiconductor light-emitting elements. A light source device according to configuration 14, characterized by the features described above. (Composition 16) At least the second reflector of the plurality of semiconductor light-emitting elements is processed into a mesa shape, and the width of the mesa of the first group of semiconductor light-emitting elements is narrower than the width of the mesa of the second group of semiconductor light-emitting elements. A light source device according to configuration 15, characterized by the features described above. (Composition 17) The semiconductor light-emitting element of the first group has a proton injection region within the second reflector, and as a result of having the proton injection region, the resistance between the first electrode and the second electrode is larger than that of the semiconductor light-emitting element of the second group. A light source device according to configuration 16, characterized by the features described above. (Composition 18) A light source device as described in any of configurations 1 to 17, A light receiving device that receives light emitted from the light source device and reflected by the object to be measured, The system includes a distance information acquisition unit that acquires information regarding the distance to the object to be measured based on the time difference between the timing at which light is emitted from the light source device and the timing at which the light receiving device receives the light. A distance measuring device characterized by the following features. [Explanation of symbols]

[0148] 1-7...VCSEL 10...n-type GaAs substrate 20... First DBR 30... Semiconductor resonator 31... Quantum well layer 40... Second DBR 41...Current confinement layer 50… Insulating film 60…Upper ring electrode 70…Back electrode 80... Semiconductor layer 90...ITO layer 100…VCSEL array 101... Anode wiring 102... Anode power supply pad 110...Spacer layer 111...Saturable absorption layer 120... Proton injection region 200…VCSEL chip 300…Distance measuring device

Claims

[Claim 1] Each of a plurality of semiconductor light-emitting elements has, in this order, a first reflector, a first semiconductor resonator including a first active layer, a second reflector, and a first electrode on the first surface side of the semiconductor substrate, and a second electrode on the second surface of the semiconductor substrate opposite to the first surface. A power supply pad for supplying power to the plurality of semiconductor light-emitting elements, The system includes wiring that connects each of the plurality of semiconductor light-emitting elements to the power supply pad, The plurality of semiconductor light-emitting elements are divided into a plurality of groups, each having at least one of the semiconductor light-emitting elements, according to the distance from the power supply pad. The semiconductor light-emitting element in the group with a shorter distance from the power supply pad is configured to have a larger resistance value between the first electrode and the second electrode. A light source device characterized by the following features.

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