Autonomous system sequencing of discrete regulators using cascaded interface signals
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- RENESAS ELECTRONICS AMERICA INC
- Filing Date
- 2025-12-09
- Publication Date
- 2026-06-24
Smart Images
Figure 2026103850000001_ABST
Abstract
Claims
1. A device including an enable pin, a power good pin, and a circuit, The enable pin is configured to receive an enable signal to enable the generation of an output voltage. The power good pin is configured to output a power good signal indicating the state of the output voltage. The aforementioned circuit is The presence of a fault condition is detected, In response to detecting the aforementioned fault condition, Deassert the power good pin to disable the downstream device. The enable pin is configured to deassert in order to disable the upstream device. Device.
2. The circuit includes a switch connected between the enable pin and ground. In response to detecting the fault condition, the circuit is configured to deassert the enable pin by turning on the switch and pulling down the voltage at the enable pin. The apparatus according to claim 1.
3. The circuit further includes a resistor connected between the switch and the enable pin, The amount of voltage pulled down is determined based on the resistance of the resistor, The amount of voltage pulled down indicates the type of fault condition. The apparatus according to claim 2.
4. The apparatus according to claim 3, wherein the resistance of the resistor is variable.
5. The apparatus according to claim 1, wherein the circuit is configured to use the power good pin as an input pin to detect deassertion of the downstream enable pin of the downstream device.
6. The aforementioned circuit is The deassertion of the power good pin caused by the deassertion of the downstream enable pin of the downstream device is detected. In response to the detection of deassertion of the power good pin, the enable pin is further configured to deassert the enable pin in order to disable the upstream device. The apparatus according to claim 5.
7. The apparatus according to claim 6, wherein the detection of deassertion of the power good pin caused by deassertion of the downstream enable pin of the downstream device includes detecting that the voltage at the power good pin is lower than a reference power good voltage.
8. A system including multiple voltage regulators, The plurality of voltage regulators include at least an upstream voltage regulator, a specific voltage regulator, and a downstream voltage regulator. The aforementioned specific voltage regulator is To activate the aforementioned specific voltage regulator, an enable pin is configured to receive an enable signal from the upstream voltage regulator, A power good pin configured to output a power good signal for controlling the downstream enable pin of the downstream voltage regulator, Circuits and, Includes, The aforementioned circuit is The presence of a fault condition in the aforementioned specific voltage regulator is detected, In response to detecting the aforementioned fault condition, To disable the downstream voltage regulator, the power good pin is deasserted. The enable pin is configured to deassert in order to disable the upstream voltage regulator. system.
9. The circuit includes a switch connected between the enable pin and ground. In response to detecting the fault condition, the circuit is configured to deassert the enable pin by turning on the switch and pulling down the voltage at the enable pin. The system according to claim 8.
10. The circuit further includes a resistor connected between the switch and the enable pin, The amount of voltage pulled down is determined based on the resistance of the resistor, The amount of voltage pulled down indicates the type of fault condition. The system according to claim 9.
11. The system according to claim 10, wherein the resistance of the resistor is variable.
12. The system according to claim 8, wherein the circuit is configured to configure the power good pin as an input pin to detect deassertion of the enable pin of the downstream voltage regulator.
13. The aforementioned circuit is The deassertion of the power good pin caused by the deassertion of the enable pin of the downstream voltage regulator is detected. The enable pin is configured to deassert in order to disable the upstream voltage regulator in response to the detection of deassertion of the power good pin. The system according to claim 12.
14. The system according to claim 13, wherein the detection of deassertion of the power good pin caused by deassertion of the enable pin of the downstream voltage regulator includes detecting that the voltage at the power good pin is lower than a reference power good voltage.
15. A system comprising a plurality of voltage regulators and a controller configured to activate a first voltage regulator among the plurality of voltage regulators, The plurality of voltage regulators include at least the first voltage regulator and the second voltage regulator, The first voltage regulator is A first enable pin configured to receive an enable signal from the controller in order to activate the first voltage regulator, A first power good pin configured to output a first power good signal for controlling the second enable pin of the second voltage regulator, A first circuit configured to use the first power good pin as an input pin to detect the deassertion of the second enable pin of the second voltage regulator, Includes, The second voltage regulator described above is The second enable pin is configured to receive a first power good signal from the first power good pin, A second power good pin configured to output a second power good signal for controlling the downstream voltage regulator among the plurality of voltage regulators, The second circuit and, Includes, The second circuit described above is In order to detect the deassertion of the enable pin of the downstream voltage regulator, the second power good pin is configured as an input pin. The presence of a fault condition in the second voltage regulator is detected, In response to detecting the aforementioned fault condition, The second power good pin is deasserted in order to disable the downstream voltage regulator. The second enable pin is configured to deassert in order to disable the first voltage regulator. system.
16. The second circuit includes a switch connected between the enable pin and ground. In response to detecting the fault condition, the second circuit is configured to deassert the enable pin by turning on the switch and pulling down the voltage at the enable pin. The system according to claim 15.
17. The second circuit further includes a resistor connected between the switch and the enable pin, The amount of voltage pulled down is determined based on the resistance of the resistor, The amount of voltage pulled down indicates the type of fault condition. The system according to claim 16.
18. The system according to claim 17, wherein the resistance of the resistor is variable.
19. The second circuit described above is The deassertion of the second power good pin caused by the deassertion of the enable pin of the downstream voltage regulator is detected. The second enable pin is further configured to deassert in order to disable the first voltage regulator in response to the detection of deassertion of the second power good pin. The system according to claim 15.
20. The system according to claim 19, wherein the detection of deassertion of the second power good pin caused by the enable pin of the downstream voltage regulator includes detecting that the voltage at the second power good pin is lower than a reference power good voltage.