Electronic components

Abstract

To provide an electronic component that achieves both heat dissipation and voltage resistance while minimizing variations in device temperature. [Solution] The elastic wave device 100 comprises a first substrate 10 having a first layer 11 which is a sapphire layer, spinel layer, quartz layer, HTCC layer, LTCC layer, or FRP layer, and a second layer 12 which is provided on the surface 15 of the first layer 11 and has a greater thermal conductivity than the first layer 11, and the ratio of the thickness T2 of the second layer 12 to the total thickness T0 is 50% or more, an elastic wave element 50 provided on the surface of the second layer 12 opposite to the first layer 11, a second substrate 40 on which the first substrate 10 is mounted and which has wiring 42 electrically connected to the elastic wave element 50, and a frame 30 which is provided between the first substrate 10 and the second substrate 40 surrounding the elastic wave element 50 and sealing the elastic wave element 50 in the gap 32 between the first substrate 10 and the second substrate 40.

Description

Technical Field

[0001] The present invention relates to electronic components.

Background Art

[0002] As an electronic component, for example, a high-frequency filter is known. A high-frequency filter is used to remove unnecessary signals outside the frequency band used for communication in a high-frequency communication system represented by a mobile phone. For the high-frequency filter, for example, a surface acoustic wave resonator or a piezoelectric thin film resonator is used (for example, Patent Documents 1 and 2). A configuration is known in which a frame surrounding an elastic wave element is provided to seal the elastic wave element in a gap provided between two substrates (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] A configuration may be considered in which a first substrate provided with an element such as an elastic wave element is mounted on a second substrate by bumps, and the element is sealed in a gap between the first substrate and the second substrate by a frame provided so as to surround the element between the first substrate and the second substrate. In this case, it is desired to achieve both heat dissipation and pressure resistance. Further, even when manufacturing variations occur in the thickness of the first substrate, it is desired that variations in the device temperature be small.

[0005] The present invention has been made in view of the above problems, and an object thereof is to achieve both heat dissipation and pressure resistance and to suppress variations in the device temperature.

Means for Solving the Problems

[0006] The present invention relates to an electronic component comprising: a first layer which is a sapphire layer, a spinel layer, a quartz layer, an HTCC layer, an LTCC layer, or an FRP layer; a second layer which is provided on the first surface of the first layer and has a greater thermal conductivity than the first layer, wherein the ratio of the thickness of the second layer to the total thickness is 50% or more; an element provided on the surface of the second layer opposite to the first layer; a second substrate on which the first substrate is mounted and which has wiring electrically connected to the element; and a frame provided between the first substrate and the second substrate surrounding the element and sealing the element in the gap between the first substrate and the second substrate.

[0007] In the above configuration, the frame can be configured to be in contact with the second layer.

[0008] In the above configuration, the frame can be made of metal.

[0009] In the above configuration, the second layer can be a silicon layer, an alumina layer, a silicon carbide layer, or a graphite layer.

[0010] In the above configuration, the second layer is a silicon layer, and the ratio of the thickness of the second layer to the total thickness of the first substrate is 80% or less.

[0011] In the above configuration, the first substrate may have a third layer provided on the second surface opposite to the first surface of the first layer, and formed of the same material as the second layer.

[0012] In the above configuration, the first layer may be a sapphire layer and the second layer may be a silicon layer.

[0013] In the above configuration, the element can be configured to be an elastic wave element. [Effects of the Invention]

[0014] According to the present invention, it is possible to achieve both heat dissipation and pressure resistance, and to suppress variations in device temperature to a small extent.

Brief Description of the Drawings

[0015] [Figure 1] FIG. 1 is a cross-sectional view of an elastic wave device according to Example 1. [Figure 2] FIG. 2 is a plan view of the first substrate in Example 1 as viewed from the -Z direction. [Figure 3] FIG. 3(a) is a plan view of an elastic wave element in Example 1, and FIG. 3(b) is a cross-sectional view of an elastic wave element of another example used in Example 1. [Figure 4] FIGS. 4(a) to 4(d) are cross-sectional views showing a method for manufacturing an elastic wave device according to Example 1. [Figure 5] FIGS. 5(a) and 5(b) are cross-sectional views of elastic wave devices according to Comparative Example 1 and Comparative Example 2. [Figure 6] FIGS. 6(a) to 6(c) are cross-sectional views of Models A, B, and C, and FIG. 6(d) is a plan view of the second substrate in Models A, B, and C. [Figure 7] FIG. 7 is a cross-sectional view of an elastic wave device according to Comparative Example 3. [Figure 8] FIG. 8 is a diagram showing simulation results of the surface temperature of a piezoelectric layer with respect to the ratio of the thickness of the second layer. [Figure 9] FIG. 9 is a diagram showing simulation results of the stress generated on the lower surface of the first substrate with respect to the ratio of the thickness of the second layer. [Figure 10] FIGS. 10(a) to 10(c) are cross-sectional views of elastic wave devices according to Modification 1 to Modification 3 of Example 1. [Figure 11] FIGS. 11(a) and 11(b) are plan views when passive elements are provided on the first substrate and the second substrate.

Modes for Carrying Out the Invention

[0016] Hereinafter, with reference to the drawings, the case of an elastic wave device will be described as an example of an embodiment of the present invention.

[0017] FIG. 1 is a cross-sectional view of an elastic wave device 100 according to Embodiment 1. FIG. 2 is a plan view of the first substrate 10 in Embodiment 1 as viewed from the -Z direction. In FIG. 1, for clarity of the drawing, the cross-section of the elastic wave device 100 according to Embodiment 1 is schematically illustrated (the same applies to the following similar drawings). In FIG. 2, for clarity of the drawing, the frame 30 is hatched.

[0018] As shown in FIG. 1, a first substrate 10 provided with one or more elastic wave elements 50 is mounted on a second substrate 40 by bumps (columnar electrodes) 33. The first substrate 10 has a first layer 11 and a second layer 12. The first layer 11 has surfaces 14 and 15. The second layer 12 has surfaces 16 and 17. Let the thickness of the first layer 11 be T1, the thickness of the second layer 12 be T2, and the thickness of the first substrate 10 be T0. In Embodiment 1, the thickness T0 is the thickness T1 + the thickness T2. The thickness T0 is, for example, 30 μm to 100 μm. The thickness T2 is 50% or more and 80% or less of the thickness T0.

[0019] The first layer 11 is, for example, a sapphire layer. The sapphire layer is a single crystal Al2O3 layer. The second layer 12 is provided on the surface 15 of the first layer 11. The surface 16 of the second layer 12 and the surface 15 of the first layer 11 are joined. The second layer 12 has a higher thermal conductivity than the first layer 11. The second layer 12 is, for example, a silicon layer. The silicon layer is a single crystal or polycrystal Si layer.

[0020] A piezoelectric layer 20 is joined to the surface 17 of the second layer 12. The piezoelectric layer 20 is, for example, a single crystal lithium tantalate layer, a single crystal lithium niobate layer, or a quartz layer, and has a thickness of 0.5 μm to 30 μm. The thickness of the piezoelectric layer 20 may be smaller than the wavelength of the elastic wave (for example, elastic surface wave) of the main mode excited by the elastic wave element 50.

[0021] One or more elastic wave elements 50 are provided on the piezoelectric layer 20. Figure 3(a) is a plan view of the elastic wave element 50 in Embodiment 1. Figure 3(b) is a cross-sectional view of another example of an elastic wave element 50a used in Embodiment 1. As shown in Figure 3(a), the elastic wave element 50 is a surface acoustic wave resonator and comprises an IDT (Interdigital Transducer) 51 and a reflector 52 provided on the piezoelectric layer 20. The IDT 51 comprises a pair of comb-shaped electrodes 53. The comb-shaped electrodes 53 comprises a plurality of electrode fingers 54 and a busbar 55 to which the plurality of electrode fingers 54 are connected. The region where the electrode fingers 54 of the pair of comb-shaped electrodes 53 intersect is the intersection region 56. The pair of comb-shaped electrodes 53 face each other such that the electrode fingers 54 are substantially staggered in at least a portion of the intersection region 56. The main mode elastic wave (e.g., surface acoustic wave) that excites the electrode fingers 54 in the intersection region 56 propagates mainly in the direction of the arrangement of the electrode fingers 54. The pitch of the electrode fingers 54 of one comb-shaped electrode 53 is approximately equal to the wavelength λ of the surface acoustic wave. The wavelength λ is approximately twice the average pitch D of the multiple electrode fingers 54. The average pitch D can be calculated by dividing the length of the IDT 51 in the direction of the arrangement of the electrode fingers 54 by the number of electrode fingers 54. The reflector 52 reflects the surface acoustic wave excited by the electrode fingers 54. As a result, the surface acoustic wave is confined within the intersection region 56. The IDT 51 and the reflector 52 are formed from a metal film such as aluminum, copper, or molybdenum.

[0022] As shown in Figure 3(b), in addition to the elastic wave element 50, which is an acoustic surface wave resonator, an elastic wave element 50a, which is a piezoelectric thin film resonator, may also be provided. The elastic wave element 50a comprises a piezoelectric layer 20a provided on the first substrate 10 and a pair of electrodes 57 provided so as to sandwich the piezoelectric layer 20a. A gap 58 is formed between the lower electrode 57 and the first substrate 10. The region where the pair of electrodes 57 face each other across the piezoelectric layer 20a is the resonance region 59. In the resonance region 59, the pair of electrodes 57 excite elastic waves in the piezoelectric layer 20a. The electrodes 57 are metal films, such as a ruthenium film. The piezoelectric layer 20a is, for example, an aluminum nitride layer, a zinc oxide layer, a single-crystal lithium tantalate layer, or a single-crystal lithium niobate layer. Instead of the gap 58, an acoustic reflective film that reflects elastic waves may be provided.

[0023] As shown in Figure 1, the second substrate 40 has electrodes 41 and a metal layer 44 on its upper surface, terminals 43 on its lower surface, and wiring 42 inside that connects the electrodes 41 and terminals 43. The wiring 42 includes planar wiring and vertically extending via wiring. The second substrate 40 is, for example, a package substrate or a mounting substrate. The first substrate 10 is mounted on the second substrate 40 by bonding bumps 33 to the electrodes 41 of the second substrate 40 with a bonding layer (not shown) such as solder. The elastic wave element 50 is electrically connected to terminals 43 via wiring 21, bumps 33, electrodes 41, and wiring 42. Electrical connection basically means DC conduction, but conduction of signals (AC) in the frequency band of approximately 500MHz to 2500MHz is also permitted. The wiring 21, electrode 41, wiring 42, terminal 43, and metal layer 44 are metal layers containing, for example, titanium, copper, aluminum, platinum, nickel, and / or gold. The bump 33 is, for example, a copper pillar.

[0024] No piezoelectric layer 20 is provided in the peripheral region of the first substrate 10. A frame 30 is provided between the first substrate 10 and the second substrate 40 in the peripheral region of the first substrate 10. The frame 30 is provided, for example, in contact with the surface 17 of the second layer 12.

[0025] As shown in Figure 2, the filter 70 is formed by a plurality of elastic wave elements 50. Specifically, series resonators S1 to S7 connected in series between bump 33a connected to the input terminal 43 and bump 33b connected to the output terminal 43, and parallel resonators P1 to P4 connected in parallel are formed by the elastic wave elements 50. One end of each parallel resonator P1 to P4 is connected to the wiring 21 connecting bumps 33a and 33b, and the other end is connected to bump 33c connected to the ground terminal 43. The frame 30 is provided on the first substrate 10 so as to surround the piezoelectric layer 20 and the elastic wave elements 50 in a plan view (viewed from the -Z direction). The height of the frame 30 is, for example, 15 μm to 30 μm, and the width is, for example, 10 μm to 40 μm.

[0026] As shown in Figure 1, the frame 30 is joined to a metal layer 44 provided on the upper surface of the second substrate 40 by a bonding layer (not shown) such as solder. The elastic wave element 50 is sealed in the gap 32 between the first substrate 10 and the second substrate 40 by the frame 30. The frame 30 is a metal layer containing, for example, copper, Kovar, gold, aluminum, and / or tungsten.

[0027] [Manufacturing method] Figures 4(a) to 4(d) are cross-sectional views showing a method for manufacturing an elastic wave device 100 according to Example 1. As shown in Figure 4(a), the first layer 11 and the second layer 12 are bonded at room temperature using a surface activation method, and then the second layer 12 is polished to the desired thickness using a chemical mechanical polishing (CMP) method. Next, the piezoelectric layer 20 is bonded to the second layer 12 at room temperature using a surface activation method. After that, the first layer 11 and the piezoelectric layer 20 are polished to the desired thickness using the CMP method.

[0028] As shown in Figure 4(b), a portion of the piezoelectric layer 20 is removed using photolithography and etching. Next, an elastic wave element 50 and wiring 21 connected to the elastic wave element 50 are formed on the piezoelectric layer 20. The elastic wave element 50 is formed, for example, using photolithography and etching. The wiring 21 is formed, for example, using the lift-off method.

[0029] As shown in Figure 4(c), a frame 30 surrounding the piezoelectric layer 20 and the elastic wave element 50, and a bonding layer (not shown) on the frame 30 are formed on the first substrate 10. In addition, bumps 33 and a bonding layer (not shown) on the bumps 33 are formed on the wiring 21. The frame 30, bumps 33, and bonding layer are formed, for example, by electroplating.

[0030] As shown in Figure 4(d), the first substrate 10 is mounted on the second substrate 40 by bonding the bump 33 and frame 30 to the electrodes 41 and metal layer 44 provided on the second substrate 40 using a bonding layer (not shown). This forms the elastic wave device 100 according to Example 1.

[0031] [Comparative Examples 1 and 2] Figure 5(a) is a cross-sectional view of the elastic wave device 500 according to Comparative Example 1. As shown in Figure 5(a), in Comparative Example 1, the first substrate 10 is formed only by the first layer 11. The other configurations are the same as in Example 1, so their description is omitted.

[0032] Figure 5(b) is a cross-sectional view of the elastic wave device 510 according to Comparative Example 2. As shown in Figure 5(b), in Comparative Example 2, the first substrate 10 is formed only by the second layer 12. The other configurations are the same as in Example 1, so their description is omitted.

[0033] [Simulation 1] For each model of the elastic wave device in Example 1, Comparative Example 1, and Comparative Example 2, simulations were performed to determine the surface temperature of the piezoelectric layer 20 when a predetermined power consumption is assumed in each resonator. The conditions used in the simulations are as follows. Common conditions Second substrate 40: HTCC (High Temperature Co-fired Ceramics) substrate Electrode 41, wiring 42, metal layer 44: tungsten layer Terminal 43: Tin-silver-copper solder Frame 30 and bump 33: copper layer IDT 51 and reflector 52 of elastic wave element 50: aluminum layer Wiring 21: Gold layer Piezoelectric layer 20: Lithium tantalate layer Conditions for Example 1 First substrate 10: A laminated substrate consisting of a first layer 11 made of a 50 μm thick sapphire layer and a second layer 12 made of a 50 μm thick silicon layer. Conditions for Comparative Example 1 First substrate 10: A single-layer substrate consisting of a first layer 11 made of a sapphire layer with a thickness of 100 μm. Conditions for Comparative Example 2 First substrate 10: A single-layer substrate consisting of a second layer 12 made of a silicon layer with a thickness of 100 μm.

[0034] Table 1 shows the thermal conductivity of each material used in the simulation. [Table 1]

[0035] Table 2 shows the simulation results for the surface temperature of the piezoelectric layer 20. [Table 2] As shown in Table 2, the maximum temperature for Example 1 was 100.9°C, for Comparative Example 1 it was 115.4°C, and for Comparative Example 2 it was 98.5°C. As shown in Table 1, silicon has a higher thermal conductivity than sapphire. For this reason, Comparative Example 2, which used a single-layer substrate with a silicon layer for the first substrate 10 and a second layer 12 made of silicon, showed improved heat dissipation compared to Comparative Example 1, which used a single-layer substrate with a sapphire layer for the first layer 11, and it is thought that the surface temperature of the piezoelectric layer 20 was kept low. In Example 1, which used a laminated substrate with a sapphire layer for the first substrate 10 and a silicon layer for the second layer 12, it is thought that the surface temperature of the piezoelectric layer 20 was between that of Comparative Example 1 and Comparative Example 2.

[0036] [Simulation 2] Simulations were performed on the stress generated on the lower surface of the first substrate 10 when a load was applied to the upper surface of the first substrate 10 for models A, B, and C. Figure 6(a) is a cross-sectional view of model A, Figure 6(b) is a cross-sectional view of model B, Figure 6(c) is a cross-sectional view of model C, and Figure 6(d) is a plan view of the second substrate 40 in models A, B, and C. As shown in Figures 6(a) to 6(d), models A to C are configured in which the first substrate 10 is mounted on the upper surface of the second substrate 40 by bumps 33. Terminals 43 are provided on the lower surface of the second substrate 40. As shown in Figure 6(a), in model A, the first substrate 10 is a laminated substrate consisting of a first layer 11 made of a sapphire layer and a second layer 12 made of a silicon layer. As shown in Figure 6(b), in model B, the first substrate 10 is a single-layer substrate consisting of a first layer 11 made of a sapphire layer. As shown in Figure 6(c), in Model C, the first substrate 10 is a single-layer substrate consisting of a second layer 12 made of a silicon layer.

[0037] The simulation conditions are as follows: Common conditions Second board 40: HTCC board with length L1 of 1.09 mm, width W1 of 0.89 mm, and height H1 of 0.117 mm. Terminal 43: Tin-silver-copper solder with length L2 of 0.244 mm, width W2 of 0.174 mm, and height H2 of 0.03 mm. Bump 33: Gold layer with a diameter D of 0.075 mm and a height H3 of 0.0193 mm. Load F applied to the upper surface of the first substrate 10: 30 MPa Conditions for Model A First substrate 10: A laminated substrate consisting of a first layer 11 made of a sapphire layer with a thickness T1 of 50 μm and a second layer 12 made of a silicon layer with a thickness T2 of 50 μm. Conditions for Model B First substrate 10: A single-layer substrate consisting of a first layer 11 made of a sapphire layer with a thickness T1 of 100 μm. Conditions for Model C First substrate 10: A single-layer substrate consisting of a second layer 12 made of a silicon layer with a thickness T2 of 100 μm.

[0038] Table 3 shows the Young's modulus and Poisson's ratio of each material used in the simulation. [Table 3]

[0039] Table 4 shows the simulation results for stress. [Table 4]

[0040] As shown in Table 4, the maximum stress on the underside of the first substrate 10 was 198 MPa for Model A, 379 MPa for Model B, and 312 MPa for Model C. Model B, which uses a single-layer substrate with a first layer 11 made of a sapphire layer, was able to suppress damage to the first substrate 10 because the bending strength of sapphire is approximately 470 MPa. On the other hand, Model C, which uses a single-layer substrate with a second layer 12 made of a silicon layer, was able to suppress damage to the first substrate 10 because the bending strength of silicon is approximately 250 MPa. Model A, which uses a laminated substrate with a first layer 11 made of a sapphire layer and a second layer 12 made of a silicon layer, was able to suppress damage to the first substrate 10 because the maximum stress on the underside of the first substrate 10 was 198 MPa. From this, it can be seen that by using a laminated substrate consisting of a first layer 11 which is a silicon layer and a second layer 12 which is a sapphire layer with greater bending strength than silicon as the first substrate 10, damage to the first substrate 10 can be suppressed.

[0041] From the results of Simulation 1, it is preferable from the viewpoint of heat dissipation to make the first substrate 10 a single-layer substrate of silicon with high thermal conductivity. However, as shown in the results of Simulation 2, if the first substrate 10 is a single-layer substrate of silicon, it is possible that the first substrate 10 will break down. Therefore, the first substrate 10 will be a laminated substrate of sapphire layer and silicon layer. This makes it possible to achieve both heat dissipation and pressure resistance.

[0042] [Comparative Example 3] Figure 7 is a cross-sectional view of the elastic wave device 520 according to Comparative Example 3. As shown in Figure 7, in Comparative Example 3, the positions of the first layer 11 and the second layer 12 on the first substrate 10 are swapped compared to Example 1. That is, the piezoelectric layer 20 is bonded to the surface 15 of the first layer 11. The second layer 12 is bonded to the surface 14 of the first layer 11 opposite to the piezoelectric layer 20. The other configurations are the same as in Example 1, so their explanation is omitted.

[0043] [Simulation 3] For each model of the elastic wave device in Example 1 and Comparative Example 3, simulations were performed to determine the surface temperature of the piezoelectric layer 20 when the ratio of the thicknesses of the first layer 11 and the second layer 12 of the first substrate 10 was changed, assuming that a predetermined power consumption was consumed in each resonator. The simulation conditions were the same as in Simulation 1, except for the change in the thickness ratio of the first layer 11 and the second layer 12.

[0044] Figure 8 shows the simulation results of the surface temperature of the piezoelectric layer 20 with respect to the thickness ratio of the second layer 12. In Figure 8, the horizontal axis represents the ratio of the thickness T2 of the second layer 12 to the thickness T0 of the first substrate 10, and the vertical axis represents the maximum surface temperature of the piezoelectric layer 20. As shown in Figure 8, in Example 1, the surface temperature of the piezoelectric layer 20 was kept lower than in Comparative Example 3, regardless of the ratio of the thickness T2 of the second layer 12. This is because in Comparative Example 3, the first layer 11, made of a sapphire layer, is provided near the elastic wave element 50, which is the heat source, whereas in Example 1, the second layer 12, made of a silicon layer, is provided. Since silicon has a higher thermal conductivity than sapphire, it is thought that providing the second layer 12, made of a silicon layer, near the elastic wave element 50 makes it easier for the heat generated by the elastic wave element 50 to be dissipated to the first substrate 10. For this reason, it is thought that the surface temperature of the piezoelectric layer 20 was kept lower in Example 1 compared to Comparative Example 3.

[0045] Furthermore, as shown in Figure 8, when the proportion of the thickness T2 of the second layer 12, which is the silicon layer, increases, the surface temperature of the piezoelectric layer 20 decreases linearly in Comparative Example 3, whereas in Example 1, the surface temperature of the piezoelectric layer 20 decreases inversely. The thickness T2 of the second layer 12 may have errors from the design value (for example, about ±10 μm) during manufacturing. If there is variation in the thickness T2 of the second layer 12, there will also be variation in the surface temperature of the piezoelectric layer 20. The device may be temperature controlled using a temperature compensation circuit or the like, but if the variation in the device temperature is large, it may fall outside the range in which the temperature can be controlled by the temperature compensation circuit or the like. Therefore, even if there is variation in the thickness T2 of the second layer 12, it is preferable that the variation in the device temperature is small. From this viewpoint, it is preferable that the proportion of the thickness T2 of the second layer 12 is 50% or more.

[0046] [Simulation 4] For Model A shown in Figure 6(a), a simulation was performed to determine the stress generated on the lower surface of the first substrate 10 when a load is applied to the upper surface of the first substrate 10, while varying the thickness ratio of the first layer 11 to the second layer 12. The simulation conditions were the same as in Simulation 2, except for the change in the thickness ratio of the first layer 11 to the second layer 12.

[0047] Figure 9 shows the simulation results of the stress generated on the lower surface of the first substrate 10 in relation to the thickness ratio of the second layer 12. In Figure 9, the horizontal axis represents the ratio of the thickness of the second layer 12 to the thickness of the first substrate 10, and the vertical axis represents the maximum stress generated on the lower surface of the first substrate 10. As shown in Figure 9, the maximum stress generated on the lower surface of the first substrate 10 increased as the thickness ratio of the second layer 12 increased. The second layer 12 is a silicon layer, and the bending strength of silicon is approximately 250 MPa. Therefore, from the viewpoint of suppressing fracture of the first substrate 10, it is preferable that the ratio of the second layer 12 is 80% or less.

[0048] [Differentiation] Figure 10(a) is a cross-sectional view of an elastic wave device 110 according to a modified example 1 of Embodiment 1. As shown in Figure 10(a), the first substrate 10 may include a third layer 13 bonded to the surface 14 of the first layer 11. The third layer 13 may be a layer formed of the same material as the second layer 12, for example (e.g., a silicon layer). Let the thickness of the third layer 13 be T3. In this case, the thickness T0 of the first substrate 10 is thickness T1 + thickness T2 + thickness T3. Even when the third layer 13 is provided, the thickness T2 is 50% or more and 80% or less of the thickness T0. The other configurations are the same as in Embodiment 1, so their description is omitted.

[0049] Figure 10(b) is a cross-sectional view of an elastic wave device 120 according to a modified example 2 of Example 1. As shown in Figure 10(b), an insulating layer 25 may be provided between the second layer 12 and the piezoelectric layer 20. The insulating layer 25 may be a single layer or may consist of multiple layers stacked together. The insulating layer 25 may include, for example, a silicon oxide layer, an aluminum oxide layer, and / or an aluminum nitride layer. Also, the first substrate 10 may not have the second layer 12 in its peripheral region. The frame 30 may be provided between the first substrate 10 and the second substrate 40, in contact with the first layer 11. The other configurations are the same as in Example 1, so their description is omitted.

[0050] Figure 10(c) is a cross-sectional view of an elastic wave device 130 according to a modification 3 of Example 1. As shown in Figure 10(c), the second substrate 40 is, for example, a sapphire substrate, a silicon substrate, or a spinel substrate, and may be provided with via wiring 45 that penetrates from the top surface to the bottom surface. The elastic wave element 50 may be electrically connected to the terminal 43 via the bump 33 and the via wiring 45. Also, as with modification 2, the first substrate 10 does not have a second layer 12 in the peripheral region, and the frame 30 may be in contact with the first layer 11 and provided between the first substrate 10 and the second substrate 40. The other configurations are the same as in Example 1, so their description is omitted. When the first layer 11 and the second substrate 40 are made of the same material (for example, when they are both sapphire substrates), the stress generated in the frame 30 can be reduced.

[0051] According to Example 1 and its modified form, the first substrate 10 mounted on the second substrate 40 has a first layer 11 which is a sapphire layer, and a second layer 12 which is a silicon layer with a higher thermal conductivity than the first layer 11, provided on the surface 15 (first surface) of the first layer 11, and the ratio of the thickness T2 of the second layer 12 to the thickness T0 of the first substrate 10 is 50% or more. The elastic wave element 50 is provided on the surface 17 of the second layer 12 opposite to the first layer 11. By providing the second layer 12, which has a higher thermal conductivity than the first layer 11, near the elastic wave element 50, the heat generated by the elastic wave element 50 is more easily dissipated to the first substrate 10. Because the first layer 11 is a sapphire layer, the stress generated on the lower surface of the first substrate 10 is reduced, as shown in Simulation 2, and damage to the first substrate 10 can be suppressed. Therefore, both heat dissipation and pressure resistance can be achieved. By having a ratio of the thickness T2 of the second layer 12 to the thickness T0 of the first substrate 10 of 50% or more, as shown in Figure 8, even if the thickness of the second layer 12 varies during manufacturing, the variation in device temperature can be kept to a minimum. From the viewpoint of keeping the variation in device temperature to a minimum, the ratio of the thickness T2 of the second layer 12 to the thickness T0 of the first substrate 10 is preferably 55% or more, more preferably 60% or more, and even more preferably 65% ​​or more.

[0052] Furthermore, in Model A of Simulation 2, as shown in Figure 6(a), when the first substrate 10 has a laminated structure of a first layer 11 and a second layer 12, the stress generated on the lower surface of the first substrate 10 was reduced when the first layer 11 was a sapphire layer. However, the first layer 11 may be a spinel layer, a quartz layer, a silicon carbide layer, an HTCC layer, an LTCC layer, or an FRP layer, in addition to a sapphire layer. In these cases as well, since the rigidity is higher than that of a silicon layer, the stress generated on the lower surface of the first substrate 10 is reduced, similar to the case of a sapphire layer. Also, in these cases, the bending strength of the first layer 11 is increased. Therefore, damage to the first substrate 10 can be suppressed. The spinel layer is a polycrystalline or amorphous MgAl2O4 layer, the quartz layer is a single-crystal SiO2 layer, and the silicon carbide layer is a polycrystalline or single-crystal SiC layer. The HTCC layer is a High Temperature Co-fired Ceramics layer, the LTCC layer is a Low Temperature Co-fired Ceramics layer, and the FRP layer is a Fiber Reinforced Plastics layer.

[0053] Furthermore, in Example 1 and its modified form, the second layer 12 is a silicon layer. In this case, because silicon has high thermal conductivity, the heat generated in the elastic wave element 50 is easily dissipated to the first substrate 10. However, the second layer 12 may be an insulating layer made of a material other than silicon, as long as its thermal conductivity is greater than that of the first layer 11. For example, the second layer 12 may be an alumina layer, a silicon carbide layer, or a graphite layer, in addition to a silicon layer. In these cases as well, heat dissipation can be improved. Also, Figure 8 shows the results when the second layer 12 is a silicon layer, but since the relationship is that the second layer 12 has higher thermal conductivity than the first layer 11, it is thought that similar results can be obtained even if the second layer 12 is not a silicon layer, as long as its thermal conductivity is greater than that of the first layer 11. In other words, by making the thickness ratio of the second layer 12 50% or more, it is thought that the variation in device temperature can be kept small even if the thickness of the second layer 12 varies. The alumina layer is a polycrystalline or amorphous Al2O3 layer, the silicon carbide layer is a polycrystalline or single-crystal SiC layer, and the graphite layer consists of stacked sheets of carbon atoms bonded in a hexagonal lattice structure.

[0054] Furthermore, in Example 1, the elastic wave element 50 is placed between the first substrate 10 and the second substrate 40, and the frame 30 that seals the elastic wave element 50 in the gap 32 between the first substrate 10 and the second substrate 40 is in contact with the second layer 12. As a result, the heat dissipated from the elastic wave element 50 to the second layer 12 is more easily dissipated to the second substrate 40 via the frame 30.

[0055] Furthermore, in Example 1 and its modified form, the frame 30 is made of metal. This makes it easier for the heat dissipated from the elastic wave element 50 to the first substrate 10 to be dissipated to the second substrate 40 via the frame 30. The frame 30 is preferably made of a metal material with high thermal conductivity, for example, it is preferably made containing copper.

[0056] Furthermore, in Example 1 and its modified form, the second layer 12 is a silicon layer, and the ratio of the thickness T2 of the second layer 12 to the thickness T0 of the first substrate 10 is 80% or less. This suppresses damage to the first substrate 10, as shown in Figure 9. From the viewpoint of suppressing damage to the first substrate 10, the ratio of the thickness T2 of the second layer 12 to the thickness T0 of the first substrate 10 is preferably 77% or less, more preferably 74% or less, and even more preferably 70% or less.

[0057] Furthermore, in the modified example 1 of Embodiment 1, as shown in Figure 10(a), the first substrate 10 comprises a first layer 11, a second layer 12, and a third layer 13. The second layer 12 is provided on the surface 15 (first surface) of the first layer 11, and the third layer 13 is provided on the surface 14 (second surface) of the first layer 11. The third layer 13 is formed from the same material as the second layer 12 (for example, silicon). In this way, by providing the second layer 12 and the third layer 13, made of the same material, on either side of the first layer 11, the warping that occurs in the first substrate 10 can be reduced.

[0058] In Example 1 and its modified form, elements such as inductors may be provided on the first substrate 10 and / or the second substrate 40. Figure 11(a) is a plan view when passive elements are provided on the first substrate 10, and Figure 11(b) is a plan view when passive elements are provided on the second substrate 40. As shown in Figures 11(a) and 11(b), a resistor 60, a capacitor 61, and an inductor 62 connected by wiring 21 may be provided on the first substrate 10 in an area where the piezoelectric layer 20 is not provided. A capacitor 71 and an inductor 72 connected by wiring 46 may be provided on the second substrate 40. The resistor 60, capacitor 61, and inductor 62 of the first substrate 10 and the capacitor 71 and inductor 72 of the second substrate 40 may be electrically connected to each other via bumps 33d joined to the electrode 41a.

[0059] In Example 1 and its modified form, a multiplexer such as a duplexer may be formed by the elastic wave element 50 provided on the first substrate 10. Furthermore, the element provided on the first substrate 10 may be something other than the elastic wave element 50. For example, it may be a MEMS (Micro Electro Mechanical System) element or an odor sensor element, or something other than a piezoelectric element.

[0060] Although embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention as described in the claims. [Explanation of Symbols]

[0061] 10...First substrate, 11...First layer, 12...Second layer, 13...Third layer, 14...Surface, 15...Surface, 16...Surface, 17...Surface, 20, 20a...Piezoelectric layer, 21...Wiring, 25...Insulating layer, 30...Frame, 32...Void, 33, 33a, 33b, 33c, 33d...Bump, 40...Second substrate, 41, 41a...Electrode, 42...Wiring, 43...Terminal, 44...Metal layer, 45...Via wiring, 46...Wiring, 50 50a...Elastic wave element, 51...IDT, 52...Reflector, 53...Comb electrode, 54...Electrode finger, 55...Busbar, 56...Crossing region, 57...Electrode, 58...Air gap, 59...Resonant region, 60...Resistor, 61...Capacitor, 62...Inductor, 70...Filter, 71...Capacitor, 72...Inductor, 100, 110, 120, 130, 500, 510, 520...Elastic wave device

Claims

1. A first substrate having a first layer which is a sapphire layer, spinel layer, quartz layer, HTCC layer, LTCC layer, or FRP layer, and a second layer provided on the first surface of the first layer which has a greater thermal conductivity than the first layer, wherein the ratio of the thickness of the second layer to the total thickness is 50% or more, An element provided on the surface of the second layer opposite to the first layer, A second substrate on which the first substrate is mounted and which has wiring electrically connected to the element, An electronic component comprising: a frame provided between the first substrate and the second substrate, surrounding the element, and sealing the element in the gap between the first substrate and the second substrate.

2. The electronic component according to claim 1, wherein the frame is in contact with the second layer.

3. The electronic component according to claim 1 or 2, wherein the frame is made of metal.

4. The electronic component according to claim 1 or 2, wherein the second layer is a silicon layer, an alumina layer, a silicon carbide layer, or a graphite layer.

5. The aforementioned second layer is a silicon layer, The electronic component according to claim 1 or 2, wherein the ratio of the thickness of the second layer to the total thickness of the first substrate is 80% or less.

6. The electronic component according to claim 1 or 2, wherein the first substrate has a third layer provided on a second surface opposite to the first surface of the first layer, and is made of the same material as the second layer.

7. The electronic component according to claim 1 or 2, wherein the first layer is a sapphire layer and the second layer is a silicon layer.

8. The electronic component according to claim 1 or 2, wherein the element is an elastic wave element.

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