Power module
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- ROHM CO LTD
- Filing Date
- 2026-04-24
- Publication Date
- 2026-06-25
AI Technical Summary
【0150】 (作用) 次に、本実施形態の作用について、比較例のパワーモジュールとの比較に基づいて説明する。比較例のパワーモジュールは、本実施形態のパワーモジュール1から上側ダイオード71及び下側ダイオード72を省略した構成である。
Smart Images

Figure 2026105133000001_ABST
Abstract
Claims
1. A plurality of first chips are provided on the front side of a wide-bandgap semiconductor layer having a front surface and a back surface, each chip having a plurality of transistor cells that perform switching operations between a first electrode and a second electrode in accordance with the control of a control electrode. A plurality of second chips, each having a cathode connected to the first electrode and an anode connected to the second electrode, A diode is provided as a parasitic element of each transistor cell included in the plurality of transistor cells, with the cathode connected to the first electrode and the anode connected to the second electrode, A substrate on which the plurality of first chips and the plurality of second chips are mounted, A sealing resin that seals at least a portion of the substrate, the plurality of first chips, and the plurality of second chips, Equipped with, The forward threshold voltage of each of the plurality of second chips is lower than the forward threshold voltage of the diode. Power module.
2. The allowable DC rated current of the plurality of second chips is less than the allowable DC rated current of the plurality of first chips. The power module according to claim 1.
3. The second chip is a Schottky barrier diode. The power module according to claim 1.
4. The second electrode is electrically connected to the first terminal and to a second terminal different from the first terminal. The power module according to claim 1.
5. The aforementioned wide-bandgap semiconductor layer is composed of a semiconductor using SiC. The power module according to claim 1.
6. The aforementioned transistor cell is a MISFET, The first electrode is a drain electrode, the second electrode is a source electrode, and the control electrode is an gate electrode. A power module according to any one of claims 1 to 5.
7. The substrate is a graphite substrate. The power module according to claim 1.
8. The plurality of first chips and the plurality of second chips are arranged in a line on the substrate. The aforementioned multiple first chips are connected in parallel. The aforementioned multiple second chips are connected in parallel. The power module according to claim 1.
9. The aforementioned plurality of first chips are An upper switching element having a first upper terminal connected to the first electrode, a second upper terminal connected to the second electrode, and an upper control terminal connected to the control electrode, A lower switching element having a first lower terminal connected to the first electrode, a second lower terminal connected to the second electrode, and a lower control terminal connected to the control electrode, Includes, The aforementioned plurality of second chips are An upper Schottky barrier diode is provided between the first upper terminal and the second upper terminal such that the first upper terminal is connected to the cathode, A lower Schottky barrier diode is provided between the first lower terminal and the second lower terminal such that the first lower terminal is connected to the cathode, including, The power module according to claim 1.
10. The substrate comprises a first substrate having a first surface-side metal layer and a second substrate having a second surface-side metal layer. In a plan view of the substrate, the first substrate and the second substrate are arranged side by side in a first direction. The first substrate and the second substrate are arranged in a rectangular shape such that the second direction, which is perpendicular to the first direction in a plan view of the substrate, is the longitudinal direction. The second upper terminals of the plurality of upper switching elements are each electrically connected to the second surface metal layer by an upper power connecting member. The second lower terminals of the plurality of lower switching elements are each electrically connected to the connection portion by a lower power connection member. The power module according to claim 9.