Semiconductor device and method for manufacturing the same
The semiconductor device addresses high integration and miniaturization challenges by using a vertical and horizontal nanosheet arrangement with air gaps between pads, reducing parasitic capacitance and enhancing reliability in 3D memory devices.
JP2026105833APending Publication Date: 2026-06-26SK HYNIX INC
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- SK HYNIX INC
- Filing Date
- 2025-11-18
- Publication Date
- 2026-06-26
Smart Images
Figure 2026105833000001_ABST
Abstract
To provide a semiconductor device equipped with highly integrated memory cells and a method for manufacturing the same. [Solution] The semiconductor device may include a vertical and horizontal arrangement of nanosheets, a horizontal conductive line oriented horizontally while surrounding the horizontal arrangement of nanosheets, pads connected to the edges of the horizontal conductive line, and an inter-pad insulating layer having an air gap located between the pads.
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