Multilayer electronic components

Abstract

We provide multilayer ceramic capacitors (MLCCs) with excellent capacitance, temperature-dependent characteristics, and lifetime reliability. [Solution] In the dielectric layer contained in the MLCC, a plurality of first dielectric crystal grains 11 have a first core-shell structure including a first core 11a and a first shell 11b, and a plurality of second dielectric crystal grains 12 have a second core-shell structure including a second core 12a and a second shell 12b. When the average Ca content (at%) contained in the first core and the second core are C1 and C2, respectively, and the maximum Ca content (at%) contained in the first shell and the second shell are S1 and S2, respectively, one or more of the plurality of first dielectric crystal grains satisfy S1-C1≧0.7at%, and one or more of the plurality of second dielectric crystal grains satisfy C2-S2<0.5at%.

Description

[Technical Field]

[0001] This invention relates to a stacked electronic component. [Background technology]

[0002] Multi-Layered Ceramic Capacitors (MLCCs), a type of multilayer electronic component, are chip-type capacitors mounted on printed circuit boards of various electronic products such as LCDs (Liquid Crystal Displays) and PDPs (Plasma Display Panels), computers, smartphones, and mobile phones, where they play the role of charging or discharging electricity. MLCCs are used as components in a wide range of electronic devices due to their advantages of being small, yet guaranteeing high capacitance, and being easy to mount.

[0003] In the case of MLCCs used in automotive electrical components, the demand for high-temperature guarantees is increasing due to the harsher operating environments. However, BaTiO3 (BT), which has a Curie temperature of approximately 120°C, has the problem of a rapid decrease in dielectric constant at temperatures above that.

[0004] To improve the temperature coefficient of capacitance (TCC) of MLCCs (Ba 1-x Ca x While TiO3 (BCT) can be used, BCT has the drawback of having a lower room-temperature dielectric constant compared to BT.

[0005] Therefore, methods have been proposed to form dielectric layers by mixing BT and BCT. However, in order to develop MLCCs with superior capacitance, temperature change characteristics, and lifetime reliability, further research is needed on the microstructure of the dielectric crystal grains constituting the dielectric layer. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Korean Published Patent Gazette No. 10-2013-0062343 [Overview of the project] [Problems that the invention aims to solve]

[0007] One of the several objectives of the present invention is to provide a multilayer electronic component with excellent capacitance and reliability.

[0008] However, the objectives of the present invention are not limited to those described above and can be more easily understood in the process of describing specific embodiments of the present invention. [Means for solving the problem]

[0009] A stacked electronic component according to one embodiment of the present invention includes a body containing Ba, Ti, and Ca, a dielectric layer having a plurality of first dielectric crystal grains and a plurality of second dielectric crystal grains, and internal electrodes arranged alternately with the dielectric layer, and external electrodes arranged on the body, wherein the plurality of first dielectric crystal grains have a first core-shell structure including a first core and a first shell arranged on at least a part of the first core, and the plurality of second dielectric crystal grains have a second core-shell structure including a second core and a second shell arranged on at least a part of the second core, and when the average content (at%) of Ca contained in the first core and the second core are C1 and C2, respectively, and the maximum content (at%) of Ca contained in the first shell and the second shell are S1 and S2, respectively, one or more of the plurality of first dielectric crystal grains can satisfy S1-C1≧0.7at%, and one or more of the plurality of second dielectric crystal grains can satisfy C2-S2<0.5at%. [Effects of the Invention]

[0010] One of the various effects of the present invention is that it can provide a stacked electronic component with excellent capacity and reliability.

Brief Description of the Drawings

[0011] [Figure 1] It is a perspective view schematically showing a laminated electronic component according to an embodiment of the present invention. [Figure 2] It is a cross-sectional view schematically showing a cut cross-section along the line I-I' of FIG. 1. [Figure 3] It is a cross-sectional view schematically showing a cut cross-section along the line II-II' of FIG. 1. [Figure 4] It is an enlarged view schematically showing the K1 region of FIG. 2. [Figure 5a] It is a graph showing the content of Y by position according to a line profile for dielectric crystal grains. [Figure 5b] It is a graph showing the content of Ca by position according to a line profile for the first dielectric crystal grains. [Figure 5c] It is a graph showing the content of Ca by position according to a line profile for the second dielectric crystal grains. [Figure 6a] It is an image obtained by measuring the Ca distribution inside the dielectric layer using transmission electron microscope-energy dispersive X-ray analysis (TEM-EDS). [Figure 6b] It is an image of line analysis of the first dielectric crystal grains using TEM-EDS. [Figure 6c] It is an image of line analysis of the second dielectric crystal grains using TEM-EDS.

Embodiments for Carrying Out the Invention

[0012] Hereinafter, embodiments of the present invention will be described with reference to specific embodiments and the accompanying drawings. However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Also, the embodiments of the present invention are provided to more fully explain the present invention to ordinary technicians. Therefore, the shape, size, etc. of the elements in the drawings can be exaggerated for a clearer explanation, and the elements indicated by the same reference numerals in the drawings are the same elements.

[0013] Furthermore, in order to clearly illustrate the present invention in the drawings, parts unrelated to the explanation have been omitted, and the size and thickness of each component shown in the drawings are arbitrarily shown for the convenience of explanation; therefore, the present invention is not necessarily limited to what is shown. Components with the same function within the scope of the same concept are described using the same reference numerals. Moreover, throughout the specification, when a part "includes" a certain component, this does not exclude other components unless otherwise stated, but rather means that it may further include other components.

[0014] In the drawing, the first direction X can be defined as the thickness T direction, the second direction Y as the length L direction, and the third direction Z as the width W direction.

[0015] Multilayer electronic components Figure 1 is a schematic perspective view of a stacked electronic component according to one embodiment of the present invention, Figure 2 is a schematic cross-sectional view showing a section along the line I-I' in Figure 1, Figure 3 is a schematic cross-sectional view showing a section along the line II-II' in Figure 1, Figure 4 is a schematic enlarged view showing the K1 region in Figure 2, Figure 5a is a graph showing the positional Y content by line profile for dielectric crystal grains, Figure 5b is a graph showing the positional Ca content by line profile for the first dielectric crystal grain, Figure 5c is a graph showing the positional Ca content by line profile for the second dielectric crystal grain, Figure 6a is an image of the Ca distribution inside the dielectric layer measured using transmission electron microscopy-energy dispersive X-ray analysis (TEM-EDS), Figure 6b is an image of line analysis of the first dielectric crystal grain using TEM-EDS, and Figure 6c is an image of line analysis of the second dielectric crystal grain using TEM-EDS.

[0016] Hereinafter, with reference to Figures 1 to 6c, a multilayer electronic component 100 according to one embodiment of the present invention will be described in detail. Furthermore, a multilayer ceramic capacitor will be described as an example of a multilayer electronic component, but the present invention is not limited thereto and can be applied to various multilayer electronic components, such as inductors, piezoelectric elements, varistors, or thermistors.

[0017] A stacked electronic component 100 according to one embodiment of the present invention may include a body 110 including a dielectric layer 111 and internal electrodes 121, 122, and external electrodes 131, 132 disposed on the body 110.

[0018] There are no particular restrictions on the specific shape of the main body 110, but as shown in the figure, the main body 110 can be a hexahedron or a similar shape. Due to the shrinkage of the ceramic powder contained in the main body 110 during the firing process, or due to the polishing process on the corners of the main body 110, the main body 110 may not be a perfectly straight hexahedron, but may have a substantially hexahedron shape.

[0019] The main body 110 may have a first surface 1 and a second surface 2 facing each other in a first direction, a third surface 3 and a fourth surface 4 connected to the first surface 1 and the second surface 2 and facing each other in a second direction, a fifth surface 5 and a sixth surface 6 connected to the first surface 1, the second surface 2, the third surface 3 and the fourth surface 4 and facing each other in a third direction.

[0020] The main body 110 may include dielectric layers 111 and internal electrodes 121 and 122 arranged alternately with the dielectric layers 111. The multiple dielectric layers 111 forming the main body 110 are in a fired state, and the boundaries between adjacent dielectric layers 111 can be integrated to such an extent that they are difficult to confirm without using a scanning electron microscope (SEM).

[0021] The internal electrodes 121 and 122 may include, for example, a first internal electrode 121 and a second internal electrode 122 that are alternately arranged in a first direction with the dielectric layer 111 in between. The main body 110 may include a capacitance forming section Ac that forms capacitance, which includes the first internal electrode 121 and the second internal electrode 122 that are arranged facing each other with the dielectric layer 111 in between.

[0022] The first internal electrode 121 is separated from the fourth surface 4 and can be connected to the first external electrode 131 at the third surface 3. The second internal electrode 122 is separated from the third surface 3 and can be connected to the second external electrode 132 at the fourth surface 4.

[0023] The conductive metal contained in the internal electrodes 121 and 122 may be one or more of Ni, Cu, Pd, Ag, Au, Pt, Sn, W, Ti, and alloys thereof, and may more preferably contain Ni, but the present invention is not limited thereto.

[0024] The main body 110 may include cover portions 112 and 113 arranged on both sides facing the first direction of the capacitance forming portion Ac, and margin portions 114 and 115 arranged on both sides facing the third direction of the capacitance forming portion Ac. The cover portions 112 and 113 and the margin portions 114 and 115 may have a configuration similar to that of the dielectric layer 111, except that they do not include internal electrodes.

[0025] The external electrodes 131 and 132 may include a first external electrode 131 positioned on the third surface 3 and extending over parts of the first surface 1, the second surface 2, the fifth surface 5, and the sixth surface 6, and a second external electrode 132 positioned on the fourth surface 4 and extending over parts of the first surface 1, the second surface 2, the fifth surface 5, and the sixth surface 6.

[0026] The type and form of the external electrodes 131 and 132 are not particularly limited and may have a multilayer structure. For example, the external electrodes 131 and 132 may include base electrode layers 131a and 132a that come into contact with the internal electrodes 121 and 122, and plating layers 131b and 132b placed on the base electrode layers 131a and 132a.

[0027] The base electrode layers 131a and 132a may be fired electrode layers containing metal and glass. The metal contained in the base electrode layers 131a and 132a may include, for example, Cu, Ni, Pd, Pt, Au, Ag, Pb, and / or alloys containing these. The glass contained in the base electrode layers 131a and 132a may include, for example, one or more oxides of Ba, Ca, Zn, Al, B, and Si.

[0028] The base electrode layers 131a and 132a can consist solely of fired electrode layers, but the present invention is not limited thereto. The base electrode layers 131a and 132a may include fired electrode layers containing metal and glass, as well as resin electrode layers disposed on the fired electrode layers and containing metal particles and resin.

[0029] The metal particles contained in the resin electrode layer may include one or more spherical particles and flake-shaped particles. The metal particles contained in the resin electrode layer may include, for example, Cu, Ni, Pd, Pt, Au, Ag, Pb, Sn and / or alloys containing these. The resin contained in the resin electrode layer may include, for example, one or more epoxy resin, acrylic resin, and ethylcellulose.

[0030] The plating layers 131b and 132b may include, for example, Ni, Sn, Pd, and / or alloys containing these, and may be formed in multiple layers. The plating layers 131b and 132b may be, for example, a Ni plating layer or a Sn plating layer, and may be in a form in which the Ni plating layer and the Sn plating layer are formed sequentially. The plating layers 131b and 132b may also include multiple Ni plating layers and / or multiple Sn plating layers.

[0031] The drawings illustrate a structure in which the stacked electronic component 100 has two external electrodes 131 and 132, but it is not limited to this, and the number and shape of the external electrodes 131 and 132 can be changed according to the form of the internal electrodes 121 and 122 or other purposes.

[0032] The dielectric layer 111 can contain, for example, a perovskite compound represented by the general formula ABO3. The above A contains one or more of Ba and Ca, and the above B can contain one or more of Ti and Zr. The dielectric layer 111 can contain the perovskite compound as a main component.

[0033] The dielectric layer 111 can contain Ba and Ti. The dielectric layer 111 can contain, for example, a barium titanate (BaTiO3)-based compound as a main component. The barium titanate-based compound includes BaTiO3, (Ba 1-x Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1), and Ba(Ti 1-y Zr y )O3 (0 < y < 1), and can contain one or more of them.

[0034] The dielectric layer 111 can contain Ca. The Ca contained in the dielectric layer 111 may be derived from a main component such as (Ba 1-x Ca x )TiO3 (BCT), or may be derived from CaCO3 as a sub-component. Although Ca has the same valence as Ba that constitutes the lattice structure of BT, its ionic radius is slightly smaller, so it can effectively replace the Ba-site. In this case, lattice shrinkage can be induced without defective chemical bonding, and the phase transition temperature can be increased by lattice distortion, improving the TCC characteristics of the dielectric.

[0035] In the present invention, "main component" can mean a component that occupies a relatively large weight ratio or atomic ratio compared to other components, and can mean a component that accounts for more than 50 wt% of the total weight of the entire dielectric composition or the entire dielectric layer, more than 50 at% based on the number of atoms, or more than 50 mol% based on the number of moles. In the present invention, "minor component" can mean a component that occupies a relatively small ratio compared to the main component.

[0036] The dielectric layer 111 may include a plurality of first dielectric crystal grains 11 and a plurality of second dielectric crystal grains 12. The plurality of first dielectric crystal grains 11 and the plurality of second dielectric crystal grains 12 may have a core-shell structure. Specifically, the plurality of first dielectric crystal grains 11 may have a first core-shell structure including a first core 11a and a first shell 11b disposed on at least a portion of the first core 11a. The plurality of second dielectric crystal grains 12 may have a second core-shell structure including a second core 12a and a second shell 12b disposed on at least a portion of the second core 12a.

[0037] The above core-shell structure can be formed by adding rare earth elements to the perovskite-type compound. Specifically, the rare earth elements can form shells 11b and 12b by substituting the A site or B site of the perovskite-type compound. Such shells 11b and 12b essentially act as barriers to the flow of oxygen vacancies, thus preventing leakage current.

[0038] The shells 11b and 12b may be arranged to cover all of the surfaces of the cores 11a and 12a, but the present invention is not limited thereto, and the shells 11b and 12b may not cover any part of the surfaces of the cores 11a and 12a. For example, the shells 11b and 12b may be arranged to cover 90% or more of the total length of the surfaces of the cores 11a and 12a, in which case the reliability improvement effect of the present invention may be more pronounced.

[0039] On the other hand, the dielectric layer 111 may also contain one or more third dielectric crystal grains 13 that do not have a core-shell structure.

[0040] Considering the capacitance and reliability of multilayer electronic components, conventional dielectric layers in a mixed grain form composed of BT and BCT crystal grains have been proposed. The BT crystal grains can improve the room-temperature capacitance of the multilayer electronic component, and the BCT crystal grains can improve the TCC of the multilayer electronic component. However, if the microstructure of the dielectric crystal grains is not appropriately controlled, it may be difficult to optimize the capacitance, TCC, and MTTF of the multilayer electronic component if the dielectric layer simply has two types of dielectric crystal grains.

[0041] Therefore, in the stacked electronic component 100 according to one embodiment of the present invention, when the average Ca content (at%) in the first core 11a and the second core 12a are C1 and C2, respectively, and the maximum Ca content (at%) in the first shell 11b and the second shell 12b are S1 and S2, respectively, one or more of the plurality of first dielectric crystal grains 11 can satisfy S1-C1≧0.7at%, and one or more of the plurality of second dielectric crystal grains 12 can satisfy C2-S2<0.5at%. The crystal grain among the plurality of first dielectric crystal grains 11 that satisfies S1-C1≧0.7at% can be defined as the first specific crystal grain, and the crystal grain among the plurality of second dielectric crystal grains 12 that satisfies C2-S2<0.5at% can be defined as the second specific crystal grain. By including the above-mentioned first specific crystal grain and second specific crystal grain that satisfy the above-mentioned numerical range in the stacked electronic component 100, the capacitance, TCC, and MTTF of the stacked electronic component 100 can all be effectively improved.

[0042] If the above S1-C1 is less than 0.7 at%, the TCC of the multilayer electronic component 100 may decrease, and if the above C2-S2 is 0.5 at% or more, the capacitance and / or MTTF of the multilayer electronic component 100 may decrease.

[0043] The upper limit of S1-C1 is not particularly limited, but one or more of the multiple first dielectric crystal grains 11 can satisfy 0.7at% ≤ S1-C1 ≤ 3.0at%. That is, the first specific crystal grain may have an S1-C1 of 3.0at% or less. If S1-C1 exceeds 3.0at%, the dielectric constant of the dielectric layer 111 may decrease. The lower limit of C2-S2 is not particularly limited, and the second specific crystal grain may have a C2-S2 of 0at% or more.

[0044] The above values ​​C1 and S1 can be measured, for example, by a line profile obtained by analyzing the first dielectric crystal grain 11 via TEM-EDS. Referring to Figure 5b, C1 can be measured by taking the average value after measuring the Ca content at multiple equally spaced points located in the first core 11a, for example, five points P1, P3, P5, P7, and P9. S1 can represent the maximum Ca content contained in the first shell 11b as measured by the above line profile.

[0045] The above values ​​C2 and S2 can be measured, for example, by a line profile obtained by analyzing the second dielectric crystal grain 12 via TEM-EDS. Referring to Figure 5c, C2 can be measured by taking the average value after measuring the Ca content at multiple equally spaced points located in the second core 12a, for example, five points P2, P4, P6, P8, and P10. The above value S2 can represent the maximum Ca content contained in the second shell 12b as measured by the line profile.

[0046] On the other hand, the boundaries between the cores 11a, 12a and the shells 11b, 12b can be defined according to the content of the minor component rare earth element (e.g., Y). For example, a plurality of first dielectric crystal grains 11 and a plurality of second dielectric crystal grains 12 may contain the rare earth element Y, the first core 11a and the second core 12a can be defined as regions where the Y content is less than 0.2 at%, and the first shell 11b and the second shell 12b can be defined as regions where the Y content is 0.2 at% or more.

[0047] The Y content can be measured, for example, by analyzing the dielectric crystal grains 11 and 12 via TEM-EDS and obtaining a line profile. Referring to Figure 5a, in the line profile, the boundary between the cores 11a and 12a and the shells 11b and 12b can be defined as the point where the Y content is 0.2 at%. The line profile can be obtained by analyzing the cross-sections in the first and second directions, polished to the center of the third direction of the stacked electronic component 100, using TEM-EDS, for example, from the central regions of the first and second directions of the main body 110 (region K1 in Figure 2).

[0048] Referring to Figure 5a, in one embodiment, the maximum content Y1 of Y contained in the first shell 11b may be 1.0 at% or more, and the maximum content Y2 of Y contained in the second shell 12b may be 1.0 at% or more. This improves the reliability of the stacked electronic component 100 by ensuring that the first dielectric crystal grains 11 and the second dielectric crystal grains 12 have a robust core-shell structure. The upper limits of Y1 and Y2 are not particularly limited, but for example, they may be 5.0 at% or less. If Y1 and Y2 exceed 5.0 at%, the dielectric constant of the dielectric layer 111 may decrease.

[0049] Referring to FIG. 6a, the first dielectric crystal grains 11 and the second dielectric crystal grains 12 can be distinguished by color and / or light and darkness in an image where the Ca distribution is measured using TEM-EDS. However, the first dielectric crystal grains 11 and the second dielectric crystal grains 12 can be more accurately distinguished from the Ca contents of the cores 11a, 12a and the shells 11b, 12b measured by a line profile. Specifically, among the dielectric crystal grains having a core-shell structure, the dielectric crystal grains in which the average content of Ca contained in the core is smaller than the maximum content of Ca contained in the shell can be defined as the first dielectric crystal grains 11, and among the dielectric crystal grains having a core-shell structure, the dielectric crystal grains in which the average content of Ca contained in the core is larger than or the same as the maximum content of Ca contained in the shell can be defined as the second dielectric crystal grains 12. That is, the plurality of first dielectric crystal grains 11 can satisfy C1 < S1, and the plurality of second dielectric crystal grains 12 can satisfy C2 ≧ S2.

[0050] In addition, the first dielectric crystal grains 11 and the second dielectric crystal grains 12 can also be distinguished from the Ca contents of the cores 11a, 12a measured by a line profile. Specifically, among the dielectric crystal grains having a core-shell structure, the dielectric crystal grains in which the average content of Ca contained in the core is less than 0.8 at% can be defined as the first dielectric crystal grains 11, and among the dielectric crystal grains having a core-shell structure, the dielectric crystal grains in which the average content of Ca contained in the core is 0.8 at% or more can be defined as the second dielectric crystal grains 12. That is, the plurality of first dielectric crystal grains 11 can satisfy C1 < 0.8 at%, and the plurality of second dielectric crystal grains 12 can satisfy C2 ≧ 0.8 at%. The upper limit of C2 is not particularly limited, but for example, it may be 5.0 at% or less.

[0051] In one embodiment, among the plurality of first dielectric crystal grains 11, the number ratio of the crystal grains satisfying S1 - C1 ≧ 0.7 at% may be 70% or more. That is, among the plurality of first dielectric crystal grains 11, the number ratio of the first specific crystal grains may be 70% or more. Thereby, the improvement effects of the capacitance, TCC, and MTTF of the present invention can be further remarkable.

[0052] In one embodiment, the number ratio of crystal grains satisfying C2-S2 < 0.5 at% among the plurality of second dielectric crystal grains 12 may be 70% or more. That is, the number ratio of the above-mentioned second specific crystal grains among the plurality of second dielectric crystal grains 12 may be 70% or more. This can further enhance the improvement effects of the present invention on capacitance, TCC, and MTTF.

[0053] The dielectric layer 111 only needs to contain a plurality of first dielectric crystal grains 11 and a plurality of second dielectric crystal grains 12, and the ratio of the plurality of first dielectric crystal grains 11 and the plurality of second dielectric crystal grains 12 in the dielectric layer 111 is not particularly limited. However, the ratio of the area occupied by the plurality of first dielectric crystal grains 11 in the cross-section of the dielectric layer 111 may be, for example, 10% or more and 50% or less. This makes it possible to further effectively improve the capacitance, TCC and MTTF of the multilayer electronic component 100.

[0054] The ratio of the number of the specified crystal grains can be calculated by identifying a predetermined region in an image obtained by analyzing an arbitrary cross-section of the dielectric layer 111 with analytical equipment such as TEM-EDS, and then calculating the total number of dielectric crystal grains 11 and 12 present in that region and the number of the specified crystal grains. The ratio of the area occupied by multiple first dielectric crystal grains 11 can be calculated by identifying a predetermined region in an image obtained by analyzing an arbitrary cross-section of the dielectric layer 111 with analytical equipment such as TEM-EDS, and then calculating the total area of ​​that region and the area occupied by multiple first dielectric crystal grains 11.

[0055] The total number of dielectric crystal grains 11 and 12 extracted from a predetermined region may be, for example, 10 or more, but the present invention is not limited thereto.

[0056] In one embodiment, one or more of the plurality of first dielectric crystal grains 11 may have a maximum diameter of 100 nm to 450 nm, and one or more of the plurality of second dielectric crystal grains 12 may have a maximum diameter of 100 nm to 450 nm. The maximum diameter of the dielectric crystal grains 11 and 12 can mean the maximum straight length from one grain boundary to another of the dielectric crystal grains 11 and 12. When the above maximum diameter satisfies the above numerical range, the dielectric properties of the dielectric crystal grains 11 and 12 can be excellent, and sintering and grain growth can be easily controlled.

[0057] In one embodiment, one or more of the plurality of first dielectric crystal grains 11 may have a maximum diameter of 70 nm or more and 400 nm or less for the first core 11a, and one or more of the plurality of second dielectric crystal grains 12 may have a maximum diameter of 70 nm or more and 400 nm or less for the second core 12a. The maximum diameters of the cores 11a and 12a can mean the maximum length of the straight line from one grain boundary of dielectric crystal grains 11 and 12 to another grain boundary, corresponding to the cores 11a and 12a. If the maximum diameters of the cores 11a and 12a are less than 70 nm, it may be difficult to achieve the target dielectric properties, and if they exceed 400 nm, the reliability of the stacked electronic component 100 may decrease.

[0058] Furthermore, the average size of the multiple first dielectric crystal grains 11 may be between 100 nm and 450 nm, and the average size of the multiple second dielectric crystal grains 12 may be between 100 nm and 450 nm. The average size of the multiple first cores 11a may be between 70 nm and 400 nm, and the average size of the multiple second cores 12a may be between 70 nm and 400 nm.

[0059] The average size of dielectric crystal grains 11 and 12 can be defined as the average of the maximum diameters of multiple dielectric crystal grains 11 and 12 present in a 3 μm × 4 μm (width × length) region when observed by SEM or TEM in any region of the cross-section of the dielectric layer 111. The average size of cores 11a and 12a can be defined as the average of the maximum diameters of multiple cores 11a and 12a present in the 3 μm × 4 μm region. The 3 μm × 4 μm region can be identified in the cross-sections of the first and second directions after polishing to the center of the third direction of the stacked electronic component 100, and can be identified in the central regions of the first and second directions of the main body 110.

[0060] The following describes the minor components that may be contained in the dielectric layer 111. The minor components are described below based on the number of moles of elements, and can be calculated by converting this to the content of oxides or carbonates added as additives before firing. Unless there are special circumstances, the elemental content before and after firing is unlikely to have a large margin of error, and the types and content of elements contained in the dielectric layer 111 can be measured after firing using various measurement methods such as SEM-EDS, TEM-EDS, and STEM-EDS.

[0061] As a more specific example of a method for measuring the content of each element contained in the dielectric layer 111, in the case of destructive methods, the components inside the dielectric crystal grains in the central part of the main body 110 can be analyzed using TEM-EDS or STEM-EDS. First, an analytical sample is prepared by thinning the region containing the dielectric layer 111 in the cross-section of the sintered main body 110 using a focused ion beam (FIB) system. Then, the surface damage layer of the thinned sample is removed using Ar ion milling, and then qualitative / quantitative analysis is performed by mapping each component using an image obtained with (S)TEM-EDS. In this case, the qualitative / quantitative analysis graph of each component can be expressed by converting it to the mass fraction (wt%), atomic percentage (at%), or mole fraction (mol%) of each element.

[0062] Another method involves crushing the main body 110 to remove the internal electrodes 121 and 122, then separating the dielectric layer 111, and analyzing the components of the separated dielectric layer 111 using instruments such as an inductively coupled plasma spectrometer (ICP-OES) or inductively coupled plasma mass spectrometer (ICP-MS).

[0063] 1) First subcomponent The dielectric layer 111 may further contain other rare earth elements in addition to Y. For example, the dielectric layer 111 may further contain a first subcomponent comprising one or more of Dy, Tb, Sc, La, Nd, Eu, Gd, Ho, Er, Yb, and Lu. This first subcomponent can play a role in improving the reliability of the multilayer electronic component 100.

[0064] The content of the first minor component in the dielectric layer 111 may be between 2.5 moles and 10.0 moles per 100 moles of Ti. This can improve the dielectric constant at room temperature and / or the insulation resistance characteristics.

[0065] 2)Second subcomponent The dielectric layer 111 may contain one or more valence-fixed acceptor elements and valence-variable acceptor elements. Here, the valence-fixed acceptor elements may include one or more of Mg and Zr, and the valence-variable acceptor elements may include one or more of Mn, V, Cr, Fe, Ni, Co, Cu, and Zn. That is, the dielectric layer 111 may further contain a second subcomponent which includes one or more of Mg, Zr, Mn, V, Cr, Fe, Ni, Co, and Zn.

[0066] Valence-variable acceptor elements and valence-fixed acceptor elements can play a role in reducing electron concentration, thereby lowering the firing temperature of multilayer electronic components and improving high-temperature withstand voltage characteristics. The content of the above second minor component contained in the dielectric layer 111 may be, for example, 0.01 moles or more and 8.0 moles or less per 100 moles of Ti.

[0067] 3) Third subcomponent The dielectric layer 111 may further contain a third subcomponent comprising one or more of Si and Al. This third subcomponent can improve sintering density and enhance dielectric constant and Dc-bias characteristics.

[0068] The content of the third minor component contained in the dielectric layer 111 may be, for example, 1.0 mole or more and 5.0 moles or less per 100 moles of Ti.

[0069] In order to appropriately control the microstructure of the dielectric layer 111, the dielectric layer 111 may further contain Y, Dy, Mg, Zr, Mn, V, Si, and Al from among the aforementioned minor components.

[0070] In the line profile obtained by analyzing the first dielectric crystal grain 11 via TEM-EDS, the average content of Dy contained in the first core 11a may be less than the maximum content D1 of Dy contained in the first shell 11b. The average content of Zr contained in the first core 11a may be less than the maximum content Z1 of Zr contained in the first shell 11b.

[0071] One or more of the multiple first dielectric crystal grains 11 can satisfy one or more of, for example, Y1>S1, Y1>D1, and Y1>Z1. One or more of the multiple first dielectric crystal grains 11 can satisfy one or more of, for example, S1>D1 and S1>Z1. In one embodiment, one or more of the multiple first dielectric crystal grains 11 can satisfy Y1>S1>D1 and Y1>S1>Z1. As a result, the reliability of the stacked electronic component 100 can be improved because the first dielectric crystal grains 11 have a robust core-shell structure.

[0072] Similarly, in the line profile obtained by analyzing the second dielectric crystal grain 12 via TEM-EDS, the average Dy content in the second core 12a may be less than the maximum Dy content D2 in the second shell 12b. The average Zr content in the second core 12a may be less than the maximum Zr content Z2 in the second shell 12b.

[0073] One or more of the multiple second dielectric crystal grains 12 can satisfy, for example, one or more of Y2>D2 and Y2>Z2. One or more of the multiple second dielectric crystal grains 12 can satisfy, for example, one or more of S2>D2 and S2>Z2. One or more of the multiple second dielectric crystal grains 12 can satisfy, for example, one or more of C2>Y2, C2>D2 and C2>Z2. In one embodiment, one or more of the multiple second dielectric crystal grains 12 can satisfy C2>Y2>D2 and C2>Y2>Z2. In one embodiment, one or more of the multiple second dielectric crystal grains 12 can satisfy S2>D2, S2>Z2, Y2>D2 and Y2>Z2. As a result, the reliability of the stacked electronic component 100 can be improved because the second dielectric crystal grains 12 have a robust core-shell structure.

[0074] On the other hand, the average or maximum content of Dy and Zr contained in cores 11a, 12a and shells 11b, 12b can be measured in the same manner as C1, S1, C2, and S2 described above.

[0075] The size of the stacked electronic component 100 is not particularly limited, but the maximum length of the stacked electronic component 100 in the second direction may be 0.1 mm to 6.0 mm, the maximum width of the stacked electronic component 100 in the third direction may be 0.1 mm to 5.0 mm, and the maximum thickness of the stacked electronic component 100 in the first direction may be 0.05 mm to 3.5 mm.

[0076] The average thickness td of the dielectric layer 111 may be, for example, 0.1 μm to 20 μm, 0.1 μm to 10 μm, 0.1 μm to 5 μm, 0.1 μm to 2 μm, or 0.1 μm to 0.4 μm. The average thickness te of the internal electrodes 121 and 122 may be, for example, 0.1 μm to 3.0 μm, 0.1 μm to 1.0 μm, or 0.1 μm to 0.4 μm.

[0077] The average thickness td of the dielectric layer 111 and the average thickness te of the internal electrodes 121 and 122 refer to the thickness of the dielectric layer 111 and the internal electrodes 121 and 122 in the first direction, respectively. The average thickness td of the dielectric layer 111 and the average thickness te of the internal electrodes 121 and 122 can be measured by scanning the cross-sections of the main body 110 in the first and second directions with a scanning electron microscope (SEM) at 10,000x magnification. More specifically, the average thickness td of the dielectric layer 111 can be measured by taking the average value after measuring the thickness at multiple points on one dielectric layer 111, for example, at five points equally spaced in the second direction. Similarly, the average thickness te of one internal electrode 121 and 122 can be measured by taking the average value after measuring the thickness at multiple points on one internal electrode 121 and 122, for example, at five points equally spaced in the second direction. The five equally spaced points can be specified in the capacitance forming section Ac. On the other hand, if such average values ​​are measured for 10 dielectric layers 111 and 10 internal electrodes 121 and 122, and then the average values ​​are measured again, the average thickness td of the dielectric layer 111 and the average thickness te of the internal electrodes 121 and 122 can be further generalized.

[0078] The average thickness tc of the cover portions 112 and 113 may be, for example, 150 μm or less, 100 μm or less, 30 μm or less, or 20 μm or less. The average thickness of the cover portions 112 and 113 may be, for example, 5 μm or more, 10 μm or more, or 30 μm or more. The average thickness of the margin portions 114 and 115 may be, for example, 150 μm or less, 100 μm or less, 20 μm or less, or 15 μm or less. The average thickness of the margin portions 114 and 115 may be, for example, 5 μm or more, 10 μm or more, or 30 μm or more.

[0079] Here, the average thickness tc of the cover portions 112 and 113 refers to the average thickness of the first cover portion 112 and the second cover portion 113, respectively, and the average thickness of the margin portions 114 and 115 refers to the average thickness of the first margin portion 114 and the second margin portion 115, respectively.

[0080] The average thickness tc of the cover portions 112 and 113 can mean the average thickness of the cover portions 112 and 113 in the first direction, and can be a value obtained by averaging the thicknesses in the first direction measured at five equally spaced points in the cross sections of the main body 110 in the first and second directions. The average thickness of the margin portions 114 and 115 can mean the average thickness of the margin portions 114 and 115 in the third direction, and can be a value obtained by averaging the thicknesses in the third direction measured at five equally spaced points in the cross sections of the main body 110 in the first and third directions.

[0081] Hereinafter, an example of a method for forming the multilayer electronic component 100 will be described. However, the manufacturing method of the multilayer electronic component 100 is not limited thereto.

[0082] First, prepare the main component powder for forming the dielectric layer 111. The main component powder can include one or more of BaTiO3, (Ba 1-x Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1), and Ba(Ti 1-y Zr y )O3 (0 < y < 1). The main component powder can contain 10 to 40 parts by weight of the BT powder with respect to a total of 100 parts by weight of the BT powder and the BCT powder.

[0083] The first to third sub-component powders can be added to the main component powder. The sub-component powder can include, for example, one or more of CaCO3 powder, Y2O3 powder, Dy2O3 powder, MgO powder, ZrO2 powder, MnO2 powder, V2O5 powder, SiO2, and Al2O3 powder.

[0084] Next, the main component powder, to which the auxiliary component powder has been added, is mixed with an organic solvent such as ethanol and a binder such as polyvinyl butyral, and then ball-milled to produce a dielectric composition. The dielectric composition is then applied to a carrier film and dried to provide a ceramic green sheet.

[0085] Next, an internal electrode pattern is formed on a ceramic green sheet by printing a conductive paste for internal electrodes, containing metal powder, a binder, an organic solvent, etc., to a predetermined thickness using a screen printing method or gravure printing method.

[0086] Subsequently, after peeling the ceramic green sheet with the printed internal electrode pattern from the carrier film, a predetermined number of layers of ceramic green sheets with the printed internal electrode pattern are laminated and pressed together to form a ceramic laminate. A predetermined number of ceramic green sheets without the printed internal electrode pattern can be laminated on the upper and lower parts of the ceramic laminate to form cover portions 112 and 113 after firing. Then, the ceramic laminate is cut to a predetermined chip size, and the cut chips are fired in a 1.0%H2 / 99.0%N2~3.5%H2 / 96.5%N2 (H2O / H2 / N2 atmosphere) at a temperature of 1000°C to 1400°C for 1 to 3 hours to form the main body 110.

[0087] Next, external electrodes 131 and 132 are formed. For example, if the base electrode layers 131a and 132a include a fired electrode layer, the main body 110 can be dipped in a conductive paste for external electrodes containing metal powder, glass frit, binder, and organic solvent, and then the conductive paste for external electrodes can be fired at a temperature of 500°C to 900°C to form a fired electrode layer.

[0088] For example, if the base electrode layers 131a and 132a include a resin electrode layer, the main body can be dipped in a conductive resin composition containing metal powder, resin, binder, and organic solvent, and then cured at a temperature of 250°C to 550°C to form the resin electrode layer.

[0089] Further, an electrolytic plating method and / or an electroless plating method may be further performed to form plating layers 131b and 132b on the base electrode layers 131a and 132a.

[0090] (Example) Hereinafter, the present invention will be described in more detail with reference to examples. However, the following examples are for helping the specific understanding of the present invention, and the scope of the present invention is not limited by the following examples.

[0091] Examples 1 to 7 BT powder and a main component powder in which BCT powder having a composition of (Ba 1-x Ca x )TiO3 (0 < x < 1) was mixed at a ratio of 10:90 to 40:60 based on weight% were provided. Then, CaCO3 powder, Y2O3 powder, Dy2O3 powder, MgO powder, ZrO2 powder, MnO2 powder, V2O5 powder, SiO2, and Al2O3 powder were mixed with the main component powder at a predetermined ratio, and after adding an organic solvent and a binder, ball milling was performed to form a dielectric composition. On the other hand, the CaCO3 powder was added in an amount of 1 part to 10 parts by weight with respect to 100 parts by weight of the main component powder.

[0092] Also, Ni powder and an organic solvent were mixed to form a conductive paste for an internal electrode. After forming a ceramic laminate using the dielectric composition and the conductive paste for an internal electrode, the ceramic laminate was cut into a predetermined size to form a laminated chip. Next, the laminated chip was fired to form a main body. Then, a fired electrode layer containing Cu, a Ni plating layer, and a Sn plating layer were sequentially formed on the surface of the main body to provide a sample chip. The sample chip was manufactured in a 1005 size (length: about 1.0 mm, width: about 0.5 mm, thickness: about 0.5 mm).

[0093] Comparative Example (Ref) As the main component powder, only BT powder was used without using a mixed powder of BT powder and BCT powder. Also, CaCO3 powder was not added. Otherwise, it was manufactured in the same manner as in Example 1.

[0094] Measurement of Ca content The central regions of the first and second directions of the cross-sections in the first and second directions, which have been polished to the center of the third direction of the sample chip, are analyzed by TEM-EDS.

[0095] Subsequently, line profile analysis was performed on the first and second dielectric crystal grains. As shown in Figures 6b and 6c, the line profiles were analyzed over the range from one grain boundary to the other of the dielectric crystal grains.

[0096] On the other hand, in the line profile showing the positional Y content within the dielectric crystal grain (for example, Figure 5a), the region with a Y content of less than 0.2 at% was defined as the core, and the region with a Y content of 0.2 at% or more was defined as the shell. Subsequently, C1, S1, C2, and S2 were measured using the line profile showing the positional Ca content within the dielectric crystal grain.

[0097] Based on the line profile results obtained by analyzing the Ca distribution in the first dielectric crystal grain, the Ca content was measured at five equally spaced points located in the first core. The average value was defined as C1, and the maximum Ca content in the first shell was defined as S1.

[0098] Similarly, based on the line profile results obtained by analyzing the Ca distribution in the second dielectric crystal grain, the Ca content was measured at five equally spaced points located in the second core. The average value was defined as C2, and the maximum Ca content in the second shell was defined as S2.

[0099] Based on the above C1, S1, C2, and S2, the values ​​of S1-C1 and C2-S2 were calculated and then listed in Table 1 below.

[0100] Capacitance evaluation Capacitance was measured using an LCR meter at 1 kHz and 1 Vrms after heat treatment of the sample chip at 150°C for 24 hours. The relative capacitance values ​​of the examples are shown in Table 1 below, with the comparative example capacitance set to 2. A relative capacitance value of 1 or greater was considered good (OK), while a value less than 1 was considered poor (NG).

[0101] TCC Rating The TCC was measured at 150°C. When the TCC of the comparative example was set to 0.5, the relative TCC values ​​of the examples are shown in Table 1 below. A relative TCC value of 1 or greater was judged as good (OK), and a value less than 1 was judged as poor (NG).

[0102] MTTF rating Mean Time To Failure (MTTF) was measured by applying a temperature of 150°C and a voltage three times the rated voltage to 80 sample chips for each sample number, and averaging the time until the insulation resistance measurement of all sample chips was 100kΩ or less. When the MTTF of the comparative example was set to 1.5, the relative values ​​of the MTTF of the examples are shown in Table 1 below. If the relative value of the MTTF is 1 or greater, it was judged as good (OK), and if it is less than 1, it was judged as poor (NG).

[0103] [Table 1]

[0104] In Example 1, since S1-C1 is less than 0.7 at%, it can be confirmed that the TCC characteristics of the sample chip are degraded. In Examples 3 and 5, since C2-S2 is greater than 0.5 at%, it can be confirmed that the capacitance and MTTF characteristics of the sample chip are degraded. In contrast, in Examples 2, 4, 6, and 7, by satisfying S1-C1 ≥ 0.7 at% and C2-S2 < 0.5 at%, it can be confirmed that the capacitance, TCC, and MTTF characteristics of the sample chip are all excellent.

[0105] The present invention is not limited by the embodiments described above or the accompanying drawings, but is limited by the claims provided herein. Accordingly, various forms of substitution, modification, and alteration are possible by persons with ordinary skill in the art, without departing from the technical idea of ​​the present invention as described in the claims, and these also fall within the scope of the present invention.

[0106] Furthermore, the expression "one embodiment" does not mean that each embodiment is the same as another, but is provided to highlight and explain the unique and distinct characteristics of each embodiment. However, the above-presented embodiments do not preclude their realization in combination with the features of other embodiments. For example, even if a matter described in one embodiment is not described in another embodiment, it can be understood as a description related to the other embodiment, unless there is a description in the other embodiment that contradicts or is contrary to that matter.

[0107] In this invention, "connected" is a concept that includes not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, "electrically connected" is a concept that includes both cases where physically connected and cases where not connected. In addition, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, within the scope of the rights, the first component may be named the second component, and similarly, the second component may be named the first component. [Explanation of symbols]

[0108] 100: Stacked Electronic Components 110: Main unit 111: Dielectric layer 11, 12, 13: Dielectric crystal grains 11a, 12a: Core 11b, 12b: Shell 112, 113: Cover section 114, 115: Margin section 121, 122: Internal electrode 131, 132: External electrode 131a, 132a: Base electrode layer 131b, 132b: Plating layer

Claims

1. A body comprising a dielectric layer containing Ba, Ti, and Ca, having a plurality of first dielectric crystal grains and a plurality of second dielectric crystal grains, and internal electrodes arranged alternately with the dielectric layer, The body includes an external electrode disposed on the main body, The plurality of first dielectric crystal grains have a first core-shell structure including a first core and a first shell disposed on at least a portion of the first core. The plurality of second dielectric crystal grains have a second core-shell structure including a second core and a second shell disposed on at least a portion of the second core. Let C1 and C2 be the average Ca content (at%) in the first core and the second core, respectively, and let S1 and S2 be the maximum Ca content (at%) in the first shell and the second shell, respectively. A multilayer electronic component in which one or more of the plurality of first dielectric crystal grains satisfy S1-C1 ≥ 0.7 at%, and one or more of the plurality of second dielectric crystal grains satisfy C2-S2 < 0.5 at%.

2. The stacked electronic component according to claim 1, wherein one or more of the plurality of first dielectric crystal grains satisfy 0.7 at% ≤ S1 - C1 ≤ 3.0 at%.

3. The plurality of first dielectric crystal grains and the plurality of second dielectric crystal grains include Y, The stacked electronic component according to claim 1, wherein the first core and the second core are regions in which the Y content is less than 0.2 at%, and the first shell and the second shell are regions in which the Y content is 0.2 at% or more.

4. The maximum content of Y contained in the first shell is 1.0 at% or more. The stacked electronic component according to claim 3, wherein the maximum content of Y contained in the second shell is 1.0 at% or more.

5. The plurality of first dielectric crystal grains satisfy C1 < S1, The multilayer electronic component according to claim 1, wherein the plurality of second dielectric crystal grains satisfy C2 ≥ S2.

6. The plurality of first dielectric crystal grains satisfy C1 < 0.8 at%, The multilayer electronic component according to claim 1, wherein the plurality of second dielectric crystal grains satisfy C2 ≥ 0.8 at%.

7. The stacked electronic component according to claim 5, wherein the number ratio of crystal grains satisfying S1-C1 ≥ 0.7 at% among the plurality of first dielectric crystal grains is 70% or more.

8. The stacked electronic component according to claim 5, wherein the number ratio of crystal grains satisfying C2-S2 < 0.5 at% among the plurality of second dielectric crystal grains is 70% or more.

9. The stacked electronic component according to claim 5, wherein the ratio of the area occupied by the plurality of first dielectric crystal grains in the cross-section of the dielectric layer is 10% or more and 50% or less.

10. One or more of the plurality of first dielectric crystal grains have a maximum diameter of 100 nm or more and 450 nm or less. The stacked electronic component according to claim 1, wherein one or more of the plurality of second dielectric crystal grains have a maximum diameter of 100 nm or more and 450 nm or less.

11. One or more of the plurality of first dielectric crystal grains have a maximum diameter of 70 nm or more and 400 nm or less of the first core. The stacked electronic component according to claim 1, wherein one or more of the plurality of second dielectric crystal grains have a maximum diameter of 70 nm or more and 400 nm or less of the second core.

12. The laminated electronic component according to any one of claims 1 to 11, wherein the dielectric layer further comprises one or more of Dy, Tb, Sc, La, Nd, Eu, Gd, Ho, Er, Yb, and Lu.

13. The laminated electronic component according to any one of claims 1 to 11, wherein the dielectric layer further comprises one or more of Mg, Zr, Mn, V, Cr, Fe, Ni, Co, and Zn.

14. The laminated electronic component according to any one of claims 1 to 11, wherein the dielectric layer further comprises one or more of Si and Al.

15. The laminated electronic component according to any one of claims 1 to 11, wherein the dielectric layer further comprises Y, Dy, Mg, Zr, Mn, V, Si, and Al.

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