Multilayer ceramic electronic components

Abstract

The present invention provides a multilayer ceramic electronic component that reduces the occurrence of short circuits caused by contact between external electrodes. [Solution] The multilayer ceramic electronic component comprises: first and second internal electrode layers alternately stacked via a plurality of first ceramic layers; a laminate 16 having a first side surface perpendicular to a second axis perpendicular to the stacking direction and including a first end 121 of the first internal electrode layer and second ends 131, 132 of the second internal electrode layer, a second side surface opposite to the first side surface, a third side surface 16c perpendicular to a third axis perpendicular to the stacking direction and the second axis direction, and a fourth side surface 16d opposite to the third side surface; and a side margin portion 17 covering at least one of the third and fourth side surfaces. The first end is arranged so as to not overlap with the second end when viewed from the first axis direction, and all first and second internal electrode layers have a second ceramic layer 141 between the first end and the second end when viewed from the stacking direction, and the second ceramic layer has a higher Si content than the first ceramic layer.

Description

Technical Field

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[0001] The present invention relates to a multilayer ceramic electronic component.

Background Art

[0002] In recent years, with the high-capacity requirements from the market, various types of multilayer ceramic capacitors such as high-stack type and thin-layer type have been used.

[0003] As an example, Patent Document 1 discloses a multi-terminal multilayer ceramic capacitor having three or more external electrode terminals for reducing ESR (Equivalent Series Resistance).

Prior Art Document

Patent Document

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In recent years, there has been a demand for the development of a multilayer ceramic capacitor in which the occurrence of a short circuit due to contact between external electrodes arranged adjacent to the surface of the multilayer ceramic capacitor is reduced.

[0006] An object of the present invention is to provide a multilayer ceramic electronic component capable of reducing the occurrence of a short circuit due to contact between external electrodes.

Means for Solving the Problems

[0007] According to one aspect of the present invention, the multilayer ceramic electronic component is A laminate comprising: a plurality of first ceramic layers stacked in the first axial direction; first internal electrode layers and second internal electrode layers, each alternately stacked via the first ceramic layers; a first side surface perpendicular to the second axial direction orthogonal to the first axial direction and including the first end of the first internal electrode layer and the second end of the second internal electrode layer; a second side surface opposite to the first side surface; a third side surface perpendicular to the third axial direction orthogonal to the first and second axial directions; and a fourth side surface opposite to the third side surface. It comprises a side margin portion that covers at least one of the third side and the fourth side, The first end is positioned such that, when viewed from the first axial direction, it does not overlap with the second end. All of the first internal electrode layers and all of the second internal electrode layers, when viewed from the first axial direction, have a second ceramic layer between the first end and the second end. The second ceramic layer has a higher Si content than the first ceramic layer. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a multilayer ceramic electronic component that can reduce the occurrence of short circuits due to contact between external electrodes. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic perspective view showing a multilayer ceramic electronic component 100 according to the first embodiment of the present invention. [Figure 2] This is a schematic cross-sectional view of the multilayer ceramic electronic component 100 shown in Figure 1, cut along line AA'. [Figure 3] This is a schematic cross-sectional view of the multilayer ceramic electronic component 100 shown in Figure 1, cut along the BB' line. [Figure 4A] Figure 1 is a schematic plan view of the first internal electrode layer 12 in the multilayer ceramic electronic component 100, as seen from the first axial direction. [Figure 4B]Figure 1 is a schematic plan view of the second internal electrode layer 13 in the multilayer ceramic electronic component 100, as seen from the first axial direction. [Figure 4C] This is a schematic plan view of a structure in which the first internal electrode layer 12 (Figure 4A), the first ceramic layer 11, and the second internal electrode layer 13 (Figure 4B) are stacked in sequence and viewed through from the first axis direction. [Figure 5] This is a schematic diagram showing the first side surface 16a of the laminate 16 in the multilayer ceramic electronic component 100 shown in Figure 1. [Figure 6A] This is a schematic plan view of the first internal electrode layer 12 in a multilayer ceramic electronic component according to a second embodiment of the present invention, as viewed from the first axial direction. [Figure 6B] This is a schematic plan view of the second internal electrode layer 13 in a multilayer ceramic electronic component according to the second embodiment of the present invention, as viewed from the first axial direction. [Figure 6C] This is a schematic plan view of a structure in which the first internal electrode layer 12 (Figure 6A), the first ceramic layer 11, and the second internal electrode layer 13 (Figure 6B) are stacked in sequence and viewed through from the first axis direction. [Figure 7] This is a schematic perspective view showing a multilayer ceramic capacitor 1000 according to a third embodiment of the present invention. [Figure 8] This is a flowchart showing a method for manufacturing a multilayer ceramic capacitor 1000 according to a third embodiment of the present invention. [Modes for carrying out the invention]

[0010] Conventionally, short circuits of the external electrodes in multilayer ceramic capacitors have been prevented during the manufacturing process by increasing the viscosity of the paste used to form the external electrodes or by improving the application accuracy of the paste. However, in recent years, with the miniaturization of multilayer ceramic capacitors, there has been a need for even greater application accuracy of the paste used to form the external electrodes, as well as a need to control the wetting spread of the paste.

[0011] The inventors have found that the above means alone are insufficient as a means for preventing short circuits in external electrodes of multilayer ceramic capacitors, which have been miniaturized in recent years. As a result of intensive studies to prevent problems caused by such short circuits, the inventors have arrived at the following embodiments.

[0012] (Multilayer ceramic electronic component) The multilayer ceramic electronic component of the present invention includes a laminate and a side margin portion, and may include other portions as needed.

[0013] Hereinafter, a first embodiment of the present invention will be described in detail, but the present invention is not limited thereto. In this specification and the drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to omit redundant descriptions. In the drawings, an X-axis, a Y-axis, and a Z-axis that are orthogonal to each other are shown as appropriate. In the first embodiment of the present invention, the X-axis corresponds to the second axis, the Y-axis corresponds to the third axis, and the Z-axis corresponds to the first axis.

[0014] [Figs. 1 to 5] FIG. 1 is a schematic perspective view showing a multilayer ceramic electronic component 100 according to a first embodiment of the present invention. FIG. 2 is a schematic cross-sectional view when the multilayer ceramic electronic component 100 of FIG. 1 is cut along line A-A'. FIG. 3 is a schematic cross-sectional view when the multilayer ceramic electronic component 100 of FIG. 1 is cut along line B-B'. FIG. 4A is a schematic plan view of the first internal electrode layer 12 in the multilayer ceramic electronic component 100 of FIG. 1 as viewed from the first axial direction. FIG. 4B is a schematic plan view of the second internal electrode layer 13 in the multilayer ceramic electronic component 100 of FIG. 1 as viewed from the first axial direction. FIG. 4C is a schematic plan view when the first internal electrode layer 12 of FIG. 4A, the first ceramic layer 11, and the second internal electrode layer 13 of FIG. 4B are laminated in order and viewed in perspective from the first axial direction. FIG. 5 is a schematic view showing the first side surface 16a of the laminate 16 in the multilayer ceramic electronic component 100 of FIG. 1. Note that FIG. 1 shows the state after the external electrodes 21 are formed for convenience.

[0015] As shown in Figures 1 to 3, the multilayer ceramic electronic component 100 comprises a laminate 16 and a side margin portion 17.

[0016] <Laminate> As shown in Figures 1 to 3, the laminate 16 has a plurality of first ceramic layers 11 stacked in the first axial direction (Z-axis direction in the figures), and first internal electrode layers 12 and second internal electrode layers 13, each alternately stacked via the first ceramic layers 11.

[0017] The laminate 16 comprises a capacitance forming section 18 consisting of a first ceramic layer 11, a first internal electrode layer 12, and a second internal electrode layer 13. In other words, the first internal electrode layer 12 and the second internal electrode layer 13 in the capacitance forming section 18 are arranged to face each other in the first axial direction with the first ceramic layer 11 in between.

[0018] With this configuration, when a voltage is applied between the external electrode 21 connected to the first internal electrode layer 12 and the external electrode 21 connected to the second internal electrode layer 13, a voltage is applied to the first ceramic layer 11 between the first internal electrode layer 12 and the second internal electrode layer 13, and a charge corresponding to that voltage is stored in the capacitance forming section 18.

[0019] As shown in Figures 1 to 3, the laminate 16 has a first side surface 16a perpendicular to the second axis direction (X-axis direction in the figure) which is orthogonal to the first axis direction (Z-axis direction in the figure), and which includes the first end of the first internal electrode layer 12 and the second end of the second internal electrode layer 13; a second side surface 16b opposite to the first side surface 16a; a third side surface 16c perpendicular to the third axis direction (Y-axis direction in the figure) which is orthogonal to the first and second axis directions; and a fourth side surface 16d opposite to the third side surface 16c. The laminate 16 may also have a fifth side surface 16e perpendicular to the first axis direction and a sixth side surface 16f opposite to the fifth side surface 16e. Details of the first and second ends will be described later.

[0020] In this specification, if the first end and the second end are included not only in the first side surface 16a but also in the second side surface 16b, the side designated as the first side surface 16a can be arbitrarily selected from a pair of side surfaces perpendicular to the second axial direction. Similarly, the side designated as the third side surface 16c can be arbitrarily selected from a pair of side surfaces perpendicular to the third axial direction, and the side designated as the fifth side surface 16e can be arbitrarily selected from a pair of side surfaces perpendicular to the first axial direction.

[0021] The first to sixth sides 16a to 16f of the laminate 16 are all configured as flat surfaces. In this invention, a flat surface does not have to be strictly planar as long as it is perceived as flat when viewed as a whole, and includes, for example, surfaces with minute irregularities on the surface or gently curved shapes within a predetermined range.

[0022] <<First Ceramic Layer>> In the first ceramic layer 11, it is preferable to use a dielectric ceramic with a high dielectric constant from the viewpoint of increasing the capacitance of each ceramic layer in the capacitance forming section 18. There are no particular restrictions on the dielectric ceramic with a high dielectric constant, and it can be appropriately selected according to the purpose. Examples include perovskite materials containing barium (Ba) and titanium (Ti), such as barium titanate (BaTiO3).

[0023] The first ceramic layer 11 is not particularly limited and can be appropriately selected depending on the purpose. For example, it may be composed of a composition system such as strontium titanate (SrTiO3), calcium titanate (CaTiO3), magnesium titanate (MgTiO3), calcium zirconate (CaZrO3), calcium zirconate titanate (Ca(Zr,Ti)O3), barium zirconate (BaZrO3), or titanium oxide (TiO2).

[0024] <<First internal electrode layer and second internal electrode layer>> As shown in Figure 4A, the first internal electrode layer 12 has a first end portion 121 that is included in the first side surface 16a of the laminate 16. Here, the first end portion 121 refers to the exposed portion of the first internal electrode 120 that is exposed from the laminate 16 on the first side surface 16a of the laminate 16.

[0025] As shown in Figure 4B, the second internal electrode layer 13 has second ends 131 and 132 that are included in the first side surface 16a of the laminate 16. Here, the second ends 131 and 132 refer to the exposed portions of the second internal electrode 130 that are exposed from the laminate 16 on the first side surface 16a of the laminate 16. For convenience, the second ends 131 and 132 are given different reference numerals, but they do not need to be distinguished.

[0026] As shown in Figures 4A to 4C, when the first internal electrode layer 12 and the second internal electrode layer 13 are stacked, the first end portion 121 is positioned so as not to overlap with the second end portions 131 and 132 when viewed from the first axial direction.

[0027] The first internal electrode layer 12 and the second internal electrode layer 13 are preferably formed of a good electrical conductor. There are no particular restrictions on the good electrical conductor that forms the first internal electrode layer 12 and the second internal electrode layer 13, and it can be appropriately selected according to the purpose. Examples include metals or alloys mainly composed of nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), etc.

[0028] As shown in Figures 4A to 5, all first internal electrode layers 12 and all second internal electrode layers 13 have a second ceramic layer 141 between the first end 121 and the second end 131 and second end 132 when viewed from the first axial direction.

[0029] The second ceramic layer 141 has a higher Si content than the first ceramic layer 11. Specifically, the Si concentration in the second ceramic layer 141 is preferably 1% to 20% higher than the Si concentration in the first ceramic layer 11. This configuration suppresses the spreading of the external electrode formation paste when it is applied to the surface of the multilayer ceramic electronic component 100. Specifically, when forming external electrodes in a desired area (external electrode formation area 20 in Figure 5) on the multilayer ceramic electronic component 100, conventional techniques may cause short circuits between adjacent external electrodes due to the spreading of the external electrode formation paste during application. However, with the multilayer ceramic electronic component of the present invention having the above configuration, the external electrode formation area 20 is sandwiched between the second ceramic layer 141 with a high Si content, thus suppressing the spreading of the external electrode formation paste and allowing for the precise formation of external electrodes in the desired area. In other words, the multilayer ceramic electronic component of the present invention eliminates the problem of short circuits occurring due to contact between external electrodes.

[0030] The second ceramic layer 141 can be appropriately selected according to the purpose, as long as its composition has a higher Si content than the first ceramic layer 11, but it is preferable that it be mainly composed of polycrystalline ceramics. In this specification, "main component" refers to the component with the highest content ratio.

[0031] The polycrystalline material preferably contains dispersed glass particles whose total volume fraction relative to the polycrystalline material is 1% to 20%. There are no particular restrictions on the median diameter of the glass particles, and they can be appropriately selected depending on the purpose, but it is preferably 0.20 μm or more and less than 0.75 μm. Furthermore, it is preferable that the proportion of glass particles with a diameter of 0.20 μm or more and less than 0.75 μm among the glass particles constituting the polycrystalline material be 90% or more.

[0032] In the laminate, it is preferable that the first side surface has multiple first ends and multiple second ends, and the second side surface has multiple third ends and multiple fourth ends. Specifically, this is as follows:

[0033] As shown in Figure 4A, the first internal electrode layer 12 has a third end portion 122 that is included in the second side surface 16b of the laminate 16. Alternatively, the first internal electrode layer 12 may have only a first end portion 121 and no third end portion 122. Furthermore, the first end portion 121 and the third end portion 122 may each be present as one or multiple portions.

[0034] As shown in Figure 4B, the second internal electrode layer 13 has fourth ends 133 and 134 included in the second side surface 16b of the laminate 16. Alternatively, the second internal electrode layer 13 may have only second ends 131 and 132, without the fourth ends 133 and 134. Furthermore, the second internal electrode layer 13 may have one or more second ends 131, 132, 133, and 134. For convenience, the fourth ends 133 and 134 are given different reference numerals, but they do not need to be distinguished.

[0035] As shown in Figures 4A to 5, when the first internal electrode layer 12 has a third end portion 122 included in the second side surface 16b, and the second internal electrode layer 13 has fourth end portions 133 and 134 included in the second side surface 16b, a third ceramic layer 142 is provided between the third end portion 122 and the fourth end portions 133 and 134. Since the third ceramic layer 142 is the same as the second ceramic layer 141, redundant descriptions are omitted.

[0036] As shown in Figures 2-3 and 5, the laminate 16 may have cover margin portions 19 provided on both sides of the first axial direction of the volume forming portion 18. The pair of cover margin portions 19 constitute the fifth side surface 16e and the sixth side surface 16f.

[0037] The composition of the cover margin portion 19 is not particularly limited and can be appropriately selected depending on the purpose. For example, it may be formed of insulating ceramics and may contain dielectric ceramics similar to those of the first ceramic layer 11. This suppresses internal stress that may occur between the cover margin portion 19 and the capacitance forming portion 18. In this specification, the pair of cover margin portions 19 are also included in the first ceramic layer 11.

[0038] <Side margin section> As shown in Figures 1, 3, and 5, the multilayer ceramic electronic component 100 includes a side margin portion 17 that covers at least one of the third side surface 16c and the fourth side surface 16d of the laminate 16.

[0039] There are no particular restrictions on the composition of the side margin portion 17, and it can be appropriately selected according to the purpose, but it is preferable that it has a higher Si content than the first ceramic layer 11. That is, the composition of the side margin portion 17 may be the same as that of the second ceramic layer 141.

[0040] When the side margin portion 17 has such a configuration, the external electrode formation region 20 is sandwiched between the side margin portion 17 or the second ceramic layer 141, which has a high Si content. This suppresses the wetting and spreading of the paste for forming the external electrodes, thus eliminating problems such as short circuits caused by contact between external electrodes. Furthermore, it eliminates problems such as external electrodes being formed in undesirable locations, resulting in deviations from specifications and mounting defects.

[0041] [Figures 6A-6C] Figure 6A is a schematic plan view of the first internal electrode layer 12 in a multilayer ceramic electronic component according to the second embodiment of the present invention, as viewed from the first axis direction. Figure 6B is a schematic plan view of the second internal electrode layer 13 in a multilayer ceramic electronic component according to the second embodiment of the present invention, as viewed from the first axis direction. Figure 6C is a schematic plan view of the first internal electrode layer 12 of Figure 6A, the first ceramic layer 11, and the second internal electrode layer 13 of Figure 6B stacked in order and viewed through from the first axis direction.

[0042] As shown in Figures 6A to 6C, in a multilayer ceramic electronic component, the first end 121 of the first internal electrode layer 12 and the second end 131 and second end 132 of the second internal electrode layer 13 may be formed on the YZ plane (first side surface 16a). Similarly, the third end 122 of the first internal electrode layer 12 and the fourth end 133 and fourth end 134 of the second internal electrode layer 13 may be formed on the YZ plane (second side surface 16b) opposite to the first side surface. In this case, the pair of XZ planes correspond to the third side surface 16c and the fourth side surface 16d.

[0043] (Multilayer ceramic capacitor) The multilayer ceramic capacitor according to the present invention comprises the multilayer ceramic electronic component described above and an external electrode, and may have other parts as needed.

[0044] [Figure 7] Figure 7 is a schematic perspective view showing a multilayer ceramic capacitor 1000 according to a third embodiment of the present invention.

[0045] As shown in Figure 7, the multilayer ceramic capacitor 1000 comprises a multilayer ceramic electronic component 100 and an external electrode 21.

[0046] <External electrode> The shape of the external electrode 21 is not particularly limited as long as it covers the external electrode formation region 20 on the first side (and second side) of the laminate 16, as shown in Figure 7, and can be appropriately selected according to the purpose.

[0047] The external electrode 21 is preferably formed of a good electrical conductor. There are no particular restrictions on the good electrical conductor used to form the external electrode 21, and it can be appropriately selected depending on the purpose. Examples include metals or alloys mainly composed of copper (Cu), nickel (Ni), tin (Sn), palladium (Pd), platinum (Pt), silver (Ag), and gold (Au).

[0048] Next, the manufacturing method for the multilayer ceramic capacitor 1000 will be described.

[0049] Figure 8 is a flowchart showing a method for manufacturing a multilayer ceramic capacitor 1000 according to a third embodiment of the present invention.

[0050] (Step S01: Preparation of the laminate) In step S01, an unfired laminate 16 is prepared. The unfired laminate 16 can be made using a laminate sheet in which multiple large ceramic sheets (first ceramic layers) are stacked in the first axial direction. A conductive paste for forming the first internal electrode layer 12 and the second internal electrode layer 13, and a ceramic slurry for forming the second ceramic layer 141 and the third ceramic layer 142 are patterned on the ceramic sheet corresponding to the volume forming section 18.

[0051] For the second ceramic layer 141 and the third ceramic layer 142, a ceramic slurry mixed with an organosilicon compound as a sintering aid is used. Silicone resin and silicon oligomers can be used as the organosilicon compound. The ceramic slurry can be prepared as follows: First, a dispersion of the organosilicon compound and a binder is prepared. Polyvinyl butyral (PVB) can be used as the binder. Next, the slurry of dielectric ceramics constituting the second ceramic layer 141 and the third ceramic layer 142, such as barium titanate, is dispersed in the dispersion and then emulsified. In this way, a ceramic slurry for the second ceramic layer 141 and the third ceramic layer 142 in which the organosilicon compound is uniformly dispersed can be prepared.

[0052] The unfired laminate 16 is obtained by cutting the laminated sheet along the XZ plane and the YZ plane. For cutting the laminated sheet, a cutting device equipped with, for example, a push-cutting blade or a rotary blade can be used. As a result, in the unfired laminate 16, a pair of side surfaces are obtained as cut surfaces where both ends in the Y-axis direction of the first internal electrode layer 12 and the second internal electrode layer 13 are aligned.

[0053] (Step S02: Formation of side margins) In step S02, a pair of unfired side margins 17 are provided on each of the two sides of the unfired laminate 16 fabricated in step S01. This results in an unfired multilayer ceramic electronic component 100 in which a pair of sides are formed by the unfired side margins 17.

[0054] For the unfired side margin portion 17, a ceramic slurry mixed with an organosilicon compound as a sintering aid is used. Silicone resin and silicon oligomers can be used as the organosilicon compound. The ceramic slurry can be prepared as follows: First, a dispersion of the organosilicon compound and a binder is prepared. Polyvinyl butyral (PVB) can be used as the binder. Next, the slurry of the dielectric ceramic constituting the side margin portion 17, such as barium titanate, is dispersed in the dispersion and then emulsified. In this way, a ceramic slurry for the side margin portion 17 in which the organosilicon compound is uniformly dispersed can be prepared.

[0055] The side margin portion 17 can be formed by any method. For example, the side margin portion 17 can be formed using a ceramic sheet obtained by forming a ceramic slurry into a sheet. In this case, the ceramic sheet can be punched out on the side of the laminate 16, or it can be pre-cut and attached to the side of the laminate 16.

[0056] To form the side margin portion 17, an unformed ceramic slurry can be used instead of a pre-formed ceramic sheet. In this case, the ceramic slurry can be applied to the side surface of the laminate 16 by, for example, immersing the side surface of the laminate 16.

[0057] (Step S03: Firing) In step S03, the unfired multilayer ceramic electronic component 100 obtained in step S02 is fired to produce the multilayer ceramic electronic component 100 shown in Figures 6A to 6C.

[0058] (Step S04: Formation of external electrodes) In step S04, external electrodes 21 are formed on the external electrode formation regions 20 located at both ends in the X-axis direction of the multilayer ceramic electronic component 100 fired in step S03, thereby fabricating the multilayer ceramic capacitor 1000 shown in Figure 7. The method for forming the external electrodes 21 in step S04 can be arbitrarily selected from known methods. Alternatively, the external electrodes 21 may be formed on the unfired multilayer ceramic electronic component 100 and then fired simultaneously.

[0059] With the above steps, the multilayer ceramic capacitor 1000 shown in Figure 7 is completed.

[0060] (Example 1) Various evaluations were performed using a standard multilayer ceramic electronic component A (a three-terminal multilayer ceramic capacitor component described in the embodiment of Japanese Patent Publication No. 2023-153569) and the multilayer ceramic electronic component 100 shown in Figure 1. The results are shown in Table 1.

[0061] <Evaluation of wetness spread> Using a microscope, the width of the external electrode coating after application was measured, and the ratio of the maximum wetting spread width to the designed external electrode coating width (a ratio with the designed electrode width set to 100) was calculated and evaluated.

[0062] <Implementation rejected> The pickup error rate when mounting chips using a mounting machine (FUJI NXT3III) was defined as the mounting failure rate.

[0063] <Capacity Evaluation> The capacitance was measured using an LCR meter under the conditions of 1kHz-0.5V.

[0064] (Example 2) An evaluation similar to that in Example 1 was performed using a standard multilayer ceramic electronic component B (a three-terminal multilayer ceramic capacitor described in the example of Japanese Patent Publication No. 2023-153569) and a multilayer ceramic electronic component 101. Note that multilayer ceramic electronic component 101 is a modified version of multilayer ceramic electronic component 100, with the first internal electrode layer replaced by the one shown in Figure 6A and the second internal electrode layer by the one shown in Figure 6B. The results are shown in Table 1.

[0065] [Table 1]

[0066] From the above results, it can be seen that if the multilayer ceramic electronic component of this embodiment has a specific structure in the internal electrode layer and side margin portion, the wetting and spreading of the paste for forming the external electrodes can be suppressed, and the occurrence of short circuits due to contact between external electrodes can be reduced. Furthermore, it can be seen that the occurrence of defects such as deviating from specifications and resulting in mounting defects due to the formation of external electrodes in undesirable positions can be reduced. In addition, since the side margin portion is formed on the side surface of the laminate after the laminate has been formed, the cross-area loss due to the lamination accuracy is eliminated, and the capacity can be maximized.

[0067] [Other embodiments] Although embodiments have been described in detail above, the present invention is not limited to any particular embodiment, and various modifications and changes are possible within the scope described in the claims.

[0068] For example, in the above embodiment, a multilayer ceramic capacitor was described as an example of a multilayer ceramic electronic component, but the present invention is applicable to multilayer ceramic electronic components in general. Examples of such multilayer ceramic electronic components include chip varistors, chip thermistors, and multilayer inductors.

[0069] Examples of the present invention are as follows: <1> A laminate comprising: a plurality of first ceramic layers stacked in the first axial direction; first internal electrode layers and second internal electrode layers, each alternately stacked via the first ceramic layers; a first side surface perpendicular to the second axial direction orthogonal to the first axial direction and including the first end of the first internal electrode layer and the second end of the second internal electrode layer; a second side surface opposite to the first side surface; a third side surface perpendicular to the third axial direction orthogonal to the first and second axial directions; and a fourth side surface opposite to the third side surface. It comprises a side margin portion that covers at least one of the third side and the fourth side, The first end is positioned such that, when viewed from the first axial direction, it does not overlap with the second end. All of the first internal electrode layers and all of the second internal electrode layers, when viewed from the first axial direction, have a second ceramic layer between the first end and the second end. The second ceramic layer is characterized by having a higher Si content than the first ceramic layer, making it a multilayer ceramic electronic component. <2> The second side surface includes the third end of the first internal electrode layer and the fourth end of the second internal electrode layer, The third end is positioned such that, when viewed from the first axial direction, it does not overlap with the fourth end. All of the first internal electrode layers and all of the second internal electrode layers, when viewed from the first axial direction, have a third ceramic layer between the third end and the fourth end. <2> This is a multilayer ceramic electronic component as described above. <3> The first side surface has a plurality of at least one of the first end and the second end, The second side surface has a plurality of at least one of the third end and the fourth end, <2> This is a multilayer ceramic electronic component as described above. <4> The side margin portion has a higher Si content than the first ceramic layer. <1> From the above <3> It is a multilayer ceramic electronic component as described in any of the following. [Explanation of Symbols]

[0070] 100 Multilayer Ceramic Electronic Components 101 Multilayer Ceramic Electronic Components 11. First ceramic layer 12 First internal electrode layer 120 1st internal electrode 121 First end 122 Third end 13 Second internal electrode layer 130 2nd internal electrode 131 Second end 132 Second end 133 4th end 134 4th end 141 Second ceramic layer 142 Third Ceramic Layer 16 Laminate 16a 1st side 16b Second side 16c 3rd side 16d 4th side 16e 5th aspect 16f 6th side 17 Side margin section 18 Capacity forming part 19 Cover margin section 20 External electrode formation area 21 External electrode 1000 Multilayer Ceramic Capacitors

Claims

1. A laminate comprising: a plurality of first ceramic layers stacked in the first axial direction; first internal electrode layers and second internal electrode layers, each alternately stacked via the first ceramic layers; a first side surface perpendicular to the second axial direction which is orthogonal to the first axial direction and includes the first end of the first internal electrode layer and the second end of the second internal electrode layer; a second side surface opposite to the first side surface; a third side surface perpendicular to the third axial direction which is orthogonal to the first and second axial directions; and a fourth side surface opposite to the third side surface. It comprises a side margin portion that covers at least one of the third side and the fourth side, The first end is positioned such that, when viewed from the first axial direction, it does not overlap with the second end. All of the first internal electrode layers and all of the second internal electrode layers, when viewed from the first axial direction, have a second ceramic layer between the first end and the second end. A multilayer ceramic electronic component characterized in that the second ceramic layer has a higher Si content than the first ceramic layer.

2. The second side surface includes the third end of the first internal electrode layer and the fourth end of the second internal electrode layer, The third end is positioned such that, when viewed from the first axial direction, it does not overlap with the fourth end. The multilayer ceramic electronic component according to claim 1, wherein all of the first internal electrode layers and all of the second internal electrode layers have a third ceramic layer between the third end and the fourth end when viewed from the first axial direction.

3. The first side surface has a plurality of at least one of the first end and the second end, The multilayer ceramic electronic component according to claim 2, wherein the second side surface has a plurality of at least one of the third end and the fourth end.

4. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein the side margin portion has a higher Si content than the first ceramic layer.

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