Drive signal generation circuit, recording element substrate, recording head, and recording device

Abstract

This prevents a decrease in output characteristics when the number of recording elements turned on simultaneously increases. [Solution] A drive signal generation circuit used in a recording element substrate comprising a plurality of first recording elements, a plurality of second recording elements, a plurality of first drive elements for driving the plurality of first recording elements, and a plurality of second drive elements for driving the plurality of second recording elements, wherein the circuit generates a first drive signal, waits for a waiting time, and then generates a second drive signal, at least one first drive element operates based on the first drive signal or the second drive signal, and at least one second drive element operates based on the first drive signal or the second drive signal.

Description

Technical Field

[0004] , , , , , , , , ,

[0001] The present disclosure relates to a drive signal generation circuit, a recording element substrate, a recording head, and a recording apparatus.

Background Art

[0002] As a method of driving an inkjet recording head (simply referred to as a "recording head"), an electrothermal conversion element (heater) is provided at a portion communicating with a discharge port for discharging ink droplets, and a current is supplied to the heater to generate heat, and ink droplets are discharged by film boiling of the ink. A switching element is connected to each heater, and a current flows through the heater when the switching element is turned on according to data. In order to drive a plurality of heaters provided corresponding to a plurality of discharge ports arranged in a row, a method of dividing the plurality of heaters into a plurality of blocks and driving the heaters of each block in a time-division manner is generally used.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] This disclosure has been made in view of the above points and aims to avoid a decrease in output characteristics when the number of recording elements that are turned on simultaneously increases. [Means for solving the problem]

[0006] One embodiment of the present disclosure is a drive signal generation circuit used in a recording element substrate comprising a plurality of first recording elements, a plurality of second recording elements, a plurality of first drive elements for driving the plurality of first recording elements, and a plurality of second drive elements for driving the plurality of second recording elements, wherein the drive signal generation circuit generates a first drive signal, waits for a waiting time, and then generates a second drive signal, and at least one of the first drive elements operates based on the first drive signal or the second drive signal, and at least one of the second drive elements operates based on the first drive signal or the second drive signal. [Effects of the Invention]

[0007] According to this disclosure, it is possible to avoid a decrease in output characteristics when the number of recording elements that are turned on simultaneously increases. [Brief explanation of the drawing]

[0008] [Figure 1] A perspective view showing an example of the external configuration of an inkjet recording apparatus according to an embodiment of the present disclosure. [Figure 2] Functional block diagram showing the functional configuration of the recording device shown in Figure 1. [Figure 3] Circuit diagram showing the circuit of the recording element substrate. [Figure 4] Timing chart showing the signal received by the LVDS method and the signal generated by the internal circuitry of the recording element board. [Figure 5] Circuit diagram showing the drive signal generation circuit of the first embodiment. [Figure 6] Timing chart showing detailed signal timing within one block time of the first embodiment [Figure 7] Image diagram showing the drive voltage and drive current in the first embodiment. [Figure 8] Circuit diagram showing the drive signal generation circuit of the second embodiment. [Figure 9] Circuit diagram showing the circuit of the recording element substrate. [Figure 10] Circuit diagram showing the configuration of the drive signal selection circuit. [Figure 11] The timing chart showing the operation of the recording element board is shown in Figure 9. [Modes for carrying out the invention]

[0009] The embodiments will be described in detail below with reference to the attached drawings. Note that the following embodiments do not limit the disclosures relating to the claims. While the embodiments describe multiple features, not all of these features are essential to the disclosure, and the features may be combined in any way. Furthermore, in the attached drawings, the same or similar configurations are given the same reference numerals, and redundant descriptions are omitted.

[0010] FIG. 1 is an external perspective view showing an outline of a configuration of a recording apparatus that performs recording using an inkjet recording head (also simply referred to as a “recording head”) which is a representative embodiment of the present disclosure.

[0011] As shown in FIG. 1, an inkjet recording apparatus (also simply referred to as a “recording apparatus”) 101 mounts a recording head 103 that ejects ink according to an inkjet method and performs recording on a carriage 102. Then, recording is performed by reciprocating the carriage 102 in the direction of arrow A. A recording medium P such as recording paper is fed through a paper feeding mechanism 104, conveyed to a recording position, and recording is performed by ejecting ink from the recording head 103 onto the recording medium P at the recording position.

[0012] The carriage 102 of the recording apparatus 101 not only mounts the recording head 103 but also mounts an ink tank 105 that stores ink supplied to the recording head 103. The ink tank 105 is detachable from the carriage 102.

[0013] The recording apparatus 101 shown in FIG. 1 is capable of color recording, and for this purpose, the carriage 102 mounts four ink cartridges that respectively contain magenta (M), cyan (C), yellow (Y), and black (K) inks. These four ink cartridges are each independently detachable.

[0014] The recording head 103 of this embodiment employs an inkjet method that ejects ink using thermal energy. For this reason, it includes a recording element (heater). This recording element is provided corresponding to each ejection port, and by applying a pulse voltage to the corresponding recording element according to a recording signal, ink is ejected from the corresponding ejection port. Note that the recording apparatus is not limited to the above-described serial type recording apparatus, and can also be applied to a so-called full line type recording apparatus in which a recording head (line head) having ejection ports arranged in the width direction of the recording medium is arranged in the conveyance direction of the recording medium.

[0015] FIG. 2 is a block diagram showing the control configuration of the recording apparatus 101 shown in FIG. 1.

[0016] As shown in FIG. 2, the controller 203 includes a processor 204 such as an MPU, a ROM 205, a special-purpose integrated circuit (ASIC) 206, a RAM 207, a system bus 208, and an A / D converter 209. Here, the ROM 205 stores programs corresponding to control sequences to be described later, required tables, and other fixed data. The ASIC 206 generates control signals for controlling the carriage motor M1, the conveyance motor M2, and the recording head 103. The RAM 207 is used as a development area for image data, a work area for program execution, and the like. The system bus 208 interconnects the processor 204, the ASIC 206, and the RAM 207 to perform data transfer. The A / D converter 209 inputs analog signals from a sensor group to be described below, performs A / D conversion, and supplies digital signals to the processor 204.

[0017] Also, in FIG. 2, reference numeral 201 denotes a host device corresponding to the host or MFP shown in FIG. 1 that is a source of image data. Image data, commands, status, etc. are transmitted and received by packet communication between the host device 201 and the recording apparatus 101 via an interface (I / F) 202. Note that the interface 202 may further include a USB interface separately from the network interface so that bit data and raster data serially transferred from the host can be received.

[0018] Furthermore, reference numeral 210 denotes a switch group. The switch group 210 includes a power switch 211, a print switch 212, and a recovery switch 213.

[0019] Reference numeral 214 indicates a group of sensors for detecting the device status. The sensor group 214 includes a position sensor 215 and a temperature sensor 216. In this embodiment, a photosensor (not shown) for detecting the remaining ink level is also provided. Furthermore, reference numeral 217 indicates a carriage motor driver that drives the carriage motor M1 for reciprocating scanning of the carriage 102 in the direction of arrow A. Reference numeral 218 indicates a transport motor driver that drives the transport motor M2 for transporting the recording medium P. Reference numeral 219 indicates a recording head control unit for controlling the recording head 103.

[0020] During recording scanning by the recording head 103, the ASIC 206 directly accesses the memory area of ​​the RAM 207 and transfers data to the recording head 103 to drive the recording element (heater for ink ejection). In addition, the recording device 101 includes a display unit (not shown) consisting of an LCD or LED as a user interface.

[0021] <Explanation of the recording element substrate configuration (Figures 3-4)> Figure 3 is a circuit diagram of the recording element substrate 301 built into the recording head 103.

[0022] The recording element board 301 receives data from the recording device controller 203 using the LVDS (Low Voltage Differential Signal) method. The LVDS receiver 302a receives data signals (DATA+, DATA-) via input terminals 304 and 305 and outputs internal data data. The LVDS receiver 302b receives clock signals (CLK+, CLK-) via input terminals 306 and 307 and outputs internal clock clk. The internal data data and internal clock clk are input to the data expansion circuit 309 and expanded into their respective functional circuits. The latch signal (LT) is received as a normal serial signal via input terminal 308, and the input circuit (op-amp) 303 amplifies it and outputs the lt signal.

[0023] The heater array circuits 311A ​​and 311B implement multiple recording elements (heaters 315) that heat and eject the ink in the nozzle they are responsible for, and multiple driving elements (driver transistors 314) that drive the multiple heaters 315. Transistors such as MOSFETs are used as the driver transistors 314. Furthermore, the heater array circuits 311A ​​and 311B implement logic circuits 313 (logic circuits, in this case AND circuits), flip-flop circuits (shift registers), and latch circuits 312 that operate in response to signals transmitted from the outside (the main body of the recording device 101). In the example shown in Figure 3, the multiple heaters 315 are arranged in two rows and implemented, and each row of nozzles is provided with heater array circuits 311A ​​and 311B to drive them. In addition, the drive signal generation circuit 310 is a circuit that generates a drive signal that defines the driving time of the heaters. In the heater train circuit 311A, the desired heater can be driven for a desired time by taking the AND operation between the latch circuit 312 and the he1 signal, which is the output signal of the drive signal generation circuit 310.

[0024] Figure 4 shows the timing chart of the signal received by the LVDS method and the signal generated by the internal circuit of the recording element board 301. As shown in Figure 4, the he1 signal and the he2 signal are periodically repeated with a period having a block time length. Here, an example is shown in which multiple driver transistors corresponding to multiple heaters are divided into 16 blocks (blocks 0 to 15) and driven in a time-division manner. Data transfer and driving of the recording element are performed simultaneously within one block time 401 of the time division drive. In block 1, the recording element is driven based on the data sent in block 0, and at the same time, data for driving is transmitted in block 2. The latch circuits 312 of the heater train circuits 311A ​​and 311B are provided with shift registers and latch circuits 312, and hd_clk and hd_data are transmitted to the shift registers of the heater train circuits 311A ​​and 311B. In addition, the drive signal generation circuit 310 is also provided with a shift register and latch circuit, and he_clk and he_data are transmitted to the shift register of the drive signal generation circuit 310.

[0025] In the next block, when the LT pulse rises to High (high level), the internal signal hd_data transferred in the previous block is stored and held in the latch circuits 312 of the corresponding heater column circuits 311A ​​and 311B, respectively, and the recording element to be driven is selected.

[0026] Furthermore, the internal signal he_data transferred in the previous block is stored and held in the latch circuit (not shown) of the drive signal generation circuit 310.

[0027] The drive signal generation circuit 310 counts the internal clock clk using an internal counter (not shown) and generates a drive signal corresponding to the data transferred in the previous block. As shown in Reference 2, by resetting the same counter after counting the he1 signal and generating the he2 signal, multiple drive signals can be generated by a single drive signal generation circuit 310, thereby reducing the circuit size.

[0028] <First Embodiment> Figure 5 is a circuit diagram showing the drive signal generation circuit 310 according to the first embodiment. In Figure 5, the same reference numerals are used for components that have already been described with reference to Figure 3, and their descriptions are omitted.

[0029] The drive signal generation circuit 310 includes flip-flop / latch circuits 501 and 503, a counter 502, comparators 504, 505a to 505d, a combination circuit 506, a switching signal generation circuit 507, and a drive signal selection circuit (also called a "selector") 508, all of which store drive signal data.

[0030] From the data received from the controller 203, the data expansion circuit 309 transmits data defining each edge PT3 / 2 / 1 / 0 of the drive signal and data defining the interval time between drive signals to the flip-flop latch circuits 501 and 503. The comparator 505 compares the counter value of the counter 502, count<7:0>, with the drive signal data pt3_data<7:0> sent from the data expansion circuit 309. The counter 502 starts counting from an initial value (zero in this embodiment). When the counter value of the counter 502, count<7:0>, becomes the drive signal data pt3_data<7:0>, the comparator 505a generates a drive signal PT3 that changes from Low to High at the timing of the rising edge of the next internal clock clk.

[0031] Similarly, the counter value of counter 502, count<7:0>, and the drive signal data pt2_data<7:0> sent from the data expansion circuit 309 are compared by comparator 505b. When the counter value of counter 502, count<7:0>, becomes the drive signal data pt2_data<7:0>, comparator 505b generates a drive signal PT2 that changes from Low to High at the timing of the rising edge of the next internal clock clk.

[0032] Similarly, the counter value of counter 502, count<7:0>, and the drive signal data pt1_data<7:0> sent from the data expansion circuit 309 are compared by comparator 505c. When the counter value of counter 502, count<7:0>, becomes the drive signal data pt1_data<7:0>, comparator 505c generates a drive signal PT1 that changes from Low to High at the timing of the rising edge of the next internal clock clk.

[0033] Similarly, the counter value of counter 502, count<7:0>, and the drive signal data pt0_data<7:0> sent from the data expansion circuit 309 are compared by comparator 505d. When the counter value of counter 502, count<7:0>, becomes the drive signal data pt0_data<7:0>, comparator 505d generates a drive signal PT0 that changes from Low to High at the timing of the rising edge of the next internal clock clk.

[0034] The drive signals PT3 / 2 / 1 / 0 are calculated by the combinational circuit 506 to generate the drive signals. The combinational circuit 506 is, for example, a 4-input exclusive OR circuit, and the comparison results from comparators 505a to 505d are taken as 4 inputs, and the exclusive OR of these is output as the he_out signal. The combinational circuit 506 may also be a circuit that verifies that the drive signals PT3 / 2 / 1 / 0 are in that order from LOW level to HIGH level before taking their exclusive OR. The combinational circuit 506, including configurations with and without such verification functions, will be referred to as a composite circuit.

[0035] Furthermore, the comparator 504 compares ICS_data<7:0> stored in the flip-flop latch circuit 503 with count0<7:0> output from the counter 502. If the count values ​​match, the comparator 504 generates a High signal at the rising edge timing of the next internal clock clk.

[0036] The switching signal generation circuit 507 generates the switching signal lt_reset using pt0_end and ics_end, resets the counter 502 and comparators 504 and 505a to 505d, and switches the selector 508.

[0037] Figure 6 shows a detailed timing chart for the 1-block time 401 shown in Figure 4. At the timing of the rising edge of LT, the data transmitted in the previous block is latched by the latch circuit, and the selector 508 selects terminal A. Here, the selector 508 selectively distributes the he_out signal to terminals A, B, or C. The he_out signal is output as the he1 signal from terminal A, as the he2 signal from terminal B, and as an unused signal from terminal C. PT3 / 2 / 1 / 0 are generated as described above according to the data confirmed by the latch circuit. The combinational circuit 506 generates a drive signal and outputs the he1 signal. Figure 6 shows that when the count value count<7:0> is 0, 15, 31, or 60, the outputs pt3, pt2, pt1, and pt0 from comparators 505a to d change from Low to High, respectively. Once the count reaches PT0, the switching signal lt_reset is output from the switching signal generation circuit 507 at the timing of the rising edge of the next internal clock clk, and the counter 502 and each comparator 504, 505a~505d are reset. Also, the switching signal generation circuit 507 causes the selector 508 to become an open output (selecting terminal C, which has no output destination).

[0038] The counter 502 is reset to its initial value and then resumes counting, counting the interval time between drive signals corresponding to ICS_data<7:0>. Figure 6 shows an example when ICS_data<7:0> is 26. When the counter 502 completes counting the number of ICS_data<7:0> corresponding to the interval time, the switching signal generation circuit 507 outputs the switching signal lt_reset at the timing of the rising edge of the next internal clock clk. Then, the counter 502 and each comparator 504, 505a~505d are reset. Also, the switching signal generation circuit 507 selects terminal B on the selector 508.

[0039] From the next internal clock (clk), counter 502 restarts counting from its initial value, repeating the same operation as the he1 signal generation, and generating an he2 signal with the same pulse width as the he1 signal. Selector 508 is reset on the next rising edge of LT and selects terminal A.

[0040] For example, when driving 16 blocks (block0-15) at 18kHz, the duration of one block (401) is approximately 3.47μs. Assume that at least 0.1μs is required between the rising edge of the lt signal and the rising edge of the first internal clock (clk). Also, at least 0.4μs is required between the end of the he2 signal and the rising edge of the next lt signal. This leaves a transmission time of 2.97μs for the remaining internal clock (clk). Signals he1 and he2 each have double-pulse waveforms, and when the width of one double pulse is 1.2μs, the waiting time can be set to a maximum of 0.57μs. If the LVDS is 50MHz (1clk period is 20ns), the waiting time can be set to approximately 0.57μs by setting ICS_data to 26. The 0.57μs includes the 1clk duration from pt0 to the switching signal lt_reset and the 1clk duration from the switching signal lt_reset at the end of the waiting time to the start of the he2 signal. If the LVDS is 75MHz (1clk period is 13.3ns), setting ICS_data to 40 will reduce the waiting time to approximately 0.57μs.

[0041] As described above, the waveforms of the he1 and he2 signals are determined by the positions of the four edges PT3 / 2 / 1 / 0. The position of edge PT3 is determined by the value of the data pt3_data<7:0>. The position of edge PT2 is determined by the value of the data pt2_data<7:0>. The position of edge PT1 is determined by the value of the data pt1_data<7:0>. The position of edge PT0 is determined by the value of the data pt0_data<7:0>. Therefore, we will refer to the data pt3_data<7:0>, pt2_data<7:0>, pt1_data<7:0>, and pt0_data<7:0> as waveform data.

[0042] Furthermore, the he1 and he2 signals are inverted at the four edges PT3 / 2 / 1 / 0. Therefore, the data pt3_data<7:0>, pt2_data<7:0>, pt1_data<7:0>, and pt0_data<7:0> are defined as inversion count values.

[0043] Furthermore, the lengths of the he1 and he2 signals are determined by the position of edge PT0. Therefore, the data pt0_data<7:0> is called the duration data, and this value is referred to as the drive signal count value.

[0044] Furthermore, the waiting time is determined by the data ICS_data<7:0>. Therefore, we will refer to the data ICS_data<7:0> as the waiting time data, and this value will be called the waiting time count value.

[0045] Figure 7 shows an image of the actual drive voltage and drive current for the set drive signal. Figure 7(a) shows the case where the interval time between the signal output by the he1 signal and the signal output by the he2 signal is shortened when there are many heaters turned on simultaneously. When many heaters are turned on simultaneously, current flows through the parasitic inductance, and immediately after time t1 the drive voltage undershoots and the drive current also decreases. Conversely, immediately after time t4 when the he1 signal is off the drive voltage overshoots. If the next he2 signal comes immediately after the he1 signal, then because time t5 comes immediately after time t4, the next drive starts before the fluctuation in the drive voltage settles down. As a result, the drive current for the he1 signal (times t1 to t4) and the drive current for the he2 signal (times t5 to t8) are different, creating a difference in the energy required to drive the heater. This energy difference can affect the ink ejection speed and may cause image unevenness, etc. As a countermeasure, the interval time is set to be longer, as shown in Figure 7(b). The interval time is set so that the he2 signal is started after the fluctuation in the drive voltage that occurred by time t4 has subsided. This eliminates the current difference between the he1 signal and the he2 signal. As described above, by controlling the interval time from the controller according to the number of simultaneous ons, high-quality output can be achieved. Figure 7(c) shows an image when the number of simultaneous ons is small. When the number of simultaneous ons is small, the fluctuation in the drive voltage becomes small, so the energy difference can be made small enough to be ignored, and it becomes possible to shorten the time interval between time t4 and time t5. As described above, when the number of simultaneous ons is small, it is possible to speed up printing by shortening the interval between the he1 signal and the he2 signal. The number of simultaneous ons is the number of signals with a high level among the signals latched by the latch circuit 312 (i.e., signals that should be supplied to one input of the logic circuit 313), and is known by the controller 203. Therefore, the controller 203 can adjust the interval time according to the known number of simultaneous ons.

[0046] For example, in high-quality mode, the number of shots fired is high, so the interval time can be set longer to prioritize image quality. In high-speed mode, the number of simultaneous activations can be limited, and the interval time can be set shorter to prioritize speed.

[0047] As described above, by making the interval time between drive signals variable based on external data, a single drive signal generation circuit 310 can achieve drive according to the drive conditions. Only one drive signal selection circuit 508 is needed for each drive signal generation circuit 310, making it possible to implement this with a small circuit size. By resetting and using the same counter 502, it is only necessary to count the he1 signal, interval time, and he2 signal respectively, so the circuit size of the counter 502 can also be reduced.

[0048] Furthermore, the drive signals he1 and he2 output to the heater train circuits 311A ​​and 311B, respectively, may be delayed for each drive element within the heater train circuits 311A ​​and 311B. For example, delaying the drive signals for each time division unit prevents multiple drive elements from being switched on and off simultaneously, thus preventing rapid voltage fluctuations. In this case, the drive signals output from the drive signal selection circuit 508 are delayed slightly in terms of the timing of driving the drive elements.

[0049] Furthermore, the switching signal lt_reset signal may be divided into multiple signals, and multiple signals may be generated depending on the selection of selector 508.

[0050] Furthermore, the internal clock clk input to comparators 504 and 505a-505d may be separated for comparator 504 and comparators 505a-505d. For example, when generating the he1 signal or the he2 signal, the internal clock clk may be input only to comparators 505a-505d from the switching signal generation circuit 507, and during the standby time, the internal clock clk may be input only to comparator 504.

[0051] <Second Embodiment> Figure 8 is a circuit diagram of the recording element substrate 301 according to the second embodiment. In Figure 8, the same reference numerals are used for components that have already been described with reference to the figure, and their descriptions are omitted.

[0052] As shown in Figure 8, a flip-flop circuit 801 is used to generate edge PT3 without using a comparator. The input data of the flip-flop circuit 801 is fixed to the logic power supply VDD, and PT3 is output as soon as there is an output from the counter 502. In order to generate the two drive signals he1 and he2 within the block time, edge PT3 is fixed to the initial timing of the block time. This reduces the degree of freedom in setting edge PT3, but eliminates the need for pt3_data<7:0> which was necessary for edge PT3 generation, thus reducing the number of data. In addition, the flip-flop latch circuit 501a and comparator 505a for data storage are also unnecessary, thus suppressing the increase in circuit size.

[0053] According to the embodiment described above, by fixing one drive timing piece as a fixed timing, it becomes possible to reduce the number of data points and the circuit size.

[0054] <Third Embodiment> The third embodiment shown in Figure 9 is an addition of a drive signal selection circuit 901 compared to the first embodiment.

[0055] The drive signal selection circuit 901 has a configuration as shown in Figure 10, for example. When the drive signal selection circuit 901 has a configuration as shown in Figure 10, the drive signals he_a and he_b will be as follows, depending on the values ​​of the selection signals sel0 and sel1. If sel0=LOW and sel1=LOW, he_a = he1 he_b = he2 If sel0=HIGH and sel1=LOW, he_a = he1 he_b = he1 If sel0=LOW and sel1=HIGH, he_a = he2 he_b = he1 If sel0=HIGH and sel1=HIGH, he_a = he2 he_b = he2

[0056] In Figure 11, in even-numbered blocks from block0 to block14, sel0=LOW and sel1=LOW. In odd-numbered blocks from block1 to block15, sel0=LOW and sel1=HIGH. In blocks from block15 onward, sel0=HIGH and sel1=LOW. According to the third embodiment, either drive signal he1 or drive signal he2 can be selected as drive signal he_a. Furthermore, either drive signal he1 or drive signal he2 can be selected as drive signal he_b.

[0057] <Other Embodiments> The recording head 103 in the above embodiment employs an inkjet method that ejects ink using thermal energy. Therefore, it is equipped with a recording element (heater). However, this is not the only method; the above embodiment can also be applied to an inkjet method that ejects ink using a piezoelectric element as the recording element.

[0058] A signal indicating the aforementioned operating mode may be input from an external source. The waiting time may also be switched according to the operating mode. For example, data corresponding to pt0_data<7:0> may be stored for each operating mode, and the data selected according to the operating mode may be supplied to the comparator 505. The operating mode can be included in the serial communication DATA (and therefore data), but it may also be transmitted via a different transmission path.

[0059] The recording head may also eject droplets of liquid other than ink.

[0060] <Technical Features of This Disclosure> This disclosure includes the following components:

[0061] [Configuration 1] Multiple first recording elements, Multiple second recording elements, A plurality of first drive elements for driving the plurality of first recording elements, A plurality of second drive elements for driving the plurality of second recording elements, A drive signal generation circuit used in a recording element substrate comprising, A first drive signal is generated, and after waiting for a specified waiting time, a second drive signal is generated. At least one of the first drive elements operates based on the first drive signal or the second drive signal, and at least one of the second drive elements operates based on the first drive signal or the second drive signal. Drive signal generation circuit.

[0062] [Configuration 2] The first drive signal and the second drive signal are generated periodically. The drive signal generation circuit described in Configuration 1.

[0063] [Configuration 3] The system further includes means for providing a second waiting time between the second drive signal generated at a certain period and the first drive signal generated at the period following the certain period. The drive signal generation circuit described in Configuration 2.

[0064] [Structure 4] The first drive signal and the second drive signal have waveforms based on waveform data input from an external source. A drive signal generation circuit as described in any one of configurations 1 to 3.

[0065] [Composition 5] The system generates the first drive signal and the second drive signal having a duration based on duration data input from an external source. A drive signal generation circuit as described in any one of configurations 1 to 4.

[0066] [Composition 6] Data is input from an external source, including a plurality of inversion count values ​​indicating the timing at which the first drive signal and the second drive signal invert, a drive signal count value corresponding to the duration of the first drive signal and the second drive signal, and a standby time count value corresponding to the duration of the standby time. The counter and A means for generating the first drive signal, wherein the level inverts each time the count value output by the counter, which started counting from an initial value, matches any of the count values ​​included in the plurality of inverted count values, and the process ends when the count value output by the counter matches the drive signal count value, If the count value output by the counter, which has been restarted from the initial value after the generation of the first drive signal is completed, matches the waiting time count value, means to terminate the waiting time and restart the counter from the initial value again, A means for generating a second drive signal, wherein the level inverts each time the count value output by the counter, which has been reopened from the initial value after the aforementioned waiting time has ended, matches any of the count values ​​included in the plurality of inverted count values, and the second drive signal is terminated when the count value output by the counter matches the drive signal count value, Equipped with, A drive signal generation circuit as described in any one of configurations 1 to 5.

[0067] [Composition 7] Data is input from an external source, including a plurality of inversion count values ​​indicating the timing at which the first drive signal and the second drive signal invert, a drive signal count value corresponding to the duration of the first drive signal and the second drive signal, and a standby time count value corresponding to the duration of the standby time. The counter and Multiple first comparators that compare the count value output by the counter with the multiple inverted count values, A second comparator that compares the count value output by the counter with the drive signal count value, A third comparator that compares the count value output by the counter with the waiting time count value, A synthesis circuit that generates the first drive signal and the second drive signal based on the multiple comparison results from the multiple first comparators and the comparison results from the second comparator, A switching signal generation circuit that generates a switching signal based on the comparison result of the first comparator corresponding to the largest inverted count value among the plurality of first comparators and the comparison result of the third comparator, A selector that, based on the switching signal, distributes the first drive signal and the second drive signal to a first heater train circuit including the plurality of first drive elements and a second heater train circuit including the plurality of second drive elements, respectively. Equipped with, The counter, the second comparator, the third comparator, and the switching signal generation circuit are used to provide the waiting time between the first drive signal and the second drive signal based on the comparison result of the third comparator. A drive signal generation circuit as described in any one of configurations 1 to 5.

[0068] [Structure 8] Data is input from an external source, including a plurality of inversion count values ​​indicating the timing at which the waveforms of the first drive signal and the second drive signal invert, a drive signal count value corresponding to the duration of the first drive signal and the second drive signal, and a standby time count value corresponding to the duration of the standby time. The counter and Multiple first comparators that compare the count value output by the counter with the multiple inverted count values, A second comparator that compares the count value output by the counter with the drive signal count value, A third comparator that compares the count value output by the counter with the waiting time count value, The aforementioned counter is set when it starts counting, and a flip-flop circuit is reset by a switching signal, A combination circuit that generates the first drive signal and the second drive signal based on the multiple comparison results from the multiple first comparators, the comparison result from the second comparator, and the output of the flip-flop circuit, A switching signal generation circuit that generates a switching signal that switches based on the comparison result of the first comparator corresponding to the largest inverted count value among the plurality of first comparators and the comparison result of the third comparator, A selector that, based on the switching signal, distributes the first drive signal and the second drive signal to a first heater train circuit including the plurality of first drive elements and a second heater train circuit including the plurality of second drive elements, respectively. Equipped with, The counter, the second comparator, the third comparator, and the switching signal generation circuit are used to provide the waiting time between the first drive signal and the second drive signal based on the comparison result of the third comparator. A drive signal generation circuit as described in any one of configurations 1 to 5.

[0069] [Composition 9] The recording element substrate is used in a first operating mode and a second operating mode in which, compared to the first operating mode, there are more of the multiple first recording elements and the multiple second recording elements that are driven simultaneously. The drive signal generation circuit makes the waiting time in the second operating mode longer than the waiting time in the first operating mode. A drive signal generation circuit as described in any one of configurations 1 to 8.

[0070] [Configuration 10] Waiting time data indicating the waiting time corresponding to the aforementioned operating mode is input from an external source. The drive signal generation circuit determines the waiting time based on the waiting time data from an external source. The drive signal generation circuit described in Configuration 9.

[0071] [Composition 11] A signal indicating the aforementioned operating mode is input from an external source. The drive signal generation circuit determines the waiting time based on the operating mode. The drive signal generation circuit described in Configuration 9.

[0072] [Composition 12] A drive signal generation circuit as described in any one of configurations 1 to 11, The plurality of first recording elements, The plurality of second recording elements, The plurality of first driving elements, The plurality of second driving elements, A recording element substrate equipped with a recording element.

[0073] [Composition 13] When the selection signal has a first value, at least one of the first drive elements operates based on the first drive signal, and at least one of the second drive elements operates based on the first drive signal. A recording element substrate as described in configuration 12.

[0074] [Composition 14] If the selection signal has a second value, at least one of the first drive elements operates based on the first drive signal, and at least one of the second drive elements operates based on the second drive signal. A recording element substrate as described in configuration 12 or 13.

[0075] [Composition 15] If the selection signal has a third value, at least one of the first drive elements operates based on the second drive signal, and at least one of the second drive elements operates based on the first drive signal. A recording element substrate as described in any one of configurations 12 to 14.

[0076] [Composition 16] If the selection signal has a fourth value, at least one of the first drive elements operates based on the second drive signal, and at least one of the second drive elements operates based on the second drive signal. A recording element substrate according to any one of claims 12 to 15.

[0077] [Composition 17] A recording head using the recording element substrate described in configuration 12, characterized in that it has a plurality of discharge ports for discharging liquid.

[0078] [Composition 18] A recording device that uses the recording head described in configuration 17 as an ink, with the liquid being used as the ink, and records onto a recording medium, A recording device characterized by driving the plurality of first recording elements and the plurality of second recording elements to eject ink from an ejection port.

Claims

1. Multiple first recording elements, Multiple second recording elements, A plurality of first drive elements for driving the plurality of first recording elements, A plurality of second drive elements for driving the plurality of second recording elements, A drive signal generation circuit used in a recording element substrate comprising, A first drive signal is generated, and after waiting for a specified waiting time, a second drive signal is generated. At least one of the first drive elements operates based on the first drive signal or the second drive signal, and at least one of the second drive elements operates based on the first drive signal or the second drive signal. Drive signal generation circuit.

2. The first drive signal and the second drive signal are generated periodically. The drive signal generation circuit according to claim 1.

3. The system further includes means for providing a second waiting time between the second drive signal generated at a certain period and the first drive signal generated at the period following the certain period. The drive signal generation circuit according to claim 2.

4. The first drive signal and the second drive signal have waveforms based on waveform data input from an external source. The drive signal generation circuit according to claim 1.

5. The system generates the first drive signal and the second drive signal having a duration based on duration data input from an external source. The drive signal generation circuit according to claim 1.

6. Data is input from an external source, including a plurality of inversion count values ​​indicating the timing at which the first drive signal and the second drive signal invert, a drive signal count value corresponding to the duration of the first drive signal and the second drive signal, and a standby time count value corresponding to the duration of the standby time. The counter and A means for generating the first drive signal, wherein the level inverts each time the count value output by the counter, which started counting from an initial value, matches any of the count values ​​included in the plurality of inverted count values, and the first drive signal terminates when the count value output by the counter matches the drive signal count value, If the count value output by the counter, which has been restarted from the initial value after the generation of the first drive signal is completed, matches the waiting time count value, the means to terminate the waiting time and restart the counter from the initial value again, A means for generating a second drive signal, wherein the level inverts each time the count value output by the counter, which has been reopened from the initial value after the aforementioned waiting time has ended, matches any of the count values ​​included in the plurality of inverted count values, and the second drive signal is terminated when the count value output by the counter matches the drive signal count value, Equipped with, The drive signal generation circuit according to claim 1.

7. Data is input from an external source, including a plurality of inversion count values ​​indicating the timing at which the first drive signal and the second drive signal invert, a drive signal count value corresponding to the duration of the first drive signal and the second drive signal, and a standby time count value corresponding to the duration of the standby time. The counter and Multiple first comparators that compare the count value output by the counter with the multiple inverted count values, A second comparator that compares the count value output by the counter with the drive signal count value, A third comparator that compares the count value output by the counter with the waiting time count value, A synthesis circuit that generates the first drive signal and the second drive signal based on the multiple comparison results from the multiple first comparators and the comparison results from the second comparator, A switching signal generation circuit that generates a switching signal based on the comparison result of the first comparator corresponding to the largest inverted count value among the plurality of first comparators and the comparison result of the third comparator, A selector that, based on the switching signal, distributes the first drive signal and the second drive signal to a first heater train circuit including the plurality of first drive elements and a second heater train circuit including the plurality of second drive elements, respectively. Equipped with, Based on the comparison result by the third comparator, the counter, the second comparator, the third comparator, and the switching signal generation circuit, the waiting time is provided between the first drive signal and the second drive signal. The drive signal generation circuit according to claim 1.

8. Data is input from an external source, including a plurality of inversion count values ​​indicating the timing at which the waveforms of the first drive signal and the second drive signal invert, a drive signal count value corresponding to the duration of the first drive signal and the second drive signal, and a standby time count value corresponding to the duration of the standby time. The counter and Multiple first comparators that compare the count value output by the counter with the multiple inverted count values, A second comparator that compares the count value output by the counter with the drive signal count value, A third comparator that compares the count value output by the counter with the waiting time count value, The aforementioned counter is set when it starts counting, and a flip-flop circuit is reset by a switching signal, A combination circuit that generates the first drive signal and the second drive signal based on the multiple comparison results from the multiple first comparators, the comparison result from the second comparator, and the output of the flip-flop circuit, A switching signal generation circuit that generates a switching signal that switches based on the comparison result of the first comparator corresponding to the largest inverted count value among the plurality of first comparators and the comparison result of the third comparator, A selector that, based on the switching signal, distributes the first drive signal and the second drive signal to a first heater train circuit including the plurality of first drive elements and a second heater train circuit including the plurality of second drive elements, respectively. Equipped with, The counter, the second comparator, the third comparator, and the switching signal generation circuit are used to provide the waiting time between the first drive signal and the second drive signal based on the comparison result of the third comparator. The drive signal generation circuit according to claim 1.

9. The recording element substrate is used in a first operating mode and a second operating mode in which, compared to the first operating mode, there are more of the multiple first recording elements and the multiple second recording elements that are driven simultaneously. The drive signal generation circuit makes the waiting time in the second operating mode longer than the waiting time in the first operating mode. The drive signal generation circuit according to claim 1.

10. Waiting time data indicating the waiting time corresponding to the aforementioned operating mode is input from an external source. The drive signal generation circuit determines the waiting time based on the waiting time data from an external source. The drive signal generation circuit according to claim 9.

11. A signal indicating the aforementioned operating mode is input from an external source. The drive signal generation circuit determines the waiting time based on the operating mode. The drive signal generation circuit according to claim 9.

12. A drive signal generation circuit according to any one of claims 1 to 11, The plurality of first recording elements, The plurality of second recording elements, The plurality of first driving elements, The plurality of second drive elements, A recording element substrate equipped with a recording element.

13. When the selection signal has a first value, at least one of the first drive elements operates based on the first drive signal, and at least one of the second drive elements operates based on the first drive signal. A recording element substrate according to claim 12.

14. When the selection signal has a second value, at least one of the first drive elements operates based on the first drive signal, and at least one of the second drive elements operates based on the second drive signal. A recording element substrate according to claim 12.

15. When the selection signal has a third value, at least one of the first drive elements operates based on the second drive signal, and at least one of the second drive elements operates based on the first drive signal. A recording element substrate according to claim 12.

16. When the selection signal has a fourth value, at least one of the first drive elements operates based on the second drive signal, and at least one of the second drive elements operates based on the second drive signal. A recording element substrate according to claim 12.

17. A recording head using a recording element substrate as described in claim 12, characterized in that it has a plurality of discharge ports for discharging liquid.

18. A recording device that uses the recording head described in claim 17 as an ink, with the liquid being used as an ink ejection head, and records on a recording medium, A recording device characterized by driving the plurality of first recording elements and the plurality of second recording elements to eject ink from an ejection port.

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