Crystalline silicon solar cell and method for manufacturing the same

Abstract

The objective is to provide solar cells with good power generation performance and in the desired size and shape. [Solution] A solar cell that solves the above problem includes an n-type or p-type crystalline silicon layer having a first main surface and a second main surface which is the back surface thereof, an amorphous semiconductor layer or passivation layer disposed adjacent to the first main surface of the crystalline silicon layer, and an electrode layer disposed on the first main surface of the crystalline silicon layer. At least one side surface of the crystalline silicon layer has a first region that is continuous from the first main surface side and is covered by the amorphous semiconductor layer or the passivation layer.

Description

Technical Field

[0001] The present invention relates to a crystalline silicon solar cell and a method for manufacturing the same.

Background Art

[0002] Crystalline silicon solar cells are the most widely used among solar cells. A crystalline silicon solar cell module generally has a structure in which crystalline silicon solar cells are connected in series or parallel to form a string, which is sandwiched between glass and a backsheet and laminated via a sealing material. The crystalline silicon substrate used in the manufacture of solar cells is often 150 mm square or more and 200 μm or less in thickness. On the other hand, it is known that by making the size of the solar cell smaller than this, the short-circuit current value decreases and the resistance loss decreases. It is also known that by dividing the solar cell and performing single connection, the optical loss in the module is reduced. Therefore, after forming the necessary layers on a large-area crystalline silicon, it is divided into a plurality of parts (for example, Non-Patent Document 1). In recent years, from the viewpoint of design, the solar cell is also divided into strip shapes. For example, a solar cell module in which strip-shaped solar cells are arranged is very useful as a window material or the like, and there is a demand for it as a building material integrated module or the like.

[0003] Here, when manufacturing a small-sized crystalline silicon solar cell, it is preferable from the viewpoint of the manufacturing efficiency of the solar cell to form a semiconductor layer, a passivation layer, an electrode layer, etc. on a large-area crystalline silicon and then divide it into a desired size. As methods for dividing a crystalline silicon solar cell into a desired size, the following three methods are known.

[0004] One method involves forming grooves in the crystalline silicon substrate after each layer has been formed, grooves that do not penetrate all the way through, and then cutting along these grooves (scribing and cutting method, also known as the "SC method") (for example, Patent Documents 1-3 and Non-Patent Document 2, etc.). According to this SC method, it is possible to divide crystalline silicon solar cells into various sizes. Furthermore, various methods such as rotating blades and lasers can be used to form the grooves.

[0005] A second method involves heating and cooling a portion of the crystalline silicon substrate after each layer formation using laser sweeping, thereby propagating cracks through thermal shock (thermal laser splitting method) (for example, Non-Patent Document 3). This method has the advantage of suppressing damage to the split surface.

[0006] A third method involves cleaving by utilizing the tendency of the crystal structure to crack in a specific direction (cleavage method) (see, for example, Patent Document 4).

[0007] Of the methods described above, the thermal laser splitting method performs laser sweeping and water jetting simultaneously to split the material in one go, making it difficult to handle fine structures. Therefore, this method has limitations on the types of materials that can be processed and on the size of the processed material. Furthermore, in the cleavage method described above, the direction in which the material can be split is determined by the crystal orientation. As a result, there are limitations on the shape of the solar cells that can be formed. Considering these factors, the SC method is particularly preferable from the standpoint that it can split the material into any size and in any direction.

[0008] Regardless of the method used for splitting, crystalline silicon is exposed at the end faces created by the splitting. Furthermore, depending on the splitting method, the crystalline structure of the end faces may be destroyed, or impurities (such as metals that make up the electrode layer) may be introduced, resulting in many defects at the end faces. These defects lead to a decrease in power generation performance, and the effect becomes greater the smaller and thinner the crystalline silicon solar cell is split into. Therefore, when performing splitting, it is necessary to design the structure and size of the elements and select an appropriate splitting method so that the desired power generation performance is achieved. On the other hand, it has also been proposed to form a defect termination film made of aluminum oxide or the like on the crystalline silicon exposed at the end faces in order to improve the power generation performance of the solar cell after splitting (Non-Patent Literature 4). [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 2005-236017 [Patent Document 2] Japanese Patent Publication No. 2006-310774 [Patent Document 3] Japanese Patent Publication No. 2015-191969 [Patent Document 4] International Publication No. 2018 / 055847 [Non-patent literature]

[0010] [Non-Patent Document 1] J. Muller et al., "Resistive Power Loss Analysis of PV Modules Made From Halved 15.6×15.6 cm2Silicon Perc Solar Cells With Efficiencies up to 20.0%", IEEE Journal of Photovoltaics, 2015, Vol. 5, No. 1, pp. 189-194 [Non-Patent Document 2] Lei Xia et al., "Influence of laser cutting conditions on electrical characteristics of half-size bifacial silicon solar cells", Materials Science in Semiconductor Processing, 2020, Vol. 105, 104747 [Non-Patent Document 3] Zulmandakh Otgongerel et al., "Analysis of different laser cutting conditions on electrical characteristics of half-cut HJT solar cells", Journal of the Korean Physical Society, 2023, Vol. 83, pp. 437-443 [Non-Patent Document 4] Puzant Baliozian et al., “Postmetallization “Passivated Edge Technology” for Separated Silicon Solar Cells”, IEEE Journal of Photovoltaics, 2020, Vol. 10, No. 2, pp. 390-397 [Overview of the project] [Problems that the invention aims to solve]

[0011] As described above, in order to obtain solar cells of the desired size and shape, it is desirable to divide the crystalline silicon substrate using the SC method. However, when solar cells are divided using the SC method, a decrease in performance compared to before division is unavoidable. The reason for this will be explained using Figures 1A to 1E. Figures 1A to 1E are process diagrams for manufacturing silicon heterojunction (SHJ) type solar cells using the conventional SC method. In this solar cell manufacturing method, as shown in Figure 1A, a flat and relatively large-area crystalline silicon substrate 917 is prepared, and a texture structure is formed on the main surface of the crystalline silicon substrate 917 as needed (Figure 1B). Then, as shown in Figure 1C, the necessary layers (amorphous silicon layers 920, 940 and electrode layers 930, 950) are formed on the crystalline silicon substrate 917. After that, as shown in Figure 1D, a groove 961 of a predetermined depth is formed on one side of these laminates. Then, as shown in Figure 1E, the laminate is folded (cut) along the groove 961 to obtain the desired solar cell 900.

[0012] In this method, a processed alteration layer (processed alteration region) 962 is likely to form on the wall surface of the groove 961 during its formation. Figure 2A shows a photograph (a scanning electron microscope (SEM) image) of a crystalline silicon substrate when a groove was formed by laser scribing. Figure 2B shows an SEM image of the surface cut along the groove. As shown in Figures 2A and 2B, large irregularities (processed alteration layer) are present on the wall surface of the groove created by scribing. Based on their morphology, these are presumed to be Si that melted and solidified due to scribing (laser irradiation). Furthermore, analysis revealed that the Si on the surface of the processed alteration layer (processed alteration region) was oxidized.

[0013] As described above, the formation of such a processed and altered layer results in many defects and affects power generation performance, so it is preferable to remove it. However, in the conventional SC method, it is difficult to remove the processed and altered layer, and for example, as shown in Figure 1E, the processed and altered layer 962 remains on the end face of the solar cell 900.

[0014] Furthermore, as described in Non-Patent Document 4 above, covering the sides of the obtained solar cell 900 with a defective termination layer has also been considered. However, even if the processed and altered layer 962 is covered with a defective termination layer, the processed and altered layer does not disappear. Therefore, it has been difficult to significantly improve the power generation performance of the solar cell using this method.

[0015] This invention has been made in view of the above problems. Specifically, it aims to provide a method for manufacturing solar cells that have good power generation performance and are of a desired size and shape, and to provide solar cells obtained therefrom. [Means for solving the problem]

[0016] The present invention provides the following crystalline silicon solar cell. [1] A crystalline silicon solar cell comprising an n-type or p-type crystalline silicon layer having a first main surface and a second main surface which is the back surface thereof, and an amorphous semiconductor layer or passivation layer disposed adjacent to the first main surface of the crystalline silicon layer, wherein at least one side surface of the crystalline silicon layer has a first region covered by the amorphous semiconductor layer or the passivation layer, which is continuous from the first main surface side. [2] The crystalline silicon solar cell according to [1], wherein at least one side surface of the crystalline silicon layer further has a second region on the second main surface side of the first region that is not covered by either the amorphous semiconductor layer or the passivation layer. [3] The crystalline silicon solar cell according to [2], wherein the surface of the second region is composed of a (110) plane or a (100) plane of crystalline silicon. [4] The crystalline silicon solar cell according to [2] or [3], wherein the second region of the crystalline silicon layer is covered with a defect termination layer. [5] The crystalline silicon solar cell according to any one of [1] to [4], wherein the ratio of the area of ​​the first region to the total area of ​​one side surface including the first region of the crystalline silicon layer is 1 / 5 or more. [6] A crystalline silicon solar cell according to any one of [1] to [5], comprising the amorphous semiconductor layer, wherein the amorphous semiconductor layer is an amorphous silicon layer and / or a microcrystalline silicon layer, and the first region of the crystalline silicon layer is covered with the amorphous silicon layer or the microcrystalline silicon layer. [7] The crystalline silicon solar cell according to [1] to [6], wherein the electrode layer is arranged only on the first main surface of the crystalline silicon layer, and the outer circumference of the electrode layer when viewed in plan is located inward from the outer circumference of the first main surface of the crystalline silicon layer when viewed in plan. [8] A crystalline silicon solar cell according to any one of [1] to [5], comprising the passivation layer, wherein the passivation layer comprises one or more layers selected from the group consisting of silicon oxide, silicon nitride, aluminum oxide, and composites thereof, and the first region of the crystalline silicon layer is covered with the passivation layer. [9] The crystalline silicon solar cell according to any one of [1] to [8], wherein the pn junction surface is located on the first main surface side of the crystalline silicon layer.

[0017] This invention provides a method for manufacturing crystalline silicon solar cells.

[10] A method for manufacturing a crystalline silicon solar cell, comprising in this order: preparing an n-type or p-type crystalline silicon substrate having a first main surface and a second main surface which is the back surface thereof; forming grooves on the first main surface of the crystalline silicon substrate; etching the crystalline silicon substrate; forming an amorphous semiconductor layer or a passivation layer on the first main surface of the crystalline silicon substrate; and cutting the crystalline silicon substrate along the grooves.

[11] A method for manufacturing a crystalline silicon solar cell according to

[10] , further comprising the step of forming a defect termination layer so as to cover the surface created by the cutting after the step of cutting the crystalline silicon substrate.

[12] A method for manufacturing a crystalline silicon solar cell according to

[10] or

[11] , further comprising the step of forming a texture structure on a first main surface and / or a second main surface of the crystalline silicon substrate after the step of etching the crystalline silicon substrate. [Effects of the Invention]

[0018] The present invention provides a method for manufacturing a crystalline silicon solar cell having a desired size and shape and good power generation performance, as well as a solar cell obtained therefrom. [Brief explanation of the drawing]

[0019] [Figure 1] Figures 1A to 1E are process diagrams for manufacturing silicon heterojunction (SHJ) type solar cells using the conventional SC method. [Figure 2] Figure 2A is an SEM image of a crystalline silicon substrate after grooves have been formed by laser scribing, and Figure 2B is an SEM image of the surface cut along the grooves. [Figure 3] Figure 3 is a schematic cross-sectional view showing the configuration of a solar cell according to the first embodiment of the present invention. [Figure 4] Figure 4 is a diagram showing the flow of the manufacturing method for a solar cell according to the first embodiment of the present invention. [Figure 5] Figures 5A to 5F are process diagrams illustrating the manufacturing method of a solar cell according to the first embodiment of the present invention. [Figure 6] Figure 6A is an SEM image of a crystalline silicon substrate after grooves have been formed and etched, and Figure 6B is an SEM image of the surface cut along the grooves after etching. [Figure 7] Figures 7A and 7B are schematic plan views illustrating the direction of groove formation. [Figure 8] Figure 8 is a schematic cross-sectional view illustrating a modified example of a solar cell according to the first embodiment of the present invention. [Figure 9] Figure 9 is a schematic cross-sectional view illustrating another modification of a solar cell according to the first embodiment of the present invention. [Figure 10] Figure 10 is a schematic cross-sectional view showing the configuration of a solar cell according to a second embodiment of the present invention. [Figure 11]Figures 11A to 11F are process diagrams illustrating the manufacturing method of a solar cell according to a second embodiment of the present invention. [Figure 12] Figure 12 is a schematic cross-sectional view showing the configuration of a solar cell according to a third embodiment of the present invention. [Figure 13] Figures 13A to 13F are process diagrams illustrating the manufacturing method of a solar cell according to a third embodiment of the present invention. [Figure 14] Figure 14 is a schematic cross-sectional view showing the configuration of a solar cell according to a fourth embodiment of the present invention. [Figure 15] Figures 15A to 15F are process diagrams illustrating a method for manufacturing a solar cell according to a third embodiment of the present invention. [Figure 16] Figure 16 is a schematic cross-sectional view showing a modified example of a solar cell according to a fourth embodiment of the present invention. [Figure 17] Figure 17 is a graph showing the short-circuit current density Jsc (mA / cm2), open-circuit voltage VOC (V), curve factor FF, and conversion efficiency (%) of the solar cell fabricated in Reference Example 1. [Figure 18] Figure 18 is a graph showing the short-circuit current density Jsc (mA / cm2), open-circuit voltage VOC (V), curve factor FF, and conversion efficiency (%) of the solar cell (RJ structure) fabricated in Reference Example 2. [Figure 19] Figure 19 is a graph showing the short-circuit current density Jsc (mA / cm2), open-circuit voltage VOC (V), curve factor FF, and conversion efficiency (%) of the solar cell (FJ structure) fabricated in Reference Example 2. [Figure 20] Figures 20a to 20f show schematic structures of solar cells fabricated in Example 1 or Reference Example 1. [Figure 21] Figure 21 shows the results of STEM-HAADF, EDX, and compositional analysis of a portion of the first region of the crystalline silicon substrate of the solar cell fabricated in the example. [Figure 22]Figure 22 is a graph showing the short-circuit current density Jsc (mA / cm2), open-circuit voltage VOC (V), curve factor FF, and conversion efficiency (%) of the solar cells (FJ structure) fabricated in Example 1 and Reference Example 1. [Figure 23] Figure 23 is a graph showing the short-circuit current density Jsc (mA / cm2), open-circuit voltage VOC (V), curve factor FF, and conversion efficiency (%) of the solar cells (FJ structure) fabricated in Example 2 and Reference Example 1. [Modes for carrying out the invention]

[0020] Embodiments of the present invention will be described in detail below. In this specification, numerical ranges will include upper and lower limits.

[0021] The crystalline silicon solar cell of the present invention (hereinafter also simply referred to as "solar cell") comprises an n-type or p-type crystalline silicon layer and an amorphous semiconductor layer or passivation layer disposed adjacent to one main surface of the crystalline silicon layer, and optionally further comprises an electrode layer disposed on one main surface of the crystalline silicon layer. In this solar cell, an amorphous semiconductor layer or passivation layer may be disposed between the electrode layer and one main surface of the crystalline silicon layer, and the electrode layer and one main surface of the crystalline silicon layer may be in direct contact. Furthermore, in this solar cell, at least one side surface of the crystalline silicon layer has a first region covered by an amorphous semiconductor layer or passivation layer continuous from the first main surface side.

[0022] The following describes the structure and manufacturing method of the solar cell of the present invention based on four embodiments. However, the solar cell and manufacturing method of the present invention are not limited to these embodiments.

[0023] 1. First Embodiment Figure 3 shows a schematic cross-sectional view of the solar cell 100 of the first embodiment. The solar cell 100 of this embodiment is a silicon heterojunction (SHJ) type solar cell. The solar cell 100 includes an n-type or p-type crystalline silicon layer 110, a first amorphous semiconductor layer 120 disposed adjacent to the crystalline silicon layer 110 on one side (first main surface 111) of the crystalline silicon layer 110, a first electrode layer 130 disposed adjacent to the first amorphous semiconductor layer, a second amorphous semiconductor layer 140 disposed on the other side (second main surface 112) of the crystalline silicon layer 110, and a second electrode layer 150 disposed adjacent to the second amorphous semiconductor layer 140.

[0024] Furthermore, in the solar cell 100, the side surface 113 of the crystalline silicon layer 110 has a first region 113a that is covered by a first amorphous semiconductor layer 120 and a part of the first electrode layer 130 (first light-transmitting electrode layer 131). The first amorphous semiconductor layer 120 and the first light-transmitting electrode layer 131 are each arranged continuously from the first main surface 111 of the crystalline silicon layer 110 to the first region 113a. Here, "continuously" means that there is no intentional gap between the first amorphous semiconductor layer 120 and the first light-transmitting electrode layer 131 on the first main surface 111 of the crystalline silicon layer 110 and the first amorphous semiconductor layer 120 and the first light-transmitting electrode layer 131 on the first region 113a, and that they are formed as a single unit. Furthermore, the side surface 113 of the crystalline silicon layer 110 has a second region 113b located on the second main surface 112 side of the first region 113a, which is not covered by either the first amorphous semiconductor layer 120 or the first electrode layer 130. In this embodiment, light is incident on the solar cell 100 from the first main surface 111 side of the crystalline silicon layer 110.

[0025] In this embodiment, the reason why the side surface 113 of the crystalline silicon layer 110 has a first region 113a covered by the first amorphous semiconductor layer 120 and the first translucent electrode layer 131 lies in its manufacturing method. As will be explained in detail in the manufacturing method described later, in the manufacturing method of the solar cell 100 of this embodiment, a groove for division is formed in advance on the crystalline silicon substrate, and the processed and altered layer is removed from the groove by etching. After that, the necessary layers (first amorphous semiconductor layer 120, first electrode layer 130, etc.) are formed on the crystalline silicon substrate, and the crystalline silicon substrate is cut along the groove. In the manufacturing method of the solar cell 100 of this embodiment, since the first amorphous semiconductor layer 120, etc. are formed after the groove is formed, the first amorphous semiconductor layer 120, etc., which is continuous from the first main surface 111 side, is arranged on the first region 113a corresponding to the wall surface of the groove.

[0026] In this embodiment, the solar cell 100 manufactured by the above manufacturing method does not contain a processed and altered layer on the end face of the solar cell 100. Therefore, the solar cell 100 of this embodiment has better power generation performance compared to solar cells divided by conventional methods. Furthermore, in the solar cell 100, the first amorphous semiconductor layer 120 and the first translucent electrode layer 131 arranged on the first region 113a function as passivation films. From this point of view as well, the solar cell 100 of this embodiment has good power generation performance.

[0027] The following describes the various components of the solar cell 100 in this embodiment.

[0028] (Solar cell configuration) • Crystalline silicon layer The crystalline silicon layer 110 is an n-type or p-type crystalline silicon layer having a first main surface 111 and a second main surface 112. The crystalline silicon layer 110 may be an n-type crystalline silicon layer obtained by introducing n-type impurities such as phosphorus (P) into single-crystal silicon, or it may be a p-type crystalline silicon layer obtained by introducing p-type impurities such as boron (B) or gallium (Ga) into single-crystal silicon. In this embodiment, the crystalline silicon layer 110 is an n-type crystalline silicon layer.

[0029] The shape of the crystalline silicon layer 110 is appropriately selected according to the desired shape and performance of the solar cell 100. As described above, the solar cell 100 of this embodiment is manufactured by the SC method. Therefore, the planar shape of the crystalline silicon layer 110 can be any shape. Examples of the planar shape of the crystalline silicon layer 110 include various shapes such as rectangles, parallelograms, and polygons with arbitrary aspect ratios. The thickness of the crystalline silicon layer 110 is not particularly limited and can be, for example, about 50 μm to 300 μm. The resistance value of the crystalline silicon layer 110 is appropriately selected, but is usually preferably about 0.1 to 10 Ω.

[0030] Here, the first main surface 111 and the second main surface 112 of the crystalline silicon layer 110 may each be a flat surface consisting of a (100) plane of crystalline silicon, or they may be surfaces having a random texture structure with (111) faceted surfaces of crystalline silicon. In this embodiment, both the first main surface 111 and the second main surface 112 are surfaces having a random texture structure. When the first main surface 111 and the second main surface 112 of the crystalline silicon layer 110 have a random texture structure, the power generation efficiency of the solar cell 100 is further improved by the reflection reduction effect and light confinement effect caused by this structure.

[0031] Furthermore, as described above, the side surface 113 of the crystalline silicon layer 110 has a first region 113a covered by the first amorphous semiconductor layer 120 and the first translucent electrode layer 131, and a second region 113b not covered by these. Here, the first region 113a and the second region 113b of the crystalline silicon layer 110 differ not only in whether or not they are covered by the first amorphous semiconductor layer 120, but also in their surface state. As described above, the first region 113a is an etched surface after groove formation by scribing or the like. The surface of the first region 113a also differs depending on the crystal orientation, but for example, it can be a surface with a structure where the (111) plane of crystalline silicon is dominant. Also, depending on the crystal orientation, the surface of the first region 113a may have a pyramidal texture structure in part or on its entire surface. On the other hand, the second region 113b is a plane obtained by cleavage (crystal cleavage), and is composed of, for example, the (110) plane or (111) plane of crystalline silicon.

[0032] Here, the first region 113a and the second region 113b may lie on the same plane, but usually, as shown in Figure 3, the angle between the first region 113a and the second region 113b (the angle indicated by α in Figure 3) is often less than 180°. The angle α between the first region 113a and the second region 113b is appropriately selected depending on the angle of the scribe forming the first region 113a, the amount of etching, etc., but is usually preferably between 130° and 175°, and more preferably between 140° and 170°. When the angle α between the first region 113a and the second region 113b is 175° or less, and especially 170° or less, the inclination of the first region 113a becomes appropriate. As a result, during the manufacturing of the solar cell 100, the first region 113a is more easily covered by the first amorphous semiconductor layer 120 and the first translucent electrode layer 131. On the other hand, if the angle α is 130° or greater, especially 140° or greater, the difference between the area of ​​the first main surface 111 and the area of ​​the second main surface 112 of the crystalline silicon layer 110 does not become large, and the performance of the solar cell 100 tends to be even better. The angle α is the angle formed by the approximate straight lines drawn along the first region 113a and the second region 113b, respectively, when a cross-sectional observation of the solar cell 100 is performed.

[0033] The ratio of the area of ​​the first region 113a to the area of ​​the second region 113b on one side surface 113 of the crystalline silicon layer 110 is not particularly limited. However, the ratio of the area of ​​the first region 113a to the total area (overall area) of the side surface 113 is preferably 1 / 5 or more, and more preferably 1 / 3 or more and 2 / 3 or less. This ratio also correlates with the depth of the groove formed during manufacturing. When the groove is formed during manufacturing so that the area of ​​the first region 113a is above a certain level, the depth of the groove becomes appropriately deep. Therefore, it becomes possible to cleave without applying excessive force. In addition, if the area of ​​the first region 113a is large, the area covered by the first amorphous semiconductor layer 120, etc. becomes sufficiently large, and the performance of the solar cell 100 tends to be even better.

[0034] • First amorphous semiconductor layer (amorphous silicon layer) The first amorphous semiconductor layer 120 is a layer containing an amorphous semiconductor, which is arranged to cover the first main surface 111 of the crystalline silicon layer 110 and the first region 113a of the side surface 113 of the crystalline silicon layer 110. In this embodiment, it is a layer containing amorphous silicon.

[0035] In this embodiment, the first amorphous semiconductor layer 120 is composed of a hydrogen-doped intrinsic amorphous silicon (i-type a-Si:H) layer 121 and a p-type amorphous silicon (p-type a-Si:H) layer 122. These layers are similar to the i-type a-Si:H layer and p-type a-Si:H layer of a known SHJ-type solar cell. However, the first amorphous semiconductor layer 120 is not limited to the combination of the i-type a-Si:H layer 121 and the p-type a-Si:H layer 122. In the following description, the i-type a-Si:H layer 121 and the p-type a-Si:H layer 122 will be described as examples, but these can be appropriately modified without impairing the purpose and effects of this embodiment. For example, the i-type layer 121 may be an i-type layer containing intrinsic amorphous silicon doped not only with hydrogen but also with trace amounts of carbon atoms (C) and trace amounts of oxygen atoms (C). Furthermore, the p-type layer 122 may be a p-type microcrystalline silicon layer or the like.

[0036] The thickness of the i-type a-Si:H layer 121 may be the same or different on the first main surface 111 of the crystalline silicon layer 110 and on the first region 113a of the side surface 113. The thickness of the i-type a-Si:H layer 121 can be, for example, between 2 nm and 10 nm. Similarly, the thickness of the p-type a-Si:H layer 122 may be the same or different on the first main surface 111 of the crystalline silicon layer 110 and on the first region 113a of the side surface 113. The thickness of the p-type a-Si:H layer 122 can be, for example, between 2 nm and 20 nm.

[0037] ·First electrode layer (first transparent electrode layer and first metal electrode) The first electrode layer 130 is the electrode layer on the light incident surface side of the solar cell 100. In this embodiment, it consists of a first translucent electrode layer 131 arranged to cover the first amorphous semiconductor layer 120, and a grid-shaped first metal electrode 132 arranged on the first translucent electrode layer 131. In this embodiment, the first translucent electrode layer 131 is arranged not only on the first main surface 111 of the crystalline silicon layer 110, but also on the first region 113a of the side surface 113 of the crystalline silicon layer 110.

[0038] The first translucent electrode layer 131 can be any electrode layer that is translucent to visible light and conductive. The material of the first translucent electrode layer 131 is not particularly limited and includes indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), etc. The thickness of the first translucent electrode layer 131 may be the same or different on the first main surface 111 of the crystalline silicon layer 110 and on the first region 113a of the side surface 113. The thickness of the first translucent electrode layer 131 can usually be about 70 nm to 150 nm.

[0039] On the other hand, the first metal electrode 132 can be any electrode layer containing metal arranged in a pattern that does not obstruct the incidence of light. Examples of metal materials that constitute the first metal electrode 132 include metals such as aluminum (Al), titanium (Ti), silver (Ag), copper (Cu), nickel (Ni), and gold (Au), as well as alloys thereof. The thickness of the first metal electrode 132 is appropriately selected based on the type of material that constitutes the first metal electrode 132 and the shape of the first metal electrode 132, but is usually preferably 100 nm to 10000 nm.

[0040] • Second amorphous semiconductor layer The second amorphous semiconductor layer 140 is a layer containing an amorphous semiconductor, arranged to cover the second main surface 112 of the crystalline silicon layer 110, and in this embodiment, it is a layer containing amorphous silicon. The second amorphous semiconductor layer 140 in this embodiment is composed of a hydrogen-doped intrinsic amorphous silicon (i-type a-Si:H) layer 141 and an n-type amorphous silicon (n-type a-Si:H) layer 142. These are the same as the i-type a-Si:H layer and n-type a-Si:H layer of a known SHJ-type solar cell. However, the second amorphous semiconductor layer 140 is not limited to the combination of the i-type a-Si:H layer 141 and the n-type a-Si:H layer 142, and can be appropriately modified within a range that does not impair the purpose and effect of this embodiment. For example, the i-type layer 141 may be an i-type layer containing intrinsic amorphous silicon doped not only with hydrogen but also with trace amounts of carbon atoms (C) and trace amounts of oxygen atoms (C). Furthermore, the n-type layer 142 may be an n-type microcrystalline silicon layer or the like.

[0041] The thickness of the i-type a-Si:H layer 141 is not particularly limited, but is usually preferably between 2 nm and 10 nm. Similarly, the thickness of the n-type a-Si:H layer 142 is not particularly limited, but is usually preferably between 2 nm and 20 nm.

[0042] ·Second electrode layer (second transparent electrode layer and second metal electrode) The second electrode layer 150 is an electrode layer located on the back side of the solar cell 100, and in this embodiment, it consists of a second translucent electrode layer 151 and a second metal electrode 152. The second translucent electrode layer 151 is arranged to cover the second amorphous semiconductor layer 140. The material and thickness of the second translucent electrode layer 151 are the same as those of the first translucent electrode layer 131.

[0043] The second metal electrode 152 may be any electrode layer containing metal that is placed on the second translucent electrode layer 151. In this embodiment, the second metal electrode 152 is arranged in a pattern, but the second metal electrode 152 may be placed on the entire back side so as to cover the second translucent electrode layer 151. The material and thickness of the second metal electrode 152 are the same as those of the first metal electrode 132.

[0044] (Method for manufacturing solar cells according to this embodiment) The manufacturing method for the solar cell 100 described above will be explained below. Components similar to those described above will be denoted by the same reference numerals, and detailed explanations will be omitted.

[0045] Figure 4 shows the flow chart of the manufacturing method for the solar cell of this embodiment, and Figures 5A to 5F show the process diagrams. In this manufacturing method, as shown in Figure 5A, an n-type or p-type crystalline silicon substrate 117 having a first main surface 111 and a second main surface 112 which is the back surface of the first main surface 111 is prepared (substrate preparation step (S1)). Then, grooves 115 are formed at desired positions on the first main surface 111 of the crystalline silicon substrate 117 (groove formation step (S2), Figure 5B). Subsequently, as shown in Figure 5C, the silicon substrate with the grooves 115 formed is etched to remove the processed altered layer 116 and impurities (not shown) that have formed in the grooves 115 (etching step (S3)). Subsequently, a texture structure is formed on the first main surface 111 and the second main surface 112 of the crystalline silicon substrate 117 as needed (texture structure formation step (S4), Figure 5D). Note that the etching step (S3) and the texture structure formation step (S4) may be performed simultaneously.

[0046] Subsequently, a first amorphous semiconductor layer 120 and a second amorphous semiconductor layer 140 are formed on the first main surface 111 and the second main surface 112 of the crystalline silicon substrate 117, respectively (amorphous semiconductor layer formation step (S5), Figure 5E). Furthermore, a first electrode layer 130 and a second electrode layer 150 are formed (electrode layer formation step (S6), Figure 5E). Then, the crystalline silicon substrate 117 is cut along the groove 115 to obtain a solar cell 100 of the desired size (cutting step (S7), Figure 5F). Note that the manufacturing method of the solar cell 100 in this embodiment may further include steps other than those described above.

[0047] For reference, Figure 6A shows an SEM image of the grooves after the groove formation process (S2) and etching process (S3) have been performed on the crystalline silicon substrate. Figure 6B shows an SEM image of the surface created after the crystalline silicon substrate has been cut along the grooves. As shown in Figure 6A, the groove walls after the etching process (S3) are much smoother than before etching, and there is a significant difference compared to the SEM image after scribing shown in Figure 2A above. This indicates that the processed altered layer created by groove formation has been removed. Furthermore, from Figure 6B, it is clear that the region corresponding to the first region 113a (etched region) of the crystalline silicon layer 110 of the solar cell 100 described above has a smooth surface and does not contain a processed altered layer.

[0048] As described above, in the method of this embodiment, the solar cell 100 is manufactured by the SC method, but the end face of the solar cell 100 does not include a processing-induced alteration region. Therefore, according to this embodiment, it is possible to manufacture solar cells of any shape with good power generation performance. The following describes in detail each step of the manufacturing method of the solar cell 100 according to this embodiment.

[0049] ·Substrate preparation process (S1) In the substrate preparation step (S1), an n-type crystalline silicon substrate or a p-type crystalline silicon substrate (in this embodiment, an n-type crystalline silicon substrate) 117 having a first main surface 111 and a second main surface 112 which is the back surface of the first main surface is prepared.

[0050] The size (planar shape) and thickness of the crystalline silicon substrate 117 to be prepared are appropriately selected according to the desired size of the solar cell, the number of solar cells to be manufactured, and the desired thickness. For example, the crystalline silicon substrate 117 may be sized to manufacture only one solar cell 100, but it is preferable from the viewpoint of solar cell manufacturing efficiency if it is sized to manufacture multiple solar cells 100.

[0051] ·Groove formation process (S2) In the groove formation process (S2), grooves 115 are formed on the first main surface 111 of the crystalline silicon substrate 117 to match the desired size of the solar cell 100. The orientation and length of the grooves 115 formed on the crystalline silicon substrate 117 are appropriately selected to match the desired shape of the solar cell 100. For example, as shown in the plan view of Figure 7A, multiple grooves 115 parallel to each other may be formed on a single crystalline silicon substrate 117 to manufacture a strip-shaped solar cell 100. At this time, the crystalline silicon substrate 117 <110> When grooves 115 are formed in a certain direction, the sides of the grooves 115 tend to become smoother, but the direction is not limited to this. In a solar cell 100 obtained by forming grooves 115 in this way, one side surface 113 or two side surfaces 113 of the crystalline silicon layer 110 have the first region 113a and the second region 113b described above. On the other hand, as shown in the plan view of Figure 7B, grooves 115 may be formed in multiple directions on a single crystalline silicon substrate 117. In a solar cell 100 obtained by forming grooves 115 in this way, two to four side surfaces 113 of the crystalline silicon layer 110 have the first region 113a and the second region 113b described above.

[0052] The depth of the groove 115 formed in this process should be such that the crystalline silicon substrate 117 can be cut without applying excessive force in the subsequent cutting process (S7). The depth of the groove 115 is preferably 1 / 3 or more of the thickness of the crystalline silicon substrate 117, and more preferably 1 / 2 or more. On the other hand, if the depth of the groove 115 is excessively deep, the strength of the crystalline silicon substrate 117 will decrease, so it is preferable that the depth of the groove 115 be 2 / 3 or less of the thickness of the crystalline silicon substrate 117.

[0053] Furthermore, the cross-sectional shape of the groove 115 in the depth direction is not particularly limited, and it is sufficient if it is a shape that allows the etching solution in the etching process (S3) described later to enter.

[0054] The method for forming grooves in the crystalline silicon substrate 117 is not particularly limited. For example, grooves 115 may be formed by laser scribing, or they may be formed using a rotary blade, wire saw, or the like.

[0055] • Etching process (S3) In the etching process (S3), the crystalline silicon substrate 117 is etched to remove the processed altered layer 116 and impurities formed in the grooves 115. The etching method is not particularly limited and can be the same as known etching methods for crystalline silicon substrates. Examples include wet etching using an etching solution containing KOH or NaOH, isotropic wet etching using nitrate hydrofluoric acid, and wet etching using an aqueous solution of tetramethylammonium hydroxide.

[0056] When etching is performed using the above etching solution, the temperature should be appropriately selected depending on the type of etching solution, but when using an etching solution containing KOH, it is preferable to set the temperature between 60°C and 90°C. The immersion time can be appropriately adjusted according to the condition of the groove 115, but when using an etching solution containing KOH, it can usually be set between 2 minutes and 30 minutes. With such a time, the processed altered layer 116 is easily removed sufficiently.

[0057] The shape of the groove 115 in the etching process (S4) is not particularly limited, but a V-shape is one example of a preferred shape. When the groove 115 is V-shaped, amorphous silicon can easily penetrate into the groove in the amorphous silicon layer formation process (S5) described later, and an amorphous silicon layer of the desired thickness can be easily formed on the groove wall (the first region 113a described above).

[0058] • Texture structure formation process (S4) In the texture structure formation process, a texture structure is formed on the first main surface 111 and the second main surface 112 of the crystalline silicon substrate 117 after the etching process (S3). However, if both the first main surface 111 and the second main surface 112 of the crystalline silicon layer 110 are to be flat in the desired solar cell 100, the texture structure formation process (S4) does not need to be performed.

[0059] Furthermore, in this embodiment, a texture structure is formed on both the first main surface 111 and the second main surface 112 of the crystalline silicon substrate 117, but the texture structure may be formed on only one surface. Also, the texture structure formation step (S4) can be performed simultaneously with the etching step (S3).

[0060] One method for forming a textured structure on both the first main surface 111 and the second main surface 112 of the crystalline silicon substrate 117 is to immerse the crystalline silicon substrate 117 in an anisotropic etching solution (for example, an etching solution containing KOH and known additives). The temperature of the etching solution and the etching time are not particularly limited and can be adjusted as appropriate according to the surface condition of the crystalline silicon substrate 117.

[0061] Furthermore, when forming a textured structure on only one main surface of the crystalline silicon substrate 117, a protective film of a desired thickness, such as a silicon nitride layer (SiN), is applied to the other main surface. x A layer is formed using plasma-assisted chemical vapor deposition (plasma CVD) or the like to protect the surface. Then, a textured structure is formed on one surface using the above method, and subsequently, the silicon nitride layer can be removed with dilute hydrofluoric acid. Alternatively, a random textured structure can be formed on both sides of the crystalline silicon substrate 117, and then one surface can be flattened by etching.

[0062] • Amorphous semiconductor layer formation process (S5) In the amorphous semiconductor layer formation step (S5) of this embodiment, a hydrogen-doped intrinsic amorphous silicon (i-type a-Si:H) layer 121 and a p-type amorphous silicon (p-type a-Si:H) layer 122 are formed on the first main surface 111 side of the crystalline silicon substrate 117. Furthermore, a hydrogen-doped intrinsic amorphous silicon (i-type a-Si:H) layer 141 and an n-type amorphous silicon (n-type a-Si:H) layer 142 are formed on the second main surface 112 side. The method for forming each layer is not particularly limited and can be, for example, by plasma CVD.

[0063] In this embodiment, when forming the i-type a-Si:H layer 121 or p-type a-Si:H layer on the first main surface 111 side of the crystalline silicon substrate 117, the i-type a-Si:H layer 121 or p-type a-Si:H layer 122 is also formed within the groove 115. However, no special work is required at this time. For example, if the i-type a-Si:H layer 121 or p-type a-Si:H layer 122 is formed on the entire first main surface 111 of the crystalline silicon substrate 117, the i-type a-Si:H layer 121 or p-type a-Si:H layer 122 will naturally be formed within the groove 115.

[0064] ·Electrode layer formation process (S6) In the electrode layer formation step (S6), a first electrode layer 130 (a first translucent electrode layer 131 and a first metal electrode 132) is formed on the first main surface 111 side of the crystalline silicon substrate 117 by a known method. A second electrode layer 150 (a second translucent electrode layer 151 and a second metal electrode 152) is formed on the second main surface 112 side of the crystalline silicon substrate 117 by a known method. These formation methods are not particularly limited and may include, for example, screen printing, sputtering, vapor deposition, plating, etc.

[0065] In this embodiment, the first translucent electrode layer 131 is also formed within the groove 115 described above. No special work is required; if the first translucent electrode layer 131 is formed on the entire first main surface 111 of the crystalline silicon substrate 117, the first translucent electrode layer 131 will naturally be formed within the groove 115.

[0066] In this embodiment, the first amorphous semiconductor layer 120 and the second amorphous semiconductor layer 140 are formed on the crystalline silicon substrate 117, and then the first electrode layer 130 and the second electrode layer 150 are formed. However, the amorphous semiconductor layer formation process (S5) and the electrode layer formation process (S6) may be performed alternately. For example, the layers may be formed in the order of the first amorphous semiconductor layer 120, the first electrode layer 130, the second amorphous semiconductor layer 140, and the second electrode layer 150.

[0067] Furthermore, after forming the first electrode layer 130 and the second electrode layer 150, they may be annealed in an oven or the like if necessary.

[0068] ·Cutting process (S7) In the cleavage step (S7), the crystalline silicon substrate 117 is cleaved along the groove 115. The cleavage method is not particularly limited; for example, a method of applying a load around the groove 115 and folding it open can be used. This yields the desired solar cell 10.

[0069] (Modified version of the first embodiment) The above explanation used the case where the crystalline silicon layer 110 is an n-type crystalline silicon layer as an example. However, a similar configuration can be used even if the crystalline silicon layer 110 is a p-type crystalline silicon layer.

[0070] Furthermore, although the above explanation described the case where the pn junction surface is on the light incident surface side (the first main surface 111 side of the crystalline silicon layer 110), the same effect can be obtained when the pn junction surface is on the back side (the second main surface 112 side of the crystalline silicon layer 110). Since the solar cell 100 of this embodiment does not include a processed altered layer at the end face, its power generation performance can be improved in both cases, whether the pn junction surface is on the back side or the light incident surface side.

[0071] Furthermore, although the first main surface 111 of the crystalline silicon layer 110 was described as the light incident surface in the above explanation, the first main surface 111 of the crystalline silicon layer 110 may also be placed on the back side. In this case as well, the same effects as described above can be obtained.

[0072] Furthermore, the above description illustrates an embodiment in which the first region 113a of the side surface 113 of the crystalline silicon layer 110 is covered by the first amorphous semiconductor layer 120 and the first translucent electrode layer 131. However, it is not necessary for all of these layers to cover the first region 113a. For example, only one of the i-type a-Si:H layer 121 or the p-type a-Si:H layer 122 of the first amorphous semiconductor layer 120 may cover the first region 113a. In this case, either layer can be patterned using a known method.

[0073] Figure 8 shows a schematic cross-sectional view of a solar cell 101, which is a modified example of the solar cell 100 of the first embodiment. The modified solar cell 101 has the same structure as the solar cell 100 described above, except that the shape of the first light-transmitting electrode layer 135 is different. The same reference numerals are used for components identical to those described above, and detailed explanations are omitted.

[0074] As shown in Figure 8, in the solar cell 101, the first electrode layer 130 (first translucent electrode layer 135 and first metal electrode 132) is arranged only on the first main surface 111 of the crystalline silicon layer 110, and the first electrode layer 130 (first translucent electrode layer 135 and first metal electrode 132) is not arranged on the first region 113a of the crystalline silicon layer 110. Furthermore, when the solar cell 101 is viewed from above, the outer circumference of the first electrode layer 130 (especially the first translucent electrode layer 135) is positioned inward from the outer circumference of the first main surface 111 of the crystalline silicon layer 110. Furthermore, when viewing the solar cell 101 from above, it is preferable to adjust the first electrode layer 130 (especially the first translucent electrode layer 135) so that its edge (outer circumference) is located 0.1 mm to 2 mm inward from the edge (outer circumference) of the first main surface 111 of the crystalline silicon layer 110, and it is more preferable to adjust it so that it is located 0.3 mm to 7 mm inward.

[0075] As demonstrated in the later embodiment, arranging the first electrode layer 130 in this manner further improves the power generation performance of the solar cell 101. The reason for this is thought to be as follows: In the solar cell 100 described above, although the processed and altered layer is not included on the end face of the solar cell 100, it is difficult to completely suppress the generation of defects on the end face of the solar cell 100. Therefore, some decrease in power generation performance may occur on the end face side of the solar cell 100. However, as in this modified example, if a conductive film (first translucent conductive film) is not formed on the first region 113a, leakage current through defects remaining on the end face side of the solar cell 101 can be suppressed. As a result, recombination on the end face side becomes less likely, and the performance of the solar cell 101 is thought to improve.

[0076] In this modified example, the first translucent electrode layer 135 and the first metal electrode 132 can be formed by depositing a film in a patterned manner during the electrode layer formation step (S6) described above.

[0077] Figure 9 also shows a schematic cross-sectional view of a solar cell 102, which is yet another modification of the solar cell 100 of the first embodiment. The solar cell 102 of this modification has the same structure as the solar cell 100 of the first embodiment, except that the second region 113b of the crystalline silicon layer 110 is covered by a defect termination layer 160. The same reference numerals are used for the same components as described above, and detailed explanations are omitted.

[0078] In the solar cell 102, the second region 113b of the side surface 113 of the crystalline silicon layer 110 is covered by the defect termination layer 160. Therefore, the crystalline silicon layer 110 is not exposed, and the power generation performance of the solar cell 102 can be further improved. The material constituting the defect termination layer 160 is not particularly limited. For example, it can be a layer made of aluminum oxide (Al2O3), titanium oxide (TiO2), silicon oxide (SiO2), or silicon nitride (SiN). The thickness of the defect termination layer 160 is not particularly limited, but for example, it can be 5 nm or more and 50 nm or less. In this modified example, the defect termination layer 160 covers only the second region 113b and its vicinity, but the defect termination layer 160 may be arranged to cover the first amorphous semiconductor layer 120, the first electrode layer 130, the second amorphous semiconductor layer 140, the second electrode layer 150, etc.

[0079] The defective termination layer 160 can be formed by forming a film using a known method after the cleavage formation step (S7) of the solar cell manufacturing method described above.

[0080] 2. Second Embodiment Figure 10 shows a schematic cross-sectional view of a solar cell 200 according to the second embodiment. The solar cell 200 of this embodiment is a PERC (Passivated Emitter and Rear Cell) type solar cell. The solar cell 200 has n on the first main surface 211 side + A p-type crystalline silicon layer 210 including a diffusion layer 210n, a first passivation layer (here, a silicon nitride (SiNx) layer) 220 disposed adjacent to the crystalline silicon layer 210 on one side of the crystalline silicon layer 210 (first main surface 211), and an n + The structure includes a first electrode layer 230 electrically connected to the diffusion layer 210n, a second passivation layer 240 disposed on the other side (second main surface 212) of the crystalline silicon layer 210, and a second electrode layer 250 electrically connected to the crystalline silicon layer 210.

[0081] Furthermore, in the solar cell 200, the side surface 213 of the crystalline silicon layer 210 has a first region 213a covered by a first passivation layer 220. The first passivation layer 220 is continuously arranged from the first main surface 211 of the crystalline silicon layer 210 to the first region 213a. Here, "continuously" means that the first passivation layer 220 on the first main surface 211 and the first passivation layer 220 on the first region 213a are arranged as a single unit without any intentional gaps. Note that the first region 213a contains n + A diffusion layer 210n is also formed. On the other hand, the side surface 213 of the solar cell 200 further has a second region 213b on the second main surface 212 side of the first region 213a that is not covered by either the first passivation layer 220 or the first electrode layer 230. In this second region 213b, n + No diffusion layer 210n is formed. In this embodiment, the first main surface 211 side of the crystalline silicon layer 210 is the light incident surface, and the second main surface 212 side is the back surface.

[0082] In this embodiment, the side surface 213 of the crystalline silicon layer 210 is n + The reason why it has a diffusion layer 210n and a first region 213a covered by a first passivation layer 220 is also due to its manufacturing method. In the manufacturing method of the solar cell 200 of this embodiment, a dividing groove is formed in advance on the crystalline silicon substrate, and the groove is cleaned by etching. After that, n + A diffusion layer 210n is formed, or necessary layers (e.g., a first passivation layer 220 or a first electrode layer 230) are formed on the crystalline silicon substrate. Then, the crystalline silicon substrate is cut along the groove. Therefore, n + A portion of the side surface 213 (first region 213a) of the crystalline silicon layer 210 on which the diffusion layer 210n is formed is covered by the first passivation layer 220 which is continuous from the main surface side.

[0083] Similar to the first embodiment, the end face of the solar cell 200 in this embodiment does not include a processed and deteriorated layer. Therefore, the solar cell 200 can exhibit good power generation performance as compared with a solar cell divided by a known division method. Further, in the solar cell 200, the first passivation layer 220 disposed on the first region 213a functions as a passivation film. Also in this regard, the solar cell 200 in this embodiment has good power generation performance.

[0084] Hereinafter, each component of the solar cell 200 in this embodiment will be described.

[0085] (Configuration of solar cell) · Crystalline silicon layer The crystalline silicon layer 210 is a p-type crystalline silicon layer having a first main surface 211 and a second main surface 212. The crystalline silicon layer 210 is p-type and has an n + diffusion layer 210n on the first main surface 211 side. Except for including the diffusion layer 210n, it is the same as the crystalline silicon layer 110 of the first embodiment, and the shape of the side surface 213 is also the same. In this embodiment, both the first main surface 211 and the second main surface 212 of the crystalline silicon layer 210 have a random texture structure, but either one or both of them may be flat.

[0086] n + The diffusion layer 210n is a layer made of an n-type semiconductor, and the + means a high concentration. The n + diffusion layer 210n is a layer formed by thermally diffusing an n-type dopant such as phosphorus on the first main surface 211 side of the crystalline silicon layer 210. In this embodiment, the diffusion layer 210n is also formed in the first region 213a of the side surface 213 of the crystalline silicon layer 210. + The amount of the n-type dopant is preferably 10 18 ~10 20 cm 3 .

[0087] Note that, on the second main surface 212 side of the crystalline silicon layer 210, if necessary, p obtained by diffusing boron or gallium+ It may further have a diffusion layer (not shown).

[0088] • First passivation layer (silicon nitride layer) The first passivation layer 220 is n + This layer is arranged to cover the first main surface 211 of the crystalline silicon layer 210 on which the diffusion layer 210n is formed, and the first region 213a of the side surface 213 of the crystalline silicon layer 210, and in this embodiment, it is a layer containing silicon nitride. However, it is not limited to a silicon nitride layer, and may be a layer made of silicon oxide, aluminum oxide, or a composite thereof, or it may be a laminate. The first passivation layer 220 is similar to the passivation layer of a known PERC type solar cell.

[0089] The thickness of the first passivation layer 220 may be the same or different on the first main surface 211 of the crystalline silicon layer 210 and on the first region 213a of the side surface 213. The thickness of the first passivation layer 220 can be, for example, 60 nm to 100 nm.

[0090] ·1st electrode layer The first electrode layer 230 is located on the first main surface 211 of the crystalline silicon layer 210, penetrates the first passivation layer 220, and the above n + Any electrode layer that is electrically connected to the diffusion layer 210n is acceptable, and it can be a grid-like electrode layer made of silver.

[0091] ·Second passive layer The second passivation layer 240 can be any layer that covers the second main surface 212 of the crystalline silicon layer 210, and in this embodiment, it is composed of a laminate of an aluminum oxide layer and a silicon nitride layer. Each layer constituting the second passivation layer 240 can be the same as the aluminum oxide layer and silicon nitride layer of a known PERC type solar cell, and its thickness is not particularly limited. The second passivation layer 240 may also be a layer other than an aluminum oxide layer or a silicon nitride layer.

[0092] ·Second electrode layer The second electrode layer 250 can be any electrode layer electrically connected to the crystalline silicon layer 210. The second electrode layer 250 can be an electrode layer made of aluminum or the like. The shape and thickness of the second electrode layer 250 can be the same as that of the second electrode layer of a known PERC type solar cell.

[0093] (Method for manufacturing solar cells according to this embodiment) The manufacturing method for the solar cells described above will be explained below. Components similar to those described above will be denoted by the same reference numerals, and detailed explanations will be omitted.

[0094] Figures 11A to 11F show the process diagrams for the manufacturing method of the solar cell of this embodiment. In this manufacturing method, as shown in Figure 11A, a p-type crystalline silicon substrate 217 having a first main surface 211 and a second main surface 212 which is the back surface of the substrate is prepared (substrate preparation step). Then, as shown in Figure 11B, grooves 215 are formed at desired positions on the first main surface 211 of the crystalline silicon substrate 217 (groove formation step). Subsequently, the silicon substrate with the grooves 215 is etched to remove the processed altered layer 216 and impurities (not shown) that have formed in the grooves 215 (etching step, Figure 11C). Subsequently, a texture structure is formed on the first main surface 211 and the second main surface 212 of the crystalline silicon substrate 117 as needed (texture structure formation step, Figure 11D).

[0095] Furthermore, on the first main surface 211 side of the crystalline silicon substrate 217, n + A diffusion layer 217n is formed. Furthermore, a first passivation layer 220, a first electrode layer 230, a second passivation layer 240, and a second electrode layer 250 are formed (Figure 11E). Note that the above n + The method for forming the diffusion layer 217n, and the methods for forming the first passivation layer 220, the first electrode layer 230, the second passivation layer 240, the second electrode layer 250, etc., can be the same as the methods for forming each layer of a known PERC type solar cell. In this embodiment as well, the entire surface of the first main surface 211 side of the crystalline silicon substrate 217 is covered with n +By forming the diffusion layer 217n or the first passivation layer 220, n can be formed on the first region 213a of the crystalline silicon layer 210 without any special process. + It is possible to form a diffusion layer 210n and a first passivation layer 220. Thereafter, the crystalline silicon substrate 217 is cut along the groove 215 to obtain a solar cell 200 of the desired size (cutting step, Figure 11F). Note that the manufacturing method of the solar cell 200 in this embodiment may further include steps other than those described above.

[0096] Thus, in the method of this embodiment, the solar cell 200 is manufactured by the SC method, but the end face of the solar cell 200 does not include a processed and altered region. Therefore, according to this embodiment, it is possible to manufacture solar cells of any shape with good power generation performance. The substrate preparation step, groove formation step, etching step, texture structure formation step, and cleavage step of the manufacturing method of the solar cell 200 in this embodiment are the same as those of the first embodiment described above.

[0097] (Modified version of the second embodiment) In the solar cell 200 shown in Figure 10, the second region 213b of the crystalline silicon layer 210 is exposed. However, a defect termination layer may be further arranged to cover the second region 213b. Furthermore, the solar cell 200 of this embodiment may include other layers as needed.

[0098] Furthermore, in the above, n is located on the first main surface 211 side of the crystalline silicon layer 210. + A configuration in which a diffusion layer 210n, a first passivation layer 220, a first electrode layer 230, etc. are arranged was described. However, on the second main surface 212 side of the crystalline silicon layer 210, n + A diffusion layer 210n or a first passivation layer 220 may be placed. In this case, a second passivation layer 240 or a second electrode layer 250 is placed on the first main surface 211 side of the crystalline silicon layer 210. In this case, the second main surface 212 side (n + The side on which the diffusion layer 210n is located is the light incident surface, and the side on which the first main surface 211 is located is the back surface.

[0099] 3. Third Embodiment Figure 12 shows a schematic cross-sectional view of a solar cell 300 according to the third embodiment. The solar cell 300 of this embodiment is a TOPCon (Tunnel Oxide Passivated Contacts) type solar cell. The solar cell 300 has a p-type dopant that is thermally diffused on the first main surface 311 side. + An n-type crystalline silicon layer 310 having a diffusion layer 310p, a passivation layer (here, a silicon nitride (SiNx) layer) 320 disposed adjacent to the crystalline silicon layer 310 on one side of the crystalline silicon layer 310 (first main surface 311), and a layer disposed on one side of the crystalline silicon layer 310 (first main surface 311), and p + A first electrode layer 330 electrically connected to the diffusion layer 310p, a silicon oxide (SiOx) layer 341 disposed on the other side (second main surface 312) of the crystalline silicon layer 310, and n disposed on the silicon oxide layer 341. + Polysilicon layer 342 and n + It has a second electrode layer 350 arranged adjacent to the polysilicon layer 342.

[0100] In the solar cell 300, the side surface 313 of the crystalline silicon layer 310 has a first region 313a covered by a passivation layer 320. The passivation layer 320 is continuously arranged from the first main surface 311 of the crystalline silicon layer 310 to the first region 313a. Here, "continuously" means that the passivation layer 320 on the first main surface 311 and the passivation layer 320 on the first region 313a are arranged as a single unit without any intentional gaps. In addition, the first region 313a contains p + A diffusion layer 310p is also formed. On the other hand, the side surface 313 of the crystalline silicon layer 310 further has a second region 313b on the second main surface 312 side from the first region 313a that is not covered by either the passivation layer 320 or the first electrode layer 330. In this second region 313b, p + The diffusion layer 310p is also not formed. In this embodiment, the first main surface 311 side of the crystalline silicon layer 310 is the light incident surface, and the second main surface 312 side is the back surface.

[0101] In this embodiment, the reason why the side surface 313 of the crystalline silicon layer 310 has a first region 313a that has a p+ diffusion layer 310p and is covered by a passivation layer 320 lies in the manufacturing method. In the manufacturing method of the solar cell 300 of this embodiment, a dividing groove is formed in the crystalline silicon substrate in advance, and the groove is cleaned by etching. After that, p + A diffusion layer 310p is formed, and other necessary layers (such as a passivation layer 320 or a first electrode layer 330) are formed on the crystalline silicon substrate. Then, the crystalline silicon substrate is cut along the groove. As a result, a portion of the side surface 313 (first region 313a) of the crystalline silicon layer 310 on which the p+ diffusion layer 310p is formed is covered by the passivation layer 320 which is continuous from the main surface side.

[0102] Similar to the first embodiment, the solar cell 300 of this embodiment does not have a processed or altered layer at its end face. Therefore, the solar cell 300 can exhibit better power generation performance compared to solar cells manufactured by known methods. Furthermore, in the solar cell 300, the passivation layer 320 placed on the first region 313a functions as a passivation film. This also contributes to the improved power generation performance of the solar cell 300 of this embodiment.

[0103] The following describes the various components of the solar cell 300 in this embodiment.

[0104] (Solar cell configuration) • Crystalline silicon layer The crystalline silicon layer 310 is an n-type crystalline silicon layer having a first main surface 311 and a second main surface 312. The crystalline silicon layer 310 is p + Except for including the diffusion layer 310p, the crystalline silicon layer 110 is the same as that of the first embodiment, and the shape of the side surface 313 is also the same. In this embodiment, the first main surface 311 of the crystalline silicon layer 310 has a random texture structure, but the first main surface 311 may be flat.

[0105] p + The diffusion layer 310p is a layer made of p-type semiconductor, and the + indicates a high concentration. + The diffusion layer 310p is a layer in which a p-type dopant such as boron is thermally diffused onto the first main surface 311 side of the crystalline silicon layer 310. In this embodiment, a p-type dopant is also present in the first region 313a of the side surface 313 of the crystalline silicon layer 310. + A diffusion layer 310p is formed. + The diffusion layer 310p is the p of a known TOPCon type solar cell. + It is similar to a diffusion layer.

[0106] • Passivation layer (silicon nitride layer) The passivation layer 320 is a layer disposed to cover the first main surface 311 of the crystalline silicon layer 310 and the first region 313a of the side surface 313 of the crystalline silicon layer 310, and in this embodiment, it is a layer containing silicon nitride. However, it is not limited to a silicon nitride layer, and may be a layer made of silicon oxide, aluminum oxide, or a composite thereof, or it may be a laminate. The passivation layer 320 is similar to the passivation layer of a known TOPCon type solar cell.

[0107] The thickness of the passivation layer 320 may be the same or different on the first main surface 311 of the crystalline silicon layer 310 and on the first region 313a of the side surface 313. The thickness of the passivation layer 320 can be, for example, 60 nm to 100 nm.

[0108] ·1st electrode layer The first electrode layer 330 is positioned on the first main surface 311 of the crystalline silicon layer 310 and penetrates the passivation layer 320, and the above p + Any electrode layer that is electrically connected to the diffusion layer 310p is acceptable, and it can be a grid-like electrode layer made of silver, aluminum, or the like.

[0109] • Silicon oxide (SiOx) layer The silicon oxide layer 341 can be any layer containing silicon oxide, and can be the same as the silicon oxide layer (SiOx) layer of a known TOPCon type solar cell. The thickness of the silicon oxide layer 341 can be any thickness that produces a sufficient effect.

[0110] ·n + Polysilicon layer n + The polysilicon layer 342 is a layer made of polycrystalline silicon or amorphous silicon containing an n-type dopant such as phosphorus. + The polysilicon layer 342 is n of a known TOPCon type solar cell + It can be similar to a polysilicon layer.

[0111] ·Second electrode layer The second electrode layer 350 can be an electrode layer made of silver or the like, and can be the same as the metal electrodes of a known TOPCon type solar cell.

[0112] (Method for manufacturing solar cells according to this embodiment) The manufacturing method for the solar cells described above will be explained below. Components similar to those described above will be denoted by the same reference numerals, and detailed explanations will be omitted.

[0113] The process diagrams for the manufacturing method of the solar cell of this embodiment are shown in Figures 13A to 13F. In this manufacturing method, an n-type crystalline silicon substrate 317 having a first main surface 311 and a second main surface 312 which is the back surface of the substrate is prepared (substrate preparation step, Figure 13A). Then, grooves 315 are formed at desired positions on the first main surface 311 of the crystalline silicon substrate 317 (groove formation step, Figure 13B). Subsequently, the silicon substrate with the grooves 315 is etched to remove the processed altered layer 316 and impurities (not shown) that have formed in the grooves 315 (etching step, Figure 13C). Next, a texture structure is formed on the first main surface 311 of the crystalline silicon substrate 317 as needed (texture structure formation step, Figure 13D).

[0114] Furthermore, on the first main surface 311 side of the crystalline silicon substrate 317, p+ A diffusion layer 317p is formed. In addition, a passivation layer 320, a first electrode layer 330, a silicon oxide layer 341, and n + A polysilicon layer 342 and a second electrode layer 350 are formed (Figure 13E). Then, the crystalline silicon substrate 317 is cut along the groove 315 to obtain a solar cell 300 of the desired size (cutting step, Figure 13F). Note that the manufacturing method of the solar cell 300 in this embodiment may further include steps other than those described above. + Method for forming the diffusion layer 317p, passivation layer 320, first electrode layer 330, silicon oxide layer 341, n + The method for forming the polysilicon layer 342, the second electrode layer 350, etc., can be the same as the method for forming each layer of a known TOPCon type solar cell. In this embodiment as well, the entire surface of the first main surface 311 side of the crystalline silicon substrate 317 is covered with p + By forming a diffusion layer 317p or a passivation layer 320, p can be formed on the first region 313a of the crystalline silicon layer 310 without any special process. + It is possible to form a diffusion layer 317p and a passivation layer 320.

[0115] Thus, according to the method of this embodiment, grooves 315 are formed in the crystalline silicon substrate 317 and the crystalline silicon substrate 317 is cut along these grooves, but the end face of the solar cell 300 does not include a processed and altered region. Therefore, according to this embodiment, it is possible to manufacture solar cells of any shape with good power generation performance. The substrate preparation step, groove formation step, etching step, texture structure formation step, and cutting step of the manufacturing method of the solar cell 300 in this embodiment are the same as those of the first embodiment described above.

[0116] (Modified version of the third embodiment) In the solar cell 300 shown in Figure 12, the second region 313b of the crystalline silicon layer 310 is exposed. However, a defect termination layer may be further arranged to cover the second region 313b. Furthermore, the solar cell 300 of this embodiment may include other layers as needed.

[0117] Furthermore, in the above, p is located on the first main surface 311 side of the crystalline silicon layer 310. + A configuration in which a diffusion layer 310p, a passivation layer 320, a first electrode layer 330, etc. are arranged was described. However, on the second main surface 312 side of the crystalline silicon layer 310, p + A diffusion layer 310p or a passivation layer 320 may be placed. In this case, a silicon oxide layer 341 or n + A polysilicon layer 342 and a second electrode layer 350 are arranged. In this case, the second main surface 312 side of the crystalline silicon layer 310 (p + The side on which the diffusion layer 310p is located is the light incident surface, and the side on which the first main surface 311 is located is the back surface.

[0118] 4. Fourth Embodiment Figure 14 shows a schematic cross-sectional view of a solar cell 400 according to the fourth embodiment. The solar cell 400 of this embodiment is a back-contact type solar cell. The solar cell 400 has a crystalline silicon layer 410, a first amorphous semiconductor layer 420 disposed adjacent to the crystalline silicon layer 410 on the first main surface 411 side of the crystalline silicon layer 410, and a passivation layer 460 disposed on the first amorphous semiconductor layer 420. It also has a second amorphous semiconductor layer 440 disposed adjacent to the crystalline silicon layer 410 on the second main surface 412 side of the crystalline silicon layer 410, and an electrode layer 450 disposed on the second amorphous semiconductor layer 440.

[0119] In the solar cell 400, the side surface 413 of the crystalline silicon layer 410 has a first region 413a covered by a first amorphous semiconductor layer 420 and a passivation layer 460. The first amorphous semiconductor layer 420 and the passivation layer 430 are arranged continuously from the first main surface 411 of the crystalline silicon layer 410 to the first region 413a. Here, "continuously" means that the first amorphous semiconductor layer 420 or passivation layer 460 on the first main surface 411 and the first amorphous semiconductor layer 420 or passivation layer 460 on the first region 313a are arranged as a single unit without any intentional gaps. On the other hand, the side surface 413 of the crystalline silicon layer 410 further has a second region 413b on the second main surface 412 side of the first region 413a that is not covered by either the first amorphous semiconductor layer 420 or the passivation layer 460. In this embodiment, the first main surface 411 side of the crystalline silicon layer 410 is the light incident surface, and the second main surface 412 side is the back surface.

[0120] In this embodiment, the reason why the side surface 413 of the crystalline silicon layer 410 has a first region 413a covered by the first amorphous semiconductor layer 420 and the passivation layer 460 lies in the manufacturing method. In the manufacturing method of the solar cell 400 of this embodiment, a groove for division is formed in advance on the crystalline silicon substrate, and the groove is cleaned by etching. Then, the first amorphous semiconductor layer 420 and the passivation layer 460 are formed, or the necessary layers are formed on the second main surface 412 side. Then, the crystalline silicon substrate is cut along the groove. Therefore, a part of the side surface 413 of the crystalline silicon layer 410 (the first region 413a) is covered by the first amorphous semiconductor layer 420 and the passivation layer 460 which are continuous from the main surface side.

[0121] Similar to the first embodiment, the solar cell 400 of this embodiment does not have a processed altered layer at its end face. Therefore, the solar cell 400 can exhibit better power generation performance compared to solar cells manufactured by known methods. In addition, in the solar cell 400, the first amorphous semiconductor layer 420 and the passivation layer 430 arranged on the first region 413a function as passivation films. This also contributes to the good power generation performance of the solar cell 400 of this embodiment.

[0122] The following describes the various components of the solar cell 400 in this embodiment.

[0123] (Solar cell configuration) • Crystalline silicon layer The crystalline silicon layer 410 is an n-type crystalline silicon layer having a first main surface 411 and a second main surface 412. The crystalline silicon layer 410 is the same as the crystalline silicon layer 110 in the first embodiment, and the shape of the side surface 413 is also the same. In this embodiment, both the first main surface 411 and the second main surface 412 of the crystalline silicon layer 410 have a random texture structure, but they may also be flat.

[0124] • First amorphous semiconductor layer The first amorphous semiconductor layer 420 is a layer disposed to cover the first main surface 411 of the crystalline silicon layer 410 and the first region 413a of the side surface 413 of the crystalline silicon layer 410, and is a hydrogen-doped intrinsic amorphous silicon (i-type a-Si:H) layer. This layer is the same as the i-type a-Si:H layer 121 of the first embodiment. However, the first amorphous semiconductor layer 420 may be an i-type layer containing intrinsic amorphous silicon doped not only with hydrogen but also with trace amounts of carbon atoms (C) and trace amounts of oxygen atoms (C).

[0125] The thickness of the i-type a-Si:H layer 420 described above may be the same or different on the first main surface 411 of the crystalline silicon layer 110 and on the first region 413a of the side surface 113. The thickness of the i-type a-Si:H layer 420 can be, for example, 2 nm to 10 nm.

[0126] ·Passive layer The passivation layer 460 is a layer disposed on the first amorphous semiconductor layer 420, and in this embodiment, it is a layer containing hydrogen-doped silicon nitride (SiNx:H). However, it is not limited to the silicon nitride layer, and may be a layer made of silicon oxide, aluminum oxide, or a composite thereof, or it may be a laminate. The passivation layer 460 is similar to the passivation layer of a known back-contact type solar cell.

[0127] The thickness of the passivation layer 460 may be the same or different on the first main surface 411 of the crystalline silicon layer 410 and on the first region 413a of the side surface 413. The thickness of the passivation layer 460 can be, for example, 60 nm to 100 nm.

[0128] • Second amorphous semiconductor layer The second amorphous semiconductor layer 440 is a layer containing an amorphous semiconductor, arranged to cover the second main surface 412 of the crystalline silicon layer 410, and in this embodiment, it is a layer containing amorphous silicon. The second amorphous semiconductor layer 440 in this embodiment is composed of a hydrogen-doped intrinsic amorphous silicon (i-type a-Si:H) layer 441, an n-type amorphous silicon (n-type a-Si:H) layer 442n arranged in a pattern adjacent to the intrinsic amorphous silicon layer 441, and a p-type amorphous silicon (p-type a-Si:H) layer 442p arranged in a pattern adjacent to the intrinsic amorphous silicon layer 441. The i-type a-Si:H layer 441, the n-type a-Si:H layer 442n, and the p-type a-Si: layer 442p are similar to the layers of known back-contact type cells, and their types and shapes can be changed as long as the purpose of this embodiment is not impaired. For example, they may be composed of microcrystalline silicon.

[0129] The thickness of the i-type a-Si:H layer 441 is not particularly limited, but is usually preferably between 2 nm and 10 nm. Similarly, the thickness of the n-type a-Si:H layer 442n and the p-type a-Si:H layer 442p are also not particularly limited, but are usually between 2 nm and 20 nm.

[0130] • Electrode layer (transparent electrode layer and metal electrode) The electrode layer 450 is an electrode layer located on the back side of the solar cell 400, and in this embodiment, it consists of a translucent electrode layer 451 and a metal electrode 452. The translucent electrode layer 451 is arranged in a pattern on the n-type a-Si:H layer 442n and the p-type a-Si:H layer 442p. More specifically, the translucent electrode layer 451 on the n-type a-Si:H layer 442n and the translucent electrode layer 451 on the p-type a-Si:H layer 442p are arranged so as not to conduct electricity. The material and thickness of the translucent electrode layer 451 are the same as those of the second translucent electrode layer 151 in the first embodiment.

[0131] Furthermore, the metal electrode 452 may be any electrode layer containing metal that is placed on the translucent electrode layer 451. The metal electrode 452 on the n-type a-Si:H layer 442n and the metal electrode 452 on the p-type a-Si:H layer 442p are arranged so that they do not conduct electricity. The material and thickness of the metal electrode 452 are the same as those of the second metal electrode 152 in the first embodiment.

[0132] (Method for manufacturing solar cells according to this embodiment) The manufacturing method for the above-mentioned solar cells will be explained below.

[0133] The process diagrams for the manufacturing method of the solar cell of this embodiment are shown in Figures 15A to 15F. Structures similar to those in Figure 14 are denoted by the same reference numerals and detailed explanations are omitted. In the manufacturing method of the solar cell of this embodiment, an n-type crystalline silicon substrate is prepared (substrate preparation step, Figure 15A). Then, grooves 415 are formed at desired positions on the first main surface 411 of the crystalline silicon substrate 417 (groove formation step, Figure 15B). Subsequently, the silicon substrate with the grooves 415 is etched to remove the processed altered layer 416 and impurities (not shown) formed in the grooves 415 (etching step, Figure 15C). Next, a texture structure is formed on the first main surface 411 and the second main surface 412 of the crystalline silicon substrate 317 as needed (texture structure formation step, Figure 13D).

[0134] Furthermore, a first amorphous semiconductor layer 420 and a passivation layer 460 are formed on the first main surface 411 side of the crystalline silicon substrate 417, and a second amorphous semiconductor layer 440 and an electrode layer 450 are formed on the second main surface 412 side of the crystalline silicon substrate 417 (Figure 15E). Subsequently, the crystalline silicon substrate 417 is cut along the groove 415 to obtain a solar cell 400 of the desired size (cutting step, Figure 15F). The manufacturing method of the solar cell 500 in this embodiment may further include steps other than those described above. The method for forming each layer can be the same as the method for forming each layer of a known back-contact type solar cell. In this embodiment as well, if the first amorphous semiconductor layer 420 and the passivation layer 460 are formed on the entire surface of the first main surface 311 side of the crystalline silicon substrate 417, it is possible to form the first amorphous semiconductor layer 420 and the passivation layer 460 on the first region 413a of the crystalline silicon layer 410 without performing any special steps.

[0135] In the method of this embodiment, grooves 415 are formed in the crystalline silicon substrate 417, and the crystalline silicon substrate 417 is cut along these grooves, but the end face of the solar cell 400 does not include a processed and altered region. Therefore, according to this embodiment, it is possible to manufacture solar cells of any shape with good power generation performance. The substrate preparation step, groove formation step, etching step, texture structure formation step, and cutting step of the manufacturing method of the solar cell 400 in this embodiment are the same as those of the first embodiment described above.

[0136] (Modification of the fourth embodiment) In the solar cell 400 shown in Figure 14, the second region 413b of the crystalline silicon layer 410 is exposed. However, a defect termination layer may be further arranged to cover the second region 413b. Furthermore, the solar cell 400 of this embodiment may include other layers as needed.

[0137] Furthermore, Figure 16 shows a modified configuration of the solar cell 400 of this embodiment. Components identical to those in the solar cell 401 shown in Figure 16 are denoted by the same reference numerals. In the solar cell 401, the second amorphous semiconductor layer 440 and the electrode layer 450 are arranged on the first main surface 411 side of the crystalline silicon layer 410, and the first amorphous semiconductor layer 420 and the passivation layer 460 are arranged on the second main surface 412 side of the crystalline silicon layer 410. In this embodiment, the i-type a-Si:H layer 441 of the second amorphous semiconductor layer 440 covers the first region 413a of the crystalline silicon layer 410. In the solar cell 401, the second main surface 412 side of the crystalline silicon layer 410 is the light incident surface, and the first main surface 411 side is the back surface. The solar cell 401 according to this modified example can be manufactured in the same manner as described above, except that the orientation of the crystalline silicon substrate is adjusted so that the second amorphous semiconductor layer 440 and the electrode layer 450 are formed on the first main surface 411 side of the crystalline silicon substrate after grooves have been formed and etched. [Examples]

[0138] [Reference example 1] (Preparation of crystalline silicon substrate) n-type Si wafer (PV-FZ manufactured by Topsil Global Wafer, with a specific surface orientation) <100> A wafer with a diameter of 150 mm, a thickness of 280 μm, polished on both sides, and a guaranteed lifetime of 2 msec was prepared. Due to the limitations of the experimental setup, a 50 mm square n-type Si wafer was diced and used as the crystalline silicon substrate.

[0139] (Formation of texture structure) The crystalline silicon substrate described above was immersed in an 80°C alkaline aqueous solution (KOH) with an additive (Hayashi Pure Chemical Industries, Pure Etch) added, and etching was performed utilizing the anisotropy of the crystals. This formed a random pyramidal texture structure on both sides of the crystalline silicon substrate. In this case, a double-sided polished wafer with a clean surface was used, so the texture structure was formed directly on the crystalline silicon substrate. However, if the crystalline silicon substrate is cut with a wire saw or the like, a processed altered layer and contamination are likely to occur on the cut surface. Therefore, it is preferable to remove these by wet etching or the like before forming the texture structure.

[0140] After forming the textured structure described above, the surface of the crystalline silicon substrate was wet-cleaned. Specifically, the surface was cleaned by sequentially immersing it in piranha cleaning solution (H2SO4:H2O2=4:1 (volume ratio)), rinsing it with pure water, immersing it in a hydrofluoric acid mixture (HF:H2O2:H2O=1:1:20 (volume ratio)), rinsing it with pure water, and immersing it in a hydrochloric acid mixture (HCl:H2O2:H2O=1:1:5 (volume ratio)). Finally, the outermost chemical oxide film was removed by immersion in a diluted hydrofluoric acid solution.

[0141] (deposition of a-Si:H film) After removing the above-mentioned chemical oxide film, the crystalline silicon substrate was immediately introduced into a plasma-assisted chemical vapor deposition (PECVD) apparatus (Shimadzu Corporation, model: SLCM-13, capacitively coupled, parallel plate type, plasma excitation frequency: 13.54 MHz) for depositing a-Si:H films.

[0142] i-type a-Si:H and p-type a-Si:H were sequentially deposited on one side of the crystalline silicon substrate described above. The wafer was then removed into the atmosphere, quickly inverted, and reintroduced into the apparatus. Then, i-type a-Si:H and n-type a-Si:H were sequentially deposited on the other side. SiH4 and H2 gases were used for the i-type a-Si:H deposition. The deposition temperature was 200°C, and the thickness of the i-type a-Si:H was approximately 7 nm. For the p-type a-Si:H deposition, in addition to SiH4 and H2, B2H6 gas was used as a doping gas. The deposition temperature was 150°C. For the n-type a-Si:H deposition, in addition to SiH4 and H2, PH3 gas was used as a doping gas. The deposition temperature was 200°C. The thicknesses of the p-type a-Si:H and n-type a-Si:H films were approximately 4 nm when positioned on the light incidence side and approximately 7 nm when positioned on the back side, respectively.

[0143] (Formation of electrode layer) Translucent electrode layers were fabricated on the above-mentioned p-type a-Si:H film and n-type a-Si:H film, respectively. Specifically, a tin-doped indium oxide thin film, so-called ITO film, was fabricated by magnetron sputtering. In2O3 with 10 mass% of SnO2 added was used as the target material, and Ar and O2 were used as process gases. In addition, the ITO film was fabricated on both sides of the Si wafer without heating, with a thickness of approximately 75 nm on each side. With this film thickness, the translucent electrode layer can also function as an anti-reflective coating.

[0144] A metal electrode was further formed on the above translucent electrode layer. The electrode material was Ag, and it was fabricated by magnetron sputtering. A shadow mask with a comb-shaped pattern was used on the light incident side to form a comb-shaped Ag electrode layer. On the other hand, an Ag electrode layer covering the entire back side was formed. At this time, the size of each solar cell after division was 40 mm in length and 5 mm in width, and the size of the Ag electrode layer was fabricated in a pattern to match so that five crystalline silicon solar cells could be extracted from the solar cell used for division. Subsequently, to recover from damage during the sputtering process, it was annealed at 160°C in a nitrogen atmosphere for 2 hours.

[0145] (Dividing solar cells for division) Grooves were formed in the solar cell prepared above using laser scribing, and the cell was cut along these grooves. This yielded five 40mm x 5mm rectangular solar cells. A UV laser marker (Keyence MD-U1000) was used for laser scribing. The laser wavelength was set to 355nm, and the maximum output was 10mW. Furthermore, the pulse frequency was set to 40kHz, the laser intensity to 80%, and the sweep speed to 10mm / s, and the same area was scanned three times. This formed grooves with a depth of approximately 150-200μm. Laser scribing was performed on the non-pn junction side. Laser scribing was also performed in the vertical and horizontal directions to extract five 40mm x 5mm rectangular cells as described above. Subsequently, the cells were folded along the grooves to obtain the desired rectangular solar cells.

[0146] (Evaluation of solar cells) Using the above method, a solar cell with a front junction (FJ) structure, in which the pn junction (p-type a-Si:H) is located on the light-receiving surface side, and a solar cell with a rear junction (RJ) structure, in which the pn junction (p-type a-Si:H) is located on the back side, were fabricated.

[0147] Regarding these, the performance of the solar cell (short-circuit current density J) before scribing, after scribing (before cleavage), and after cleavage is as follows: sc (mA / cm 2 ), open-circuit voltage V OC (V), the curve factor FF, and the conversion efficiency (%) were measured. The results are shown in Figure 17.

[0148] Each performance was measured using a dual-source solar simulator (XHS-80S1, manufactured by Sanei Electric Co., Ltd.) as the light source and a source measure unit (2400, manufactured by Keithley Corporation) as the measuring instrument, under standard conditions (light intensity 100 mW / cm²). 2 It was identified using an approximate spectrum of AM1.5g at a temperature of 25°C.

[0149] (Consideration) As shown in Figure 17, in Reference Example 1, regardless of whether it was an RJ structure or an FJ structure, the performance deteriorated significantly as the scribing and cutting processes progressed. Furthermore, in the RJ structure, the J after scribing deteriorated. SC The decrease was significant, but not so much in the FJ structure. OC There was no significant difference in the behavior of the FF between the FJ structure and the RJ structure. Furthermore, although the initial characteristics were similar for the RJ structure and the FJ structure, the FJ structure achieved higher efficiency after splitting. When light is shone on a solar cell, the density of photogenerated carriers (minority carriers) generated is highest on the light-receiving side and decreases towards the back side. In the RJ structure, the minority carriers generated by photogenerated carriers are collected on the back side. Therefore, in the RJ structure, in order to efficiently collect the carriers generated in large quantities on the light-receiving side on the back side, the diffusion length of the photogenerated carriers must be sufficiently long. However, in solar cells that have been processed into elongated shapes, recombination occurs due to end-face defects (processed altered layer) caused by scribing, etc. As a result, the carrier diffusion length becomes locally shorter near the end face of the solar cell. And a large amount of photogenerated carriers are lost by recombination before reaching the back side, J SC It is thought that this decreased. Therefore, in solar cells having a processed and altered layer and large recombination losses at the end face, as in Reference Example 1, the FJ structure, which collects photogenerated carriers on the light incident surface side, was more advantageous.

[0150] [Reference example 2] (Fabrication of solar cells) To investigate the effects of solar cell width and crystalline silicon substrate thickness on solar cells, RJ and FJ structured solar cells with widths (3 mm, 5 mm, 7 mm, 9 mm) and crystalline silicon substrate thicknesses (150 μm, 200 μm, 270 μm) were fabricated using the same method as in Reference Example 1 described above. For these, the performance as solar cells (short-circuit current density J) was investigated. sc (mA / cm 2 ), open-circuit voltage V OC (V), the curve factor FF, and the conversion efficiency (%) were measured. The results for the RJ structure are shown in Figure 18, and the results for the FJ structure are shown in Figure 19.

[0151] (Consideration) In the RJ structure, as shown in Figure 18, the effect of end face recombination becomes greater as the cell width decreases, and J SC , V OC It decreased monotonically. On the other hand, when the crystalline silicon substrate was thinned, the decrease in J SC A recovery trend was observed. This is understood to be because, as the substrate becomes thinner, the diffusion length required to collect photogenerated carriers shortens, improving carrier collection efficiency.

[0152] On the other hand, as shown in Figure 19, the FJ structure showed the following differences compared to the RJ structure: V as the cell width decreased. OC It decreased, J SC The performance was largely maintained. Furthermore, under the same conditions, the FJ structure had higher power generation efficiency than the RJ structure. The advantage of the FJ structure became greater as the cell width decreased. In the FJ structure as well, there was a slight improvement in efficiency due to the reduction in the thickness of the crystalline silicon substrate, but it was not as significant as in the RJ structure.

[0153] The results above clearly show that applying the FJ structure makes it easier to obtain higher power generation efficiency, and that the advantages of the FJ structure are greater when the cell width is small and the crystalline silicon substrate is thick.

[0154] [Example 1] (Preparation of crystalline silicon substrate and formation of grooves) A crystalline silicon substrate was prepared in the same manner as in Reference Example 1 described above. Then, a groove with a depth of approximately 150 to 200 μm was formed on one of the main surfaces (first main surface) of the crystalline silicon substrate using the same method as the scribing method in Reference Example 1 described above.

[0155] (Removal of the processed and altered layer (etching)) The crystalline silicon substrate, which had been scribed as described above, was immersed in an 80°C KOH aqueous solution (KOH concentration of approximately 5-10% by mass) for several minutes to alkali etch the processed and altered layer created by the scribing. Since the crystalline silicon substrate itself was etched along with the processed and altered layer, the thickness of the crystalline silicon substrate was reduced by approximately 10 μm to 30 μm. In this example, the scribing was performed according to the crystal orientation. <110> The etching was carried out along the direction, and anisotropic etching exposed crystal planes mainly formed by the (111) plane. The exposure of the (111) plane resulted in a V-shaped groove, and an effect of widening the opening was observed. The V-shaped groove has the advantage of facilitating film deposition in subsequent processes and is therefore desirable.

[0156] (Formation of texture structure, first amorphous silicon layer, second amorphous silicon layer, first electrode layer, and second electrode layer) A textured structure was formed on both sides of a crystalline silicon substrate from which the processed altered layer had been removed, in the same manner as in Reference Example 1 described above. Subsequently, i-type a-Si:H and p-type a-Si:H (first amorphous silicon layer) were sequentially deposited on one main surface (first main surface) of the crystalline silicon substrate in the same manner as in Reference Example 1. Then, i-type a-Si:H and n-type a-Si:H (second amorphous silicon layer) were sequentially deposited on the other main surface (second main surface) in the same manner as in Reference Example 1. Furthermore, on these, a light incident side electrode layer (transparent electrode layer and metal electrode) was formed on the first amorphous silicon layer as a first electrode layer in the same manner as in Reference Example 1, and a back side electrode layer (transparent electrode layer and metal electrode) was formed on the second amorphous silicon layer as a second electrode layer.

[0157] (Dividing solar cells for division) The solar cell prepared as described above was cut along the groove formed above. This resulted in a solar cell with an FJ structure and the first main surface facing the light incident surface (indicated as "FJ groove pn side (Example 1)" in the figure), as shown in the schematic diagram of Figure 20a. Figures 20a to 20f are schematic diagrams to show whether the pn junction of the solar cell prepared in Example 1, Reference Example 1 described above, and Example 2 described later is on the light incident surface or the back surface, and where the groove was formed. These figures do not show actual dimensional ratios, and texture structures, etc., are omitted.

[0158] (Fabrication of solar cells in a different form) A solar cell was formed in the same manner as described above, except that a first amorphous silicon layer of i-type a-Si:H and n-type a-Si:H was formed on the first main surface side of a crystalline silicon substrate, and a second amorphous silicon layer of i-type a-Si:H and p-type a-Si:H was formed on the second main surface side, and a light incident side electrode layer was formed on the first amorphous silicon layer and a back surface electrode layer was formed on the second amorphous silicon layer. This resulted in a solar cell with an RJ structure as shown in the schematic diagram of Figure 20b, and the first main surface being on the light incident side (indicated as "RJ groove nn side (Example 1)" in the figure).

[0159] Furthermore, a solar cell was formed in the same manner as described above, except that a first amorphous silicon layer of i-type a-Si:H and n-type a-Si:H was formed on the first main surface side of the crystalline silicon substrate, a second amorphous silicon layer of i-type a-Si:H and p-type a-Si:H was formed on the second main surface side, a back-side electrode layer was formed on the first amorphous silicon layer, and a light-incident side electrode layer was formed on the second amorphous silicon layer. This resulted in a solar cell with an FJ structure as shown in the schematic diagram of Figure 20c, with the first main surface on the back side (indicated as "FJ groove nn side (Example 1)" in the figure).

[0160] (Considerations on the structure of solar cells) For the solar cell (FJ groove pn side) fabricated as described above, the region indicated by the dotted line B in Figure 3 was cut out. The results of observation of this sample using a cross-sectional electron microscope are shown in the left panel of Figure 21, and the results of observation using high-angle scattering annular dark-field scanning transmission microscopy (STEM-HAADF) are shown in the center panel of Figure 21. From these, it is clear that there is no processing-altered layer between the crystalline silicon layer (Si wafer) and the first amorphous silicon layer (a-Si:H layer), and that the first amorphous silicon layer is clearly formed on the clean surface of the crystalline silicon layer. The results of energy-dispersive X-ray analysis (EDX) of this sample are shown in the right panel of Figure 21. From these results, it can be confirmed that the first amorphous silicon layer on the crystalline silicon layer is mainly formed of Si and is an a-Si:H layer. Thus, in this embodiment, the a-Si:H layer is arranged on the first region on the side surface of the crystalline silicon substrate, and passivation treatment was naturally performed in this region. Detailed observation and compositional analysis using EDX were performed at Kobelco Research Institute using a transmission electron microscope.

[0161] (Evaluation and consideration of solar cell performance) Performance of the three solar cells fabricated above (short-circuit current density J) sc (mA / cm 2 ), open-circuit voltage V OC (V), curve factor FF, and conversion efficiency (Efficiency (%)) were measured. The results are shown in Figure 22. Figure 22 also shows the performance of the FJ structure solar cell (solar cell with the structure shown in Figure 20d (labeled "FJ groove nn side (Reference Example 1)" in the figure)) and the RJ structure solar cell (solar cell with the structure shown in Figure 20e (labeled "RJ groove nn side (Reference Example 1)" in the figure)) fabricated in Reference Example 1 described above.

[0162] Comparing Reference Example 1 (with processed altered layer) and Example 1 of the RJ structure, in Example 1, J SC and V OC This has greatly improved. As a result, the power generation efficiency has also greatly improved, and the J of the RJ structure in Example 1 SC and V OC This is the J of the FJ structure in Reference Example 1. SCand V OC The improvement reached a level comparable to the previous method. In the manufacturing method of Example 1, the processed altered layer on the wall surface of the groove formed by scribing the crystalline silicon substrate is removed. Furthermore, since this region (the first region) is covered with an amorphous silicon layer, the amorphous silicon layer functions as a passivation film, which can be said to be the result of suppressing recombination loss at the edge.

[0163] On the other hand, comparing Reference Example 1 (with processed altered layer) and Example 1 of the FJ structure, the FJ structure showed relatively good properties even in Reference Example 1, but in Example 1 (structure of the present invention), V OC A clear improvement was observed. Furthermore, in Example 1, the same power generation efficiency was obtained whether the grooved side was positioned on the light-receiving surface side (e.g., FJ groove pn side) or on the back side (e.g., FJ groove nn side). Therefore, the method for manufacturing a solar cell with the structure of the present invention allows for greater flexibility in the solar cell manufacturing process, and consequently, in the device structure.

[0164] [Example 2] A solar cell was fabricated in the same manner as in Example 1, except that the translucent conductive electrode layer (ITO film) was deposited in a patterned manner so as not to overlap the grooves during the formation of the first electrode layer. More specifically, a shadow mask was positioned so that the distance between the opening end of the groove formed on the crystalline silicon substrate (the outer circumference of the first main surface of the crystalline silicon substrate) and the edge (outer circumference) of the ITO film was 0.5 mm, and the ITO film was formed. By this method, a solar cell with an FJ structure and the first main surface on the light incident surface side was obtained, as shown in Figure 20f (labeled "FJ groove pn side ITO patterning (Example 2)" in the figure).

[0165] (Evaluation of solar cells) Performance of the fabricated solar cell (short-circuit current density J) sc (mA / cm 2 ), open-circuit voltage V OC(V), curve factor FF, and conversion efficiency (Efficiency (%)) were measured. The results are shown in Figure 23. Figure 23 also shows the performance of the solar cells with the FJ structure (FJ groove nn side (Reference Example 1)) fabricated in Reference Example 1 and the FJ structure (FJ groove pn side (Example 1)) fabricated in Example 1.

[0166] (Consideration) As shown in Figure 23, by forming the translucent electrode layer (ITO film) so as in Example 2, without overlapping the side surface (first region) of the crystalline silicon layer, the power generation performance could be further improved. In this solar cell, no conductive film is placed on the side surface (first region) of the crystalline silicon layer. Therefore, carrier transport is stagnant near the end face of the solar cell, and J SC This decreased. However, from the opposite perspective, by hindering carrier transport in that region, the influence of the solar cell edge where recombination occurs actively can be mitigated. For this reason, it is thought that Voc and FF improved. The improvement in FF was particularly significant, and J SC This produced a favorable effect that outweighed the decrease in performance. As a result, the structure of Example 2 improved power generation performance. It should be noted that this effect can be expected even without completely eliminating the translucent electrode layer, as long as the conductivity on the side surface (first region) of the crystalline silicon layer can be locally and significantly reduced. [Industrial applicability]

[0167] According to the present invention, a solar cell that can be used for various applications is provided. [Explanation of symbols]

[0168] 100, 101, 102, 200, 300, 400, 401 solar cells 110, 210, 310, 410 crystalline silicon layers 111, 211, 311, 411 First main surface 112, 212, 312, 412 Second main surface 113, 213, 313, 413 Side view 113a, 213a, 313a, 413a 1st area 113b, 213b, 313b, 413b 2nd area 115, 215, 315, 415 groove 116, 216, 316, 416 Processed and altered layers 117, 217, 317, 417 crystalline silicon substrates 120, 420 First amorphous semiconductor layer 121, 141, 420, 441 i-type a-Si:H layer 122, 442p p-type a-Si:H layer 130, 230, 330 1st electrode layer 131, 135 First transparent electrode layer 132 First metal electrode 140, 440 Second amorphous semiconductor layer 142, 442n n-type a-Si:H layer 150, 250, 350 2nd electrode layer 151 2nd transparent electrode layer 152 Second metal electrode 160 Defective End Layer 210n, 217n n + Diffusion layer 220, 320 (1st) Passive layer 240 Second passive layer 310p, 317p + Diffusion layer 341 Silicon Oxide Layer 342 n + Polysilicon layer 450 Electrode layer 451 Transparent electrode layer 452 Metal electrode 460 Passive layer

Claims

1. An n-type or p-type crystalline silicon layer having a first main surface and a second main surface which is the back surface thereof, An amorphous semiconductor layer or passivation layer is disposed adjacent to the first main surface of the crystalline silicon layer, Includes, At least one side surface of the crystalline silicon layer, Having a first region that is continuous from the first main surface side and covered by the amorphous semiconductor layer or the passivation layer, Crystalline silicon solar cell.

2. At least one side surface of the crystalline silicon layer further has a second region on the second main surface side of the first region that is not covered by either the amorphous semiconductor layer or the passivation layer. The crystalline silicon solar cell according to claim 1.

3. The surface of the second region is composed of a (110) plane or a (100) plane of crystalline silicon. The crystalline silicon solar cell according to claim 2.

4. The second region of the crystalline silicon layer is covered by a defect termination layer. The crystalline silicon solar cell according to claim 2.

5. The ratio of the area of ​​the first region to the total area of ​​one side surface including the first region of the crystalline silicon layer is 1 / 5 or more. The crystalline silicon solar cell according to claim 1.

6. The amorphous semiconductor layer is included, The amorphous semiconductor layer is an amorphous silicon layer and / or a microcrystalline silicon layer. The first region of the crystalline silicon layer is covered with the amorphous silicon layer or the microcrystalline silicon layer. The crystalline silicon solar cell according to claim 1.

7. The electrode layer is arranged on the first main surface of the crystalline silicon layer. When the electrode layer is viewed in plan view, its outer circumference is located inward from the outer circumference when the first main surface of the crystalline silicon layer is viewed in plan view. The crystalline silicon solar cell according to claim 1.

8. Including the aforementioned passivation layer, The passivation layer comprises one or more layers containing at least one selected from the group consisting of silicon oxide, silicon nitride, aluminum oxide, and composites thereof. The first region of the crystalline silicon layer is covered with the passivation layer. The crystalline silicon solar cell according to claim 1.

9. The pn junction surface is located on the first main surface side of the crystalline silicon layer. The crystalline silicon solar cell according to claim 1.

10. A step of preparing an n-type or p-type crystalline silicon substrate having a first main surface and a second main surface which is the back surface thereof, The steps include forming grooves on the first main surface of the crystalline silicon substrate, The process of etching the crystalline silicon substrate, A step of forming an amorphous semiconductor layer or a passivation layer on the first main surface of the crystalline silicon substrate, The steps include: cutting the crystalline silicon substrate along the groove, It includes in this order, A method for manufacturing crystalline silicon solar cells.

11. The process further includes forming a defect termination layer to cover the surface created by the cleavage, after the step of cutting the crystalline silicon substrate. A method for manufacturing a crystalline silicon solar cell according to claim 10.

12. The process further includes etching the crystalline silicon substrate, followed by forming a textured structure on the first main surface and / or second main surface of the crystalline silicon substrate. A method for manufacturing a crystalline silicon solar cell according to claim 10.

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