Manufacturing method for producing wafer structures

Abstract

This enables improved (enhanced) charge trapping capability and suppression of parasitic surface conductivity within the wafer structure. [Solution] The wafer structure 232 includes a trap-rich layer 214 bonded to a handle wafer 224 such that the grain structure within the trap-rich layer 214 becomes coarser adjacent to the handle wafer 224, and the grain size within the grain structure decreases away from the handle wafer 224, thereby improving the trapping efficiency of the wafer structure 232 within the trap-rich layer 214 at the interface (IF) toward the top wafer. A method for manufacturing the wafer structure 232 includes the steps of depositing a trap-rich layer 214 on a top wafer 204 and bonding a handle wafer 224 onto the top wafer 204 such that the trap-rich layer 214 is located between the top wafer 204 and the handle wafer 224.

Description

Technical Field

[0001] This application generally relates to a manufacturing method for manufacturing a wafer structure.

Background Art

[0002] A high-resistivity silicon (HRS) wafer is a special semiconductor substrate typically having a resistivity greater than 1000 Ohm-cm. This high resistivity reduces the number of free carriers in the material and minimizes conduction losses and interference that can affect signal quality. Due to these properties, HRS wafers are suitable for radio frequency (RF) devices that are essential for maintaining signal integrity, reducing noise, and ensuring efficient transmission. Thus, HRS wafers improve the performance and reliability of RF circuits.

[0003] HRS wafers are further improved for RF devices by depositing a trap-rich layer on the surface of the HRS wafer. The trap-rich layer captures and traps free charges on the surface. This charge trapping ability prevents the formation of parasitic conduction paths that can degrade signal quality. The trap-rich layer helps to stabilize the electrical properties of the HRS wafer by reducing interference and improving isolation in RF circuits, which is essential for high-performance RF devices.

[0004] HRS wafers with a trap-rich layer are used in different types of RF devices, such as integrated passive devices (IPDs), filters, resonators, power amplifiers, and RF switches. These RF devices are important for efficient signal processing and transmission in wireless communication systems. Inductors, filters, and resonators, for example, benefit from the high quality factor (Q) of HRS wafers, which helps to reduce energy losses and enables accurate signal filtering. Inductors and power amplifiers also perform better on HRS wafers with a trap-rich layer because reduced interference increases efficiency.

[0005] One known wafer structure for RF devices is the so-called trap-rich silicon-on-insulator (TR-SOI) structure, which comprises a silicon wafer as a handle wafer, another silicon wafer as a top wafer, a silicon dioxide layer as an insulating layer on the silicon top wafer, and an embedded polysilicon layer as a trap-rich layer between the silicon handle wafer and the silicon dioxide layer. The TR-SOI structure is manufactured by depositing a thin polysilicon layer, 100 nm to several μm thick, onto the silicon handle wafer, oxidizing the silicon top wafer to obtain a silicon dioxide layer on it, bonding the silicon handle wafer and the top wafer so that the trap-rich layer is between the handle wafer and the insulating layer, and finally thinning the top silicon wafer to complete the desired TR-SOI structure. [Overview of the project]

[0006] One object of the present invention is to eliminate the shortcomings of known solutions and to provide a wafer structure for radio frequency (RF) devices, which includes a thicker inverted grain structure of trap-rich layers, thereby enabling improved (enhanced) charge trapping capability and suppression of parasitic surface conductivity within the wafer structure.

[0007] The inverted grain structure also provides improved RF performance (characteristics) over the typical operating temperature range, reduced thermal dependence of RF performance, and allows for higher process temperatures in subsequent steps without compromising RF performance.

[0008] One object of the present invention is achieved by providing a manufacturing method and wafer structure according to an independent claim.

[0009] Embodiments of the present invention are disclosed in the claims.

[0010] One manufacturing method for producing a wafer structure includes the following steps of establishing a top wafer. The manufacturing method further includes the following steps of depositing a trap-rich layer on the top wafer. The manufacturing method further includes the following steps of bonding a handle wafer onto the top wafer so that the trap-rich layer is between the top wafer and the handle wafer in order to produce a wafer structure. The wafer structure comprises a trap-rich layer bonded to the handle wafer such that the grain structure within the trap-rich layer becomes coarser adjacent to the handle wafer, and the grain size within the grain structure decreases away from the handle wafer, thereby improving the trapping efficiency of the wafer structure within the trap-rich layer at the interface toward the top wafer.

[0011] A wafer structure for an RF device manufactured by the aforementioned manufacturing method comprises a top wafer, a trap-rich layer, and a handle wafer. The trap-rich layer is located on the top wafer. The handle wafer is located on the top wafer such that it lies between the top wafer to which the trap-rich layer is bonded and the handle wafer. The trap-rich layer is bonded to the handle wafer such that the grain structure within the trap-rich layer becomes coarser adjacent to the handle wafer, and the grain size within the grain structure decreases away from the handle wafer, thereby improving the trapping efficiency of the wafer structure within the trap-rich layer at the interface toward the top wafer.

[0012] Exemplary embodiments of the present invention will be described with reference to the accompanying drawings. [Brief explanation of the drawing]

[0013] [Figure 1] A flowchart of the wafer structure manufacturing method is presented. [Figure 2a] This presents the resulting wafer structure for each step of the manufacturing process when an insulating layer is formed on the top layer. [Figure 2b] This document presents the wafer structure resulting from each step of a manufacturing method that does not involve an insulating layer. [Modes for carrying out the invention]

[0014] Figures 1, 2a, and 2b show a manufacturing method 100 for producing wafer structures 232, 234, 238, and 240, which are suitable substrates (platforms) for radio frequency (RF) devices (not shown), and the resulting structures for each of the manufacturing steps 210, 216, 218, 226, 228, 232, 234, 238, and 240.

[0015] The RF devices can be manufactured (integrated) on wafer structures 232 and 234 and include, for example, bulk acoustic filters (BAWs), film bulk acoustic resonators (FBARs), power amplifiers, RF switches, and other types of RF devices that can be integrated on wafer structures 232 and 234.

[0016] In step 102, the top (device) wafer 204 and the handle (substrate) wafer 224 are established. The top wafer 204 comprises a semiconductor top wafer or a piezoelectric top wafer. The semiconductor top wafer 204 comprises a silicon (Si) wafer, for example, standard or high-resistivity silicon, silicon-germanium (SiGe), or silicon carbide (SiC) wafer. The piezoelectric top wafer 204 comprises a lithium niobate (LiNbO3) or lithium tantalate (LiTaO3) wafer.

[0017] In step 106, if wafer structures 232, 238, and 240 include an insulating layer 208, the insulating layer 208 is generated on the top wafer 204 to obtain (achieve) a wafer structure 210 having the insulating layer 208 above the top wafer 204.

[0018] The insulating layer 208 comprises a layer 208 of thermal silicon dioxide (SiO2), deposited silicon dioxide, deposited silicon nitride (Si3N4), deposited silicon oxynitride (Si2N2O), deposited aluminum oxide (Al2O3), deposited hafnium oxide (HfO2), deposited titanium oxide (TiO2), deposited zirconium oxide (ZrO2), deposited lanthanum oxide (La2O3), deposited barium oxide (BaO), or deposited aluminum nitride (AlN).

[0019] In step 112, regardless of whether the insulating layer 208 is present on the top wafer 204, the trap-rich layer 214 is deposited on the top wafer 204 to establish the trap-rich layer 214 at the interface IF between the trap-rich layer 214 and the underlying structure.

[0020] The trap-rich layer 214 is deposited by chemical vapor deposition (CVD) to achieve a wafer structure 216 having the trap-rich layer 214 above the wafer structure 210, i.e., above the insulating layer 208, after the manufacturing of the insulating layer 208, or to achieve a wafer structure 218 having the trap-rich layer 214 directly above the top wafer 204 after the establishment of the top wafer 204, when the wafer structure 218 lacks an insulating layer. Alternatively, the trap-rich layer 214 is deposited by sputtering to achieve wafer structure 216 or wafer structure 218.

[0021] A trap-rich layer 214 comprising a polycrystalline trap-rich layer containing polysilicon (PSi), silicon carbide, aluminum nitride, germanium (Ge), or silicon-germanium has a deposition (growth) morphology in which the growth of the trap-rich layer 214 begins with fine (small) grains and continues with columnar structures and larger (larger) grains as the grain size increases.

[0022] Therefore, the trap-rich layer 214 has a finer grain structure adjacent to the lower structure, i.e., the insulating layer 208 or the top wafer 204, than the upper surface of the trap-rich layer 214. Due to the deposition morphology of the trap-rich layer 214, the grain size in the grain structure increases in the direction away from the insulating layer 208 or the top wafer 204, and the growth of the trap-rich layer 214 starts with fine grains and then continues with cylindrically larger grains towards the upper surface of the trap-rich layer 214 as shown in the figure.

[0023] In step 112, if the trap-rich layer 214 is modified after its deposition, the wafer structures 216, 218 are processed by high-temperature treatment at a temperature above 800 °C, for example, rapid thermal annealing, to modify the grain size of the structure or interface IF of the trap-rich layer 214 and stabilize the grain structure within the trap-rich layer 214, so that the charge trapping ability of the trap-rich layer 214 is improved, thereby more efficiently preventing the formation of parasitic conductive paths and the degradation of signal quality in the RF device.

[0024] In step 120, the trap-rich layer 214, i.e., the upper surface of the trap-rich layer 214, is polished before the bonding of the wafer structures 216, 218 and the handle wafer 224.

[0025] In step 122, the handle wafer 224 is bonded on the wafer structures 216, 218 such that the trap-rich layer 214 is between the top wafer 204 and the handle wafer 224 by direct bonding, for example, fusion bonding, for example, plasma-activated fusion bonding, by hybrid bonding, by anodic bonding, or by conductive bonding, to achieve a wafer structure 226 with an insulating layer 208 or a wafer structure 228 without an insulating layer.

[0026] The handle wafer 224 comprises a semiconductor handle wafer containing silicon, for example, standard or high-resistivity silicon, silicon carbide, or indium phosphide (InP), or an insulating handle wafer containing glass, sapphire, or quartz.

[0027] The wafer structures 226, 228 include a trap-rich layer 214 bonded to the handle wafer 224 such that the grain structure in the trap-rich layer 214 becomes coarser adjacent to the handle wafer 224 than adjacent to the insulating layer 214 when the insulating layer 214 is present within the wafer structure 216, or adjacent to the top wafer 204 when the wafer structure 218 lacks the wafer structure. The grain size within the grain structure decreases in a direction away from the handle wafer 224, and improves the trapping efficiency of the wafer structures 226, 228 within the trap-rich layer 214 at the interface IF toward the top wafer 204 when a smaller grain size causes a better trapping efficiency than a larger grain size.

[0028] In step 130, the wafer structures 226, 228 are thinned by etching, by grinding, by polishing, or by a combination of at least two of the previous thinning methods to partially remove the top wafer 204 on the trap-rich layer 214 to achieve a wafer structure 232 corresponding to a so-called trap-rich silicon-on-insulator (TR-SOI) structure comprising an insulator layer 208, or a wafer structure 234 lacking an insulator layer, and the achieved wafer structures 232, 234 are made to comprise a trap-rich layer 214 embedded between the top wafer 204 and the handle wafer 224.

[0029] In step 144, when the desired wafer structures 232, 234, 238, 240 are achieved and further thinning is not required, the wafer structures 232, 234, 238, 240 are completed by sorting, washing, inspecting, and packing a wafer structure 232, 234 comprising a thinned top wafer 204 above the insulator layer 208 or the trap-rich layer 214, a wafer structure 238 comprising an insulator layer 208 above the trap-rich layer 214, or a wafer structure 240 comprising only the trap-rich layer 214 above the handle wafer 224.

[0030] The present invention has been described above with reference to exemplary embodiments, and some of its advantages have been demonstrated. It is clear that the present invention is not limited to these embodiments, but includes all possible embodiments within the scope of the following claims.

Claims

1. A manufacturing method (100) for manufacturing wafer structures (232, 234), wherein at least the following: Step (102) to establish the top wafer (204), The steps include: (112) depositing a trap-rich layer (214) on the top wafer, To produce the aforementioned wafer structure, the process includes the step (122) of bonding the handle wafer (224) onto the top wafer such that the trap-rich layer is located between the top wafer and the handle wafer (204, 224), Manufacturing method (100), wherein the wafer structure comprises a trap-rich layer bonded to the handle wafer such that the grain structure within the trap-rich layer becomes coarser adjacent to the handle wafer, and the grain size within the grain structure decreases away from the handle wafer, thereby improving the trapping efficiency of the wafer structure within the trap-rich layer at the interface (IF) toward the top wafer.

2. The manufacturing method according to claim 1, further comprising the step (106) of generating the insulating layer (208) on the top wafer before depositing the trap-rich layer onto the insulating layer, in order to establish the trap-rich layer within the interface (IF) of the trap-rich layer and the insulating layer (208, 214).

3. The manufacturing method according to claim 2, wherein the insulating layer comprises thermal silicon dioxide, deposited silicon dioxide, deposited silicon nitride, or deposited silicon oxynitride.

4. The manufacturing method according to claim 2 or 3, wherein the granular structure of the trap-rich layer is rougher adjacent to the silicon handle wafer than adjacent to the insulating layer, so as to improve the trapping efficiency of the wafer structure in the trap-rich layer within the interface (IF) of the trap-rich layer and the insulating layer (208, 214) with respect to the trapping efficiency of the wafer structure in the trap-rich layer.

5. The manufacturing method according to any one of claims 2 to 4, further comprising the step (136) of thinning the insulating layer in order to completely remove the insulating layer on the trap-rich layer.

6. The manufacturing method according to any one of claims 1 to 5, wherein the trap-rich layer is deposited on the top wafer by chemical vapor deposition.

7. The manufacturing method according to any one of claims 1 to 6, wherein the trap-rich layer comprises a polycrystalline trap-rich layer (214).

8. The manufacturing method according to claim 7, wherein the polycrystalline trap-rich layer comprises polysilicon, silicon carbide, or aluminum nitride.

9. The manufacturing method according to any one of claims 1 to 8, wherein the trap-rich layer is annealed by rapid thermal annealing in order to stabilize the granular structure within the trap-rich layer and to improve the charge trapping ability of the trap-rich layer.

10. The manufacturing method according to any one of claims 1 to 9, further comprising the step (120) of polishing the trap-rich layer before bonding the top wafer and the handle wafer.

11. The manufacturing method according to any one of claims 1 to 10, further comprising the step (130) of thinning the wafer structure in order to obtain the wafer structure by partially removing the top wafer on the trap-rich layer.

12. The manufacturing method according to any one of claims 1 to 11, wherein the top wafer comprises a semiconductor top wafer (204) containing silicon.

13. The manufacturing method according to any one of claims 1 to 12, wherein the handle wafer comprises a semiconductor handle wafer (224) containing silicon, silicon carbide, or indium phosphide, or an insulating handle wafer (224) containing glass, sapphire, or quartz.

14. A wafer structure (232, 234) for a radio frequency device, manufactured by the manufacturing method (100) described in any one of claims 1 to 13, Top wafer (204) and, Trap-rich layer (214), A handle wafer (224) and a, The aforementioned trap-rich layer is located on the top wafer, The handle wafer is located on the top wafer such that the trap-rich layer is located between the bonded top wafer and the handle wafer (204, 224). The trap-rich layer is bonded to the handle wafer such that the grain structure within the trap-rich layer becomes coarser adjacent to the handle wafer, and the grain size within the grain structure decreases away from the handle wafer, thereby improving the trapping efficiency of the wafer structure within the trap-rich layer at the interface (IF) toward the top wafer (232, 234).

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