Electronic devices

Abstract

To provide an electronic device that can suppress the decline in reliability. [Solution] The electronic device A10 comprises an electronic component 19 having an electrode 191 positioned at one end in a first orthogonal direction perpendicular to the thickness direction z, a wiring layer 3 including a wiring portion 34 that conducts to the electrode 191, and a bonding layer 42 that joins the electrode 191 and the wiring portion 34. The wiring portion 34 includes a valley portion 342 positioned on one side (downward) of the thickness direction z of the bonding layer 42. The bonding layer 42 includes a fixing portion 422 that fixes the electrode 191 to the wiring portion 34. The fixing portion 422 is positioned inward of the electronic component 19 beyond the valley portion 342.

Description

Technical Field

[0002]

[0001] This disclosure relates to an electronic device.

Background Art

[0002] Patent Document 1 discloses an example of a conventional electronic device. The electronic device (semiconductor device) described in Patent Document 1 includes an insulating layer, a wiring layer, a plurality of bonding layers, a semiconductor element, and a plurality of electronic components. The wiring layer is disposed on the insulating layer. The wiring layer constitutes a conduction path between the plurality of electronic components and the semiconductor element. The semiconductor element is a flip-chip mounted element, for example, an LSI. Each of the plurality of electronic components is either a passive element such as a resistor, a capacitor, and an inductor, or a diode. The semiconductor element and the plurality of electronic components are each bonded to the wiring layer via one of the plurality of bonding layers.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a configuration where each of the semiconductor element and the plurality of electronic components is bonded to the wiring layer via a bonding layer as in the above-described electronic device (semiconductor device), a decrease in the bonding strength between each of the semiconductor element and the plurality of electronic components and the wiring layer, and a decrease in the electrical conductivity between each of the semiconductor element and the plurality of electronic components and the wiring layer are caused by a defect in the bonding layer. Such a decrease in the bonding strength and the electrical conductivity reduces the reliability of the electronic device.

[0005] This disclosure has been conceived in view of the above circumstances, and an object thereof is to provide an electronic device capable of suppressing a decrease in reliability.

Means for Solving the Problems

[0006] The electronic device provided by this disclosure comprises an electronic component having an electrode disposed at one end in a first orthogonal direction perpendicular to the thickness direction; a wiring layer including a wiring portion that conducts to the electrode; and a bonding layer that joins the electrode and the wiring portion, wherein the wiring portion includes a valley portion disposed in one of the thickness directions of the bonding layer, and the bonding layer includes a fixing portion that fixes the electrode to the wiring portion, the fixing portion being disposed inward of the electronic component beyond the valley portion. [Effects of the Invention]

[0007] The electronic device described herein can suppress a decrease in reliability. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a perspective view from the bottom side showing an electronic device according to the first embodiment. [Figure 2] Figure 2 is a plan view showing an electronic device according to the first embodiment, in which the sealing resin is indicated by dashed lines. [Figure 3] Figure 3 is a plan view of Figure 2, but with the sealing resin omitted and semiconductor elements and multiple electronic components shown with dashed lines. [Figure 4] Figure 4 is a magnified view of a portion of Figure 3. [Figure 5] Figure 5 is a magnified view of a portion of Figure 3. [Figure 6] Figure 6 is a bottom view showing a semiconductor device according to the first embodiment. [Figure 7] Figure 7 is a cross-sectional view along the line VII-VII in Figure 2. [Figure 8] Figure 8 is a partially enlarged cross-sectional view, which is an enlarged portion of Figure 7. [Figure 9] Figure 9 is a partially enlarged cross-sectional view, which is an enlarged portion of Figure 7. [Figure 10] Figure 10 is a cross-sectional view along line XX in Figure 2. [Figure 11]Figure 11 is a partial enlarged cross-sectional view obtained by enlarging a part of Figure 10. [Figure 12] Figure 12 is a cross-sectional view taken along line XII-XII of Figure 2. [Figure 13] Figure 13 is a cross-sectional view showing one step of a method for manufacturing an electronic device according to the first embodiment. [Figure 14] Figure 14 is a cross-sectional view showing one step of a method for manufacturing an electronic device according to the first embodiment. [Figure 15] Figure 15 is a cross-sectional view showing one step of a method for manufacturing an electronic device according to the first embodiment. [Figure 16] Figure 16 is a partially enlarged cross-sectional view showing one step of a method for manufacturing an electronic device according to the first embodiment. [Figure 17] Figure 17 is a partially enlarged cross-sectional view showing the detailed processing of the step shown in Figure 16. [Figure 18] Figure 18 is a partially enlarged cross-sectional view showing the detailed processing of the step shown in Figure 16. [Figure 19] Figure 19 is a partially enlarged cross-sectional view showing the detailed processing of the step shown in Figure 16. [Figure 20] Figure 20 is a partially enlarged cross-sectional view showing the detailed processing of the step shown in Figure 16. [Figure 21] Figure 21 is a cross-sectional view showing one step of a method for manufacturing an electronic device according to the first embodiment. [Figure 22] Figure 22 is a cross-sectional view showing one step of a method for manufacturing an electronic device according to the first embodiment. [Figure 23] Figure 23 is a cross-sectional view showing one step of a method for manufacturing an electronic device according to the first embodiment. [Figure 24] Figure 24 is a partially enlarged cross-sectional view showing the detailed processing of the step shown in Figure 23. [Figure 25] Figure 25 is a partially enlarged cross-sectional view showing the detailed processing of the step shown in Figure 23. [Figure 26] Figure 26 is a partially enlarged cross-sectional view showing the detailed processing of the step shown in Figure 23. [Figure 27]FIG. 27 is a cross-sectional view showing one step of a method for manufacturing an electronic device according to the first embodiment. [Figure 28] FIG. 28 is a cross-sectional view showing one step of a method for manufacturing an electronic device according to the first embodiment. [Figure 29] FIG. 29 is a cross-sectional view showing one step of a method for manufacturing an electronic device according to the first embodiment. [Figure 30] FIG. 30 is an enlarged cross-sectional view of a main part showing a case where cracks occur in a bonding layer for bonding an electronic component. [Figure 31] FIG. 31 is an enlarged cross-sectional view of a main part showing an electronic device according to the first modification of the first embodiment, corresponding to the partially enlarged cross-sectional view of FIG. 8. [Figure 32] FIG. 32 is an enlarged plan view of a main part showing an electronic device according to the second modification of the first embodiment, corresponding to the partially enlarged view of FIG. 5. [Figure 33] FIG. 33 is an enlarged plan view of a main part showing an electronic device according to the third modification of the first embodiment, corresponding to the partially enlarged view of FIG. 5. [Figure 34] FIG. 34 is an enlarged plan view of a main part showing an electronic device according to the fourth modification of the first embodiment, corresponding to the partially enlarged view of FIG. 5. [Figure 35] FIG. 35 is an enlarged plan view of a main part showing an electronic device according to the fifth modification of the first embodiment, corresponding to the partially enlarged view of FIG. 5. [Figure 36] FIG. 36 is an enlarged plan view of a main part showing an electronic device according to the sixth modification of the first embodiment, corresponding to the partially enlarged cross-sectional view of FIG. 8. [Figure 37] FIG. 37 is an enlarged plan view of a main part showing an electronic device according to the second embodiment, corresponding to the partially enlarged view of FIG. 5. [Figure 38] FIG. 38 is an enlarged plan view of a main part showing an electronic device according to the third embodiment, corresponding to the partially enlarged view of FIG. 5. [Figure 39] FIG. 39 is an enlarged plan view of a main part showing an electronic device according to the fourth embodiment, corresponding to the partially enlarged view of FIG. 5. [Figure 40]Figure 40 is a cross-sectional view showing an electronic device according to another modified example, corresponding to the cross-section in Figure 12. [Modes for carrying out the invention]

[0009] Preferred embodiments of the electronic devices of this disclosure will be described below with reference to the drawings. Hereafter, identical or similar components will be denoted by the same reference numerals, and redundant descriptions will be omitted. The terms "first," "second," "third," etc., used in this disclosure are used merely as labels and are not necessarily intended to assign a sequence to the objects.

[0010] In this disclosure, "object A is formed on object B" and "object A is formed on object B" include, unless otherwise specified, "object A is directly formed on object B" and "object A is formed on object B with another object interposed between object A and object B." Similarly, "object A is located on object B" and "object A is located on object B" include, unless otherwise specified, "object A is directly located on object B" and "object A is located on object B with another object interposed between object A and object B." Similarly, "object A is located on object B" includes, unless otherwise specified, "object A is located on object B in contact with object B" and "object A is located on object B with another object interposed between object A and object B." Furthermore, "object A overlaps with object B when viewed in a certain direction" includes, unless otherwise specified, "object A overlaps with all of object B" and "object A overlaps with a part of object B." Also, "object A (or its material) contains material C" includes "object A (or its material) consists of material C" and "the main component of object A (or its material) is material C." Furthermore, "a surface A faces a certain direction B (one side or the other side)" is not limited to cases where the angle of surface A with respect to direction B is 90°, but also includes cases where surface A is inclined with respect to direction B. Furthermore, "a surface A is perpendicular to surface B" is not limited to cases where the angle of surface A with respect to surface B is 90°, but also includes cases where surface A is inclined with respect to surface B within an error range. Furthermore, unless otherwise specified, the statement "object A is parallel to object B" is not limited to cases where they are strictly parallel, but also includes cases where surface A is inclined with respect to surface B within a margin of error.

[0011] Figures 1 to 12 show an electronic device A10 according to the first embodiment. The electronic device A10 comprises a semiconductor element 1, a plurality of electronic components 19, a support member 2, a wiring layer 3, a plurality of barrier layers 351, 352, 353, a plurality of bonding layers 41, 42, a plurality of terminals 5, and a plurality of sealing resins 6.

[0012] For the sake of explanation, we will refer to the mutually orthogonal thickness direction z, the first direction x, and the second direction y. The thickness direction z corresponds to the thickness direction of the electronic device A10. In the following explanation, one direction of the thickness direction z may be referred to as "up" and the other as "down." Note that terms such as "up," "down," "upper," "downward," "upper surface," and "lower surface" indicate the relative positional relationship of each component in the thickness direction z, and do not necessarily define a relationship with the direction of gravity. Also, "plan view" refers to the view in the thickness direction z.

[0013] Electronic device A10 is a surface-mount device for circuit boards in electronic devices and electric vehicles. Electronic device A10 is a leadless package type, and in particular, a QFN package (Quad Flat Non-leaded Package) type. Electronic device A10 has a rectangular shape in plan view.

[0014] The semiconductor element 1 is a core component of the electronic device A10. The semiconductor element 1 is, for example, an integrated circuit such as an LSI. In contrast to this example, the semiconductor element 1 may also be a voltage control element such as an LDO (Low Dropout), an amplification element such as an operational amplifier, or a discrete element such as a transistor and a diode. The semiconductor element 1 is rectangular in plan view. The semiconductor element 1 is supported by a support member 2. In plan view, the semiconductor element 1 overlaps the support member 2.

[0015] As shown in Figures 7, 10, and 12, the semiconductor element 1 has an opposing surface 10a and an element top surface 10b. The opposing surface 10a and the element top surface 10b are spaced apart in the thickness direction z. The opposing surface 10a and the element top surface 10b face opposite each other. The opposing surface 10a faces the support member 2. The element top surface 10b is covered with a sealing resin 6.

[0016] As shown in Figures 9 and 11, the semiconductor element 1 has a main body 11 and a plurality of electrodes 12. The opposing surface 10a corresponds to the lower surface of the main body 11 (the surface facing downward in the thickness direction z). An insulating film (not shown) is placed on the lower surface (opposing surface 10a) of the main body 11, and the plurality of electrodes 12 are exposed from this insulating film. The insulating film contains polyimide or polybenzoxazole. As a result, each of the plurality of electrodes 12 is bonded to the wiring layer 3 by a plurality of bonding layers 41.

[0017] Multiple electrodes 12 include multiple pads 121, 122, and 123. Each of the multiple pads 121 and 122 is conductive to a functional circuit (not shown) formed in the main body 11. Each of the multiple pads 123 is not conductive to the functional circuit formed in the main body 11. Therefore, each of the multiple pads 123 is a dummy pad. In contrast to this example, each of the multiple pads 123 may be conductive to a functional circuit formed in the main body 11.

[0018] As shown in Figures 9 and 11, each of the multiple pads 121 includes two metal layers 1211 and 1212. Metal layer 1211 is positioned on the opposing surface 10a. In the illustrated example, the lower surface of metal layer 1211 is flush with the opposing surface 10a. Unlike this example, the lower surface of metal layer 1211 may be recessed upward in the thickness direction z or protrude downward in the thickness direction z relative to the opposing surface 10a. Metal layer 1212 is laminated relative to metal layer 1211 downward in the thickness direction z (the side on which the wiring layer 3 is positioned). The constituent material of metal layer 1211 is not limited, but may include, for example, aluminum. The constituent material of metal layer 1212 is not limited, but may include copper.

[0019] Each of the multiple pads 121 has an end face 121a. As shown in Figures 9 and 11, the end face 121a faces downward in the thickness direction z and faces the wiring layer 3. The end face 121a corresponds to the lower surface of the metal layer 1212.

[0020] As shown in Figure 9, each of the multiple pads 122 includes a metal layer 1221. The metal layer 1221 is positioned on the opposing surface 10a. In the illustrated example, the lower surface of the metal layer 1221 is flush with the opposing surface 10a. Unlike this example, the lower surface of the metal layer 1221 may be recessed upward in the thickness direction z or protrude downward in the thickness direction z relative to the opposing surface 10a. The constituent material of the metal layer 1221 is not limited, but may include, for example, aluminum. Because each pad 121 includes two metal layers 1211 and 1212, while each pad 122 includes a metal layer 1221, the thickness of each pad 121 is greater than the thickness of each pad 122.

[0021] Each of the multiple pads 122 has an end face 122a. As shown in Figure 9, the end face 122a faces downward in the thickness direction z and faces the wiring layer 3. The end face 122a corresponds to the lower surface of the metal layer 1221.

[0022] As shown in Figure 11, each of the multiple pads 123 contains two metal layers 1231 and 1232. Metal layer 1231 is positioned on the opposing surface 10a. In the illustrated example, the lower surface of metal layer 1231 is flush with the opposing surface 10a. Unlike this example, the lower surface of metal layer 1231 may be recessed upward in the thickness direction z or protrude downward in the thickness direction z relative to the opposing surface 10a. Metal layer 1232 is laminated relative to metal layer 1231 downward in the thickness direction z (the side on which the wiring layer 3 is positioned). The dimension of metal layer 1232 along the thickness direction z is the same as the dimension of metal layer 1212 along the thickness direction z. The constituent material of metal layer 1231 is not limited, but includes, for example, aluminum. The constituent material of metal layer 1232 is not limited, but includes, for example, copper.

[0023] Each of the multiple pads 123 has an end face 123a. As shown in Figure 11, the end face 123a faces downward in the thickness direction z and faces the wiring layer 3. The end face 123a corresponds to the lower surface of the metal layer 1232.

[0024] In the illustrated example, the end faces 121a, 122a, and 123a have the following positional relationships. Firstly, as shown in Figure 11, in the thickness direction z, the end face 121a of each pad 121 and the end face 123a of each pad 123 are located at the same position. Therefore, the thickness (dimension in the thickness direction z) of each pad 121 is the same as the thickness (dimension in the thickness direction z) of each pad 123. Secondly, as can be seen from Figure 9, the end face 122a of each pad 122 is located higher in the thickness direction z (towards the semiconductor element 1) than the end face 121a of each pad 121 and the end face 123a of each pad 123. Therefore, the thickness (dimension in the thickness direction z) of each pad 122 is smaller than the thickness of each pad 121 and the thickness of each pad 123. Note that the positional relationships of the end faces 121a, 122a, and 123a are not limited to this example.

[0025] Each of the multiple electronic components 19 is supported by a support member 2, as shown in Figures 2, 7, 10, and 12. Each of the multiple electronic components 19 is an SMD (Surface Mount Device). Each of the multiple electronic components 19 is, for example, a resistor, a capacitor, or a diode. The multiple electronic components 19, together with the semiconductor element 1, are functional elements of the electronic device A10. In the illustrated example, each electronic component 19 is rectangular in plan view.

[0026] Each of the multiple electronic components 19 has a pair of electrodes 191. In each electronic component 19, the pair of electrodes 191 are individually positioned at both ends of a first orthogonal direction OD1 (see Figure 5) that is perpendicular to the thickness direction z. In this embodiment, the first orthogonal direction OD1 corresponds to the longitudinal direction of the electronic component 19 in a plan view. That is, in this embodiment, the pair of electrodes 191 are individually positioned at both ends of the longitudinal direction of the electronic component 19 in a plan view. Unlike this example, in each electronic component 19, the pair of electrodes 191 may be individually positioned at both ends of the short direction of the electronic component 19 in a plan view. In the electronic device A10, as can be understood from Figure 2, the multiple electronic components 19 include those in which the first orthogonal direction OD1 (longitudinal direction) is the first direction x, and those in which the first orthogonal direction OD1 (longitudinal direction) is the second direction y. Also, in each electronic component 19, the direction perpendicular to the thickness direction z and the first orthogonal direction OD1 is called the second orthogonal direction OD2 (see Figure 5). In this embodiment, the second orthogonal direction OD2 corresponds to the short-side direction of the electronic component 19 in a plan view. The number of electronic components 19 is not limited to the illustrated example.

[0027] As shown in Figures 2, 7, 10, and 12, the support member 2 supports the semiconductor element 1 and a plurality of electronic components 19. The support member 2 includes, for example, a resin material. This resin material is, for example, the same as the sealing resin 6, but may be different from the sealing resin 6. The support member 2 may also contain fillers such as silica mixed into the aforementioned resin material. The support member 2 may also be made of a single-crystal intrinsic semiconductor (for example, silicon (Si)), glass, or ceramic, instead of a resin material. As shown in Figures 2, 3, and 6, the support member 2 is rectangular in plan view. The thickness of the support member 2 (dimension along the thickness direction z) is not limited, but is, for example, 30 μm or more and 300 μm or less. The support member 2 has a mounting surface 21, a back surface 22, and a plurality of side surfaces 23.

[0028] As shown in Figures 7, 10, and 12, the mounting surface 21 and the back surface 22 are spaced apart in the thickness direction z. The mounting surface 21 and the back surface 22 face opposite each other. The mounting surface 21 is the upper surface of the support member 2, and the back surface 22 is the lower surface of the support member 2. The mounting surface 21 faces the semiconductor element 1 (opposing surface 10a). The back surface 22 faces the circuit board when the electronic device A10 is mounted on the aforementioned circuit board. In this embodiment, the mounting surface 21 is covered by the sealing resin 6, and the back surface 22 is exposed from the sealing resin 6.

[0029] As shown in Figures 2, 3, and 6, each of the multiple side surfaces 23 is sandwiched between the mounting surface 21 and the back surface 22. The upper end of each side surface 23 in the thickness direction z connects to the mounting surface 21, and the lower end of each side surface 23 in the thickness direction z connects to the back surface 22. Each side surface 23 is flat and perpendicular to the mounting surface 21 and the back surface 22, respectively.

[0030] The wiring layer 3 is a conductor placed inside the electronic device A10. The wiring layer 3 is formed on the mounting surface 21 and is in contact with the mounting surface 21. The wiring layer 3 electrically connects the semiconductor element 1, the multiple electronic components 19, and the multiple terminals 5 to each other. As shown in Figures 2 to 4, the wiring layer 3 is divided into multiple parts. The multiple wiring layers 3 include multiple wiring sections 31, multiple wiring sections 32, multiple wiring sections 33, and multiple wiring sections 34. The semiconductor element 1 is bonded to each of the multiple wiring sections 31, 32, and 33, and one of the multiple electronic components 19 is bonded to each of the multiple wiring sections 34.

[0031] Multiple pads 121 of the semiconductor element 1 are individually electrically connected to each of the multiple wiring sections 31. Each of the multiple wiring sections 31 includes a pattern layer 311, as shown in Figures 9 and 11. The pattern layer 311 described below is common to each wiring section 31 unless otherwise specified.

[0032] The pattern layer 311 extends along a plane (xy plane) perpendicular to the thickness direction z. In a plan view, the pattern layer 311 overlaps one of the multiple pads 121. The pattern layer 311 has a seed layer 311a and a plating layer 311b. The seed layer 311a is formed on the mounting surface 21 and is in contact with the mounting surface 21. The plating layer 311b is laminated on the seed layer 311a. The seed layer 311a and the plating layer 311b each contain a conductive material. For example, the seed layer 311a contains Ti and the plating layer 311b contains Cu.

[0033] As shown in Figures 9 and 11, each of the multiple wiring sections 31 has a wiring main surface 31a. The wiring main surface 31a faces upward in the thickness direction z and faces the opposing surface 10a of the semiconductor element 1 in the thickness direction z. In this embodiment, the wiring main surface 31a is the upper surface of the plating layer 311b.

[0034] Multiple pads 122 of the semiconductor element 1 are electrically connected to each of the multiple wiring sections 32. Each of the multiple wiring sections 32 is connected to one of the multiple wiring sections 31. Unlike this example, the multiple wiring sections 32 do not have to be connected to any of the multiple wiring sections 31, and there may be a mixture of those connected to the multiple wiring sections 31 and those not connected to the multiple wiring sections 31. Each of the multiple wiring sections 32 includes a pattern layer 321 and a base section 322, as shown in Figure 9. The pattern layer 321 and base section 322 described below are common to each wiring section 32 unless otherwise specified.

[0035] The pattern layer 321 extends along a plane (xy plane) perpendicular to the thickness direction z. The pattern layer 321 has a seed layer 321a and a plating layer 321b. The seed layer 321a is formed on the mounting surface 21 and is in contact with the mounting surface 21. The plating layer 321b is laminated on the seed layer 321a. The seed layer 321a and the plating layer 321b each contain a conductive material. For example, the seed layer 321a contains Ti and the plating layer 321b contains Cu.

[0036] The base portion 322 protrudes upward in the thickness direction z from the pattern layer 321. In a plan view, the base portion 322 is positioned on a part of the pattern layer 321. The base portion 322 contains, for example, the same material as the plating layer 321b. In this case, the base portion 322 may be formed integrally with the plating layer 321b. In a plan view, the base portion 322 overlaps one of the plurality of pads 122.

[0037] As shown in Figure 9, each of the multiple wiring sections 32 has a wiring main surface 32a. The wiring main surface 32a of each wiring section 32 is positioned above the wiring main surface 31a of each wiring section 31 in the thickness direction z. Therefore, the wiring main surface 32a of each wiring section 32 is closer to the opposing surface 10a of the semiconductor element 1 than the wiring main surface 31a of each wiring section 31 in the thickness direction z. In this embodiment, the wiring main surface 32a of each wiring section 32 is the upper surface (top surface) of the base portion 322 of the corresponding wiring section 32.

[0038] In this embodiment, the distance between the main wiring surface 31a and the main wiring surface 32a in the thickness direction z is the difference between the thickness of pad 121 (dimension in the thickness direction z) and the thickness of pad 122 (dimension in the thickness direction z).

[0039] Multiple pads 123 of the semiconductor element 1 are electrically connected to each of the multiple wiring sections 33. In this embodiment, each wiring section 33 is not electrically connected to any of the other wiring sections 31, 32, or 34. The multiple wiring sections 33 include a pattern layer 331 and a base section 332. The pattern layer 331 and base section 332 described below are common to each wiring section 33 unless otherwise specified.

[0040] The pattern layer 331 extends along a plane (xy plane) perpendicular to the thickness direction z in each wiring section 33. The pattern layer 331 has a seed layer 331a and a plating layer 331b. The seed layer 331a is formed on the mounting surface 21 and is in contact with the mounting surface 21. The plating layer 331b is laminated on the seed layer 331a. The seed layer 331a and the plating layer 331b each contain a conductive material. For example, the seed layer 331a contains Ti and the plating layer 331b contains Cu.

[0041] The base portion 332 protrudes upward in the thickness direction z from the pattern layer 331. In a plan view, the base portion 332 is positioned on a part of the pattern layer 331. The base portion 332 contains, for example, the same material as the plating layer 331b. In this case, the base portion 332 may be formed integrally with the plating layer 331b. In a plan view, the base portion 332 overlaps one of the pads 123. The thickness (dimension in the thickness direction z) of each wiring portion 33 is partially greater than the thickness (dimension in the thickness direction z) of each wiring portion 31 due to the base portion 332.

[0042] As shown in Figure 11, each of the multiple wiring sections 33 has a wiring main surface 33a. The wiring main surface 33a of each wiring section 33 is positioned above the wiring main surface 31a of each wiring section 31 in the thickness direction z. Therefore, the wiring main surface 33a of each wiring section 33 is closer to the opposing surface 10a of the semiconductor element 1 than the wiring main surface 31a of each wiring section 31 in the thickness direction z. In this embodiment, the wiring main surface 33a of each wiring section 33 is located between the wiring main surface 31a of each wiring section 31 and the wiring main surface 32a of each wiring section 32 in the thickness direction z. In this embodiment, the wiring main surface 33a of each wiring section 33 is the upper surface (top surface) of the base section 332 of the corresponding wiring section 33.

[0043] In this embodiment, the gap ΔG1 in the thickness direction z between corresponding wiring sections 31 and pads 121 (see Figures 9 and 11), the gap ΔG2 in the thickness direction z between corresponding wiring sections 32 and pads 122 (see Figure 9), and the gap ΔG3 in the thickness direction z between corresponding wiring sections 33 and pads 123 (see Figure 11) have the following dimensional relationships. Firstly, the size of gap ΔG1 and the size of gap ΔG2 are the same. Unlike this example, the sizes of these gaps ΔG1 and ΔG2 may be different. Secondly, the size of gap ΔG1 is larger than the size of gap ΔG3. Thirdly, the difference between the size of gap ΔG1 and the size of gap ΔG3 is the same as the distance in the thickness direction z between the main wiring surface 31a of each wiring section 31 and the main wiring surface 33a of each wiring section 33. The size of gap ΔG1 is the distance along the thickness direction z between opposing wiring main surfaces 31a and end surfaces 121a in the thickness direction z, as shown in Figures 9 and 11. The size of gap ΔG1 is not limited in any way, but is approximately 15 μm. The size of gap ΔG2 is the distance along the thickness direction z between opposing wiring main surfaces 32a and end surfaces 122a in the thickness direction z, as shown in Figure 9. The size of gap ΔG3 is the distance along the thickness direction z between opposing wiring main surfaces 33a and end surfaces 123a in the thickness direction z, as shown in Figure 11. Note that the dimensional relationships of these gaps ΔG1, ΔG2, and ΔG3 are not limited to this example.

[0044] Multiple electronic components 19 are joined to multiple wiring sections 34. One of a pair of electrodes 191 of the electronic components 19 is electrically joined to each of the multiple wiring sections 34. Each wiring section 34 has a seed layer 340a and a plating layer 340b. The seed layer 340a is formed on the mounting surface 21 and is in contact with the mounting surface 21. The plating layer 340b is laminated on the seed layer 340a. The seed layer 340a and the plating layer 340b contain conductive materials. For example, the seed layer 340a contains Ti and the plating layer 340b contains Cu.

[0045] Each of the multiple wiring sections 34 includes a pattern layer 341, at least one valley 342, and at least one peak 343. In this embodiment, as shown in Figures 5 and 8, each wiring section 34 includes two valleys 342 and three peaks 343. Note that the number of valleys 342 and peaks 343 in each wiring section 34 is not limited to the illustrated example. The aforementioned seed layer 340a and plating layer 340b are formed across the pattern layer 341, the two valleys 342, and the three peaks 343. That is, each of the pattern layer 341, the two valleys 342, and the three peaks 343 has a seed layer 340a and a plating layer 340b.

[0046] The pattern layer 341 extends along a plane (xy plane) perpendicular to the thickness direction z in each wiring section 34.

[0047] The two valleys 342 are recessed downward in the thickness direction z from the pattern layer 341. The two valleys 342 are spaced apart in the first orthogonal direction OD1 of the corresponding electronic component 19 and are parallel to each other. Each of the two valleys 342 is adjacent to one of the three apex 343. The thickness of the plating layer 340b in each valley 342 (dimension z in the thickness direction) is smaller than the thickness of the plating layer 340b in the pattern layer 341 (dimension z in the thickness direction).

[0048] The three vertices 343 are recessed upward in the thickness direction z from the pattern layer 341. The three vertices 343 are spaced apart in the first orthogonal direction OD1 of the corresponding electronic component 19 and are parallel to each other. The thickness of the plating layer 341b at each vertex 343 (dimension in the thickness direction z) is greater than the thickness of the plating layer 340b at the pattern layer 341 (dimension in the thickness direction z).

[0049] The two valleys 342 and the three peaks 343 are each positioned below the thickness direction z of any of the multiple bonding layers 42. In a plan view, the two valleys 342 and the three peaks 343 each extend along the second orthogonal direction OD2 (short direction) of the corresponding electronic component 19. The two valleys 342 and the three peaks 343 are alternately positioned along the first orthogonal direction OD1 (long direction) of the corresponding electronic component 19. With this configuration, as shown in Figure 8, the surface of each wiring portion 34 becomes uneven below the thickness direction z of the electrode 191 of the corresponding electronic component 19. In this embodiment, the two valleys 342 and the three peaks 343 are arranged in a stripe pattern.

[0050] Each of the barrier layers 351 to 353 contains a different metal from the wiring layer 3. This metal is, for example, nickel (Ni). Each of the barrier layers 351 to 353 is composed of a metal layer containing Ni and an alloy layer laminated on the metal layer and containing tin (Sn) in its composition. This alloy layer is, for example, an alloy of Sn and silver (Ag). The thickness (dimension z in the thickness direction) of each barrier layer 351 to 353 is, for example, 1 μm or more and 10 μm or less. Note that the electronic device A10 does not necessarily have to include any of the barrier layers 351 to 353.

[0051] Each of the multiple barrier layers 351 is individually positioned on the lower surface (the surface facing downward in the thickness direction z) of each of the multiple electrodes 12. The multiple barrier layers 351 include those positioned on the end faces 121a of the multiple pads 121 and on the end faces 122a of the multiple pads 122, as shown in Figure 9, and those positioned on the end faces 123a of the multiple pads 123, as shown in Figure 11.

[0052] Each of the multiple barrier layers 352 is placed on the wiring layer 3. The multiple barrier layers 352 include those placed on the main wiring surfaces 31a and 32a of multiple wiring sections 31, as shown in Figure 9, and those placed on the main wiring surfaces 33a of multiple wiring sections 33, as shown in Figure 11.

[0053] Each of the multiple barrier layers 353 is positioned on each of the multiple wiring sections 34. Each barrier layer 353 is individually positioned between each of the multiple bonding layers 42 and each of the multiple wiring sections 34. Each barrier layer 353 is formed spanning multiple valleys 342 and multiple peaks 343 in the corresponding wiring section 34. Each barrier layer 353 is in contact with the multiple valleys 342 and multiple peaks 343 of the corresponding wiring section 34. Therefore, the surface (upper surface) of each barrier layer 353 is uneven along the surface (upper surface) of the corresponding wiring section 34.

[0054] Each of the multiple bonding layers 41 bonds the semiconductor element 1 to the wiring layer 3. Each of the multiple bonding layers 41 is interposed between the opposing surface 10a of the semiconductor element 1 and the wiring layer 3. On both sides of each of the multiple bonding layers 41 in the thickness direction z, one of the multiple barrier layers 351 and one of the multiple barrier layers 352 are individually arranged. Each of the multiple bonding layers 41 is, for example, solder. The solder contains an alloy that includes tin (Sn) in its composition (for example, a Sn-silver (Ag) alloy). The solder may also contain flux. Each of the multiple bonding layers 41 may be a sintered metal (for example, sintered silver) or a metal paste (for example, silver paste) instead of solder. The multiple bonding layers 41 include multiple joints 411, 412, 413.

[0055] As shown in Figures 9 and 11, each of the multiple joints 411 is individually interposed between each of the multiple pads 121 and each of the multiple wiring portions 31. Each of the multiple joints 411 joins the corresponding pad 121 and the corresponding wiring portion 31. As shown in Figures 9 and 11, a pair of barrier layers 351 and 352 are individually arranged on both sides of each joint 411 in the thickness direction z. Therefore, a barrier layer 351 is interposed between each joint 411 and the corresponding pad 121, and a barrier layer 352 is interposed between each joint 411 and the corresponding wiring portion 31. This suppresses the penetration of the joints 411 into the wiring portion 31 and the pads 121, respectively.

[0056] As shown in Figure 9, each of the multiple joints 411 has a side surface 411a. In each joint 411, the side surface 411a faces in a direction perpendicular to the thickness direction z and connects to the upper and lower surfaces of the joint 411. In this embodiment, the side surface 411a is inclined such that the cross section perpendicular to the thickness direction z of each joint 411 decreases monotonically in the thickness direction z as it moves from the wiring section 31 toward the semiconductor element 1. In each joint 411, the side surface 411a may be flat or curved.

[0057] As shown in Figure 9, each of the multiple joints 412 is individually interposed between the multiple pads 122 and the multiple wiring sections 32 (base sections 322). Each of the multiple joints 412 joins the corresponding pad 122 and the corresponding wiring section 32. In this embodiment, the thickness of each of the multiple joints 412 (dimension in the thickness direction z) is the same as the thickness of each of the multiple joints 411 (dimension in the thickness direction z). As shown in Figure 9, a pair of barrier layers 351 and 352 are individually arranged on both sides of each joint 412 in the thickness direction z. Therefore, a barrier layer 351 is interposed between each joint 412 and the corresponding pad 122, and a barrier layer 352 is interposed between each joint 412 and the corresponding wiring section 32 (base section 322). This suppresses the penetration of the joints 412 into the wiring section 32 and the pads 122, respectively.

[0058] In the wiring layer 3, in portions where at least one joint 411 and at least one joint 412 are mixed and joined, at least one joint 411 and at least one joint 412 are adjacent to each other. For example, in the example shown in Figure 4, in the portion of the wiring layer 3 located on one side in the second direction y, three joints 411 and two joints 412 are mixed, and these joints 411 and 412 are arranged alternately in the first direction x. Also, for example, in the example shown in Figure 4, in the portion of the wiring layer 3 located on the other side in the second direction y, three joints 411 and three joints 412 are mixed, and these joints 411 and 412 are arranged alternately in a matrix.

[0059] As shown in Figure 9, each of the multiple joints 412 has a side surface 412a. In each joint 412, the side surface 412a faces in a direction perpendicular to the thickness direction z and connects to the upper and lower surfaces of the joint 412. In this embodiment, the side surface 412a is inclined such that the cross section perpendicular to the thickness direction z of each joint 412 decreases monotonically in the thickness direction z as it moves from the wiring section 32 toward the semiconductor element 1. In each joint 412, the side surface 412a may be flat or curved.

[0060] As shown in Figure 9, the center position h411 of each joint 411 in the thickness direction z and the center position h412 of each joint 412 in the thickness direction z are different from each other. In this embodiment, the center position h412 of each joint 412 is located above the center position h411 of each joint 411 in the thickness direction z. In this embodiment, as shown in Figure 9, each joint 411 and each joint 412 do not overlap when viewed in a direction perpendicular to the thickness direction z (for example, the first direction x in Figure 9). Therefore, the upper end of each joint 411 (the end above the thickness direction z) is located below the lower end of each joint 412 (the end below the thickness direction z). Unlike this example, parts of each joint 411 and parts of each joint 412 may overlap when viewed in a direction perpendicular to the thickness direction z.

[0061] As shown in Figure 11, each of the multiple joints 413 is individually interposed between the multiple pads 123 and the multiple wiring sections 33 (base sections 332). Each of the multiple joints 413 joins the corresponding pad 123 and the corresponding wiring section 33. As shown in Figure 11, the thickness of each of the multiple joints 413 (dimension in the thickness direction z) is smaller than the thickness of each of the multiple joints 411 (dimension in the thickness direction z). As shown in Figure 11, a pair of barrier layers 351 and 352 are individually arranged on both sides of each joint 413 in the thickness direction z. Therefore, a barrier layer 351 is interposed between each joint 413 and the corresponding pad 123, and a barrier layer 352 is interposed between each joint 413 and the corresponding wiring section 33 (base section 332). This suppresses the penetration of the joints 413 into the wiring section 33 and the pads 123, respectively.

[0062] As shown in Figure 11, each of the multiple joints 413 has a side surface 413a. In each joint 413, the side surface 413a faces in a direction perpendicular to the thickness direction z and connects to the upper and lower surfaces of the joint 413. In each joint 413, the side surface 413a is curved in a convex shape.

[0063] Multiple bonding layers 42 bond multiple electronic components 19 to the wiring layer 3. Each of the multiple bonding layers 42 is individually interposed between one of the electrodes 191 of the multiple electronic components 19 and the multiple wiring sections 34. As shown in Figure 8, a barrier layer 353 is interposed between each bonding layer 42 and the corresponding wiring section 34. This suppresses the penetration of the bonding layer 42 into the wiring section 34. Each of the multiple bonding layers 42 includes an intervening portion 421 and a fillet 423. The intervening portion 421 and fillet 423 described below are common to each bonding layer 42 unless otherwise specified.

[0064] The intervening portion 421 is interposed between the electrode 191 and the wiring portion 34. The intervening portion 421 is in contact with the barrier layer 353 placed on the wiring portion 34. The intervening portion 421 includes a fixing portion 422.

[0065] The fixing portion 422 is the part of the intervening portion 421 that is interposed between the electrode 191 and the top portion 343. In a plan view, the fixing portion 422 is positioned inward of the electronic component 19 (especially the electrode 191) from among the multiple valleys 342, specifically the valley 342 that is positioned furthest outward in the first orthogonal direction OD1 of the corresponding electronic component 19. In a plan view, the fixing portion 422 overlaps the top portion 343 sandwiched between two valleys 342. The fixing portion 422 fixes the electrode 191 to the wiring portion 34.

[0066] As shown in Figure 8, the fillet 423 is in contact with the side of the electrode 191. In the illustrated example, the side surface of the fillet 423 is flat, but it may be convex or concave.

[0067] Each of the terminals 5 is conductive to the wiring layer 3 and is a conductor exposed to the outside of the electronic device A10. Each of the terminals 5 becomes a terminal when the electronic device A10 is mounted on a circuit board. As shown in Figures 10 and 12, each of the terminals 5 penetrates the support member 2 in the thickness direction z. Some of the terminals 5 are conductive to the semiconductor element 1 via the wiring layer 3, some are conductive to the semiconductor element 1 and one of the multiple electronic components 19 via the wiring layer 3, some are conductive to one of the multiple electronic components 19 via the wiring layer 3, and some are not conductive to either the semiconductor element 1 or the multiple electronic components 19. In the illustrated example, the terminals 5 are arranged along each side surface 23 extending in the first direction x in a plan view. Also, in the illustrated example, one of the terminals 5 overlaps the semiconductor element 1 and one of the multiple electronic components 19 in a plan view. Furthermore, with the exception of the aforementioned single terminal 5, the multiple terminals 5 are positioned outside the semiconductor element 1 in a plan view and do not overlap with either the semiconductor element 1 or the multiple electronic components 19 in a plan view.

[0068] Each of the multiple terminals 5 includes a columnar portion 51 and an external electrode portion 52, as shown in Figures 10 and 12. The columnar portion 51 and external electrode portion 52 described below are common to each terminal 5 unless otherwise specified.

[0069] As shown in Figures 10 and 12, the columnar portion 51 penetrates the support member 2 in the thickness direction z. The columnar portion 51 includes, for example, a metal material. The metal material is not limited in any way, but for example, Cu. The plan view shape of the columnar portion 51 is not limited in any way, but in the illustrated example it is rectangular or polygonal. The upper surface of the columnar portion 51 (the surface facing upward in the thickness direction z) is flush with, for example, the mounting surface 21 of the support member 2. This upper surface of the columnar portion 51 is in contact with the wiring layer 3. Note that some of the terminals 5 may have upper surfaces of the columnar portion 51 that are not in contact with the wiring layer 3. Such terminals 5 are dummy terminals. The lower surface of the columnar portion 51 (the surface facing downward in the thickness direction z) is exposed from the support member 2. This lower surface of the columnar portion 51 is flush with, for example, the back surface 22 of the support member 2. In this embodiment, the side surface of the columnar portion 51 (the surface facing the first direction x or the second direction y) of all terminals 5 is covered by the support member 2. However, unlike this example, some terminals 5 may have exposed side surfaces of the columnar portion 51.

[0070] As shown in Figures 10 and 12, the external electrode portion 52 contacts the portion of the columnar portion 51 that is exposed from the back surface 22 of the support member 2. The external electrode portion 52 protrudes from the back surface 22. The external electrode portion 52 is formed by electroless plating. The external electrode portion 52 is composed of multiple metal layers stacked in the order of Ni layer, palladium (Pd) layer, and gold (Au) layer from the side in contact with the columnar portion 51. The external electrode portion 52 can also be composed of multiple metal layers stacked in the order of Ni layer, Au layer from the side in contact with the columnar portion 51, or multiple metal layers stacked in the order of Cu layer, Ag layer, and Sn layer. The material and formation method of the external electrode portion 52 are not limited to these examples.

[0071] The sealing resin 6 is a synthetic resin, for example, primarily composed of black epoxy resin. The sealing resin 6 may contain fillers such as silica mixed into the epoxy resin. As shown in Figures 2, 7, 10, and 12, the sealing resin 6 covers the semiconductor element 1, multiple electronic components 19, and wiring layer 3. The sealing resin 6 also covers a part of the support member 2, multiple bonding layers 41, and multiple bonding layers 42, as shown in Figures 2, 7, 10, and 12. The sealing resin 6 is formed on the mounting surface 21. The sealing resin 6 is rectangular in plan view. The thickness of the sealing resin 6 (dimension along the thickness direction z) is not limited, but is for example 300 μm or more and 1200 μm or less. As shown in Figures 1, 2, 6, 7, 10, and 12, the sealing resin 6 has a main resin surface 61, a back surface 62, and multiple resin side surfaces 63.

[0072] As shown in Figures 7, 10, and 12, the resin main surface 61 and the resin back surface 62 are spaced apart in the thickness direction z. The resin main surface 61 and the resin back surface 62 face opposite each other in the thickness direction z. The resin main surface 61 faces the same direction as the mounting surface 21 in the thickness direction z, and the resin back surface 62 faces the same direction as the back surface 22 in the thickness direction z. The resin back surface 62 is in contact with the mounting surface 21. The resin back surface 62 has irregularities according to the shape of the wiring layer 3. As shown in Figures 7, 10, and 12, each of the multiple resin side surfaces 63 is sandwiched between the resin main surface 61 and the resin back surface 62 in the thickness direction z, and is connected to them. The multiple resin side surfaces 63 are flush with one of the corresponding side surfaces 23.

[0073] Next, an example of a manufacturing method for the electronic device A10 will be described with reference to Figures 13 to 29. Figures 13 to 29 are cross-sectional views showing one step in the manufacturing method of the electronic device A10. Of these cross-sectional views, Figures 13 to 15, 21 to 23, and 27 to 29 correspond to the cross-section shown in Figure 12, respectively. Figures 16 to 20 are enlarged views of key parts showing each process in the step shown in Figure 15. Figures 24 to 26 are enlarged views of key parts showing each process in the step shown in Figure 23.

[0074] First, as shown in Figure 13, a support substrate 80 is prepared, and a plurality of columnar conductors 851 are formed on the support substrate 80. The support substrate 80 includes, for example, a single-crystal intrinsic semiconductor material. The semiconductor material is, for example, Si. In the step of preparing the support substrate 80, for example, a silicon wafer is prepared as the support substrate 80. The support substrate 80 has a main substrate surface 80a and a back surface 80b that face opposite each other in the thickness direction z. The plurality of columnar conductors 851 are formed by, for example, the following steps. First, a seed layer is formed on the main substrate surface 80a. The seed layer is formed by, for example, a sputtering method. Then, a resist is patterned on the seed layer, and a plurality of columnar conductors 851 are formed by electroplating. After that, the resist layer and the unnecessary seed layer are removed. Through these steps, a plurality of columnar conductors 851 are formed on the main substrate surface 80a of the support substrate 80. The columnar conductors 851 are the parts that will later become the columnar portion 51 of the terminal 5.

[0075] Next, as shown in Figure 13, a first resin layer 82 covering the columnar conductor 851 is formed on the main surface 80a of the support substrate 80. The first resin layer 82 is formed, for example, by molding. The first resin layer 82 is a synthetic resin mainly composed of, for example, black epoxy resin. The first resin layer 82 may be made of other insulating resin materials instead of the aforementioned synthetic resin. The first resin layer 82 has a main surface 821 and a bottom surface 822 that face opposite each other in the thickness direction z. The main surface 821 faces the same direction as the main surface 80a of the substrate, and the bottom surface 822 faces the main surface 80a of the substrate. The first resin layer 82 is a member that will later become the support member 2.

[0076] Next, as shown in Figure 14, the first resin layer 82 is ground. The first resin layer 82 is ground from the main surface 821 side until the columnar conductor 851 is exposed from the main surface 821. The method of grinding is not particularly limited. Alternatively, the first resin layer 82 may be reduced in height by a method other than grinding. This forms the columnar portion 51 from the columnar conductor 851. Through the above steps, the support member 2 is formed from the first resin layer 82.

[0077] Next, as shown in Figure 15, the wiring layer 3 is formed. For example, the wiring layer 3 is formed by the process shown in Figures 16 to 20.

[0078] In forming the wiring layer 3, first, a seed layer 301 is formed over the entire surface of the mounting surface 21, as shown in Figure 16. This seed layer 301 contains, for example, Ti. The seed layer 301 is formed by, for example, a sputtering method.

[0079] Next, as shown in Figure 16, a first plating layer 302 is formed by electroplating using the seed layer 301 as a conductive path. Specifically, a resist is patterned on the seed layer 301, and the first plating layer 302 is deposited on the seed layer 301 exposed from the resist by electroplating. Then, the unnecessary resist is removed. The first plating layer 302 contains, for example, copper. As a result, multiple pattern layers 311, 321, 331, and 341 are formed. The first plating layer 302 is the plating layer 311b of the pattern layer 311 of each wiring section 31, the plating layer 321b of the pattern layer 321 of each wiring section 32, the plating layer 331b of the pattern layer 331 of each wiring section 33, and a part of the plating layer 340b of each wiring section 34. Therefore, the formation of the first plating layer 302 forms a plating layer 311b for each wiring section 31, a plating layer 321b for each wiring section 32, a plating layer 331b for each wiring section 33, and a portion of the plating layer 340b for each wiring section 34. As shown in Figure 16, each pattern layer 311, 321, 331, and 341 has a seed layer 301 in part. Furthermore, as shown in Figure 16, the formed pattern layer 341 is separated into multiple individual patterns 341a by multiple grooves 349. The method for forming each groove 349 is not limited, but for example, the aforementioned resist can be placed in the formation area of ​​each groove 349 to hollow out the first plating layer 302, or regions corresponding to each groove 349 can be removed from a first plating layer of uniform thickness by etching or the like.

[0080] Next, as shown in Figure 17, a second plating layer 303 is formed by electroplating using the seed layer 301 as a conductive path. The material of the second plating layer 303 is the same as the material of the first plating layer 302. The material of the second plating layer 303 may be different from the material of the first plating layer 302, as long as it is a conductive material. Similarly, it may include copper, for example. The second plating layer 303 may contain a different conductive material than the first plating layer 302. The formed second plating layer 303 is laminated onto a part of the individual pattern 341a while filling each groove 349. As a result, a pattern layer 341, a plurality of valleys 342, and a plurality of peaks 343 are formed, as shown in Figure 17. The second plating layer 303 that forms the plurality of valleys 342 and the second plating layer 303 that forms the plurality of peaks 343 may be formed together or individually. The second plating layer 303 is part of the plating layer 340b of the electronic device A10. Therefore, the formation of the first plating layer 302 and the second plating layer 303 results in the formation of the plating layer 340b of each wiring portion 34.

[0081] Next, as shown in Figure 18, a third plating layer 304 is formed by electroplating using the seed layer 301 as a conductive path. The material of the third plating layer 304 is the same as the material of the first plating layer 302. The material of the third plating layer 304 may be different from the material of the first plating layer 302, as long as it is a conductive material. The formed third plating layer 304 is laminated on a part of the pattern layer 331. The third plating layer 304 is the base portion 332 of each wiring portion 33. Therefore, the base portion 332 of each wiring portion 33 is formed by the formation of the third plating layer 304.

[0082] Next, as shown in Figure 19, a fourth plating layer 305 is formed by electroplating using the seed layer 301 as a conductive path. The material of the fourth plating layer 305 is the same as the material of the first plating layer 302. The material of the fourth plating layer 305 may be different from the material of the first plating layer 302, as long as it is a conductive material. The formed fourth plating layer is laminated on a part of the pattern layer 321. The fourth plating layer 305 is the base portion 322 of each wiring portion 32. Therefore, the base portion 322 of each wiring portion 32 is formed by the formation of the fourth plating layer.

[0083] Next, as shown in Figure 20, the unnecessary seed layer 301 is removed. The seed layer 301 is removed, for example, by etching. The seed layer 301 to be removed is the portion of the seed layer 301 formed on the entire surface of the mounting surface 21 that is exposed from each pattern layer 311, 321, 331, 341. After going through the processes shown in Figures 16 to 20 above, multiple wiring sections 31, 32, 33, 34 (wiring layers 3) are formed. Note that the processes shown in Figures 16 to 20 are examples, and the specific processing method is not limited in any way as long as the wiring layer 3 with the shape shown in Figure 15 is formed. Also, the formation order of the second plating layer 303, the third plating layer 304, and the fourth plating layer 305 may differ from the example above, and any two or more of these plating layers may be formed at once.

[0084] Next, as shown in Figure 21, a plurality of barrier layers 352, 353 and a plurality of bonding layers 42 are sequentially formed on the wiring layer 3. The plurality of barrier layers 352, 353 contain a different metal from the wiring layer 3, for example, Ni. Note that the barrier layers 352, 353 to be formed may not only be layers containing Ni, but an alloy layer (for example, a layer made of Sn-Ag alloy) may be further laminated on the Ni layer. The formation of each barrier layer 352, 353 is not limited in any way, but may be done by electroplating, for example. In this electroplating, the seed layer that will serve as the conductive path may be newly formed, or the seed layer 301 that was left in place without being removed may be used. The plurality of bonding layers 42 are each formed individually on the plurality of barrier layers 353. The plurality of bonding layers 42 are formed by, for example, screen printing of solder paste.

[0085] Next, as shown in Figure 21, multiple electronic components 19 are mounted, and then the multiple electronic components 19 are joined together. As shown in Figure 21, in the process of mounting multiple electronic components 19, the electrodes 191 of the electronic components 19 and the bonding layer 42 are placed in correspondence. Next, with each electronic component 19 mounted, reflow is performed. The heat from this reflow melts each bonding layer 42. Note that if each barrier layer 353 has a laminated structure of a Ni layer and an alloy layer, the heat from the reflow mixes the alloy layer of the barrier layer 353 with the bonding layer 42. As a result, only the Ni layer remains in each barrier layer 353. After that, by cooling the molten bonding layer 42, each bonding layer 42 solidifies, and each electronic component 19 is joined together.

[0086] Next, as shown in Figure 23, the semiconductor element 1 is mounted, and then the semiconductor element 1 is joined. For example, the semiconductor element 1 is joined by the process shown in Figures 24 to 26. Note that the mounting (joining) of the semiconductor element 1 may be performed before the mounting (joining) of the multiple electronic components 19.

[0087] In the joining of semiconductor element 1, first, as shown in Figure 24, semiconductor element 1 is prepared. Semiconductor element 1 has a plurality of electrodes 12 (a plurality of pads 121, 122, 123), and a barrier layer 351 is formed on each end face (the face facing downward in the thickness direction z) of the plurality of electrodes 12 (a plurality of pads 121, 122, 123). Furthermore, a joint portion 411 is formed on each pad 121 via the barrier layer 351, a joint portion 412 is formed on each pad 122 via the barrier layer 351, and a joint portion 413 is formed on each pad 123 via the barrier layer 351.

[0088] Next, as shown in Figure 25, the semiconductor element 1 is placed such that the junction 411 corresponds to the pattern layer 311, the junction 412 corresponds to the base portion 322, and each junction 413 corresponds to the base portion 332. In the state shown in Figure 25, each junction 413 is in contact with the barrier layer 352 on the base portion 332, but each junction 411 and each junction 412 are not in contact with the corresponding pattern layer 311 or the barrier layer 352 on the base portion 322.

[0089] Next, as shown in Figure 26, reflow is performed with the semiconductor element 1 placed on it. The heat from this reflow melts each of the joints 411, 412, and 413. At this time, each joint 413 is crushed by the weight of the semiconductor element 1. In addition to the weight of the semiconductor element 1, a pressing force to fix the semiconductor element 1 may also be applied. Due to this crushing of each joint 413, as mentioned above, the sides of each joint 413 become convexly curved. Furthermore, due to the crushing of each joint 413, each joint 411 comes into contact with the barrier layer 352 on the corresponding pattern layer 311, and each joint 412 comes into contact with the barrier layer 352 on the corresponding base portion 322. In addition, each joint 413 ensures a gap (distance) in the thickness direction z between each pad 121 and the corresponding pattern layer 311, and a gap (distance) in the thickness direction z between each pad 122 and the corresponding base portion 322. Therefore, each joint 411 and each joint 412 are not crushed by the weight of the semiconductor element 1, and the sides of each joint 411 and each joint 412 take on the inclined shape as described above. Subsequently, by cooling each joint 411, 412, and 413, each joint 411, 412, and 413 solidifies, and the semiconductor element 1 is joined. Note that if each barrier layer 352 has a laminated structure of a Ni layer and an alloy layer, the heat of reflow causes the alloy layer of the barrier layer 352 to mix with each joint 411, 412, and 413. Therefore, only the Ni layer remains in each barrier layer 352.

[0090] Next, as shown in Figure 27, a sealing resin 6 is formed. The sealing resin 6 is formed above the support member 2 so as to cover the semiconductor element 1, the plurality of electronic components 19, and the wiring layer 3. The sealing resin 6 is formed, for example, by mold molding. The sealing resin 6 is, for example, a synthetic resin mainly composed of black epoxy resin. As the sealing resin 6, other insulating resin materials may be used instead of the synthetic resin.

[0091] Next, as shown in Figure 28, the support substrate 80 is removed. In removing the support substrate 80, for example, in the state shown in Figure 27, the support substrate 80 is ground from the back surface 80b side of the substrate. This grinding is performed on the support substrate 80 from the back surface 80b side of the substrate. In the illustrated example, this grinding is continued even after the removal of the support substrate 80 to reduce the height of the support member 2 and the columnar portion 51. This height reduction is optional.

[0092] Next, as shown in Figure 29, an external electrode portion 52 is formed. The external electrode portion 52 is formed on the top surface of the columnar portion 51 that is exposed from the back surface 22. The external electrode portion 52 is formed, for example, by electroless plating. In this electroless plating, a Ni layer, a Pd layer, and an Au layer are stacked in that order from the side in contact with the columnar portion 51. This forms a plurality of terminals 5, each including a columnar portion 51 and an external electrode portion 52.

[0093] Subsequently, the sealing resin 6 is cut along the cutting line CL shown in Figure 29 to separate it into individual pieces. The sealing resin 6 is cut, for example, by cutting using a dicing blade.

[0094] Through the above steps, the electronic device A10 shown in Figures 1 to 12 is manufactured. However, the manufacturing method of the electronic device A10 is not limited to the example described above. For example, if the support member 2 contains a single-crystal intrinsic semiconductor (e.g., Si), it is manufactured as follows: Grooves are formed in the support substrate 80 (silicon wafer) by etching or the like. Next, a plurality of columnar conductors 851 are formed in the grooves. Then, the wiring layer 3 is formed without forming the first resin layer 82. Furthermore, after the formation of the sealing resin 6, instead of removing the support substrate 80, it is ground until the plurality of columnar conductors 851 formed in the grooves are exposed. In this configuration, the support substrate 80 is an example of the "support member" described in the claims. By changing the process in this way, an electronic device A10 in which the support member 2 is made of a semiconductor material is manufactured.

[0095] The operation and effects of electronic device A10 are as follows:

[0096] In the electronic device A10, the wiring layer 3 (wiring section 34) includes a valley 342 located below the thickness z direction of the bonding layer 42. The bonding layer 42 includes a fixing section 422 that fixes the electrode 191 of the electronic component 19 to the wiring layer 3 (wiring section 34). In a plan view, the fixing section 422 is located inward of the electronic component 19 beyond the valley 342. One defect of the bonding layer 42 that reduces the reliability of the electronic device A10 is the occurrence of cracks. These cracks cause a decrease in the bonding strength between the electrode 191 and the wiring section 34 and lead to poor conductivity between the electrode 191 and the wiring section 34. Figure 30 shows the case where a crack 420 occurs in the bonding layer 42, and the wiring section 34 does not have a valley 342 (right side), and the wiring section 34 does have a valley 342 (left side). The crack 420 tends to propagate along the boundary between the bonding layer 42 and the wiring section 34. Therefore, if the wiring section 34 does not have a valley 342, the crack 420 can easily propagate from the side of the bonding layer 42 to the downward z-thickness direction of the electrode 191. On the other hand, if the wiring section 34 has a valley 342, the valley 342 creates a step at the boundary between the bonding layer 42 and the wiring section 34. This prevents the crack 420 from propagating to the downward z-thickness direction of the electrode 191. Thus, even if a crack 420 occurs in the electronic device A10, it can prevent it from propagating to the fixed section 422. In other words, the electronic device A10 can suppress a decrease in the bonding strength between the electrode 191 and the wiring section 34 and a decrease in conductivity between the electrode 191 and the wiring section 34, thereby suppressing a decrease in reliability.

[0097] In the electronic device A10, each wiring section 34 includes a pattern layer 341, at least one valley 342, and at least one apex 343. The at least one valley 342 is recessed below the pattern layer 341 in the thickness direction z, and the at least one apex 343 protrudes above the pattern layer 341 in the thickness direction z. The at least one valley 342 and the at least one apex 343 are positioned below the bonding layer 42 in the thickness direction z. With this configuration, the surface of each wiring section 34 becomes uneven. Therefore, the bonding strength of the bonding layer 42 can be increased by the anchoring effect. In other words, the reliability of the electronic device A10 can be improved.

[0098] In the electronic device A10, each wiring section 34 includes two valleys 342. The two valleys 342 are spaced apart in the first orthogonal direction OD1 (longitudinal direction) of the corresponding electronic component 19. In each bonding layer 42, the aforementioned cracks 420 are more likely to originate and propagate from the edge of the bonding layer 42 in the first orthogonal direction OD1 than from the edge of the bonding layer 42 in the second orthogonal direction OD2 of the electronic component 19. Therefore, by arranging the two valleys 342 spaced apart in the first orthogonal direction OD1, it is possible to enhance the effect of suppressing the propagation of cracks 420. Furthermore, the two valleys 342 are arranged on opposite sides of each other with a fixing portion 422 in between in the first orthogonal direction OD1 of the corresponding electronic component 19. With this configuration, the electronic device A10 can suppress the propagation of cracks 420 in each bonding layer 42 from the outer edge of the first orthogonal direction OD1 of the corresponding electronic component 19, while also suppressing the propagation of cracks 420 from the inner edge of the first orthogonal direction OD1 of the corresponding electronic component 19.

[0099] In the electronic device A10, each of the two valleys 342 of each wiring section 34 extends in the second orthogonal direction OD2 (short side direction) of the corresponding electronic component 19 and is parallel to each other. With this configuration, even if a crack 420 occurs, it is possible to suppress the propagation of the crack 420 along the first orthogonal direction OD1 to the fixing section 422. In particular, in the electronic device A10, as shown in Figure 5, in a plan view, each valley 342 is continuous from one edge to the other in the second orthogonal direction OD2 of the corresponding bonding layer 42. With this configuration, the range in which the propagation of the crack 420 is suppressed by each valley 342 connects from one edge to the other in the second orthogonal direction OD2 of the bonding layer 42. Therefore, even if a crack 420 occurs, the electronic device A10 can enhance the effect of suppressing the propagation of the crack 420.

[0100] In electronic device A10, the joint 411 is interposed between the pad 121 and the wiring portion 31. As shown in Figure 11, the gap ΔG1 in the thickness direction z between the pad 121 and the wiring portion 31 is larger than the gap ΔG3 in the thickness direction z between the pad 123 and the wiring portion 33. This configuration ensures an appropriate gap for positioning the joint 411 between the pad 121 and the wiring portion 31. Such a gap prevents excessive pressure from being applied to the joint 411 during the bonding of the semiconductor element 1. Therefore, it is possible to prevent cracks from occurring in the joint 411 and prevent damage to the joint 411. In other words, since defects in the joint 411 can be suppressed in electronic device A10, a decrease in reliability can be suppressed. In particular, in electronic device A10, the joint 413 is positioned between the pad 123 and the wiring portion 33. In this configuration, when the semiconductor element 1 is joined (mounted), the joint 413 contacts the wiring layer 3 (base portion 332) before the joint 411 (see Figure 25). This makes it possible to concentrate the pressure due to the weight of the semiconductor element 1 on the joint 413. As a result, the electronic device A10 can prevent excessive pressure from being applied to the joint 411.

[0101] In electronic device A10, joint 411 is interposed between pad 121 and wiring portion 31, and joint 412 is interposed between pad 122 and wiring portion 32. As shown in Figure 9, the center position h411 in the thickness direction z of joint 411 and the center position h412 in the thickness direction z of joint 412 are different from each other. With this configuration, when bonding the semiconductor element 1, a difference can be created between how pressure is applied to joint 411 and how pressure is applied to joint 412. This makes it possible to distribute the pressure applied to the two joints 411 and 412. Therefore, it is possible to suppress the occurrence of cracks in each joint 411 and 412, and to prevent damage to each joint 411 and 412. In other words, since electronic device A10 can suppress defects in each joint 411 and 412, a decrease in reliability can be suppressed.

[0102] In the electronic device A10, the support member 2 includes a resin material, which is the same as the sealing resin 6. With this configuration, the difference between the coefficient of thermal expansion of the support member 2 and the coefficient of thermal expansion of the sealing resin 6 can be reduced, thereby suppressing the thermal stress generated in the electronic device A10.

[0103] Other embodiments and modifications of the electronic device of this disclosure are described below. The configurations of the parts in each embodiment and each modification are interchangeable to the extent that no technical inconsistencies arise.

[0104] Figure 31 shows an electronic device A11 according to a first modification of the first embodiment. Figure 31 corresponds to the cross-section of Figure 8 in electronic device A10. Electronic device A11 differs from electronic device A10 in the following respect: In each wiring section 34, at least one of the multiple valleys 342 is positioned, in a plan view, outward in the first orthogonal direction OD1 (longitudinal direction) of the corresponding electronic component 19 than the electrode 191 of the electronic component 19.

[0105] As shown in Figure 31, the crack 420 may propagate from the fillet 423 in the thickness direction z. In the electronic device A11, the propagation of such a crack 420 can be guided to the valley 342 located outward from the electrode 191 in the first orthogonal direction OD1.

[0106] Figure 32 shows an electronic device A12 according to a second modification of the first embodiment. Figure 32 corresponds to Figure 5 in the electronic device A10. Electronic device A12 differs from electronic device A10 in that each valley 342 is surrounded by a vertex 343 in a plan view.

[0107] In the electronic device A12, the entirety of each valley 342 overlaps the corresponding bonding layer 42 in a plan view. Also, each valley 342 is surrounded by the apex 343 in a plan view and therefore does not come into contact with the pattern layer 341.

[0108] Figure 33 shows an electronic device A13 according to a third modification of the first embodiment. Figure 33 corresponds to Figure 5 in the electronic device A10. Electronic device A13 differs from electronic device A10 in that multiple valleys 342 are arranged in a grid pattern.

[0109] In the example shown in Figure 33, in each wiring section 34, multiple valleys 342 are arranged in three rows along the first orthogonal direction OD1 (longitudinal direction) of the corresponding electronic component 19. Within each row, the multiple valleys 342 are arranged along the second orthogonal direction OD2 (short direction) of the electronic component 19. Furthermore, of these three rows, the multiple valleys 342 in each row on either side of the first orthogonal direction OD1 and the multiple valleys 342 in the central row are arranged alternately along the second orthogonal direction OD2 (short direction) of the electronic component 19.

[0110] Figure 34 shows an electronic device A14 according to a fourth modification of the first embodiment. Figure 34 corresponds to Figure 5 in the electronic device A10. Electronic device A14 differs from electronic device A10 in that the valley portion 342 includes a strip portion 342a and a pair of strip portions 342b.

[0111] The strip portion 342a extends in the short-side direction (second orthogonal direction OD2, and in the example shown in Figure 34, the second direction y) of the corresponding electronic component 19 in a plan view. The pair of strip portions 342b extend in the longitudinal direction (first orthogonal direction OD1, and in the example shown in Figure 34, the first direction x) of the corresponding electronic component 19 in a plan view. The pair of strip portions 342b are individually connected to both ends of the strip portion 342a in the short-side direction (second orthogonal direction OD2, and in the example shown in Figure 34, the second direction y). In this modified example, the fixing portion 422 of the bonding layer 42 is located in the region demarcated by the valley portion 342 in a plan view.

[0112] Figure 35 shows an electronic device A15 according to a fifth modified example of the first embodiment. Figure 35 corresponds to Figure 5 in the electronic device A10. Electronic device A15 differs from electronic device A10 in that the valley portion 342 is rectangular in ring shape in plan view.

[0113] In the electronic device A15, each wiring section 34 includes, in a plan view, a top section 343 located inside the valley section 342 (in the region demarcated by the valley section 342) and a top section 343 located outside the valley section 342. In this modified example, the fixing section 422 of the bonding layer 42 overlaps, in a plan view, the top section 343 located inside the valley section 342 (in the region demarcated by the valley section 342).

[0114] Figure 36 shows an electronic device A16 according to a sixth modified example of the first embodiment. Figure 36 corresponds to the cross-section of electronic device A10 in Figure 8. Electronic device A16 differs from electronic device A10 in that, in each wiring section 34, the valleys 342 and the peaks 343 are not adjacent.

[0115] In each wiring section 34 of the electronic device A16, the valleys 342 and apex 343 are arranged via a pattern layer 341. In the illustrated example, the pattern layer 341 is interposed between the valleys 342 and apex 343, but there may be a mixture of cases where the valleys 342 and apex 343 are adjacent and cases where the pattern layer 341 is interposed between the valleys 342 and apex 343.

[0116] Each of the above electronic devices A11 to A16, like electronic device A10, has a wiring layer 3 (wiring section 34) that includes a valley 342 and a bonding layer 42 that includes a fixing section 422. The fixing section 422 is positioned inward of the electronic component 19 from the valley 342 in a plan view. Therefore, each of the electronic devices A11 to A16, like electronic device A10, can prevent cracks from progressing to the fixing section 422 even if a crack occurs in the bonding layer 42. In other words, each of the electronic devices A11 to A16, like electronic device A10, can suppress a decrease in bonding strength between the electrode 191 and the wiring section 34 and poor conductivity between the electrode 191 and the wiring section 34, thus suppressing a decrease in reliability. Furthermore, each of the electronic devices A11 to A16, having a configuration common to electronic device A10, achieves the same effects as electronic device A10.

[0117] In each of the above electronic devices A14 and A15, the valley portion 342 has a portion that extends in the first orthogonal direction OD1 of the corresponding electronic component 19. With this configuration, it is possible to suppress the propagation of cracks from the edge of the bonding layer 42 in the second orthogonal direction OD2 to the fixed portion 422 along the second orthogonal direction OD2.

[0118] In the above-described electronic device A16, since many steps are created on the surface of each wiring section 34, the bonding strength between each wiring section 34 and the bonding layer 42 can be further increased by the anchoring effect.

[0119] Figure 37 shows an electronic device A20 according to the second embodiment. Figure 37 corresponds to the cross-section of Figure 8 in electronic device A10. Electronic device A20 differs from electronic device A10 in the following respect: each valley 342 does not contain a plating layer 340b.

[0120] In the electronic device A20, each valley 342 is composed of a seed layer 340a. Each wiring section 34 in the electronic device A20 is formed as follows. For example, in the process of forming the second plating layer in the manufacturing method of the electronic device A10 (see Figure 17), the grooves 349 are formed by not filling them with the second plating layer.

[0121] Similar to electronic device A10, electronic device A20 has a wiring layer 3 (wiring section 34) that includes valleys 342 and a bonding layer 42 that includes a fixing section 422. The fixing section 422 is positioned inward of the electronic component 19 from the valleys 342 in a plan view. Therefore, similar to electronic device A10, even if a crack occurs in the bonding layer 42, electronic device A20 can prevent it from progressing to the fixing section 422. In other words, similar to electronic device A10, electronic device A20 can suppress a decrease in bonding strength between the electrode 191 and the wiring section 34 and poor conductivity between the electrode 191 and the wiring section 34, thus suppressing a decrease in reliability. Furthermore, electronic device A20, having a configuration common to electronic device A10, achieves the same effects as electronic device A10. Also, as can be understood from electronic device A20, in the electronic devices of this disclosure, there is no limitation as to whether or not each valley 342 includes a plating layer 340b.

[0122] Figure 38 shows an electronic device A30 according to the third embodiment. Figure 38 corresponds to the cross-section of Figure 8 in electronic device A10. Electronic device A30 differs from electronic device A10 in the following respect: the bottom surface (surface facing upward in the thickness direction z) of each valley 342 is at the same height as the top surface (surface facing upward in the thickness direction z) of the pattern layer 341 in the thickness direction z.

[0123] In the electronic device A30, the thickness of the plating layer 340b in each valley 342 is approximately the same as the thickness of the plating layer 340b in the pattern layer 341. The thickness of the plating layer 340b in each apex 343 is greater than the thickness of the plating layer 340b in the pattern layer 341 and in each valley 342. Therefore, in each wiring section 34, multiple apex 343 protrude upward in the thickness direction z from the pattern layer 341, so that the region sandwiched between multiple apex 343 is arranged as a valley 342. Each wiring section 34 of the electronic device A30 is formed as follows. For example, in the process of forming the first plating layer in the manufacturing method of the electronic device A10 (see Figure 16), it is formed by not providing each groove 349.

[0124] Electronic device A30, like electronic devices A10 and A20, has a wiring layer 3 (wiring section 34) that includes a valley 342 and a bonding layer 42 that includes a fixing section 422. The fixing section 422 is positioned inward of the electronic component 19 from the valley 342 in a plan view. Therefore, like electronic devices A10 and A20, even if a crack occurs in the bonding layer 42, electronic device A30 can prevent it from progressing to the fixing section 422. In other words, like electronic devices A10 and A20, electronic device A30 can suppress a decrease in bonding strength between the electrode 191 and the wiring section 34 and poor conductivity between the electrode 191 and the wiring section 34, thus suppressing a decrease in reliability. Furthermore, electronic device A30 has a configuration common to electronic devices A10 and A20 and therefore achieves the same effects as those electronic devices A10 and A20. Furthermore, as can be understood from electronic device A30, in the electronic device of this disclosure, there is no limitation on whether each valley 342 is recessed from the pattern layer 341 or not.

[0125] Figure 39 shows an electronic device A40 according to the fourth embodiment. Figure 39 corresponds to the cross-section of Figure 8 in electronic device A10. Electronic device A40 differs from electronic device A10 in the following respect: each wiring section 34 does not include any of the multiple top sections 343.

[0126] In the electronic device A40, a portion of each wiring section 34 is recessed downward in the thickness direction z by multiple valleys 342.

[0127] Electronic device A40, like electronic devices A10, A20, and A30, has a wiring layer 3 (wiring section 34) that includes a valley 342 and a bonding layer 42 that includes a fixing section 422. The fixing section 422 is positioned inward of the electronic component 19 from the valley 342 in a plan view. Therefore, like electronic devices A10, A20, and A30, even if a crack occurs in the bonding layer 42, electronic device A40 can prevent it from progressing to the fixing section 422. In other words, electronic device A40, like electronic devices A10, A20, and A30, can suppress a decrease in bonding strength between the electrode 191 and the wiring section 34 and poor conductivity between the electrode 191 and the wiring section 34, thus suppressing a decrease in reliability. Furthermore, electronic device A40 has a configuration common to electronic devices A10, A20, and A30, and therefore achieves the same effects as those electronic devices A10, A20, and A30. Furthermore, as can be understood from electronic device A40, in the electronic devices of this disclosure, there is no limitation on whether or not each wiring section 34 includes a top section 343.

[0128] In the electronic device of this disclosure, the sealing resin 6 may have steps on each resin side surface 63. For example, Figure 40 shows an electronic device according to such a modification, applied to the electronic device A10 according to the first embodiment. Figure 40 corresponds to the cross-section of the electronic device A10 in Figure 12. In the electronic device shown in Figure 40, at each of the multiple terminals 5, the external electrode portion 52 is also formed on the surface exposed from the side surface 23 of the columnar portion 51. With this configuration, when the electronic device shown in Figure 40 is mounted on the aforementioned circuit board, fillets can be formed in the conductive bonding material (for example, solder) used at the time of mounting. Therefore, it becomes easy to visually inspect whether the electronic device shown in Figure 40 is properly bonded to the aforementioned circuit board.

[0129] In the electronic device of this disclosure, the number and arrangement of each semiconductor element 1 and electronic component 19, the pattern of the wiring layer 3, and the number and arrangement of terminals 5 are not limited to the illustrated examples. They may be modified as appropriate depending on the specifications (size, performance, etc.) of the electronic device of this disclosure.

[0130] The electronic device of this disclosure is not limited to a configuration comprising all of the semiconductor element 1 and the plurality of electronic components 19, but may be provided with at least one electronic component 19. For example, the electronic device of this disclosure may be a configuration comprising only one electronic component 19 (a discrete device).

[0131] The electronic devices relating to this disclosure are not limited to the embodiments described above. The specific configurations of each part of the electronic devices relating to this disclosure can be modified in various ways. For example, the electronic devices relating to this disclosure include embodiments relating to the following appendices. Note 1. An electronic component having an electrode positioned at one end in a first orthogonal direction perpendicular to the thickness direction, A wiring layer including a wiring portion that is electrically connected to the electrode, A bonding layer that joins the electrode and the wiring portion, Equipped with, The wiring portion includes a valley portion located in one of the thickness directions of the bonding layer, The bonding layer includes a fixing portion for fixing the electrode to the wiring portion, The fixing portion is positioned further inward from the valley portion of the electronic component in the electronic device. Note 2. The aforementioned wiring section includes a pattern layer that forms a current conduction path, as described in Appendix 1 of the electronic device. Note 3. The wiring portion includes a top portion that protrudes from the pattern layer in the thickness direction, and is an electronic device as described in Appendix 2. Note 4. The valley portion is the electronic device described in Appendix 3, adjacent to the apex portion. Note 5. The valley portion is recessed in the thickness direction from the pattern layer, as described in any of Appendix 2 to Appendix 4 of the electronic device. Note 6. The electronic device according to any one of Appendix 2 to Appendix 5, wherein the pattern layer comprises a seed layer and a plating layer laminated on the seed layer. Note 7. The aforementioned wiring section includes a second valley, with the valley being designated as the first valley. The electronic device according to any one of Appendix 1 to Appendix 6, wherein the first valley and the second valley are arranged on opposite sides of the fixing portion in the first orthogonal direction when viewed in the thickness direction. Note 8. Each of the first valley and the second valley extends in a second orthogonal direction perpendicular to the thickness direction and the first orthogonal direction, The electronic device described in Appendix 7, wherein the first valley and the second valley are parallel to each other. Note 9. The bonding layer includes a fillet connected to the fixing portion, as described in any one of Appendix 1 to Appendix 8 of the electronic device. Note 10. The electronic device according to any one of the appendices 1 to 9, comprising a barrier layer interposed between the bonding layer and the wiring portion. Note 11. The electronic device as described in Appendix 10, wherein the surface of the barrier layer is uneven along the surface of the wiring portion. Note 12. The aforementioned bonding layer is solder, as described in any of Appendix 1 to Appendix 11. Note 13. The electronic device according to any one of appendices 1 to 12, further comprising a sealing resin covering the aforementioned electronic component. Note 14. The system further comprises a support member for supporting the aforementioned electronic component, The support member has a mounting surface on which the electronic components are mounted via the wiring layer, as described in any one of Appendix 1 to Appendix 13. Note 15. The electronic component further comprises terminals that provide electrical conductivity to the aforementioned electronic component. The electronic device according to Appendix 14, wherein the terminal includes a columnar portion that penetrates the support member and an external electrode portion that covers the portion of the columnar portion that is exposed from the support member. [Explanation of symbols]

[0132] A10~A16,A20,A30,A40:Electronic equipment 1: Semiconductor element 10a: Opposing surface 10b: Top surface of element 11: Main body 12: Electrode 121: Pad 1211,1212: Metal layer 121a: End face 122: Pad 1221: Metal layer 122a: End face 123: Pad 1231,1232: Metal layer 123a: End face 19: Electronic components 191: Electrode 2: Support member 21: Mounting surface 22: Back side 23: Side view 3: Wiring layer 301: Seed layer 302: First plating layer 303: Second plating layer 304: Third plating layer 305: Fourth plating layer 31:Wiring section 31a: Main wiring side 311: Pattern layer 311a: Seed layer 311b: Plating layer 32:Wiring section 32a: Main wiring side 321: Pattern Layer 321a: Seed layer 321b: Plating layer 322: Base 33:Wiring section 33a: Main wiring side 331: Pattern Layer 331a: Seed layer 331b: Plating layer 332: Base 34:Wiring section 340a: Seed layer 340b: Plating layer 341: Pattern Layer 341a: Individual Pattern 341b: Plating layer 342: Tanibe 342a,342b: Band-shaped area 343:Top 349: Groove 351, 352, 353: Barrier layer 41: Bonding layer 411: Joint 411a: Side 412: Joint 412a: Side 413: Joint 413a: Side view 42: Bonding layer 420: Crack 421: Interposition part 422: Fixing part 423: Fillet 5: Terminals 51: Columnar part 52:External electrode part 6: Sealing resin 61: Resin main surface 62: Resin back 63: Resin side 80: Support substrate 80a: Main surface of the substrate 80b: Back of the circuit board 82: 1st resin layer 821: Main surface 822: Bottom 851: Columnar conductor CL: Cutting line h411,h412: Center position ΔG1, ΔG2, ΔG3: gap

Claims

1. An electronic component having an electrode positioned at one end in a first orthogonal direction perpendicular to the thickness direction, A wiring layer including a wiring portion that is electrically connected to the electrode, A bonding layer that joins the electrode and the wiring portion, Equipped with, The wiring portion includes a valley portion located in one of the thickness directions of the bonding layer, The bonding layer includes a fixing portion for fixing the electrode to the wiring portion, The fixing portion is positioned further inward from the valley portion of the electronic component in the electronic device.

2. The electronic device according to claim 1, wherein the wiring portion includes a pattern layer that forms a current conduction path.

3. The wiring portion includes a top portion that protrudes from the pattern layer in the thickness direction, as described in claim 2.

4. The valley portion is adjacent to the apex portion, as described in claim 3.

5. The electronic device according to claim 4, wherein the valley portion is recessed in the thickness direction from the pattern layer.

6. The electronic device according to any one of claims 2 to 5, wherein the pattern layer comprises a seed layer and a plating layer laminated on the seed layer.

7. The aforementioned wiring section includes a second valley, with the valley being designated as the first valley. The electronic device according to any one of claims 1 to 5, wherein the first valley and the second valley are arranged on opposite sides of the fixing portion in the first orthogonal direction when viewed in the thickness direction.

8. Each of the first valley and the second valley extends in a second orthogonal direction perpendicular to the thickness direction and the first orthogonal direction, The electronic device according to claim 7, wherein the first valley and the second valley are parallel to each other.

9. The electronic device according to any one of claims 1 to 5, wherein the bonding layer includes a fillet connected to the fixed portion.

10. The electronic device according to any one of claims 1 to 5, further comprising a barrier layer interposed between the bonding layer and the wiring portion.

11. The electronic device according to claim 10, wherein the surface of the barrier layer is uneven along the surface of the wiring portion.

12. The electronic device according to any one of claims 1 to 5, wherein the bonding layer is solder.

13. The electronic device according to any one of claims 1 to 5, further comprising a sealing resin covering the electronic component.

14. The system further comprises a support member for supporting the aforementioned electronic component, The electronic device according to any one of claims 1 to 5, wherein the support member has a mounting surface on which the electronic component is mounted via the wiring layer.

15. The electronic component further comprises terminals that provide electrical conductivity to the aforementioned electronic component. The electronic device according to claim 14, wherein the terminal includes a columnar portion that penetrates the support member and an external electrode portion that covers the portion of the columnar portion that is exposed from the support member.

Images