memory devices

Abstract

To improve the operating characteristics of memory devices. [Solution] The memory device of the embodiment comprises a first string including a first memory cell and a first transistor, a second string including a second memory cell and a second transistor, a word line connected to the gates of the first and second memory cells, a first wire connected to the gate of the first transistor, a second wire connected to the gate of the second transistor and adjacent to the first wire, and a control circuit for controlling the operation of the first and second strings, wherein the control circuit applies a positive first voltage to the word line, a positive second voltage to the first wire, and a negative third voltage to the second wire when performing an operation on the first string.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory device.

Background Art

[0002] As a memory device capable of storing data non-volatily, a NAND flash memory is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] Improve the operating characteristics of the memory device.

Means for Solving the Problems

[0005] The memory device of the embodiment comprises a first string including a plurality of first memory cells and a first transistor connected to one end of the plurality of first memory cells; a second string including a plurality of second memory cells and a second transistor connected to one end of the plurality of second memory cells; a plurality of word lines connected to each of the gates of the plurality of first memory cells and each of the gates of the plurality of second memory cells; a first wire connected to the gate of the first transistor; a second wire connected to the gate of the second transistor and adjacent to the first wire; and a control circuit for controlling the operation of the first and second strings, wherein the control circuit is configured to apply a first voltage having a positive voltage value to each of the plurality of word lines, apply a second voltage having a positive voltage value to the first wire, and apply a third voltage having a negative voltage value to the second wire when performing an operation on the first string as the target of operation. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example configuration of a memory device according to the first embodiment. [Figure 2] A circuit diagram showing an example configuration of a memory cell array of a memory device according to the first embodiment. [Figure 3] A diagram showing the relationship between data and the threshold voltage of a memory cell. [Figure 4] A schematic diagram showing an example of the structure of a memory device according to the first embodiment. [Figure 5] A plan view showing an example of the structure of a memory cell array in a memory device according to the first embodiment. [Figure 6] A cross-sectional view showing an example of the structure of a memory cell array in a memory device according to the first embodiment. [Figure 7] A cross-sectional view showing an example of a memory pillar structure. [Figure 8] A plan view showing an example of the structure of the select gate line of a memory device according to the first embodiment. [Figure 9] A plan view showing an example of the structure of the select gate line of a memory device according to the first embodiment. [Figure 10] Schematic diagram showing the outline of the operation of the memory device of the first embodiment. [Figure 11] Schematic diagram showing the outline of the operation of the memory device of the first embodiment. [Figure 12] Timing chart showing an operation example of the memory device of the first embodiment. [Figure 13] Schematic diagram showing the outline of the operation of the memory device of the second embodiment. [Figure 14] Schematic diagram showing the outline of the operation of the memory device of the second embodiment. [Figure 15] Timing chart showing an operation example of the memory device of the second embodiment. [Figure 16] Timing chart showing an operation example of the memory device of the third embodiment. [Figure 17] Cross-sectional view showing a structural example of the memory cell array of the memory device of the fourth embodiment. [Figure 18] Schematic diagram for explaining the configuration and operation of the memory device of the fourth embodiment. \ [Figure 19] Schematic diagram showing the outline of the operation of the memory device of the fifth embodiment. [Figure 20] Timing chart showing an operation example of the memory device of the fifth embodiment. [Figure 21] Plan view showing a structural example of the memory cell array of the memory device of the sixth embodiment. [Figure 22] Cross-sectional view showing a structural example of the memory cell array of the memory device of the sixth embodiment. [Figure 23] Cross-sectional view showing a structural example of the memory cell array of the memory device of the sixth embodiment. [Figure 24] Plan view showing a structural example of the select gate line of the memory device of the sixth embodiment. [Figure 25] Plan view showing a structural example of the select gate line of the memory device of the sixth embodiment. [Figure 26] Circuit diagram showing a configuration example of the memory cell array of the memory device of the sixth embodiment. [Figure 27] Timing chart showing an operation example of the memory device according to the sixth embodiment. [Figure 28] Timing chart showing an operation example of the memory device according to the sixth embodiment. [Figure 29] Cross-sectional view showing a structural example of the memory cell array of the memory device according to the seventh embodiment. [Figure 30] Planar view showing a structural example of the select gate line of the memory device according to the seventh embodiment. [Figure 31] Circuit diagram showing a configuration example of the memory cell array of the memory device according to the seventh embodiment. [Figure 32] Planar view showing a structural example of the select gate line of the memory device according to the eighth embodiment. [Figure 33] Planar view showing a structural example of the select gate line of the memory device according to the eighth embodiment. [Figure 34] Cross-sectional view showing a structural example of the memory cell array of the memory device according to the eighth embodiment. [Figure 35] Cross-sectional view showing a structural example of the memory cell array of the memory device according to the eighth embodiment. [Figure 36] Circuit diagram showing a configuration example of the memory cell array of the memory device according to the eighth embodiment. [Figure 37] Cross-sectional view showing a structural example of the memory cell array of the memory device according to the ninth embodiment. [Figure 38] Cross-sectional view showing a structural example of the memory cell array of the memory device according to the ninth embodiment.

Mode for Carrying Out the Invention

[0007] (Embodiment) The embodiment of the memory device and the control method for the memory device will be described with reference to Figures 1 to 38. In the following description, elements having the same function and configuration will be denoted by the same reference numeral. In addition, in each of the following embodiments, if components that are denoted by reference numerals with distinguishing numerals / letters at the end (for example, circuits, wiring, various voltages and signals, etc.) do not need to be distinguished from one another, the description (reference numeral) will be used without the suffix numerals / letters.

[0008] (1) First Embodiment Referring to Figures 1 to 12, a memory device and a control method for the memory device according to the first embodiment will be described.

[0009] (a) Configuration example An example of the configuration of the memory device of this embodiment will be described with reference to Figures 1 to 9.

[0010] (a-1) Circuit configuration The circuit configuration of the memory device of this embodiment will be described with reference to Figures 1 to 3.

[0011] (a-1-1) Internal configuration of a memory device Figure 1 is a block diagram showing an example configuration of a memory system including the memory device of this embodiment.

[0012] The memory system MS in Figure 1 is a storage device configured to connect to an external host device (not shown). The memory system MS is, for example, an SD TM These are memory cards, UFS (Universal Flash Storage), or SSDs (Solid State Drives).

[0013] The memory system MS includes the memory device 1 and the memory controller 2 of this embodiment.

[0014] The memory controller 2 is comprised of an integrated circuit, such as a System on a Chip (SoC). The memory controller 2 controls the memory device 1 based on requests from the host device. Specifically, the memory controller 2 writes data requested by the host device to the memory device 1. The memory controller 2 reads data requested by the host device from the memory device 1 and transfers it to the host device.

[0015] Memory device 1 is, for example, a semiconductor memory capable of storing data non-volatilely. An example of memory device 1 is a NAND flash memory.

[0016] Communication between memory device 1 and memory controller 2 conforms to, for example, an SDR (Single Data Rate) interface, a toggle DDR (Toggle Double Data Rate) interface, or an ONFI (Open NAND Flash Interface).

[0017] The memory device 1 includes, for example, a memory cell array 10, an input / output circuit 11, a logic control circuit 12, a register 13, a sequencer 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0018] The memory cell array 10 is a collection of multiple memory cells and multiple select transistors. The memory cell array 10 includes multiple block blocks. A block block is a collection of multiple memory cells capable of storing data non-volatilely. A block block is used, for example, as an erase unit when erasing data stored in a memory cell. Multiple bit lines and multiple word lines are provided within the memory cell array 10. Each memory cell is associated, for example, with a combination of one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0019] The input / output circuit 11 is an interface circuit that handles the transmission and reception of input / output signals DQ between the memory device 1 and the memory controller 2. The input / output signals DQ include, for example, data DAT, command CMD, address ADD, and status information STA. The input / output circuit 11 inputs and outputs data DAT between the sense amplifier module 17 and the memory controller 2, respectively. The input / output circuit 11 outputs command CMD and address ADD, respectively, transferred from the memory controller 2, to register 13. The input / output circuit 11 outputs status information STA, transferred from register 13, to the memory controller 2. The input / output circuit 11 performs the transmission and reception of input / output signals DQ at a timing synchronized with signal DQS.

[0020] The logic control circuit 12 receives various control signals input from the memory controller 2. Based on the control signals, the logic control circuit 12 controls the input / output circuit 11 and the sequencer 14, respectively. For example, the logic control circuit 12 notifies the input / output circuit 11 that the input / output signal it received is a command CMD or address ADD, etc. The logic control circuit 12 commands the input / output circuit 11 to input or output the input / output signal. The logic control circuit 12 controls the sequencer 14 and enables the memory device 1.

[0021] For example, the logic control circuit 12 receives the chip enable signal CEn, command latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, and read enable signal REn from the memory controller 2. The chip enable signal CEn is a signal to enable the chip of memory device 1. The command latch enable signal CLE is a signal indicating that the signal DQ received by memory device 1 is the command CMD. The address latch enable signal ALE is a signal indicating that the signal DQ received by memory device 1 is the address ADD. The write enable signal WEn is a signal that commands memory device 1 to input the input / output signal DQ. The read enable signal REn is a signal that commands memory device 1 to output the input / output signal DQ. Memory device 1 generates the signal DQS based on the read enable signal REn.

[0022] The logic control circuit 12 outputs a ready / busy signal RBn to the memory controller 2, indicating whether the memory device 1 is in a ready state or a busy state.

[0023] Register 13 temporarily stores the command CMD, address ADD, and status information STA. The command CMD includes, for example, instructions to cause the sequencer 14 to perform read operations, write operations, erase operations, etc. Address ADD includes, for example, the block address BA, page address PA, and column address CA. For example, the block address BA, page address PA, and column address CA are used for selecting the block BLK, word line, and bit line, respectively. The status information STA is updated based on the control of the sequencer 14 and transferred to the input / output circuit 11.

[0024] The sequencer 14 controls the overall operation of the memory device 1. For example, the sequencer 14 controls the driver module 15, the row decoder module 16, and the sense amplifier module 17, etc., based on the command CMD stored in register 13. This enables operations such as reading, writing, or erasing to be performed.

[0025] The driver module 15 generates multiple voltages of different magnitudes used in read, write, and erase operations. The driver module 15 supplies the generated voltages to the row decoder module 16 and the sense amplifier module 17, etc. The driver module 15 applies the generated voltages to the signal lines corresponding to the word lines selected based on the page address PA stored in register 13, for example. For example, the driver module 15 includes a negative voltage generation circuit 150. The negative voltage generation circuit 150 generates a negative voltage lower than 0V.

[0026] The row decoder module 16 selects a corresponding block BLK in the memory cell array 10 based, for example, on the block address BA stored in register 13. The row decoder module 16 then transfers, for example, the voltage supplied to the signal line by the driver module 15 to the selected word line in the selected block BLK.

[0027] The sense amplifier module 17 includes a sense amplifier capable of determining data based on the voltage of the associated bit line, a data latch circuit for temporarily storing data, and the like. In a write operation, the sense amplifier module 17 applies a desired voltage to each bit line according to the write data DAT transferred from the input / output circuit 11. In a read operation, the sense amplifier module 17 determines the data stored in the memory cell based on the presence or absence of discharge in the bit line or the magnitude of the bit line voltage. Subsequently, the sense amplifier module 17 transfers the determination result as read data DAT to the input / output circuit 11.

[0028] In the following, the set of circuits 11, 12, 13, 14, 15, 16, and 17 other than the memory cell array 10 in the memory device 1 is referred to as a CMOS circuit (or control circuit).

[0029] (a-1-2) Circuit configuration of memory cell array Figure 2 is a circuit diagram showing an example of the configuration of a memory cell array in the memory device 1 of this embodiment. In Figure 2, the circuit configuration of a certain block BLK included in the memory cell array 10 is shown as an example.

[0030] As shown in Figure 2, block BLK includes, for example, four string units SU0, SU1, SU2, and SU3. Each string unit SU is a set of multiple NAND strings (memory strings) NS that are selected collectively in a write or read operation. Each string unit SU includes multiple NAND strings NS associated with bit lines BL0, BL1, ..., BLm-1, respectively, where m is an integer greater than or equal to 1. A NAND string NS is a set of multiple memory cells MC (MC0, MC1, MC2, ..., MCn-2, MCn-1) connected in series. Each NAND string NS includes, for example, memory cells MC0, MC1, MC2, ..., MCn-2, MCn-1, select transistor ST1, and select transistor ST2, where n is an integer greater than or equal to 1.

[0031] A memory cell (also called a memory cell transistor) MC is a field-effect transistor that includes a control gate and a charge storage layer.

[0032] The select transistors ST1 and ST2 are switching elements. Each of the select transistors ST1 and ST2 is used to select the string unit SU during various operations.

[0033] In each NAND string NS, memory cells MC0, ..., MCn-1 are connected in series. The drain of select transistor ST1 is connected to the associated bit line BL. The source of select transistor ST1 is connected to one end of the series-connected memory cells MC0, ..., MCn-1. The drain of select transistor ST2 is connected to the other end of the series-connected memory cells MC0, ..., MCn-1. The source of select transistor ST2 is connected to the source line SL.

[0034] Within the same block BLK, each control gate of memory cells MC0, MC1, MC2, ..., MCn-2, MCn-1 is commonly connected to each of the word lines WL0, WL1, WL2, ..., WLn-2, ​​WLn-1 across multiple NAND strings NS.

[0035] The gate of each select transistor ST1 in string units SU0, SU1, SU2, and SU3 is connected in common between multiple NAND strings NS to one of the multiple drain-side select gate lines SGD0, SGD1, SGD2, and SGD3.

[0036] The gate of each select transistor ST2 within string units SU0, SU1, SU2, and SU3 is connected in common between multiple NAND strings NS to one of the multiple source-side select gate lines SGS0, SGS1, SGS2, and SGS3.

[0037] In the following, when drain-side select gate lines SGD (SGD0, SGD1, SGD2, SGD3) and source-side select gate lines SGS (SGS0, SGS1, SGS2, SGS3) are not distinguished, they are referred to as select gate lines SG.

[0038] In the circuit configuration of the memory cell array 10 described above, the bit line BL is shared, for example, by NAND strings NS to which the same column address is assigned in each string unit SU. The source line SL is shared, for example, by multiple string units SU and multiple blocks BLK.

[0039] In the following, a collection of memory cells MCs CU that are commonly connected to the same word line WL within a string unit SU is also called a cell unit CU.

[0040] Memory cell MCs (Memory Cells) store one or more bits of data. A memory cell MC that stores one bit of data is called an SLC (Single Level cell). A memory cell MC that stores two bits of data is called an MLC (Multi Level cell). A memory cell MC that stores three bits of data is called a TLC (Triple Level cell). A memory cell MC that stores four bits of data is called a QLC (Quad Level cell). A memory cell MC that stores five bits of data is called a PLC (Penta Level cell).

[0041] In this example, one memory cell (MC) stores 3 bits of data. Hereafter, these 3 bits of data are referred to as the lower bits, middle bits, and upper bits, from least significant to most significant. The set of lower bits held by memory cells (MCs) belonging to the same cell unit (CU) is called the lower page (or lower data), the set of middle bits is called the middle page (or middle data), and the set of upper bits is called the upper page (or upper data).

[0042] If a single memory cell MC can store 3 bits of data, then 3 pages are allocated to a single word line WL (a single cell unit CU) within a single string unit SU. A “page” can also be defined as a portion of the memory space formed within a cell unit CU. Data writing and reading may be performed on a page-by-page basis or on a cell unit CU basis.

[0043] The number of string units SU within block BLK is arbitrary.

[0044] (a-1-3) Relationship between the threshold voltage of a memory cell and the data Referring to Figure 3, the relationship between the threshold voltage of the memory cell MC and the data stored in the memory cell MC in the memory device 1 of this embodiment will be explained.

[0045] Figure 3 is a schematic diagram illustrating the relationship between the data stored in a memory cell (MC) and the threshold voltage distribution of the memory cell (MC). Figure 3 shows the possible data, threshold voltage distribution, and voltage used when reading data for each memory cell (MC). An example of a TLC (Telescopic Cell) memory cell (MC) is shown in Figure 3.

[0046] As shown in Figure 3, if a memory cell MC can store 3 bits of data, the memory cell MC can take on eight states (threshold voltage distributions) D0, D1, ..., D7 depending on the threshold voltage. These eight states are called, in order from the lowest threshold voltage, “Er” state D0, “A” state D1, “B” state D2, “C” state D3, “D” state D4, “E” state D5, “F” state D6, and “G” state D7.

[0047] The read voltage includes multiple voltages (hereinafter referred to as read levels) VAR, VBR2, VCR, VDR, VER, VFR, and VGR, depending on the page being read. The read level is the voltage used to determine whether the threshold voltage of the memory cell MC is above or below a certain voltage. The memory cell MC is turned on or off by the application of the read level.

[0048] In state D0, "Er," the threshold voltage of the memory cell MC is less than the read level VAR, corresponding to the data erasure state. In state D1, "A," the threshold voltage of the memory cell MC is greater than or equal to the read level VAR and less than the read level VBR. In state S2, "B," the threshold voltage of the memory cell MC is greater than or equal to the read level VBR and less than the read level VCR. In state D3, "C," the threshold voltage of the memory cell MC is greater than or equal to the read level VCR and less than the read level VDR. In state D4, "D," the threshold voltage of the memory cell MC is greater than or equal to the read level VDR and less than the read level VER. In state D5, "E," the threshold voltage of the memory cell MC is greater than or equal to the read level VER and less than the read level VFR. In state D6, "F," the threshold voltage of the memory cell MC is greater than or equal to the read level VFR and less than the read level VGR. In state D7, "G," the threshold voltage of the memory cell MC is greater than or equal to the read level VGR and less than the voltage VREAD. The relationship between these read level VAR, read level VGR, and voltage VREAD is VAR <VBR<VCR<VDR<VER<VFR<VGR<VREADである。

[0049] Of the eight states D0, ..., D7 distributed in this manner, state D7, "G", is the state with the highest threshold voltage of the memory cell. Each state D0, ..., D7 has a range of voltage values ​​associated with the corresponding data.

[0050] Voltage VREAD is, for example, the voltage applied to a word line (non-selected word line) WL that is not being read during a read operation. When voltage VREAD is applied to a memory cell MC, the memory cell MC turns on regardless of the data stored in it.

[0051] For example, among the eight states D0, ..., D7, the memory cell MC in state D0 of “Er”, state D1 of “A”, or state D2 of “B”, has a negative threshold voltage less than 0V. The memory cell MC in state D3 of “C”, state D4 of “D”, state D5 of “E”, state D6 of “F”, or state D7 of “G”, has a positive threshold voltage greater than or equal to 0V. In this case, the read levels VAR and VBR have negative voltage values, while the read levels VCR, VDR, VER, VFR, VGR, and voltage VREAD have positive voltage values.

[0052] The threshold voltage distribution is formed by writing 3 bits (3 pages) of data, including the lower bit, middle bit, and upper bit described above, to the memory cell MC in the memory cell array 10. An example of the relationship between the threshold voltage state and the upper bit, middle bit, and lower bit is as follows.

[0053] “Er” state: “111” (listed in the order of “Upper / Middle / Lower”) "A" State: "110" "B" State: "100" "C" state: "000" "D" State: "010" “E” State: “011” "F" State: "001" “G” State: “101”

[0054] Thus, in the threshold voltage distribution, only one of the three bits changes between data corresponding to two adjacent states.

[0055] For reading the lower bits of a memory cell (MC), a voltage corresponding to the boundary where the value of the lower bit ("0" or "1") changes is used. For reading the upper bits of a memory cell (MC), a voltage corresponding to the boundary where the value of the upper bit changes is used. For reading the middle bits, a voltage corresponding to the boundary where the value of the middle bit changes is used.

[0056] To read the lower bits of the memory cell MC, memory device 1 reads the lower pages of the cell unit CU. As shown in Figure 3, the reading of the lower pages is performed using read level VAR, which distinguishes between the “Er” state D0 and the “A” state D1, and read level VER, which distinguishes between the “D” state V4 and the “E” state D5, as the read voltages.

[0057] To read the middle bit of the memory cell MC, the memory device 1 reads the middle page of the cell unit CU. The middle page reading is performed using the read voltages VBR, which distinguishes between "A" state D1 and "B" state D2; VDR, which distinguishes between "C" state D3 and "D" state D4; and VFR, which distinguishes between "E" state D5 and "F" state D6.

[0058] To read the higher bits of the memory cell MC, memory device 1 reads the higher pages of the cell unit CU. The reading of the higher pages is performed using read level VCR, which distinguishes between "B" state D2 and "C" state D3, and read level VGR, which distinguishes between "F" state D6 and "G" state D7, as the read voltages.

[0059] By reading using the read level VAR, the memory cell MC in the erased state is identified.

[0060] In the following, readouts (determinations) using the readout level VAR are also called AR readouts. Similarly, readouts using each readout level VBR, VCR, VDR, VER, VFR, and VGR are called BR readouts, CR readouts, DR readouts, ER readouts, FR readouts, and GR readouts, respectively.

[0061] For example, multiple verify levels VAV, VBV, VCV, VDV, VEV, VFV, and VGV, used for verifying write operations, are set between the lower limits of each threshold voltage distribution D1, D2, D3, D4, D5, D6, and D7 and each read level VAR, VBR, VCR, VDR, VER, VFR, and VGR. Based on the on / off result of the memory cell MC in response to the application of each verify level VAV, VBV, VCV, VDV, VEV, VFV, and VGV, the threshold voltage state of the memory cell MC during the write operation is verified.

[0062] (a-2) Structure The structure of the memory device of this embodiment will be described with reference to Figures 4 to 9.

[0063] (a-2-1) Structure of memory devices Referring to Figure 4, an example of the structure of the memory device 1 in this embodiment will be described.

[0064] Figure 4 is a bird's-eye view showing an example of the structure of the memory device 1 in this embodiment.

[0065] As shown in Figure 4, the memory device 1 of this embodiment has a bonded structure. The memory device 1 of this embodiment includes two bonded semiconductor chips 100 and 200.

[0066] One of the two semiconductor chips 100, 200 is a memory cell array chip 100. The memory cell array chip 100 is a chip on which a memory cell array 10 is provided.

[0067] Of the two semiconductor chips 100 and 200, the other is a CMOS circuit chip 200. The CMOS circuit chip 200 is a chip equipped with a CMOS circuit that controls the memory cell array chip 100.

[0068] Multiple memory cell array chips 100 may be provided within the memory device 1. In this case, multiple memory cell array chips 100 may be bonded together so as to be stacked on a CMOS circuit chip 200. Multiple CMOS circuit chips 200 may be provided within the memory device 1.

[0069] As shown in Figure 4, the memory cell array chip 100 includes a plurality of pads 111 on plane F1. The CMOS circuit chip 200 includes a plurality of pads 211 on plane F2. The pads 111 and 211 are used to bond the two chips 100 and 200 together.

[0070] In the bonded memory device 1, the surface F1 of the memory cell array chip 100 is bonded to the surface F2 of the CMOS circuit chip 200. Thus, the surface F1 on which the pads 111 of the memory cell array chip 100 are located faces the surface F2 on which the pads 211 of the CMOS circuit chip 200 are located.

[0071] In the bonded structure, the pad 111 of the memory cell array chip 100 and the pad 211 of the CMOS circuit chip 200 are bonded together. This forms a single bonded pad BP within the memory device 1. In other words, the electrodes constituting the pad 111 on the memory cell array chip 100 are bonded to the electrodes constituting the pad 211 on the CMOS circuit chip 200. In this way, the bonded pad BP of the bonded memory device 1 is formed.

[0072] (a-2-2) Structure of memory cell array Referring to Figures 5 to 9, an example of the structure of the memory cell array 10 of the memory device 1 of this embodiment will be described.

[0073] Figure 5 is a plan view showing an example of the structure of the memory cell array 10 in the memory device 1 of this embodiment. In Figure 5, a portion of a certain block BLK within the memory cell array 10 is extracted and shown.

[0074] As shown in Figure 5, the memory cell array 10 is divided in the X direction into two memory areas MA1 and MA2, and a hookup area HA. ​​The hookup area HA is located between memory area MA1 and memory area MA2.

[0075] Memory regions MA1 and MA2 are regions containing NAND strings NS used for data storage. Memory regions MA1 and MA2 contain multiple wiring layers (conductive layers) 22, 23, and 24 stacked spaced apart in the Z direction. Multiple wiring layers 22, 23, and 24 are led from memory regions MA1 and MA2 to the hookup region HA. Multiple wiring layers 22, 23, and 24 correspond to word lines WL and select gate lines SG. Below, an example is shown in which there are eight word lines WL in block BLK.

[0076] The hookup region HA is the region used for connecting multiple wiring layers 22, 23, and 24 with the low decoder module 16.

[0077] The components SLT, OPS1, and OPS2 are provided within the memory cell array 10.

[0078] Each of the multiple member SLTs extends along the X direction. The multiple member SLTs are aligned in the Y direction. Each member SLT is located within the boundary region between adjacent blocks BLK. In the X direction, the member SLTs traverse the memory regions MA1, MA2 and the hookup region HA. The region demarcated by the member SLTs corresponds to one block BLK in the memory cell array 10. Each member SLT has a structure in which, for example, plate-shaped contacts LI and spacers SX are embedded. The member SLTs separate adjacent wiring layers 22, 23, and 24 through the member SLTs.

[0079] Multiple members OPS1 are provided in memory areas MA1 and MA2, respectively. Each of the multiple members OPS1 within memory area MA1 crosses memory area MA1 in the X direction. The multiple members OPS1 within memory area MA1 are aligned in the Y direction. Each of the multiple members OPS1 within memory area MA2 crosses memory area MA2 in the X direction. The multiple members OPS1 within memory area MA2 are aligned in the Y direction. For example, the end of each member OPS1 on the hookup area HA side is located within hookup area HA.

[0080] For example, in memory regions MA1 and MA2, three members OPS1 are arranged between adjacent members SLT in the Y direction. Each combination of the regions demarcated by members SLT and OPS1 in memory region MA1 and each region demarcated by members SLT and OPS1 in memory region MA2 corresponds to one string unit SU in the memory cell array 10. Each member OPS1 is, for example, a structure including an insulator embedded in a slit. Each member OPS1 separates adjacent wiring layers 22 via this member OPS1. Each wiring layer 22 corresponds to a drain-side select gate line SGD.

[0081] Multiple members OPS2 are provided in memory areas MA1 and MA2, respectively. Each of the multiple members OPS2 within memory area MA1 crosses memory area MA1 in the X direction. The multiple members OPS2 within memory area MA1 are aligned in the Y direction. Each of the multiple members OPS2 within memory area MA2 crosses memory area MA2 in the X direction. The multiple members OPS2 within memory area MA2 are aligned in the Y direction. For example, each member OPS2 extends from memory areas MA1 and MA2 into the hookup area HA. ​​Each member OPS2 is continuous between memory areas MA1 and MA2 via the hookup area HA.

[0082] For example, in memory regions MA1 and MA2, three members OPS2 are arranged between adjacent members SLT in the Y direction. Each combination of the regions demarcated by members SLT and OPS2 in memory region MA1 and each region demarcated by members SLT and OPS2 in memory region MA2 corresponds to one string unit SU in the memory cell array 10. Each member OPS2 is, for example, a structure including an insulator embedded in a slit. Each member OPS2 separates adjacent wiring layers 24 through this member OPS2. Each wiring layer 24 corresponds to a source-side select gate line SGS.

[0083] Multiple wiring layers 23 are drawn from memory areas MA1 and MA2 to the hookup area HA. ​​Each wiring layer 23 corresponds to a word line WL.

[0084] Multiple pillar sections PLR are provided within memory areas MA1 and MA2. Each of the multiple pillar sections PLR contains a memory pillar MP. Each memory pillar MP extends in the Z direction. Each memory pillar MP penetrates multiple wiring layers 22, 23, and 24. The memory pillar MPs are laid out in a staggered pattern in the XY plane of memory areas MA1 and MA2. A collection of memory pillar MPs aligned on the same straight line along the X direction forms a row.

[0085] Multiple bit lines BL are provided above the memory areas MA1 and MA2 in the Z direction. The multiple bit lines BL are aligned in the X direction. Each bit line BL extends in the Y direction. Each bit line BL is electrically connected to the corresponding memory pillar MP in each string unit SU via contact CV.

[0086] The planar layout of the memory cell array 10 of the memory device 1 in this embodiment is not limited to the layout described above. For example, the number of members OPS1 and OPS2 placed between the two members SLT can be designed to be any number depending on the number of string units SU in the block BLK.

[0087] The hook-up region HA is located between two memory regions MA1 and MA2, which are aligned in the X direction. The hook-up region HA includes a staircase section SS and a bridge section BRG. Between two members SLT, which are aligned in the Y direction, the staircase section SS is aligned with the bridge section BRG in the Y direction.

[0088] Within the staircase section SS, the collection of multiple wiring layers 22, 23, and 24 has a structure processed in a staircase shape (hereinafter also referred to as the staircase structure). Each wiring layer 22, 23, and 24 has an exposed portion (hereinafter referred to as the terrace) that is not covered by the upper wiring layer. Contacts (contact plugs) CC are provided on the terraces of each wiring layer 22, 23, and 24. Each wiring layer 22, 23, and 24 is electrically connected to the corresponding wiring of the low decoder module 16 via the contacts CC.

[0089] The bridge section BRG includes a plurality of wiring layers 29 that electrically connect the wiring layers 22, 23, 24 of memory area MA1 to the wiring layers 22, 23, 24 in memory area MA2. For example, each wiring layer 29 in the bridge section BRG is continuous with the wiring layers 22, 23, 24 of memory area MA1 and the wiring layers 22, 23, 24 of memory area MA2.

[0090] For example, the wiring layer 24, which serves as the source-side select gate line SGS, is continuous between memory area MA1 and memory area MA2 via the hookup area HA.

[0091] Figure 6 is a cross-sectional view showing an example of the structure of a memory cell array 10 in the memory device 1 of this embodiment. Figure 6 shows the cross-sectional structure of the memory cell array 10 along line AA in Figure 5. In Figure 6, members in the depth direction or front direction of the paper are shown by dashed lines.

[0092] In the following explanation, the Z1 direction is considered upward and the Z2 direction is considered downward. When the Z1 and Z2 directions are not distinguished, they are both referred to as the Z direction.

[0093] As shown in Figure 6, the memory cell array 10 includes a plurality of wiring layers 22, 23, 24 stacked in the Z direction. Each of the plurality of wiring layers 22, 23, 24 includes, for example, a stacked film of tungsten (W) and titanium nitride (TiN).

[0094] Multiple wiring layers 24 are provided on the wiring layers 42 that constitute the source lines SL, via an insulating layer 99. The multiple wiring layers 24 are aligned in the Y direction. Each of the multiple wiring layers 24 functions as one of several independent source-side select gate lines SGS. For example, if four string units SU are set up in one block BLK, the number of wiring layers 24 in each memory area MA1, MA2 is four. Hereinafter, the wiring layers 24 are also referred to as source-side select gate line layers 24.

[0095] Multiple wiring layers 23 are provided between multiple wiring layers 22 and multiple wiring layers 24 in the Z direction. An insulating layer 99 is provided between each of the two wiring layers 23 stacked in the Z direction. The wiring layers 23 and the insulating layer 99 are alternately stacked above the multiple wiring layers 24. This separates the multiple wiring layers 23 from each other. Each of the multiple wiring layers 23 functions as a word line WL. If one block BLK contains eight word lines WL, then the number of wiring layers 23 is eight. Hereafter, wiring layers 23 will also be called word line layers 23.

[0096] Multiple wiring layers 22 are provided above multiple wiring layers 23 in the Z direction, via an insulating layer 99. Multiple wiring layers 22 are aligned in the Y direction. Each of the multiple wiring layers 22 functions as one of several independent drain-side select gate lines SGD. For example, if four string units SU are configured within one block BLK, the number of wiring layers 22 in each memory area MA1, MA2 is four. Hereinafter, wiring layers 22 will also be referred to as drain-side select gate line layers 22.

[0097] The source wire SL includes multiple stacked wiring layers (conductive layers) 40, 41, and 42. The multiple wiring layers 40, 41, and 42 are located below the wiring layer 24 in the Z direction. Wiring layer 41 is located between two wiring layers 40 and 42 in the Z direction. The wiring layers 40, 41, and 42 contain phosphorus-doped silicon. Hereinafter, the collection SL of the multiple wiring layers (conductive layers) 40, 41, and 42 will also be called the source wire layer SL.

[0098] Multiple memory pillars MP are provided within multiple stacked wiring layers 22, 23, and 24. Each memory pillar MP penetrates through the wiring layers 22, 23, and 24. The Z2 end of each memory pillar MP is provided within the source wiring layer SL. The memory pillars MP have a tapered structure. The diameter of the memory pillar MP on the wiring layer 22 side (dimension along the XY plane) is larger than the diameter of the memory pillar MP on the wiring layer 24 side.

[0099] Each memory pillar MP includes a core layer 30, a semiconductor layer 31, and a memory layer 32. The core layer 30 is stretched in the Z direction. The semiconductor layer 31 is stretched in the Z direction so as to cover the sides of the core layer 30. The memory layer 32 is stretched in the Z direction so as to cover the outer peripheral sides of the semiconductor layer 31. The semiconductor layer 31 functions as the channel region for the memory cell MC and select transistors ST1 and ST2. The memory layer 32 has electrical properties that change depending on the data to be stored.

[0100] The sides of the memory pillar MP face the wiring layers 22, 23, and 24 in the X and Y directions. At the Z2-direction end of the memory pillar MP, the semiconductor layer 31 contacts the wiring layer 41 of the source wire layer SL through an opening formed in the memory layer 32. This electrically connects the semiconductor layer 31 to the source wire SL.

[0101] Figure 7 is a cross-sectional view showing a specific example of the cross-sectional structure of a memory pillar MP along the XY plane (planar shape of the memory pillar MP viewed from the Z direction) in a certain wiring layer 23.

[0102] As shown in Figure 7, the core layer 30 has a circular (or elliptical) planar shape when viewed from the Z direction. The core layer 30 has a cylindrical structure.

[0103] The semiconductor layer 31 has a circular (or elliptical) planar shape when viewed from the Z direction. The semiconductor layer 31 has a cylindrical structure. Within the memory pillar MP, the semiconductor layer 31 is provided between the core layer 30 and the memory layer 32.

[0104] The memory layer 32 has a circular (or elliptical) planar shape when viewed from the Z direction. The memory layer 32 has a cylindrical structure. The memory layer 32 is a laminated film including a tunnel insulating film 320, a charge storage layer 321, and a block insulating film 322.

[0105] The tunnel insulating film 320 is provided between the semiconductor layer 31 and the charge storage layer 321. The charge storage layer 321 is provided between the tunnel insulating film 320 and the block insulating film 322. The block insulating film 322 is provided between the charge storage layer 321 and the wiring layer 23.

[0106] In the structure of the memory pillar MP shown in Figure 7, the portion where the memory pillar MP intersects with the wiring layer (source-side select gate line layer) 24 functions as a select transistor ST2. The portion where the memory pillar MP intersects with the wiring layer (word line layer) 23 functions as a memory cell MC. The portion where the memory pillar MP intersects with the wiring layer (drain-side select gate line layer) 22 functions as a select transistor ST1.

[0107] Returning to Figure 6, let's explain the structure of the memory cell array 10.

[0108] An insulating layer 98 is provided above the wiring layer 22. Multiple wiring layers 45 are provided above the insulating layer 98. An insulating layer 97 is provided above the wiring layers 45. The wiring layers 45 have, for example, a linear structure extending along the Y direction. The wiring layers 45 function as bit lines BL. In the depth or front direction of the drawing, the multiple wiring layers 45 are aligned along the X direction. The wiring layers 45 include, for example, copper. Each of the wiring layers 45 is electrically connected to a corresponding one of a plurality of memory pillars MP belonging to each string unit SU.

[0109] Multiple contacts CV are embedded within the insulating layer 98. Each contact CV contacts the upper surface of the semiconductor layer 31 within the memory pillar MP. Each contact CV electrically connects one memory pillar MP to one wiring layer 45 (bit line BL).

[0110] The member SLT is formed, for example, to extend along the XZ plane. The member SLT penetrates multiple wiring layers 22, 23, 24 and multiple insulating layers 99. The Z2-direction end of the member SLT reaches the source wire layer SL.

[0111] The contact LI of component SLT is provided so as to extend along the XZ plane. The spacer SX of component SLT is provided between the contact LI and the wiring layers 22, 23, and 24. The Z1-direction end (upper end) of contact LI is located, for example, within the uppermost insulating layer 99. The Z2-direction end (lower end) of contact LI is in contact with, for example, the conductive layer 41 of the source wire layer SL. Note that contact LI may be omitted depending on the structure of the memory cell array 10.

[0112] Component OPS1 has, for example, a plate-like structure extending along the XZ plane. Component OPS1 divides adjacent wiring layers 22 in the Y direction. Component OPS1 is provided within the boundary region between string units SU. The Z2-direction end (lower end) of component OPS1 is located, for example, within the region between wiring layer 22 and the uppermost wiring layer 23. Component OPS1 includes an insulator, for example, silicon oxide. The insulator of component OPS1 is filled into a slit formed within the boundary region between string units SU. Component OPS1 overlaps with the end of the memory pillar MP between two adjacent wiring layers 22 in the Y direction.

[0113] Component OPS2 has a linear structure extending in the X direction. Component OPS2 separates two adjacent wiring layers 24 in the Y direction. Component OPS2 includes an insulator (insulating layer 99) filled in the slit between the wiring layers 24.

[0114] Figure 8 is a cross-sectional view showing the cross-sectional structure of the memory pillar MP along the XY plane in the wiring layer 22.

[0115] As shown in Figure 8, each component OPS1 is provided between the wiring layers 22 that serve as the drain-side select gate wire SGD. Component OPS1 independently separates multiple wiring layers 22 from one another. In this way, component OPS1 is provided within the boundary of adjacent string units SU.

[0116] Within the wiring layer 22, component OPS1 partially overlaps with the memory pillar MP near the boundary of the string unit SU. Component OPS1 is in direct contact with the memory pillar MP.

[0117] The end of the memory pillar MP on the component OPS1 side is missing due to component OPS1 (and the formation process of component OPS1). For example, the semiconductor layer 31 and the memory layer 32 are partially removed from the memory pillar MP. The side surface of the core layer 30 contacts the side surface of component OPS1. In the missing portion of the memory pillar MP, the semiconductor layer 31 and the memory layer 32 contact component OPS1. Note that the semiconductor layer 31 may remain between the core layer 30 and component OPS1.

[0118] Thus, within the layers of the wiring layer 22, the upper part of the memory pillar MP on the boundary of the string unit SU has a planar shape with a partially missing arc when viewed from the Z direction (hereinafter also called a missing circle shape, semicircular shape, or semicircular shape). A planar shape that is a circle (elliptical shape) without a missing arc is also called a full circle shape.

[0119] Figure 9 is a cross-sectional view showing the cross-sectional structure of the memory pillar MP along the XY plane in the wiring layer 24.

[0120] As shown in Figure 9, within the layers of the wiring layer 24, member OPS2 passes through the region between memory pillars MP near the boundary of the string unit SU. For example, member OPS2 does not come into contact with the memory pillars MP.

[0121] Furthermore, depending on the manufacturing process of the memory cell array 10, within the layers of the wiring layer 24, the memory pillar MP may have a segmental shape (or semicircular shape) in which at least one of the semiconductor layer 31 and the memory layer 32 is partially removed.

[0122] The memory device 1 of this embodiment can be formed by a combination of well-known memory device manufacturing processes.

[0123] In this embodiment, when performing an operation on the memory cell array 10, the memory device 1 applies a negative voltage (a voltage less than 0V) to one or two unselected drain-side select gate lines SGDs adjacent to the drain-side select gate line SGD selected from among a plurality of drain-side select gate lines SGDs (wiring layer 22) corresponding to the string unit SU to be operated on.

[0124] In the following, the drain-side select gate line selected as the target of operation will also be referred to as the selected drain-side select gate line SGD-SEL. The unselected drain-side select gate line adjacent to the selected drain-side select gate line SGD-SEL will also be referred to as the adjacent drain-side select gate line SGD-USEL1.

[0125] Furthermore, when performing an operation on the memory cell array 10, the memory device 1 of this embodiment applies a negative voltage (a voltage less than 0V) to one or two unselected source-side select gate lines SGS adjacent to the source-side select gate line SGS selected from among the multiple source-side select gate lines SGS corresponding to the string unit SU to be operated on.

[0126] In the following, the source-side select gate line selected for operation will also be referred to as the selected source-side select gate line SGS-SEL. The unselected source-side select gate line adjacent to the selected source-side select gate line SGS-SEL will also be referred to as the adjacent source-side select gate line SGS-USEL1.

[0127] Furthermore, drain-side select gate lines SGD other than the selected drain-side select gate line SGD-SEL and the adjacent drain-side select gate line SGD-USEL1 are denoted as non-selected drain-side select gate lines SGD-USEL2. Source-side select gate lines SGS other than the selected source-side select gate line SGS-SEL and the adjacent source-side select gate line SGS-USEL1 are denoted as non-selected source-side select gate lines SGS-USEL2.

[0128] The selected drain-side select gate line SGD-SEL and the selected source-side select gate line SGS-SEL belong to the selected string unit SU that is being operated on. The unselected string unit SU includes the NAND string NS which contains the memory cells that are being operated on. The adjacent / unselected drain-side select gate lines SGD-USEL1, SGD-USEL2 and the adjacent / unselected source-side select gate lines SGS-USEL1, SGS-USEL2 belong to the unselected string unit SU that is not being operated on.

[0129] In the following, when the selected drain-side select gate line SGD-SEL and the selected source-side select gate line SGS-SEL are not distinguished, they will also be referred to as the selected select gate line SG-SEL. When the adjacent drain-side select gate line SGD-USEL1 and the adjacent source-side select gate line SGS-USEL1 are not distinguished, they will also be referred to as the adjacent select gate line SG-USEL1. When the non-selected drain-side select gate line SGD-USEL2 and the non-selected source-side select gate line SGS-USEL2 are not distinguished, they will also be referred to as the non-selected select gate line SG-USEL2.

[0130] (a-3) Overview of memory device operation Referring to Figures 10 and 11, the general operation of the memory device 1 in this embodiment will be described.

[0131] Figures 10 and 11 are schematic diagrams illustrating the general operation of the memory device 1 of this embodiment. Figure 10 is a schematic diagram showing the voltage application state to the selected / unselected select gate lines SGD and SGS in the memory cell array 10 during the operation of the memory device 1 of this embodiment. Figure 11 is a schematic diagram showing the state of the memory pillar MP of the adjacent drain-side select gate line SGD-USEL1 during the operation of the memory device 1 of this embodiment.

[0132] As shown in Figure 10, when the memory device 1 is running, it applies a voltage (selection voltage) VON with a positive voltage value to the selected drain-side select gate line SGD-SEL and the selected source-side select gate line SGS-SEL. In the example in Figure 10, the string unit SU1 is selected, and the drain-side select gate line SGD1 and the source-side select gate line SGS1 are set to the selected drain-side select gate line SGD-SEL and the selected source-side select gate line SGS-SEL.

[0133] Memory device 1 applies a voltage (non-selection voltage) VOFF1, which has a negative voltage value, to the adjacent drain-side select gate line SGD-USEL1 and the adjacent source-side select gate line SGS-USEL1. In string units SU0 and SU2, the drain-side select gate lines SGD0 and SGD2 are set to the adjacent drain-side select gate line SGD-USEL1, and the source-side select gate lines SGS0 and SGS2 are set to the adjacent source-side select gate line SGS-USEL1. Voltage VOFF1 has a voltage value within the range of -2.5V to -1.5V. For example, voltage VOFF1 is -2.0V. However, the voltage value of voltage VOFF1 may be lower than -2.5V or higher than -1.5V, as long as it is less than 0V. For example, the voltage value of voltage VOFF1 is different from the read levels VAR and VBR, which have negative voltage values. Furthermore, the voltage value of VOFF1 applied to the adjacent source-side select gate line SGS-USEL1 may differ from the voltage value of VOFF1 applied to the adjacent drain-side select gate line SGD-USEL1, provided that the voltage value is negative.

[0134] Memory device 1 applies, for example, a voltage of 0V (non-selection voltage) VOFF2 to the non-selection drain-side select gate line SGD-USEL2 and the non-selection source-side select gate line SGS-USEL2. The drain-side select gate line SGD3 and the source-side select gate line SGS3 of string unit SU3 are set to the non-selection drain-side select gate line SGD-USEL2 and the non-selection source-side select gate line SGS-USEL2.

[0135] Memory device 1 applies various voltages to multiple word lines WL to perform operations on the selected memory cell MC.

[0136] As shown in Figure 11, when a positive voltage VON is applied to the select drain-side select gate line SGD-SEL, an electric field EF is generated from the select gate line SGD-SEL. The generated electric field EF is applied to the circular memory pillar MP near the boundary of the string unit SU (the boundary of adjacent wiring layers 22). The electric field EF is applied to the semiconductor layer 31 of the circular memory pillar MP through the insulator of member OPS1.

[0137] When a voltage of 0V is applied to the adjacent drain-side select gate line SGD-USEL1, the electric field from the select gate line SGD-SEL may weakly turn on the select transistor ST1 formed from the semicircular memory pillar MPa. This weakly turned-on state of the select transistor ST1 causes leakage (leakage current) within the memory pillar MP connected to the adjacent drain-side select gate line SGD-USEL1. This leakage causes capacitance between the memory pillar MP and the wiring layer (word line) 23 to affect the operation of the memory device 1.

[0138] In this embodiment, when the memory device 1 is operating, a negative voltage VOFF1 less than 0V is applied to the adjacent drain-side select gate line SGD-USEL1. The application of this negative voltage causes the semiconductor layer 31 of the select transistor ST1 in the memory pillar MPa, which has a semicircular upper section connected to the adjacent drain-side select gate line SGD-USEL1, to enter an accumulation state.

[0139] As a result, even if the electric field EF generated from the select gate line SGD-SEL is applied to the memory pillar MPa connected to the adjacent drain-side select gate line SGD-USEL1, the effect of the electric field EF on the memory pillar MP is reduced (e.g., canceled out).

[0140] Therefore, in the adjacent drain-side select gate line SGD-USEL1, the select transistor ST1 on the circular memory pillar MPa is cut off without entering a weakly ON state.

[0141] As a result, leakage is suppressed in the memory pillars MP and MPa connected to the adjacent drain-side select gate line SGD-USEL1. Therefore, the capacitance effect between the memory pillar MP and the wiring layer 22 is suppressed. Consequently, in the memory device 1 of this embodiment, channel boost leakage of the memory pillar MP is suppressed.

[0142] As described above, similar to the drain-side select gate line SGD, when a positive voltage VON is applied to the selected source-side select gate line SGS-SEL, a negative voltage VOFF1 is applied to the adjacent source-side select gate line SGS-USEL1. This suppresses the weak ON state of the select transistor ST2 connected to the adjacent source-side select gate line SGS-USEL1, which corresponds to the electric field EF from the selected source-side select gate line SGS-SEL. Therefore, leakage of the select transistor ST2 connected to the adjacent source-side select gate line SGS-USEL1 is suppressed. Consequently, the semiconductor layer 31 within the memory pillar MP is channel-boosted while the capacitance between the memory pillar MP and the wiring layer 22 is suppressed.

[0143] Thus, the memory pillars MP and MPa connected to the adjacent select gate lines SGD-USEL1 and SGS-USEL1 are electrically isolated from the bit line BL and the source line SL.

[0144] Therefore, as shown in Figure 10, in string units SU (e.g., string units SU0, SU1) including adjacent select gate lines SGD-USEL1, SGS-USEL1, the inside of the semiconductor layer (channel) 31 of the memory pillar MP is boosted without the effects of leakage.

[0145] Thus, during the operation of the memory device 1, the effect of capacitance between the memory pillar MP and the word line WL in the string unit SU, which includes adjacent select gate lines SGD-USEL1 and SGS-USEL1, is reduced.

[0146] In other words, in this embodiment, the memory device 1 only needs to have the capacitance between the memory pillar MP and the word line WL of the selected string unit SU charged.

[0147] Therefore, the memory device 1 of this embodiment can reduce the charging current of the word line WL during operation of the memory device 1. By reducing the charging current, the memory device 1 of this embodiment can improve the charging speed (operating speed) of the wiring layer 23 (word line WL).

[0148] (b) Example of operation Referring to Figure 12, an example of the operation of the memory device 1 in this embodiment will be described. Note that the operation of the memory device may include a control method for the memory device.

[0149] Figure 12 is a timing chart (waveform diagram) showing an example of the operation of the memory device 1 of this embodiment. In Figure 12, the horizontal axis corresponds to time, and the vertical axis corresponds to the voltage value or current value of each wire. In Figure 12, the read operation of the memory device 1 is shown as an example of the operation of the memory device 1 of this embodiment.

[0150] <Time t0> As shown in Figure 12, at time t0, the memory device 1 initiates a read operation on the target specified by address ADD, based on the command CMD from the memory controller 2. The driver module 15 generates various voltages that are supplied to each wire of the memory cell array 10.

[0151] The memory device 1 applies a predetermined voltage to each wire under the control of the sequencer 14.

[0152] <Time t1> At time t1, memory device 1 begins applying voltage to multiple wires WL, SGD, and SGS within the selected block (hereinafter referred to as the selected block) BLK based on address ADD. This causes the potentials of the multiple wires WL, SGD, and SGS within the selected block BLK to change.

[0153] For example, memory device 1 applies a non-selection voltage VREAD to the selected word line WL-SEL and the non-selected word line WL-USEL. Memory device 1 also applies a voltage VON to the selected drain-side select gate line SGD-SEL, the non-selected drain-side select gate lines SGD-USEL1 and SGD-USEL2, the selected source-side select gate line SGS-SEL, and the non-selected source-side select gate lines SGS-USEL1 and SGS-USEL2.

[0154] The potentials of multiple word lines WL-SEL and WLUSEL rise to a positive voltage value. The potentials of multiple drain-side select gate lines SGD-SEL, SGD-USEL1, and SGD-USEL2 rise to a positive voltage value. The potentials of multiple source-side select gate lines SGS-SEL, SGS-USEL1, and SGS-USEL2 rise to a positive voltage value.

[0155] In response to the application of voltage to the word line WL and the select gate lines SGD and SGS, a charging current IWL is generated in the word line WL. The current value of the charging current IWL increases. For example, the magnitude of the charging current IWL reaches a current value (peak value) i1 between time t1 and time t2.

[0156] <Time t2> At time t2, the potentials of the drain-side select gate lines SGD-SEL, SGD-USEL1, SGD-USEL2 and the source-side select gate lines SGS-SEL, SGS-USEL1, SGS-USEL2 reach a certain voltage value. Memory device 1 stops applying a positive voltage to the unselected drain-side select gate lines SGD-USEL1, SGD-USEL2 and the unselected source-side select gate lines SGS-USEL1, SGS-USEL2. Note that "stopping the application of voltage" includes applying a voltage of 0V.

[0157] At time t2, memory device 1 begins applying a negative voltage VOFF1 to one or two adjacent drain-side select gate lines SGD-USEL1 and SGD-USEL2, which are unselected drain-side select gate lines SGD-USEL1 and SGD-USEL2. Memory device 1 also begins applying a negative voltage VOFF1 to one or two adjacent source-side select gate lines SGS-USEL1 and SGS-USEL2, which are unselected source-side select gate lines SGS-USEL1 and SGS-USEL2, which are unselected source-side select gate lines SGS-USEL1 and SGS-USEL2, which are charged with a negative voltage VOFF1 lower than 0V. Voltage VOFF1 is generated by the negative voltage generation circuit 150 of the driver module 15.

[0158] Furthermore, at time t2, memory device 1 begins applying a 0V voltage VOFF2 to the non-selected drain-side select gate line SGD-USEL2, which is different from the adjacent drain-side select gate line SGD-USEL1. Memory device 1 begins applying a 0V voltage VOFF2 to the non-selected source-side select gate line SGS-USEL2, which is different from the adjacent source-side select gate line SGS-USEL1.

[0159] <Time t3> At time t3, the potential of the adjacent drain-side select gate line SGD-USEL1 and the potential of the adjacent source-side select gate line SGS-USEL1 reach a negative voltage VOFF1. For example, the voltage value of VOFF1 is -2V.

[0160] As a result, in the memory device 1 of this embodiment, the select transistor ST1 connected to the adjacent drain-side select gate line SGD-USEL1 and the select transistor ST2 connected to the adjacent source-side select gate line SGS-USEL1 are turned off without being affected by the electric field EF generated from the selected drain-side select gate line SGD-SEL and the selected source-side select gate line SGS-SEL.

[0161] Furthermore, the potential of the non-selected drain-side select gate line SGD-USEL2 and the potential of the non-selected source-side select gate line SGS-USEL2 reach voltage VOFF2. As a result, the select transistor ST1 connected to the adjacent drain-side select gate line SGD-USEL2 and the select transistor ST2 connected to the adjacent source-side select gate line SGS-USEL2 are cut off.

[0162] During the period from time t2 to time t3, depending on the off state of select transistors ST1 and ST2, the semiconductor layer (channel) CHN-USEL of the memory pillar MP connected to the unselected select gate lines SGD-USEL1, SGS-USEL1, SGD-USEL2, and SGS-USEL2 rises in proportion to the charge potential ΔV of the unselected word line WL-USEL. For example, the potential of the semiconductor layer CHN-USEL reaches the voltage VBoost.

[0163] As the potential of the off-state select transistors ST1 and ST2 and the semiconductor layer CHN-USEL rises, the magnitude of the charging current IWL decreases from its peak value i1.

[0164] After time t3, the potentials of the word lines WL-SEL and WL-USEL reach the voltage VREAD. The potentials of the selected drain-side select gate line SGD-SEL and the selected source-side select gate line SGS-SEL reach the voltage VON. The select transistor ST1 connected to the selected drain-side select gate line SGD-SEL and the select transistor ST2 connected to the selected source-side select gate line SGS-SEL are turned on. As a result, the capacitance between the word line and the memory pillar in the selected string unit SU is charged.

[0165] <Time t4> After the potential of the word lines WL-SEL and WL-USEL reaches the voltage VREAD, at time t4, memory device 1 applies the read voltage VCGRV to the selected word line WL-SEL. Memory device 1 also applies the voltage VBL to the bit line BL and the voltage VCELSRC to the source line SL.

[0166] For example, in a memory pillar MP connected to the selected select gate lines SGD-SEL and SGS-SEL, the potential of the semiconductor layer (channel) CHN-SEL rises to approximately the voltage VCELSRC.

[0167] When the non-selection voltage VREAD is applied, the memory cell MC connected to the non-selection word line WL-USEL turns on, regardless of the data stored in that memory cell MC.

[0168] When the read voltage VCGRV is applied, the memory cell MC connected to the selection word line WL-SEL is turned on or off depending on the relationship between the threshold voltage of the memory cell MC corresponding to the data to be stored and the voltage value (read level) of the read voltage VCGRV.

[0169] If the read operation is a read of a lower page, the read voltage VCGRV includes two read levels VER and VAR. For example, memory device 1 applies a voltage value corresponding to the read level VER to the selection word line WL-SEL. After applying the read level VER, memory device 1 applies a voltage value corresponding to the read level VAR, which is lower than the read level ER, to the selection word line WL-SEL. For example, if the read level VAR is a negative voltage value, the potential of the selection word line WL-SEL will be lower than 0V. However, when a negative voltage is applied to the selection word line WL-SEL, the voltage value of the negative voltage applied to the selection word line WL-SEL is different from the voltage value of the negative voltage VOFF1.

[0170] Furthermore, if the page being read is a higher-level page, the read voltage VCGRV includes read levels VCR and VGR. Also, if the page being read is a middle-level page, the read voltage VCGRV includes read levels BR, VDR, and VFR.

[0171] <Time t8> At time t8, memory device 1 stops applying the read voltage VCGRV to the selected word line WL-SEL, the voltage VBL to the bit line BL, and the voltage VCELSRC to the source line SL.

[0172] Memory device 1 begins applying a deselection voltage VREAD to the selection word line WL-SEL. This raises the potential of the selection word line WL-SEL to the deselection voltage VREAD. The memory cell MC connected to the selection word line WL is turned on by the deselection voltage VREAD.

[0173] Memory device 1 stops applying voltage VOFF1 to the adjacent drain-side select gate line SGD-USEL1 and the adjacent source-side select gate line SGS-USEL1, and stops applying voltage VOFF2 to the non-selected drain-side select gate line SGD-USEL2 and the non-selected source-side select gate line SGS-USEL2.

[0174] Memory device 1 begins applying a positive voltage (e.g., voltage VON) to the adjacent drain-side select gate line SGD-USEL1, the adjacent source-side select gate line SGS-USEL1, the unselected drain-side select gate line SGD-USEL2, and the unselected source-side select gate line SGS-USEL2. As a result, the potentials of the unselected drain-side select gate lines SGD-USEL1, SGD-USEL2 and the unselected source-side select gate lines SGS-USEL1, SGS-USEL2 rise to a positive voltage. The select transistor ST1 connected to the unselected drain-side select gate lines SGD-USEL1, SGD-USEL2, and the select transistor ST2 connected to the unselected source-side select gate lines SGS-USEL1, SGS-USEL2, are turned on by the applied positive voltage.

[0175] Memory pillar MP connected to the unselected select gate lines SGD-USEL1, SGD-USEL2, SGS-USEL1, and SGS-USEL2 temporarily conducts to the bit line BL and source line SL via the ON select transistors ST1 and ST2. This releases carriers (electrons / holes) trapped within the memory pillar MP.

[0176] <Time t9> At time t9, memory device 1 stops applying voltage to the word lines WL-SEL, WL-USEL, the drain-side select gate lines SGD-SEL, SGD-USEL1, SGD-USEL2, and the source-side select gate lines SGS-SEL, SGS-USEL1, SGS-USEL2. As a result, the potentials of the word lines WL-SEL, WL-USEL, the drain-side select gate lines SGD-SEL, SGD-USEL1, SGD-USEL2, and the source-side select gate lines SGS-SEL, SGS-USEL1, SGS-USEL are set to 0V.

[0177] The memory device 1 transfers the data output from the memory cell array 10 to the memory controller 2 as read data.

[0178] With the above operations, the memory device 1 of this embodiment terminates its read operation.

[0179] The operation example of the memory device 1 in this embodiment may also be applied to the verification operation of the write operation of the memory device 1. In the verification operation, the verification voltage is applied to the selected word line WL-SEL, which differs from the example of the read operation in Figure 12. The verification voltage includes one or more verification levels. During the verification operation, the memory device 1 in this embodiment applies a negative voltage VOFF1 to the adjacent drain-side / source-side select gate lines SGD-USEL1 and SGS-USEL1. This suppresses the adverse effect of the electric field from the selected drain-side / source-side select gate lines SGD-SEL and SGS-SEL on the off state of the select transistors ST1 and ST2 of the adjacent drain-side / source-side select gate lines SGD-USEL1 and SGS-USEL1 during the verification operation of the write operation.

[0180] Furthermore, the operation of the memory device 1 in this embodiment may be applied to the verify operation of the erase operation.

[0181] (c) Summary During the operation of the memory device, a large charging current is generated in accordance with the charging of the word lines. The current required to charge the capacitance between the word lines and the memory pillars increases with the number of word lines.

[0182] To improve the performance of memory devices, it is desirable to suppress the charging current of the word lines without delaying the charging speed of the word lines.

[0183] During the operation of the memory device, the capacitance between the word line and the memory pillar is suppressed by electrically isolating the memory pillar of unselected string units from the bit line and bit line.

[0184] Various techniques have been proposed to control non-selected string units independently of the operation of selected string units. For example, multiple physically separated select gate lines are provided within each block of the memory cell array. To suppress increases in the manufacturing cost of memory devices, the spacing between adjacent select gate lines is kept relatively small.

[0185] During operation of the memory device, the electric field from the selected drain / source select gate line may weakly turn on the select transistor of the non-selected drain / source select gate line adjacent to the selected drain / source select gate line. This weakly turned-on state of the select transistor causes leakage within the corresponding memory pillar of the non-selected drain / source select gate line. This leakage results in the effect of capacitance (e.g., capacitance charge) between the memory pillar MP and the wiring layer (word line) 22 affecting the operation of the memory device 1. As a result, the corresponding memory pillar of the non-selected drain / source select gate line is not sufficiently boosted.

[0186] In this embodiment, when the memory device 1 is operating, a voltage with a negative voltage value is applied to the non-selected drain-side / source-side select gate lines (adjacent drain-side / source-side select gate lines) SGD-USEL1 and SGS-USEL1 that are adjacent to the selected drain-side / source-side select gate lines SGD-SEL and SGS-SEL.

[0187] As a result, in the memory device 1 of this embodiment, even if an electric field EF from the selected drain-side / source-side select gate lines SGD-SEL and SGS-SEL is applied to the adjacent drain-side / source-side select gate line, the select transistors ST1 and ST2 connected to the adjacent drain-side / source-side select gate lines SGD-USEL1 and SGS-USEL1 will be turned off.

[0188] Therefore, the memory device 1 of this embodiment can suppress leakage occurring in the memory pillar MP of the non-selected string unit SU. As a result, the memory device 1 of this embodiment only needs to charge the capacitance between the word line and the memory pillar in the selected string unit SU, without charging the capacitance between the word line and the memory pillar in the non-selected string unit SU.

[0189] Therefore, the memory device 1 of this embodiment can reduce the charging current of the word line WL.

[0190] In Figure 10, the dashed current waveform of the charging current IWL shows the current waveform when the select transistors ST1 and ST2 connected to the adjacent select gate lines SGD-USEL1 and SGS-USEL1 are weakly turned on by the electric field generated from the select gate lines SGD-SEL and SGS-SEL. When the select transistors ST1 and ST2 connected to the adjacent select gate lines SGD-USEL1 and SGS-USEL1 are weakly turned on, a charging current with a current peak value i0 is generated due to leakage.

[0191] As in this embodiment, by applying a negative voltage VOFF1 to the adjacent select gate lines SGD-USEL1 and SGS-USEL1, the electric fields generated from the select gate lines SGD-SEL and SGS-SEL are substantially canceled out. As a result, the select transistors ST1 and ST2 connected to the adjacent select gate lines SGD-USEL1 and SGS-USEL1 can be completely cut off. Therefore, the occurrence of leakage in the memory pillar MP connected to the adjacent select gate lines SGD-USEL1 and SGS-USEL1 is suppressed. Consequently, the effect of capacitance between the memory pillar MP connected to the adjacent select gate lines SGD-USEL1 and SGS-USEL1 and the word line WL is reduced.

[0192] As a result, in this embodiment, the charging current IWL has a current peak value i1 that is lower than the current peak value i0. For example, the current peak value i1 is about one-quarter of the current peak value i0.

[0193] Thus, the memory device 1 of this embodiment can reduce the charging current IWL.

[0194] The memory device 1 of this embodiment can increase the charging speed of the word line WL in accordance with the reduction of the charging current IWL.

[0195] As described above, the memory device 1 of this embodiment can improve the operating characteristics of the memory device.

[0196] (2) Second embodiment Referring to Figures 13 to 15, a memory device and a control method for the memory device according to a second embodiment will be described.

[0197] Figures 13 and 14 are schematic diagrams illustrating the general operation of the memory device 1 in this embodiment.

[0198] As shown in Figure 13, the memory device 1 of this embodiment applies a negative voltage VOFF3 to the non-selected drain-side / source-side select gate lines SGD-USEL2 and SGS-USEL2 that are not adjacent to the selected drain-side / source-side select gate lines SGD-USEL2 and SGS-USEL2, along with the adjacent drain-side / source-side select gate lines SGD-USEL1 and SGS-USEL1.

[0199] Voltage VOFF3 is, for example, lower than 0V and higher than voltage VOFF1. For example, the voltage value of voltage VOFF3 is within the range of -1.7V to -1V. Note that the voltage value of voltage VOFF3 may be the same as the voltage value of voltage VOFF1, as long as it is less than 0V.

[0200] As shown in Figure 14, when a negative voltage VOFF3 is applied to the non-selected drain-side select gate line SGD-USEL2 adjacent to the adjacent drain-side select gate line SGD-USEL1, the potential difference between the non-selected drain-side select gate line SGD-USEL2 and the adjacent drain-side select gate line SGD-USEL1 is reduced.

[0201] This reduces interference caused by the potential difference between the non-selected drain-side select gate line SGD-USEL2 and the adjacent drain-side select gate line SGD-USEL1.

[0202] Similarly, by applying a negative voltage VOFF3 to the non-selected source-side select gate line SGS-USEL2, interference caused by the potential difference between the non-selected source-side select gate line SGS-USEL2 and the adjacent source-side select gate line SGS-USEL1 is reduced.

[0203] Figure 15 is a timing chart showing an example of the operation of the memory device 1 in this embodiment.

[0204] As shown in Figure 15, at time t1, memory device 1 applies a positive voltage (e.g., voltage VON) to the drain-side select gate lines SGD-SEL, SGD-USEL1, SGD-USEL2 and the source-side select gate lines SGS-SEL, SGS-USEL1, SGS-USEL2.

[0205] At time t2, memory device 1 applies a negative voltage VOFF1 to the adjacent drain-side select gate line SGD-USEL1 and the adjacent source-side select gate line SGS-USEL1. At the same time, along with applying voltage VOFF1 to the adjacent drain-side / source-side select gate lines SGD-USEL1 and SGS-USEL1, memory device 1 also applies a negative voltage VOFF3 to the unselected drain-side select gate line SGD-USEL2 and the unselected source-side select gate line SGS-USEL2.

[0206] At time t3, the potentials of the unselected drain-side select gate line SGD-USEL2 and the unselected source-side select gate line SGS-USEL2 reach a negative voltage VOFF3.

[0207] At time t4, memory device 1 applies the read voltage VCGRV to the selected word line WL-SEL.

[0208] At time t8, memory device 1 applies voltage VON to the adjacent drain-side / source-side select gate lines SGD-USEL1 and SGS-USEL1, as well as to the unselected drain-side select gate line SGD-USEL2 and the unselected source-side select gate line SGS-USEL2.

[0209] At time t9, memory device 1 stops applying voltage to the word lines WL-SEL, WL-USEL, drain-side select gate lines SGD-SEL, SGD-USEL1, SGD-USEL2, and source-side select gate lines SGS-SEL, SGS-USEL1, SGS-USEL2.

[0210] As described above, the memory device 1 of this embodiment terminates its read operation.

[0211] As described above, by applying a negative voltage VOFF3 to the non-selected drain-side select gate line SGD-USEL2 and the non-selected source-side select gate line SGS-USEL2, the influence of the potential difference between the non-selected drain-side select gate line SGD-USEL2 and the adjacent drain-side select gate line SGD-USEL1, and the influence of the potential difference between the non-selected source-side select gate line SGS-USEL2 and the adjacent source-side select gate line SGS-USEL1 can be suppressed.

[0212] Therefore, the memory device 1 of this embodiment can improve the reliability of the operation of the memory device 1.

[0213] As a result, the memory device 1 of this embodiment can improve the operating characteristics of the memory device.

[0214] (3) Third Embodiment Referring to Figure 16, a memory device and a control method for the memory device according to a third embodiment will be described.

[0215] Figure 16 is a timing chart showing an example of the operation of the memory device 1 in this embodiment.

[0216] As shown in Figure 16, the timing (time) of applying the negative voltage VOFF1 to the adjacent drain-side select gate line SGD-USEL1 is different from the timing of applying the negative voltage VOFF1 to the adjacent source-side select gate line SGS-USEL1. Also, the timing of applying the negative voltage VOFF3 to the non-selected drain-side select gate line SGD-USEL2 is different from the timing of applying the negative voltage VOFF3 to the non-selected source-side select gate line SGS-USEL2.

[0217] For example, at time t2, memory device 1 applies a negative voltage VOFF1 to the adjacent drain-side select gate line SGD-USEL1 and a negative voltage VOFF3 to the non-selected drain-side select gate line SGD-USEL2. At this time, a positive voltage VON is applied to the adjacent source-side select gate line SGS-USEL1 and the non-selected source-side select gate line SGS-USEL2.

[0218] At time t2z, after time t2, memory device 1 applies a negative voltage VOFF1 to the adjacent source-side select gate line SGS-USEL1 and a negative voltage VOFF3 to the non-selected source-side select gate line SGS-USEL2. For example, the potential of the adjacent source-side select gate line SGS-USEL1 and the potential of the non-selected source-side select gate line SGS-USEL2 reach the desired value after time t3.

[0219] At time t4, memory device 1 applies the read voltage VCGRV to the selected word line WL-SEL.

[0220] At time t8, memory device 1 applies a positive voltage VON to the adjacent drain-side / source-side select gate lines SGD-USEL1, SGS-USEL1 and the non-selected drain-side / source-side select gate lines SGD-USEL2, SGS-USEL2.

[0221] At time t9, memory device 1 applies a voltage of 0V to the adjacent drain-side / source-side select gate lines SGD-USEL1, SGS-USEL1 and the non-selected drain-side / source-side select gate lines SGD-USEL2, SGS-USEL2.

[0222] As described above, the memory device 1 of this embodiment terminates its read operation.

[0223] Negative voltages VOFF1 and VOFF3 may be applied to adjacent / unselected source-side select gate lines SGS-USEL1 and SGS-USEL2, and then to adjacent / unselected drain-side select gate lines SGD-USEL1 and SGD-USEL2.

[0224] The voltage applied to the non-selected drain-side select gate line SGD-USEL2 and the non-selected source-side select gate line SGS-USEL2 may be a voltage of 0V, VOFF2.

[0225] The timing for stopping the application of voltages VOFF1 and VOFF3 to adjacent / unselected source-side select gate lines SGS-USEL1 and SGS-USEL2 may differ from the timing for stopping the application of voltages VOFF1 and VOFF3 to adjacent / unselected drain-side select gate lines SGD-USEL1 and SGD-USEL2.

[0226] As in this embodiment, the stability of the operation of the memory device 1 can be adjusted by differentiating the timing of voltage application to the adjacent / unselected source-side select gate lines SGS-USEL1 and SGS-USEL2 from the timing of voltage application to the adjacent / unselected drain-side select gate lines SGD-USEL1 and SGD-USEL2.

[0227] As a result, the memory device 1 of this embodiment can improve the reliability of the memory device's operation.

[0228] Therefore, the memory device 1 of this embodiment can improve the operating characteristics of the memory device.

[0229] (4) Fourth Embodiment Referring to Figures 17 and 18, a memory device of the fourth embodiment and an example of the operation of the memory device will be described.

[0230] Figure 17 is a cross-sectional view showing an example of the structure of the memory device 1 of this embodiment.

[0231] As shown in Figure 17, the memory device 1 of this embodiment includes dummy word lines WLDD and WLDS within the memory cell array 10.

[0232] The wiring layer 25D, which serves as the dummy word line WLDD, is located between the drain-side select gate line layer 22 and the uppermost word line layer 23 (WL7). The wiring layer 25S, which serves as the dummy word line WLDS, is located between the source-side select gate line layer 24 and the lowermost word line layer 23 (WL0). Each wiring layer 25D and 25S extends in the X direction.

[0233] The memory pillar MP penetrates the wiring layers 25D and 25S.

[0234] The portion where the memory pillar MP and the wiring layer 25D intersect functions as a memory cell (dummy cell) DCD, which is not used to store data such as user information and setting information. The portion where the memory pillar MP and the wiring layer 25S intersect functions as a dummy cell DCS.

[0235] Figure 18 shows the circuit configuration of the NAND string NS, including the dummy word lines WLDD and WLDS, in the memory device 1 of this embodiment, and the voltage applied to each wire during operation of the memory device 1.

[0236] As shown in Figure 18, dummy cell DCD is connected between select transistor ST1 and memory cell MC7, and dummy cell DCS is connected between select transistor ST2 and memory cell MC1.

[0237] The gate of dummy cell DCD on the drain side of NAND string NS is connected to dummy word line WLDD. The gate of dummy cell DCS on the source side of NAND string NS is connected to dummy word line WLDS. Dummy word lines WLDD and WLDS are word lines to which dummy cells DCD and DCS are connected, and are word lines that are not accessible to the user.

[0238] At a certain point during a read operation of memory device 1, as described above, memory device 1 applies a negative voltage VOFF1 to the adjacent drain-side / source-side select gate lines SGD-USEL1 and SGS-USEL1. Memory device 1 also applies a non-selection voltage VREAD to the word line WL.

[0239] In this embodiment, the memory device 1 applies a voltage VDMY to the dummy word lines WLDD and WLDS. The voltage VDMY has a voltage value between the non-selective voltage VREAD and the voltage VOFF1. For example, the voltage VDMY is a positive voltage. The voltage VDMY has a voltage value of approximately +2V to +4V.

[0240] Applying voltage to the dummy word lines WLDD and WLDS makes the voltage gradient (amount of change) between the select gate line SG (SGD, SGS) and the word line WL gentler.

[0241] As a result, the memory device 1 of this embodiment can suppress the deterioration of reliability caused by the high electric field generated between the select gate line SG and the word line WL.

[0242] As described above, the memory device 1 of this embodiment can improve the operating characteristics of the memory device.

[0243] (5) Fifth embodiment Referring to Figures 19 and 20, a memory device and a control method for the memory device according to the fifth embodiment will be described.

[0244] Figure 19 is a schematic diagram illustrating the operating state of the memory device 1 of this embodiment during a write operation.

[0245] As shown in Figure 19, during the program operation of a write operation, the memory device 1 of this embodiment applies a program voltage VPGM or a non-selection voltage VPASS to the word line WL.

[0246] Memory device 1 applies a voltage VSGD having a positive voltage value to the selected drain side select gate line SGD-SEL (e.g., select gate line SGD1). The voltage value of voltage VSGD is, for example, +2V. Memory device 1 applies a voltage VOFF2 having a voltage value of 0V to the non-selected drain side select gate line (e.g., select gate line SGD3) SGD-USEL2.

[0247] During program operation, memory device 1 applies a voltage VOFF2 (VSGS) with a voltage value of 0V to the source-side select gate lines SGS-SEL, SGS-USEL1, and SGS-USEL2.

[0248] In this embodiment, the memory device 1 applies a voltage VOFF4 having a negative voltage value to the adjacent drain-side select gate line SGD-USEL1 (for example, select gate lines SGD0, SGD2). The voltage value of voltage VOFF4 is within the range of -2V to -1V.

[0249] This suppresses leakage from the memory pillar MP connected to the adjacent drain-side select gate line SGD-USEL1 during program operation.

[0250] Figure 20 is a timing chart showing an example of the operation of the memory device 1 in this embodiment.

[0251] <Time t10> As shown in Figure 20, at time t10, memory device 1 initiates a write operation on the target specified by address ADD, based on the command CMD from memory controller 2.

[0252] <Time t11> In the jth write loop (where j is an integer greater than or equal to 1), at time t11, memory device 1 begins applying voltage to the bit line BL, source line SL, and select gate lines SGD and SGS.

[0253] Memory device 1 applies a voltage of 0V to bit line BL to which memory cell MC to be programmed is connected. Memory device 1 applies a voltage VDDSA having a positive voltage value to bit line BL to which memory cell MC not to be programmed is connected.

[0254] Memory device 1 applies a voltage VSL having a positive voltage value to source line SL.

[0255] Memory device 1 applies a voltage VOFF2 having a voltage value of 0V to selected source side select gate line SGS-SEL, adjacent source side select gate line SGS-USEL1, and non-selected source side select gate line SGS-USEL2.

[0256] Memory device 1 applies a voltage VSGD having a positive voltage value to selected drain side select gate line SGD-SEL corresponding to selected string unit SU. Memory device 1 applies a voltage VOFF2 having a voltage value of 0V to non-selected drain side select gate line SGD-USEL2 not adjacent to selected drain side select gate line SGD-SEL.

[0257] In this embodiment, memory device 1 applies a voltage VOFF4 having a negative voltage value (for example, -2V) to adjacent drain side select gate line SGD-USEL1.

[0258] Select transistors ST1 connected to bit line BL to which voltage VDDSA is applied and non-selected drain side select gate lines SGD-USEL1, SGD-USEL2 are cut off.

[0259] <Time t12> At time t12, memory device 1 applies non-selection voltage VPASS to selected word line WL-SEL and non-selected word line WL-USEL. Thereby, semiconductor layer 31 of memory pillar MP connected to adjacent / non-selected drain side select gate lines SGD-USEL1, SGD-USEL2 is boosted.

[0260] In this embodiment, by applying a negative voltage VOFF4 to the adjacent drain-side select gate line SGD-USEL1, leakage occurring in the memory pillar MP connected to the adjacent drain-side select gate line SGD-USEL1 is suppressed. Therefore, defects in the channel boost of the semiconductor layer 31 during program operation are suppressed.

[0261] <Time t13> At time t13, memory device 1 applies a program voltage VPGM, which is higher than the non-selection voltage VPASS, to the selected word line WL-SEL. The potential of the selected word line WL-SEL rises from the non-selection voltage VPASS to the program voltage VPGM.

[0262] When the program voltage VPGM is applied, the threshold voltage of the memory cell MC to be programmed increases.

[0263] <Time t14> At time t14, memory device 1 stops applying the program voltage VPGM. Memory device 1 applies the non-selection voltage VPASS to the selection word line WL-SEL. The potential of the selection word line WL-SEL decreases from the program voltage VPGM to the non-selection voltage VPASS.

[0264] <Time t15> At time t15, memory device 1 stops applying voltage to the selected word line WL-SEL and the unselected word line WL-USEL. The potentials of the selected word line WL-SEL and the unselected word line WL-USEL become 0V.

[0265] <Time t19> At time t19, memory device 1 stops applying voltage to the bit line BL, source line SL, and select gate lines SGD and SGS. The potentials of the bit line BL and source line become 0V. The potential of the selected source side select gate line SGS-SEL, and the potentials of the adjacent / unselected source side select gate lines SGS-USEL1 and SGS-USEL2 become 0V. The potential of the selected drain side select gate line SGD-SEL decreases from voltage VSGD to 0V. The potential of the unselected drain side select gate line SGD-USEL2 becomes 0V. The potential of the adjacent drain side select gate line SGD-USEL1 increases from voltage VOFF4 to 0V.

[0266] As a result, memory device 1 terminates its program operation.

[0267] After the program execution, memory device 1 performs a verify operation. As described above, during the verify operation, memory device 1 applies a negative voltage VOFF1 to the adjacent drain-side / source-side select gate lines SGD-USEL1 and SGS-USEL1. During the verify operation, memory device 1 may also apply a negative voltage VOFF3 to the non-selected drain-side / source-side select gate lines SGD-USEL2 and SGS-USEL2.

[0268] If the verification operation fails, memory device 1 attempts the program operation again. If the verification operation passes, the memory device terminates the write operation.

[0269] As described above, memory device 1 terminates the write operation.

[0270] During program operation, a negative voltage VOFF4 may be applied to the adjacent source-side select gate line SGS-USEL1. The negative voltage VOFF4 may be applied to the non-select drain-side select gate line SGD-USEL2 and the non-select source-side select gate line SGS-USEL2. During program operation, a negative voltage VOFF4 may be applied to the select source-side select gate line SGS-SEL.

[0271] In the memory device 1 of this embodiment, during program operation, it is possible to suppress the select transistor ST1 connected to the adjacent select gate line SGD-USEL1 from entering a weak-on state due to the influence of the electric field from the select gate line SGD-SEL.

[0272] Therefore, during program operation, the memory device 1 of this embodiment can boost the potential of the semiconductor layer of the memory pillar MP connected to the adjacent select gate line SGD-USEL1 without being affected by leakage caused by the select transistor ST1 in the weak-on state.

[0273] As a result, the memory device 1 of this embodiment can achieve suppression of miswriting during write operation and improvement of the charging speed of the wiring.

[0274] As described above, the memory device 1 of this embodiment can improve the operating characteristics of the memory device.

[0275] (6) Sixth Embodiment Referring to FIGS. 21 to 27, the memory device of the seventh embodiment and an operation example of the memory device will be described.

[0276] (a) Configuration Example Referring to FIGS. 21 to 26, a configuration example of the memory device 1 of this embodiment will be described.

[0277] (a-1) Structure of Memory Cell Array Referring to FIGS. 21 to 25, the structure of the memory device 1 of this embodiment will be described.

[0278] Figure 21 is a plan view showing an example of the structure of the memory device 1 of this embodiment. Figures 22 and 23 are cross-sectional views showing an example of the structure of the memory device 1 of this embodiment. Figure 22 shows the cross-sectional structure of the memory cell array 10 along line AA in Figure 21. Figure 23 shows the cross-sectional structure of the memory cell array 10 along line BB in Figure 21.

[0279] As shown in Figures 21 to 23, the memory device 1 of this embodiment differs from the memory device 1 of the other embodiments described above in the configuration of the select gate lines SGD, SGS and the select transistors ST1 (ST1U, ST1L) and ST2 (ST2U, ST2L).

[0280] Each of the multiple drain-side select gate lines SGD (SGD0, SGD1, SGD2, SGD3) contains two wiring layers 22U, 22L. Each of the multiple source-side select gate lines SGS (SGS0, SGS1, SGS2, SGS3) contains two wiring layers 24U, 24L.

[0281] The wiring layers 22U and 22L are located above the stacked wiring layers 23 (word lines WL) in the Z direction. Multiple wiring layers 22U are located above multiple wiring layers 22L and below the bit lines BL in the Z direction. Multiple wiring layers 22U are aligned in the Y direction. Multiple wiring layers 22L are aligned in the Y direction. A pair of wiring layers 22U and 22L overlapping in the Z direction corresponds to one drain-side select gate line SGD. In one block BLK, if there are four string units SU, then in each memory area MA1 and MA2, there are four wiring layers 22U and four wiring layers 22L aligned in the Y direction. The wiring layers 22U and 22L are covered by an insulating layer 95.

[0282] In a pair of wiring layers 22U and 22L that overlap in the Z direction (wiring layers 22U and 22L forming one drain-side select gate wire SGD), the dimension of wiring layer 22U along the Y direction is different from the dimension of wiring layer 22L along the Y direction. In a pair of wiring layers 22U and 22L, the contact CC on wiring layer 22U is aligned with the contact CC on wiring layer 22L in the X direction and in a direction oblique to the Y plane.

[0283] The wiring layers 24U and 24L are located below the stacked wiring layers 23 (word lines WL) in the Z direction. Multiple wiring layers 24U are located above multiple wiring layers 24L and below the word lines WL in the Z direction. Multiple wiring layers 24U are aligned in the Y direction. Multiple wiring layers 24L are aligned in the Y direction. A pair of two wiring layers 24U and 24L overlapping in the Z direction corresponds to one source-side select gate line SGS. In one block BLK, if the number of string units SU is four, then in each memory area MA1 and MA2, there are four wiring layers 24U and four wiring layers 24L aligned in the Y direction. The wiring layers 22U and 22L are covered by an insulating layer 96.

[0284] In a pair of wiring layers 24U and 24L that overlap in the Z direction (wiring layers 24U and 24L forming one source-side select gate line SGS), the dimension of wiring layer 24U along the Y direction is different from the dimension of wiring layer 24L along the Y direction. In a pair of wiring layers 24U and 24L, the contact CC on wiring layer 24U is aligned with the contact CC on wiring layer 24L in diagonal directions with respect to the X and Y directions.

[0285] In this embodiment, the pillar section PLR includes semiconductor pillars SP1U, SP1L, SP2U, and SP2L in addition to the memory pillar MP.

[0286] Multiple semiconductor pillars SP1U and SP1L are positioned above the memory pillar MP in the Z direction. Semiconductor pillar SP1U is positioned above semiconductor pillar SP1L in the Z direction. Semiconductor pillar SP1L is positioned between semiconductor pillar SP1U and memory pillar MP. Semiconductor pillar SP1L connects semiconductor pillar SP1U to memory pillar MP. Semiconductor pillar SP1U is connected to bit line BL via contact CV.

[0287] Multiple semiconductor pillars SP1U penetrate each wiring layer 22U. An insulating layer (gate insulating film) 50 is provided between the side surface of the semiconductor pillar SP1U and the wiring layer 22U. The portion where the semiconductor pillar SP1U and the wiring layer 22U intersect functions as a select transistor ST1U.

[0288] Multiple semiconductor pillars SP1L penetrate each wiring layer 22L. An insulating layer (gate insulating film) 51 is provided between the side surface of the semiconductor pillar SP1L and the wiring layer 22L. The portion where the semiconductor pillar SP1L and the wiring layer 22L intersect functions as a select transistor ST1L.

[0289] Multiple semiconductor pillars SP2U and SP2L are located below the memory pillar MP in the Z direction. Semiconductor pillar SP2U is located above semiconductor pillar SP2L in the Z direction. Semiconductor pillar SP2U is located between semiconductor pillar SP2L and memory pillar MP. Semiconductor pillar SP2U connects semiconductor pillar SP2L to memory pillar MP. Semiconductor pillar SP2L is directly connected to the wiring layer 43 of the source line SL.

[0290] Multiple semiconductor pillars SP2U penetrate each wiring layer 24U. An insulating layer (gate insulating film) 52 is provided between the side surface of the semiconductor pillar SP2U and the wiring layer 24U. The portion where the semiconductor pillar SP2U and the wiring layer 24U intersect functions as a select transistor ST2U.

[0291] Multiple semiconductor pillars SP2L penetrate each wiring layer 24L. An insulating layer (gate insulating film) 53 is provided between the side surface of the semiconductor pillar SP2L and the wiring layer 24L. The portion where the semiconductor pillar SP2L and the wiring layer 24L intersect functions as a select transistor ST2L.

[0292] Component SHE1U is provided between adjacent wiring layers 22U in the Y direction. Component SHE1U separates adjacent wiring layers 22U. Component SHE1L is provided between adjacent wiring layers 22L in the Y direction. Component SHE1L separates adjacent wiring layers 22L. Component SHE1L does not overlap with component SHE1U in the Z direction.

[0293] Component SHE2U is provided between adjacent wiring layers 24U in the Y direction. Component SHE2U separates adjacent wiring layers 24U. Component SHE2L is provided between adjacent wiring layers 24L in the Y direction. Component SHE2L separates adjacent wiring layers 24L. Component SHE2L does not overlap with component SHE2U in the Z direction.

[0294] The memory device 1 of this embodiment can be formed by a combination of well-known memory device manufacturing processes.

[0295] Referring to Figures 24 and 25, the configuration of the drain-side select gate line SGD and the source-side select gate line SGS in the memory device of this embodiment will be described in more detail.

[0296] Figure 24 is a schematic plan view showing the structure of wiring layers 22U and 22L in the layer where wiring layer 22U is provided and the layer where wiring layer 22L is provided, with respect to the drain-side select gate wire SGD. Note that the insulating layers 50 and 51 are not shown in Figure 24. Figure 25 is a schematic plan view showing the structure of wiring layers 24U and 24L in the layer where wiring layer 24U is provided and the layer where wiring layer 24L is provided, with respect to the source-side select gate wire SGS. Note that the insulating layers 52 and 53 are not shown in Figure 25.

[0297] As shown in Figure 24, multiple semiconductor pillars SP1U and SP1L are arranged in a staggered pattern at each layer (wiring level) to correspond to the arrangement of memory pillars MP. In the following, a set of multiple semiconductor pillars SP1, SP2 (pillar section PLR) that are aligned on the same straight line in the X direction is called a pillar set. For example, one string unit SU contains four pillar sets. In this case, the boundary between two string units SU lies between the 4k-th pillar set and the 4k+1-th pillar set.

[0298] For example, in semiconductor pillars SP1U and SP1L, a pillar set of 16 rows R1, R2, ..., R15, R16 is provided between two member SLTs aligned in the Y direction. Each of the two member SLTs is provided on one end and the other end of a block BLK in the Y direction.

[0299] With respect to semiconductor pillar SP1U, four pillar sets are aligned in the Y direction in each wiring layer 22U. With respect to semiconductor pillar SP1L, four pillar sets are aligned in the Y direction in each wiring layer 22L.

[0300] As shown in Figure 25, multiple semiconductor pillars SP2U and SP2L are arranged in a staggered pattern in each layer, corresponding to the arrangement of memory pillars MP.

[0301] For example, in semiconductor pillars SP2U and SP2L, a pillar set of 16 rows R1, R2, ..., R15, R16 is provided between two SLT members aligned in the Y direction.

[0302] Regarding semiconductor pillar SP2U, in each wiring layer 24U, four pillar sets are aligned in the Y direction. Regarding semiconductor pillar SP2L, in each wiring layer 24L, four pillar sets are aligned in the Y direction.

[0303] The components SHE1U, SHE2U, SHE1L, and SHE2L are provided on the semiconductor pillars SP1U, SP2U, SP1L, and SP2L of a certain row of pillar sets.

[0304] In wiring layers 22U and 24U, members SHE1U and SHE2U overlap with semiconductor pillars SP1U and SP2U of the pillar sets of the 4th row R4, 8th row R8, and 12th row R12. Members SHE1U and SHE2U extend in the X direction so as to overlap with the centers of the semiconductor pillars SP1U and SP2U. Each of the semiconductor pillars SP1U and SP2U of the pillar sets of the 4th row R4, 8th row R8, and 12th row R12 contains two parts p1 and p2 divided in the Y direction. The two parts p1 and p2 are independent of each other.

[0305] The components SHE1U and SHE2U electrically isolate two adjacent wiring layers 22U and two adjacent wiring layers 24U in the Y direction. The wiring layer 22U between component SLT at one end and component SHE1U on the pillar set of the 4th row R4 corresponds to the drain-side select gate line SGD0. The wiring layer 22U between component SHE1U on the pillar set of the 4th row R4 and component SHE1U on the pillar set of the 8th row R8 corresponds to the drain-side select gate line SGD1. The wiring layer 22U between component SHE1U on the pillar set of the 8th row R8 and component SHE1U on the pillar set of the 12th row R12 corresponds to the drain-side select gate line SGD2. The wiring layer 22U between component SHE1U on the pillar set of the 12th row R12 and component SLT at the other end corresponds to the drain-side select gate line SGD3. The wiring layer 24U between member SLT on one end and member SHE2U on the pillar set of the 4th row R4 corresponds to source-side select gate line SGS0. The wiring layer 24U between member SHE2U on the pillar set of the 4th row R4 and member SHE2U on the pillar set of the 8th row R8 corresponds to source-side select gate line SGS1. The wiring layer 24U between member SHE2U on the pillar set of the 8th row R8 and member SHE2U on the pillar set of the 12th row R12 corresponds to source-side select gate line SGS2. The wiring layer 24U between member SHE2U on the pillar set of the 12th row R12 and member SLT on the other end corresponds to source-side select gate line SGS3.

[0306] In wiring layers 22L and 24L, members SHE1L and SHE2L overlap with SP1L and SP2L of the pillar sets in the 5th row R5, 9th row R9, and 13th row R13. Members SHE1L and SHE2L extend in the X direction so as to overlap with the centers of the semiconductor pillars SP1L and SP2L. Each of the semiconductor pillars SP1L and SP2L of the pillar sets in the 5th row R5, 9th row R9, and 13th row R13 contains two parts p3 and p4 divided in the Y direction. The two parts p3 and p4 are independent of each other.

[0307] The components SHE1L and SHE2L electrically isolate two adjacent wiring layers 22L and two adjacent wiring layers 24L in the Y direction. The wiring layer 22L between component SLT at one end and component SHE1L on the pillar set of the 5th row R5 corresponds to the drain-side select gate line SGD0. The wiring layer 22L between component SHE1L on the pillar set of the 5th row R5 and component SHE1L on the pillar set of the 9th row R9 corresponds to the drain-side select gate line SGD1. The wiring layer 22L between component SHE1L on the pillar set of the 9th row R9 and component SHE1L on the pillar set of the 13th row R13 corresponds to the drain-side select gate line SGD2. The wiring layer 22L between component SHE1L on the pillar set of the 13th row R13 and component SLT at the other end corresponds to the drain-side select gate line SGD3. The wiring layer 24L between member SLT on one end and member SHE2L on the pillar set of the 5th row R5 corresponds to source-side select gate line SGS0. The wiring layer 24L between member SHE2L on the pillar set of the 5th row R5 and member SHE2L on the pillar set of the 9th row R9 corresponds to source-side select gate line SGS1. The wiring layer 24L between member SHE2U on the pillar set of the 9th row R9 and member SHE2L on the pillar set of the 13th row R13 corresponds to source-side select gate line SGS2. The wiring layer 24L between member SHE2L on the pillar set of the 13th row R13 and member SLT on the other end corresponds to source-side select gate line SGS3.

[0308] Thus, in this embodiment, in the wiring layers 22U and 22L included in each of the multiple drain-side select gate lines SGD, member SHE1U for separating adjacent upper wiring layers 22U is provided at a position overlapping with the 4k-th row semiconductor pillar SP1U, and member SHE1L for separating adjacent lower wiring layers 22L is provided at a position overlapping with the 4k+1-th row semiconductor pillar SP1L. The position of member SHE1U is offset from the position of member SHE1L by the length of one row of semiconductor pillar SP1 in the Y direction.

[0309] Furthermore, in this embodiment, in the wiring layers 24U and 24L included in each of the multiple source-side select gate lines SGS, a member SHE2U for separating adjacent upper wiring layers 24U is provided at a position overlapping with the 4k-th row semiconductor pillar SP2U, and a member SHE2L for separating adjacent lower wiring layers 24L is provided at a position overlapping with the 4k+1-th row semiconductor pillar SP2L. The position of member SHE2U is offset from the position of member SHE2L by the length of one row of semiconductor pillar SP2 in the Y direction.

[0310] As a result, the memory device 1 of this embodiment suppresses leakage in select transistors ST1 and ST2 connected to select gate lines SGD and SGS adjacent to the selected select gate lines SGD and SGS, which is caused by the electric field generated from the selected select gate lines SGD and SGS.

[0311] As a result, the memory device 1 of this embodiment can boost the potential of the memory pillar MP while reducing the influence of the weakly ON select transistors ST1 and ST2.

[0312] Furthermore, if the positions of the members SHE1U and SHE2U between the upper wiring layers 22U and 24U are shifted by one column of pillar sets compared to the positions of the members SHE1L and SHE2U between the lower wiring layers 22L and 24L, the number of pillar sets included in one string unit SU may be three columns or less, or five columns or more.

[0313] (a-2) Circuit configuration of memory cell array Figure 26 is a circuit diagram of the memory cell array 10 of the memory device 1 in this embodiment.

[0314] The example shown in Figure 26 illustrates the configuration of the memory cell array 10 with respect to four bit lines BL. In this embodiment, the memory cell array 10 includes a plurality of configurations shown in Figure 26 that are repeatedly arranged in the X direction with respect to the period of the four bit lines BL.

[0315] As shown in Figure 26, each bit line BL (BL0, BL1, BL2, BL3) is electrically connected to the corresponding NAND string NS (pillar section PLR) within each string unit SU.

[0316] In this embodiment, the NAND string NS includes two drain-side select transistors ST1U and ST1L, and two source-side select transistors ST2U and ST2L.

[0317] In each string unit SU, the current path of one select transistor ST1U is connected in series with the current path of the other select transistor ST1L. The gates of select transistors ST1U and ST1L are electrically connected to a corresponding drain-side select gate line SGD.

[0318] In each string unit SU, the current path of one select transistor ST2U is connected in series with the current path of the other select transistor ST2L. The gates of select transistors ST2U and ST2L are electrically connected to a corresponding single source-side select gate line SGS.

[0319] The NAND string NS corresponding to the 4kth column pillar PLR is electrically connected, for example, to the 4th bit line BL3.

[0320] As shown in the structures of Figures 21 to 25, when the semiconductor pillar SP1U included in the 4kth row NAND string NS is separated into two parts p1 and p2 by component SHE1U, the transistor STxU is connected in parallel with the select transistor ST1U. The current path of transistor STxU is connected in series with the current path of transistor ST1L. The gate of transistor STxU belonging to a certain string unit SUq corresponding to a certain drain-side select gate line SGDq is electrically connected to the drain-side select gate line SGDq+1 corresponding to the adjacent string unit SUq+1. The portion where part p1 and the wiring layer 22U intersect functions as transistor ST1U. The portion where part p2 and the wiring layer 22U intersect functions as transistor STxU. q is an integer between 0 and 2, inclusive.

[0321] Thus, in a select transistor ST1U and a transistor STxU provided on a semiconductor pillar SP1U, the drain-side select gate line SGD connected to the transistor STxU is different from the drain-side select gate line SGD connected to the select transistor ST1U.

[0322] For example, the 4k-th column NAND string NS further includes a parasitic transistor PTa in the semiconductor pillar SP1U. The parasitic transistor PTa arises between a portion p1 and a wiring layer 22U that does not directly contact portion p1, or between a portion p2 and a wiring layer 22U that does not directly contact portion p2. The current path of the parasitic transistor PTa is connected in parallel with the current paths of transistors ST1U,STxU. The gate of the parasitic transistor PTa is not directly connected to the drain-side select gate line SGD. The parasitic transistor PTa operates due to the electric field generated from the wiring layer 22U that does not directly contact portions p1,p2.

[0323] Note that the fourth string unit SU3 does not include the transistors STxU,PTa in the NAND string NS connected to the fourth bit line BL3.

[0324] When semiconductor pillar SP2U, included in the 4k-th row NAND string NS, is separated into two parts p1 and p2 by component SHE2U, transistor STyU is connected in parallel with select transistor ST2U. The current path of transistor STyU is connected in series with the current path of transistor ST2L. The gate of transistor STyU belonging to a certain string unit SUq corresponding to a certain source-side select gate line SGSq is electrically connected to the source-side select gate line SGSq+1 corresponding to the adjacent string unit SUq+1. The portion where part p1 intersects with wiring layer 24U functions as transistor ST2U. The portion where part p2 intersects with wiring layer 24U functions as transistor STyU.

[0325] Thus, in a select transistor ST2U and a transistor STyU provided on a semiconductor pillar SP2U, the source-side select gate line SGS connected to transistor STyU is different from the source-side select gate line SGS connected to select transistor ST2U.

[0326] For example, the 4k-th column NAND string NS further includes a parasitic transistor PTb in the semiconductor pillar SP2U. The parasitic transistor PTb arises between a portion p1 and a wiring layer 24U that does not directly contact portion p1, or between a portion p2 and a wiring layer 24U that does not directly contact portion p2. The current path of the parasitic transistor PTb is connected in parallel with the current paths of transistors ST2U and STyU. The gate of the parasitic transistor PTb is not directly connected to the source-side select gate line SGS. The parasitic transistor PTb operates due to the electric field generated from the wiring layer 24U that does not directly contact portions p1 and p2.

[0327] Note that the fourth string unit SU3 does not include transistors STyU and PTb in the NAND string NS connected to the fourth bit line BL3.

[0328] When semiconductor pillar SP1L, included in the 4k+1th row NAND string NS, is separated into two parts p3 and p4 by component SHE1L, transistor STxL is connected in parallel with select transistor ST1L. The current path of transistor STxL is connected in series with the current path of transistor ST1U. The gate of transistor STxL belonging to a certain string unit SUq corresponding to a certain drain-side select gate line SGDq is electrically connected to the drain-side select gate line SGDq+1 corresponding to the adjacent string unit SUq+1. The portion where part p3 intersects with wiring layer 22L functions as transistor STxL. The portion where part p4 intersects with wiring layer 22L functions as transistor ST1L.

[0329] Thus, in a select transistor ST1L and a transistor STxL provided on a semiconductor pillar SP1L, the drain-side select gate line SGD connected to transistor STxL is different from the drain-side select gate line SGD connected to select transistor ST1L.

[0330] For example, the 4k+1 column NAND string NS further includes a parasitic transistor PTc in the semiconductor pillar SP1L. The parasitic transistor PTc arises between a portion p3 and a wiring layer 22L that does not directly contact portion p3, or between a portion p4 and a wiring layer 22L that does not directly contact portion p4. The current path of the parasitic transistor PTc is connected in parallel with the current paths of transistors ST1L,STxL. The gate of the parasitic transistor PTc is not directly connected to the drain-side select gate line SGD. The parasitic transistor PTc operates due to the electric field generated from the wiring layer 22L that does not directly contact portions p3,p4.

[0331] Note that the first string unit SU1 does not include transistors STxL,PTc in the NAND string NS connected to the first bit line BL0.

[0332] When semiconductor pillar SP2L in the 4k+1th row NAND string NS is separated into two parts p3 and p4 by component SHE2L, transistor STyL is connected in parallel with select transistor ST2L. The current path of transistor STyL is connected in series with the current path of transistor ST2U. The gate of transistor STyL belonging to a certain string unit SUq corresponding to a certain source-side select gate line SGSq is electrically connected to the source-side select gate line SGSq+1 corresponding to the adjacent string unit SUq+1. The portion where part p3 intersects with wiring layer 24L functions as transistor STyL. The portion where part p4 intersects with wiring layer 24L functions as transistor ST2L.

[0333] Thus, in a select transistor ST2L and a transistor STyL provided on a semiconductor pillar SP2L, the source-side select gate line SGS connected to transistor STyL is different from the source-side select gate line SGS connected to select transistor ST2L.

[0334] For example, the 4k+1 column NAND string NS further includes a parasitic transistor PTd in the semiconductor pillar SP2L. The parasitic transistor PTd arises between portion p3 and a wiring layer 24L that does not directly contact portion p3, or between portion p4 and a wiring layer 24L that does not directly contact portion p4. The current path of the parasitic transistor PTd is connected in parallel with the current paths of transistors ST2L and STyL. The gate of the parasitic transistor PTd is not directly connected to the source-side select gate line SGS. The parasitic transistor PTd operates due to the electric field generated from the wiring layer 24L that does not directly contact portions p3 and p4.

[0335] Note that the first string unit SU1 does not include transistors STyL and PTd in the NAND string NS connected to the first bit line BL0.

[0336] (b) Example of operation Referring to Figure 27, an example of the operation (control method) of the memory device 1 of this embodiment will be described.

[0337] Figure 27 is a timing chart showing an example of the operation of the memory device 1 in this embodiment. In Figure 27, the horizontal axis corresponds to time, and the vertical axis corresponds to the voltage or current value of each wire. In Figure 27, the read operation of the memory device 1 is shown as an example of the operation of the memory device 1 in this embodiment.

[0338] <Time t20> As shown in Figure 27, at time t20, memory device 1 initiates a read operation on the target specified at address ADD, based on the command CMD from memory controller 2.

[0339] <Time t21> At time t21, memory device 1 begins applying voltage to multiple wires WL, SGD, and SGS within the selection block BLK. This causes the potentials of the multiple wires WL, SGD, and SGS within the selection block BLK to change.

[0340] Memory device 1 applies a non-selection voltage VREAD to the selected word line WL-SEL and the non-selected word line WL-USEL. Memory device 1 also applies a voltage VON to the drain-side select gate lines SGD-SEL, SGD-USEL and the source-side select gate lines SGS-SEL, SGS-USEL.

[0341] In response to the application of voltage to the word line WL and the select gate lines SGD and SGS, a charging current IWL is generated in the word line WL. The current value of the charging current IWL increases.

[0342] <Time t22> At a certain time t22, the potentials of the drain-side select gate lines SGD-SEL, SGD-USEL and the source-side select gate lines SGS-SEL, SGS-USEL reach a certain voltage value. At this time t22, memory device 1 stops applying a positive voltage to the unselected drain-side select gate line SGD-USEL and the unselected source-side select gate line SGS-USEL. Memory device 1 applies a voltage of 0V VOFF0 to the unselected drain-side / source-side select gate lines SGD-USEL, SGS-USEL.

[0343] <Time t23> At time t23, the potential of the non-selected drain-side select gate line SGD-USEL and the potential of the non-selected source-side select gate line SGS-USEL reach 0V.

[0344] This turns off the select transistors ST1U and ST1L connected to the non-selected drain-side select gate line SGD-USEL, and the non-selected source-side select transistors ST2U and ST2L.

[0345] Of the transistors STxU in the 4k-th column NAND string NS mentioned above, the transistor STxU connected to the selected drain side select gate line SGD-SEL is turned ON, and the transistor STxU connected to the unselected drain side select gate line SGD-USEL is turned OFF.

[0346] In this case, in the unselected string unit SU, the gate of transistor ST1L, which is connected in series with transistor STxU connected to the selected drain-side select gate line SGD-SEL, is connected to the unselected drain-side select gate line SGD-SEL. Therefore, even if the parasitic transistor STxU is ON in the unselected string unit SU, the current path of transistor STxU is electrically isolated from the current path of the memory cell MC by the OFF-state select transistor ST1L.

[0347] Similarly, for each of the transistors STyU in the 4k-th column NAND string NS, the transistor STyU connected to the selected source side select gate line SGS-SEL is turned ON, and the transistor STyU connected to the unselected source side select gate line SGS-USEL is turned OFF.

[0348] In a non-selected string unit SU, the gate of transistor ST2L, which is connected in series with transistor STyU connected to the selected source side select gate line SGS-SEL, is connected to the non-selected source side select gate line SGS-SEL. Therefore, in a non-selected string unit SU, even if the parasitic transistor STyU is ON, the current path of transistor STyU is electrically isolated from the source line SL by the OFF select transistor ST2L.

[0349] Furthermore, for each of the transistors STxL in the 4k+1 column NAND string NS, the transistor STxL connected to the selected drain side select gate line SGD-SEL is turned ON, and the transistor STxL connected to the unselected drain side select gate line SGD-USEL is turned OFF.

[0350] In the non-selected string unit SU, the gate of transistor ST1U, which is connected in series with transistor STxL connected to the selected drain-side select gate line SGD-SEL, is connected to the non-selected drain-side select gate line SGD-SEL. Therefore, in the non-selected string unit SU, even if the parasitic transistor STxL is ON, the current path of transistor STxL is electrically isolated from the bit line BL by the OFF-state selected transistor ST1U.

[0351] For each of the transistors STyL in the 4k+1 column NAND string NS, the transistor STyL connected to the selected source side select gate line SGS-SEL is turned ON, and the transistor STyL connected to the unselected source side select gate line SGS-USEL is turned OFF.

[0352] In the non-selected string unit SU, the gate of transistor ST2U, which is connected in series with transistor STyL connected to the selected source side select gate line SGS-SEL, is connected to the non-selected source side select gate line SGS-SEL. Therefore, in the non-selected string unit SU, even if the parasitic transistor STyL is ON, the current path of transistor STyL is electrically isolated from the current path of the memory cell MC by the OFF state select transistor ST2U.

[0353] Parasitic transistors PTa, PTb, PTc, and PTd enter a weakly ON state due to the influence of electric fields from the select gate lines SGD-SEL and SGS-SEL. The weakly ON parasitic transistor PTa is electrically isolated from the current path of the memory cell MC by the OFF select transistor ST1L. The weakly ON parasitic transistor PTb is electrically isolated from the source line SL by the OFF select transistor ST2L. The weakly ON parasitic transistor PTc is electrically isolated from the bit line BL by the OFF select transistor ST1U. The weakly ON parasitic transistor PTd is electrically isolated from the current path of the memory cell MC by the OFF select transistor ST2U.

[0354] Thus, in this embodiment, in the non-selection string unit SU, at least one of the two series-connected select transistors ST1U and ST1L electrically isolates the parasitic transistors STxU, STxL, PTa, and PTc generated within the NAND string NS (pillar portion PLR) from the bit line BL or the current path of the memory cell MC. In the non-selection string unit SU, at least one of the two series-connected select transistors ST2U and ST2L electrically isolates the parasitic transistors STyU, STyL, PTb, and PTd generated within the NAND string NS (pillar portion PLR) from the source line SL or the current path of the memory cell MC.

[0355] This suppresses leakage in the NAND string NS (pillar portion PLR) in the non-selected string unit SU.

[0356] During the period from time t22 to time t23, depending on the off state of select transistors ST1U, ST1L, ST2U, ST2L, the semiconductor layer CHN-USEL of the memory pillar MP connected to the unselected select gate lines SGD-USEL and SGS-USEL rises in proportion to the charge potential ΔV of the unselected word line WL-USEL. For example, the potential of the semiconductor layer CHN-USEL reaches the voltage VBoost.

[0357] The potentials of the word lines WL-SEL and WL-USEL reach the voltage VREAD. The potentials of the selected drain-side select gate line SGD-SEL and the selected source-side select gate line SGS-SEL reach the voltage VON.

[0358] <Time t24> At time t24, memory device 1 applies the read voltage VCGRV to the selected word line WL-SEL. Memory device 1 also applies the voltage VBL to the bit line BL and the voltage VCELSRC to the source line SL. The read voltage VCGR includes one or more read levels depending on the page being read.

[0359] <Time t28> At time t28, memory device 1 stops applying the read voltage VCGRV to the selected word line WL-SEL, the voltage VBL to the bit line BL, and the voltage VCELSRC to the source line SL. Memory device 1 then starts applying the deselection voltage VREAD to the selected word line WL-SEL. As a result, the potential of the selected word line WL-SEL rises to the deselection voltage VREAD.

[0360] Memory device 1 stops applying voltage VOFF to the unselected drain-side select gate line SGD-USEL and the unselected source-side select gate line SGS-USEL. Memory device 1 starts applying a positive voltage (e.g., voltage VREAD) to the unselected drain-side / source-side select gate lines SGD-USEL and SGS-USEL. As a result, the potential of the unselected drain-side / source-side select gate lines SGD-USEL and SGS-USEL rises to a positive voltage. The transistors ST1U, ST1L, STxU, and STxL connected to the unselected drain-side select gate line SGD-USEL, and the select transistors ST2U, ST2L, STyU, and STyL connected to the source-side select gate line SGS-USEL, turn on due to the applied positive voltage.

[0361] <Time t29> At time t29, memory device 1 stops applying voltage to the word lines WL-SEL, WL-USEL, drain-side select gate lines SGD-SEL, SGD-USEL, and source-side select gate lines SGS-SEL, SGS-USEL. As a result, the potential of each wire WL, SGD, and SGS is set to 0V.

[0362] The memory device 1 transfers the data output from the memory cell array 10 to the memory controller 2 as read data.

[0363] With the above operations, the memory device 1 of this embodiment terminates its read operation.

[0364] The example of operation of the memory device 1 in this embodiment may also be applied to the verification operation of the write operation of the memory device 1.

[0365] (c) Variant A modified example of the memory device 1 of this embodiment will be described with reference to Figure 28.

[0366] Figure 28 is a timing chart showing a modified example of the operation of the memory device 1 in this embodiment.

[0367] As shown in Figure 28, the timing of applying the voltage VOFF0 to the non-selected drain-side select gate line SGD-USEL may differ from the timing of applying the voltage VOFF0 to the non-selected source-side select gate line SGS-SEL.

[0368] In the example shown in Figure 28, memory device 1 applies a voltage VOFF0 to the unselected drain-side select gate line SGD-U at time t22. Subsequently, at time t22z, memory device 1 applies a voltage VOFF0 to the unselected source-side select gate line SGS-USEL.

[0369] Furthermore, after the voltage VOFF0 is applied to the non-selected source-side select gate line SGS-USEL, the voltage VOFF0 may also be applied to the non-selected drain-side select gate line SGD-USEL.

[0370] This ensures the operational stability and reliability of the memory device 1 in this embodiment.

[0371] (d) Summary In the memory device 1 of this embodiment, each drain-side select gate line SGD is composed of two wiring layers 22U and 22L stacked in the Z direction, and each source-side select gate line SGS is composed of two wiring layers 24U and 24L stacked in the Z direction. Select transistors ST1U and ST1L are provided at the intersections of the wiring layers 22U and 22L and the semiconductor pillars SP1U and SP1L. Select transistors ST2U and ST2L are provided at the intersections of the wiring layers 24U and 24L and the semiconductor pillars SP2U and SP2L.

[0372] The member SHE1U for separating the upper wiring layer 22U that constitutes the drain-side select gate line SGD is provided so as to overlap with the semiconductor pillar SP1U of the 4k-th row pillar PLR. The member SHE1L for separating the lower wiring layer 22L that constitutes the drain-side select gate line SGD is provided so as to overlap with the semiconductor pillar SP1L of the 4k+1-th row pillar PLR.

[0373] Depending on the arrangement of components SHE1U and SHE1L, parasitic transistors STxU, STxL, STa, and STc are generated within the semiconductor pillars SP1U and SP1L.

[0374] As in this embodiment, the separation positions between multiple select gate lines SGD differ between the upper wiring layer 22U and the lower wiring layer 22L, so that one of the select transistors ST1U, ST1L, which is in the off state, electrically isolates the on-state transistors STxU, STxL, STa, STc from the bit line BL or the current path of the memory cell MC.

[0375] As a result, the memory device 1 of this embodiment can prevent leakage occurring on the drain side of the memory pillar MP of the NAND string NS of the non-selected string unit SU.

[0376] Furthermore, the member SHE2U for separating the upper wiring layer 22U that constitutes the source-side select gate line SGS is provided so as to overlap with the semiconductor pillar SP2U of the 4k-th row pillar PLR. The member SHE2L for separating the lower wiring layer 24L that constitutes the source-side select gate line SGS is provided so as to overlap with the semiconductor pillar SP2L of the 4k+1-th row pillar PLR.

[0377] Depending on the arrangement of components SHE2U and SHE2L, parasitic transistors STyU, STyL, STb, and STd are generated within the semiconductor pillars SP2U and SP2L.

[0378] Because the separation points between multiple select gate lines SGS differ between the upper wiring layer 24U and the lower wiring layer 24L, one of the select transistors ST2U and ST2L, the off-state select transistor ST2, electrically isolates the on-state transistors STyU, STyL, STb, and STd from the source line SL or the current path of the memory cell MC.

[0379] As a result, the memory device 1 of this embodiment can reduce leakage occurring on the source side of the memory pillar MP of the NAND string NS of the non-selected string unit SU.

[0380] Therefore, the memory device 1 of this embodiment can suppress channel boost failures in the memory pillar MP caused by leakage.

[0381] Furthermore, the memory device 1 of this embodiment does not require dummy members to separate the select gate lines SG within the memory cell array 10. Therefore, the memory device 1 of this embodiment can suppress the increase in manufacturing costs due to the placement of dummy members.

[0382] As described above, the memory device 1 of this embodiment can improve the operating characteristics of the memory device.

[0383] (7) Seventh Embodiment A memory device of the seventh embodiment will be described with reference to Figures 29 to 31.

[0384] Figure 29 is a cross-sectional view showing the cross-sectional structure of the memory cell array 10 in the memory device 1 of this embodiment. Figure 30 is a schematic plan view showing the structure of wiring layers 24U and 24L in the layer where wiring layer 24U is provided and the layer where wiring layer 24L is provided with respect to the source-side select gate line SGS. In Figure 30, the depiction of insulating layers 52 and 53 is omitted.

[0385] As shown in Figures 29 and 30, in the memory device 1 of this embodiment, the positions of members SHE2U and SHE2L provided in the wiring layers 24U and 24L constituting the source-side select gate line SGS are different from the positions of members SHE1U and SHE1L provided in the wiring layers 22U and 22L constituting the drain-side select gate line SGD.

[0386] As described above, in order to separate the upper wiring layers 22U of the drain-side select gate line SGD, member SHE1U is provided so as to overlap with the upper semiconductor pillar SP1U belonging to the 4k-th column pillar PLR (NAND string NS). In order to separate the lower wiring layers 22L of the drain-side select gate line SGD, member SHE1L is provided so as to overlap with the lower semiconductor pillar SP1L belonging to the 4k+1-th column pillar PLR.

[0387] In this embodiment, to separate the upper wiring layers 24U of the source-side select gate line SGS, member SHE2U is provided so as to overlap with the upper semiconductor pillar SP2 belonging to the 4k+1th column pillar PLR. To separate the lower wiring layers 24L of the source-side select gate line SGS, member SHE2L is provided so as to overlap with the lower semiconductor pillar SP2L belonging to the 4kth column pillar PLR.

[0388] Thus, the position of member SHE2U coincides with the position of member SHE1L in the Z direction. Also, the position of member SHE2L coincides with the position of member SHE1U in the Z direction.

[0389] Furthermore, with respect to the wiring layers 22U and 22L of the drain-side select gate wire SGD, member SHE1U may be provided so as to overlap with the upper semiconductor pillar SP1U belonging to the 4k+1th column pillar PLR, and member SHE1L may be provided so as to overlap with the lower semiconductor pillar SP1L belonging to the 4kth column pillar PLR.

[0390] Figure 31 is a circuit diagram of the memory cell array 10 in the memory device 1 of this embodiment.

[0391] As shown in Figure 31, in the source-side select transistors ST2U and ST2L of the 4k-th column NAND string NS, transistor STyL is connected in parallel with select transistor ST2L. Also, in the source-side select transistors ST2U and ST2L of the 4k+1-th column NAND string NS, transistor STyU is connected in parallel with select transistor ST2U.

[0392] Parasitic transistor STb is connected in parallel with select transistor ST2L. Parasitic transistor STd is connected in parallel with select transistor ST2U.

[0393] During the operation of the memory device 1 in this embodiment (for example, during a read operation), in the 4k-th column NAND string NS (pillar portion PLR), the transistor STyL connected to the selected source side select gate line SGS-SEL is electrically isolated from the current path of the memory cell MC by the select transistor ST2U connected to the non-selected select gate line SGS-USEL.

[0394] Therefore, in the unselected string unit SU, the semiconductor layer 31 of the memory pillar MP of the 4k-th column NAND string NS is channel-boosted without leakage.

[0395] In the 4k+1 column NAND string NS, the transistor STyU connected to the selected source side select gate line SGS-SEL is electrically isolated from the source line SL by the select transistor ST2L connected to the non-selected select gate line SGS-USEL.

[0396] Therefore, in the unselected string unit SU, the semiconductor layer 31 of the memory pillar MP of the 4k+1 column NAND string NS is channel-boosted without leakage.

[0397] Therefore, the memory device 1 of this embodiment can achieve substantially the same effects as the embodiment described above.

[0398] As described above, the memory device 1 of this embodiment can improve its operating characteristics.

[0399] (8) Eighth embodiment The eighth embodiment of the memory device will be described with reference to Figures 32 to 36.

[0400] Figure 32 is a schematic plan view showing the layers of the wiring layers 22U and 22L that constitute the drain-side select gate line SGD in the memory device 1 of this embodiment.

[0401] As shown in Figure 32, meandering members OPSaU and OPSaL are provided between adjacent wiring layers 22U and between adjacent wiring layers 22L, respectively, in the XY plane.

[0402] Each of the components OPSaU and OPSaL extends in the X direction. Components OPSaU and OPSaL contain an insulator.

[0403] The component OPSaU is provided between the wiring layers 22U. The component OPSaU is provided within a slit that extends in a meandering manner in the X direction. The component OPSaU is positioned, for example, in the region between the 4k-th column pillar PLR and the 4k+1-th column pillar PLR. The component OPSaU overlaps with the boundary end of the semiconductor pillar SP1U of the 4k-th column pillar PLR between the string units SU. The end of the semiconductor pillar SP1U of the 4k-th column pillar PLR is partially missing due to the component OPSaU. The planar shape of the 4k-th column semiconductor pillar SP1U, as viewed from the Z direction, has a segmental circular shape. The component OPSaU does not overlap with the semiconductor pillar SP1U of the 4k+1-th column pillar PLR. The semiconductor pillar SP1U of the 4k+1-th column pillar PLR is not missing due to the component OPSaU. The planar shape of the 4k+1 row semiconductor pillar SP1U, as viewed from the Z direction, is circular (or elliptical).

[0404] The component OPSaL is provided between the wiring layers 22L. The component OPSaL is provided within a slit that extends in a meandering manner in the X direction. The component OPSaL is positioned in the region between the 4k-th row pillar PLR and the 4k+1-th row pillar PLR. The component OPSaL does not overlap with the semiconductor pillar SP1L of the 4k-th row pillar PLR. The end of the semiconductor pillar SP1L of the 4k-th row pillar PLR is not cut off by the component OPSaL. The planar shape of the 4k-th row semiconductor pillar SP1L, as viewed from the Z direction, is circular. The component OPSaL overlaps with the boundary-side end of the semiconductor pillar SP1L of the 4k+1-th row pillar PLR between the string units SU. The end of the semiconductor pillar SP1L of the 4k+1-th row pillar PLR is partially cut off by the component OPSaL. The planar shape of the semiconductor pillar SP1L in the 4k+1 row, as viewed from the Z direction, has a segmental circular shape.

[0405] Figure 33 is a schematic plan view showing the layers of wiring layers 24U and 24L that constitute the source-side select gate line SGS in the memory device 1 of this embodiment.

[0406] As shown in Figure 33, similar to Figure 32, meandering members OPSbU and OPSbL are provided between adjacent wiring layers 24U and between adjacent wiring layers 24L, respectively.

[0407] Each of the components OPSbU and OPSbL is stretched in the X direction. Components OPSbU and OPSbL contain an insulator.

[0408] The component OPSbU is provided between the wiring layers 24U. The component OPSbU is provided within a slit that extends in a meandering manner in the X direction. The component OPSbU is positioned in the region between the 4k-th row pillar PLR and the 4k+1-th row pillar PLR. The component OPSbU overlaps with the boundary end of the semiconductor pillar SP2U of the 4k-th row pillar PLR between the string units SU. The end of the semiconductor pillar SP2U of the 4k-th row pillar PLR is partially missing due to the component OPSbU. The planar shape of the 4k-th row semiconductor pillar SP2U, as viewed from the Z direction, has a segmental circular shape. The component OPSbU does not overlap with the semiconductor pillar SP2U of the 4k+1-th row pillar PLR. The semiconductor pillar SP2U of the 4k+1-th row pillar PLR is not missing due to the component OPSbU. The planar shape of the 4k+1 row semiconductor pillar SP2U, as viewed from the Z direction, is circular.

[0409] Component OPSbL is provided between the wiring layers 24L. Component OPSbL is provided within a slit that extends in a meandering manner in the X direction. Component OPSbL is positioned in the region between the 4k-th row pillar PLR and the 4k+1-th row pillar PLR. Component OPSbL does not overlap with the semiconductor pillar SP2L of the 4k-th row pillar PLR. The end of the semiconductor pillar SP2L of the 4k-th row pillar PLR is not cut off by component OPSbL. The planar shape of the 4k-th row semiconductor pillar SP1L, as viewed from the Z direction, is circular. Component OPSbL overlaps with the boundary-side end of the semiconductor pillar SP2L of the 4k+1-th row pillar PLR between string units SU. The end of the semiconductor pillar SP2L of the 4k+1-th row pillar PLR is partially cut off by component OPSbL. The planar shape of the semiconductor pillar SP1L in the 4k+1 row, as viewed from the Z direction, has a segmental circular shape.

[0410] Figures 34 and 35 are cross-sectional views showing the cross-sectional structure of the memory device 1 of this embodiment. Figure 34 shows the cross-sectional structure of the memory cell array 10 along line AA in Figures 32 and 33. Figure 35 shows the cross-sectional structure of the memory cell array 10 along line BB in Figures 32 and 33.

[0411] As shown in Figures 34 and 35, in the layer of the wiring layer 22U above the drain-side select gate wire SGD, member OPSaU is in direct contact with the side surface of the semiconductor pillar SP1U of the 4k-th column pillar PLR. Member OPSaU is not in contact with the side surface of the upper semiconductor pillar SP1U of the 4k+1-th column pillar PLR. For example, the wiring layer 22U and the insulating layer 95 are located between member OPSaU and the side surface of the semiconductor pillar SP1U of the 4k+1-th column pillar PLR.

[0412] In the wiring layer 22L below the drain-side select gate wire SGD, component OPSaL directly contacts the side surface of the semiconductor pillar SP1L of the 4k+1 column pillar PLR. Component OPSaL does not contact the side surface of the semiconductor pillar SP1L of the 4k column pillar PLR. For example, the wiring layer 22L and the insulating layer 95 exist between component OPSaL and the side surface of the semiconductor pillar SP1L of the 4k column pillar PLR.

[0413] In the layer of the wiring layer 24U above the source-side select gate wire SGS, component OPSbU is in direct contact with the side surface of the semiconductor pillar SP2U of the 4k-th column pillar PLR. Component OPSbU is not in contact with the side surface of the semiconductor pillar SP2U of the 4k+1-th column pillar PLR. For example, the wiring layer 24U and the insulating layer 96 are located between component OPSbU and the side surface of the 4k+1-th column semiconductor pillar SP2U.

[0414] In the layer of wiring layer 24L below the source-side select gate wire SGS, component OPSbL is in direct contact with the side surface of the semiconductor pillar SP2L of the 4k+1 column pillar PLR. Component OPSbL is not in contact with the side surface of the semiconductor pillar SP2L of the 4k column pillar PLR. For example, wiring layer 24L and insulating layer 96 exist between component OPSbL and the side surface of the 4k column semiconductor pillar SP2L.

[0415] Furthermore, members OPSaU and OPSbU may be provided so as to overlap with the ends of the semiconductor pillars SP1U and SP2U in the 4k+1 row, and members OPSaL and OPSbL may be provided so as to overlap with the ends of the semiconductor pillars SP1L and SP2L in the 4k row.

[0416] Figure 36 is a circuit diagram showing the circuit configuration of the memory cell array 10 in the memory device 1 of this embodiment.

[0417] As shown in Figure 36, on the drain side of the 4kth column NAND string NS of a certain string unit SU, one select transistor ST1U is connected between the bit line BL and the select transistor ST1L. The 4kth column NAND string NS of a certain string unit SU does not contain a transistor connected to the drain side select gate line SGD of another string unit SU.

[0418] Thus, due to the meandering component OPSaU, the transistor connected in parallel to the select transistor ST1U (for example, the transistor STxU in Figure 26) is not formed within the semiconductor pillar SP1U that is common to the select transistor ST1U.

[0419] In the source side of the 4kth column NAND string NS of a certain string unit SU, one select transistor ST2U is connected between the memory cell MC and the select transistor ST2L. The 4kth column NAND string NS of a certain string unit SU does not contain a transistor connected to the source side select gate line SGS of another string unit SU.

[0420] Thus, due to the meandering component OPSbU, the transistor connected in parallel to the select transistor ST2U (for example, the transistor STyU in Figure 26) is not formed within the semiconductor pillar SP2U that is common to the select transistor ST2U.

[0421] On the drain side of the 4k+1th column NAND string NS of a certain string unit SU, one select transistor ST1L is connected between the select transistor ST1U and the memory cell MC. The 4k+1st column NAND string NS of a certain string unit SU does not contain a transistor connected to the drain-side select gate line SGD of another string unit SU.

[0422] Thus, due to the meandering component OPSaL, the transistor connected in parallel to the select transistor ST1L (for example, the transistor STxL in Figure 26) is not formed within the semiconductor pillar SP1L that is common to the select transistor ST1L.

[0423] In the source side of the 4k+1 column NAND string NS of a certain string unit SU, one select transistor ST2L is connected between the select transistor ST2U and the source line SL. The 4k+1 column NAND string NS of a certain string unit SU does not contain a transistor connected to the source side select gate line SGS of another string unit SU.

[0424] Thus, due to the meandering component OPSbL, the transistor connected in parallel to the select transistor ST2L (for example, the transistor STyL in Figure 26) is not formed within the semiconductor pillar SP2L common to the select transistor ST2L.

[0425] In this embodiment, the meandering member OPSbL divides the wiring layers 22U, 22L, 24U, and 22L for each corresponding select gate line SG so that the pillar portion PLR adjacent to the boundary of the string unit SU is not divided into multiple parts.

[0426] Therefore, the memory device 1 of this embodiment can reduce parasitic transistors that do not contribute to its operation. Consequently, the memory device 1 of this embodiment can stabilize its operation.

[0427] As described above, the memory device 1 of this embodiment can improve the operating characteristics of the memory device.

[0428] (9) The ninth embodiment A memory device of the ninth embodiment will be described with reference to Figures 37 and 38.

[0429] Figures 37 and 38 are cross-sectional views showing an example of the structure of the memory device 1 of this embodiment. Figure 37 shows a cross-section of the memory cell array 10 along a certain YZ plane. Figure 38 shows a cross-section of the memory cell array 10 along a different YZ plane than that shown in Figure 37.

[0430] As shown in Figures 37 and 38, in the memory device 1 of this embodiment, the members SHE1X and SHE2X for separating each select gate line SG are inclined diagonally with respect to the Z direction when viewed from the X direction.

[0431] Members SHE1X and SHE2X extend in the X direction. Members SHE1X and SHE2X are inclined in the Z direction from the 4k-th column pillar PLR to the 4k+1-th column pillar PLR.

[0432] Each pillar section PLR includes semiconductor pillar SP1X and semiconductor pillar SP2X. The memory pillar MP is provided between semiconductor pillar SP1X and semiconductor pillar SP2X in the Z direction. Semiconductor pillar SP1X is provided above memory pillar MP in the Z direction. Semiconductor pillar SP2X is provided below memory pillar MP in the Z direction.

[0433] The semiconductor pillar SP1X penetrates the wiring layers 22U and 22L of the drain-side select gate wire SGD. The sides of the semiconductor pillar SP1X are covered with an insulating layer 50X. The insulating layer 50X is provided between the semiconductor pillar SP1X and the wiring layer 22U, and between the semiconductor pillar SP1X and the wiring layer 22L.

[0434] The intersection of semiconductor pillar SP1X and wiring layer 22U functions as select transistor ST1U. The intersection of semiconductor pillar SP1X and wiring layer 22L functions as select transistor ST1L.

[0435] The semiconductor pillar SP2X penetrates the wiring layers 24U and 24L of the source-side select gate wire SGS. The sides of the semiconductor pillar SP2X are covered with an insulating layer 52X. The insulating layer 52X is provided between the semiconductor pillar SP2X and the wiring layer 22U, and between the semiconductor pillar SP2X and the wiring layer 24L.

[0436] The intersection of semiconductor pillar SP2X and wiring layer 24U functions as select transistor ST2U. The intersection of semiconductor pillar SP2X and wiring layer 24L functions as select transistor ST2L.

[0437] Furthermore, as in the embodiment described above, each semiconductor pillar SP1X, SP2X may be composed of two stacked semiconductor pillars.

[0438] In the hierarchy of the drain-side select gate line SGD, the inclined member SHE1X extends diagonally from the upper side of the 4k-th row semiconductor pillar SP1X to the lower side of the 4k+1-th row semiconductor pillar SP1X.

[0439] Component SHE1X is provided within a slit inclined with respect to the Z direction. Component SHE1X spans the layers of the upper wiring layer 22U and the lower wiring layer 22L.

[0440] Component SHE1X electrically isolates each of the multiple wiring layers 22U along the arrangement direction of the 4k-th row pillar PLR. The upper part of component SHE1X is provided on the semiconductor pillar SP1X of the 4k-th row pillar PLR and is also provided between the wiring layers 22U.

[0441] Component SHE1X electrically isolates each of the multiple wiring layers 22L along the arrangement direction of the 4k+1th row pillar PLR. The lower part of component SHE1X is provided on the semiconductor pillar SP1X of the 4k+1th row pillar PLR and is also provided between the wiring layers 22L.

[0442] The upper part of component SHE1X is located within the semiconductor pillar SP1X of the 4kth row. Preferably, the upper part of component SHE1X is located on the side of the semiconductor pillar SP1X of the 4k+1th row from the center of the semiconductor pillar SP1X of the 4kth row. The lower part of component SHE1X is located within the semiconductor pillar SP1X of the 4k+1th row. Preferably, the lower part of component SHE1X is located on the side of the semiconductor pillar SP21 of the 4kth row from the center of the semiconductor pillar SP1X of the 4k+1th row.

[0443] In each semiconductor pillar SP1X that overlaps with component SHE1X, the current path between the bit line BL and the memory pillar MP is secured within the semiconductor pillar SP1X.

[0444] In the hierarchy of the source-side select gate line SGS, the inclined member SHE2X extends diagonally from the upper side of the 4k-th row semiconductor pillar SP2X to the lower side of the 4k+1-th row semiconductor pillar SP2X.

[0445] Component SHE2X is provided within a slit inclined with respect to the Z direction. Component SHE2X spans the layers of the upper wiring layer 24U and the lower wiring layer 24L.

[0446] The component SHE2X electrically isolates each of the multiple wiring layers 24U along the arrangement direction of the 4k-th row pillar PLR. The upper part of component SHE2X is provided on the semiconductor pillar SP2X of the 4k-th row pillar PLR, and is also provided between the wiring layers 24U.

[0447] The component SHE2X electrically isolates each of the multiple wiring layers 24L along the arrangement direction of the 4k+1th row pillar PLR. The lower part of component SHE2X is provided on the semiconductor pillar SP2X of the 4k+1th row pillar PLR and is also provided between the wiring layers 24L.

[0448] The upper part of component SHE2X is located within the 4k-th row semiconductor pillar SP2X. Preferably, the upper part of component SHE2X is located on the side of the 4k+1-th row semiconductor pillar SP2X that is centered on the 4k-th row semiconductor pillar SP2X. The lower part of component SHE2X is located within the 4k+1-th row semiconductor pillar SP2X. Preferably, the lower part of component SHE2X is located on the side of the 4k-th row semiconductor pillar SP2X that is centered on the 4k-th row semiconductor pillar SP2X that is centered on the 4k-th row semiconductor pillar SP2X.

[0449] In each of the semiconductor pillars SP2X that overlap with component SHE2X, the current path between the source line SL and the memory pillar MP is secured within the semiconductor pillar SP2X.

[0450] The inclined members SHE1X and SHE2X are located within the boundary between adjacent string units SU.

[0451] In semiconductor pillars SP1X and SP2X within 4k rows of a certain string unit SU, the portion (semiconductor portion) facing the wiring layers 22U, 22L, 24U, and 24L belonging to the adjacent string unit SU is electrically isolated from the current path of the portion facing the wiring layers 22U, 22L, 24U, and 24L belonging to the string unit SU by members SHE1X and SHE2X that extend diagonally from the 4k row region to the 4k+1 row region.

[0452] In semiconductor pillars SP1X and SP2X within 4k+1 rows of a certain string unit SU, the portions facing the wiring layers 22U, 22L, 24U, and 24L belonging to the adjacent string unit SU are electrically isolated from the current path of the portions facing the wiring layers 22U, 22L, 24U, and 24L belonging to the string unit SU by members SHE1X and SHE2X that extend from the 4k row region to the 4k+1 row region.

[0453] Therefore, parasitic transistors connected in parallel with select transistors ST1 and ST2 are not formed within the same semiconductor pillars SP1X and SP2X as the select transistors ST1 and ST2.

[0454] As a result, the memory device 1 of this embodiment can suppress defects in the channel boost of the semiconductor layer of the memory pillar MP caused by leakage of transistors (e.g., parasitic transistors).

[0455] Therefore, the memory device 1 of this embodiment can improve the characteristics of the memory device.

[0456] (10) Others While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0457] 1: Memory device, 10: Memory cell array, MC0,..., MCn-1: Memory cell, ST1, ST2U, ST1L, ST2, ST2U, ST2L: Select transistor, WL0, WLn-1: Word line, BL0,..., BLm-1: Bit line, SGD0, SGD1, SGD2, SGD3: Drain-side select gate line, SGS0, SGS1, SGS2, SGS3: Source-side select gate line, PLR: Pillar section, MP: Memory pillar, SP1U, SP1L, SP2U, SP2L, SP1X, SP2X: Semiconductor pillar, OPS1, OPS2, OPS1X, OPSaU, OPSL, OPSbU, OPSbL, SHE1U, SHE1L, SHE2U, SHE2L, SHE1X, SHE2X: Components.

Claims

1. A first string including a plurality of first memory cells and a first transistor connected to one end of the plurality of first memory cells, A second string comprising a plurality of second memory cells and a second transistor connected to one end of the plurality of second memory cells, A plurality of word lines connected to each of the gates of the plurality of first memory cells and each of the gates of the plurality of second memory cells, A first wire connected to the gate of the first transistor, The second wiring is connected to the gate of the second transistor and is adjacent to the first wiring, A control circuit for controlling the operation of the first and second strings, It is equipped with, When the control circuit performs an operation on the first string as the target of the operation, A first voltage having a positive voltage value is applied to each of the plurality of word lines. A second voltage having a positive voltage value is applied to the first wiring, A third voltage having a negative voltage value is applied to the second wiring. It is configured in such a way. Memory device.

2. The device further comprises a first member for separating the first wiring and the second wiring. The first string includes a first pillar portion on which the first memory cell and the first transistor are provided. The second string includes a second pillar portion on which the second memory cell and the second transistor are provided. The first member is provided between the first pillar portion and the second pillar portion, and overlaps one end of the first pillar portion and one end of the second pillar portion. The memory device according to claim 1.

3. A third string comprising a plurality of third memory cells having gates connected to each of the plurality of word lines, and a third transistor connected to one end of the plurality of third memory cells, A third wire connected to the gate of the third transistor, It further includes, The second wiring is provided between the first wiring and the third wiring. The control circuit is configured to apply a fourth voltage having a voltage value of 0V or less to the third wiring when the operation is performed. The memory device according to claim 1.

4. The voltage value of the fourth voltage is a negative voltage value between the voltage value of the third voltage and 0V. The memory device according to claim 3.

5. The fourth wiring and, The fifth wiring adjacent to the fourth wiring, Furthermore, it is equipped with, The first string includes a fourth transistor connected to the other end of the plurality of first memory cells. The second string includes a fifth transistor connected to the other end of the plurality of second memory cells. The fourth wire is connected to the gate of the fourth transistor, The fifth wiring is connected to the gate of the fifth transistor, The control circuit, when executing the above operation, A fifth voltage having a positive voltage value is applied to the fourth wiring, A sixth voltage having a negative voltage value is applied to the fifth wiring. It is configured in such a way. The memory device according to claim 1.

6. The aforementioned control circuit is At the first time, the third voltage is applied to the second wiring. At a second time different from the first time, the sixth voltage is applied to the fifth wiring. The memory device according to claim 5.

7. The voltage value of the sixth voltage is different from the voltage value of the third voltage. The memory device according to claim 5.

8. It also includes a dummy word line, The first string includes a first dummy cell connected between the first transistor and one end of the plurality of first memory cells, The second string includes a second dummy cell connected between the second transistor and one end of the plurality of second memory cells. The dummy word line is connected to the gate of the first dummy cell and the gate of the second dummy cell. The control circuit applies a seventh voltage having a positive voltage value lower than the first voltage to the dummy word line when the operation is performed. The memory device according to claim 1.

9. The aforementioned operation is a read operation, The control circuit is configured to apply the first voltage to the plurality of word lines, and then apply a read voltage lower than the first voltage to a selected word line from among the plurality of word lines. The memory device according to claim 1.

10. The aforementioned operation is a write operation, The control circuit is configured to apply the first voltage to the plurality of word lines, and then apply a program voltage higher than the first voltage to a selected word line among the plurality of word lines. The memory device according to claim 1.

11. The first wiring layer that constitutes the word line, A second wiring layer is provided above the first wiring layer in a first direction perpendicular to the surface of the first wiring layer and constitutes the first wiring, A third wiring layer is provided between the first wiring layer and the second wiring layer, and constitutes the first wiring. A fourth wiring layer is provided above the first wiring layer in the first direction, adjacent to the second wiring layer in a second direction parallel to the surface of the first wiring layer, and constituting the second wiring. A fifth wiring layer is provided between the first wiring layer and the fourth wiring layer, and constitutes the second wiring. A plurality of pillar portions extending in the first direction, penetrating the first to fifth wiring layers, and arranged in an array, A first member provided between the second wiring layer and the fourth wiring layer, separating the fourth wiring layer from the second wiring layer, A second member is provided between the third wiring layer and the fifth wiring layer, separating the fifth wiring layer from the fifth wiring layer. It is equipped with, The position of the second member is offset from the position of the first member in the second direction. Memory device.

12. The plurality of pillar portions are arranged in the second direction, The first member overlaps with the kth pillar portion among the plurality of pillar portions, The second member overlaps with the k+1 pillar portion among the plurality of pillar portions, The aforementioned k is an integer greater than or equal to 1. The memory device according to claim 11.

13. Each of the plurality of pillar portions includes a first semiconductor pillar and a second semiconductor pillar provided on the first semiconductor pillar in the first direction. The first member overlaps with the second semiconductor pillar of the k-th pillar portion, The second member overlaps with the first semiconductor pillar of the k+1th pillar portion. The memory device according to claim 12.

14. The first semiconductor pillar of the k-th pillar portion penetrates the third wiring layer, The k-th pillar portion of the second semiconductor pillar includes a first portion facing the second wiring layer and a second portion facing the fourth wiring layer. The first semiconductor pillar of the k+1th pillar portion includes a third portion facing the third wiring layer and a fourth portion facing the fifth wiring layer, The second semiconductor pillar of the k+1th pillar portion penetrates the fourth wiring layer. The memory device according to claim 13.

15. A sixth wiring layer is provided below the first wiring layer in the first direction and constitutes the third wiring, A seventh wiring layer is provided between the first wiring layer and the sixth wiring layer, and the seventh wiring layer constitutes the wiring. An eighth wiring layer is provided below the first wiring layer in the first direction, adjacent to the sixth wiring layer in the second direction, and constituting the fourth wiring, A ninth wiring layer is provided between the first wiring layer and the eighth wiring layer, and constitutes the fourth wiring. A third member is provided between the sixth wiring layer and the eighth wiring layer, separating the eighth wiring layer from the sixth wiring layer. A fourth member is provided between the seventh wiring layer and the ninth wiring layer, separating the ninth wiring layer from the seventh wiring layer. Furthermore, it is equipped with, The position of the fourth member is offset from the position of the third member in the second direction. The memory device according to claim 11.

16. The position of the third member overlaps with the position of the second member in the first direction. The position of the fourth member coincides with the position of the first member in the first direction. The memory device according to claim 15.

17. The position of the third member overlaps with the position of the first member in the first direction. The position of the fourth member coincides with the position of the second member in the first direction. The memory device according to claim 15.

18. Each of the first and second members extends in a meandering manner in a third direction parallel to the surface of the first wiring layer and intersecting the second direction. The plurality of pillar portions are arranged in the second direction, The first and second members are provided between the k-th pillar portion and the (k+1)-th pillar portion among the plurality of pillar portions. The first member overlaps with the end of the k-th pillar portion, The second member overlaps with the end of the k+1 pillar portion, The k-th pillar portion faces the fourth wiring layer via the first member, The k+1th pillar portion corresponds to the third wiring layer via the second member, The aforementioned k is an integer greater than or equal to 1. The memory device according to claim 11.

19. Each of the plurality of pillar portions includes a first semiconductor pillar and a second semiconductor pillar provided on the first semiconductor pillar in the first direction. The first semiconductor pillar of the k-th pillar portion has a circular planar shape, The second semiconductor pillar of the k-th pillar overlaps with the first member, and the second semiconductor pillar of the k-th pillar has a non-circular planar shape with a missing arc when viewed from the first direction. The first semiconductor pillar of the k+1th pillar overlaps with the second member, and the first semiconductor pillar of the k+1th pillar has a non-circular planar shape with a missing arc when viewed from the first direction. The second semiconductor pillar of the k+1th pillar portion has a circular planar shape. The memory device according to claim 18.

20. The first member is continuous with the second member, The first member extends toward the second member in a direction oblique to the first direction. The memory device according to claim 11.

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