Semiconductor memory

Abstract

To improve the integration density of semiconductor memory devices. [Solution] The semiconductor memory device 3 according to the embodiment includes wiring layers 21 and a plurality of wiring layers 23 of memory cell array 10-1 and wiring layers 21 and a plurality of wiring layers 23 of memory cell array 10-2, which are arranged to overlap in this order in the Z direction, a first contact CC connected to one terrace portion of the plurality of wiring layers 23 of memory cell array 10-2 and extending in the Z direction, a second contact CX penetrating the bridge portion of the plurality of wiring layers 23 of memory cell array 10-1 in the Z direction, a third contact CC connected to one terrace portion of the plurality of wiring layers 23 of memory cell array 10-1 and extending in the Z direction, and first and second memory pillars MP provided, respectively, penetrating the plurality of wiring layers 23 of each of memory cell array 10-1 and 10-2 in the Z direction, wherein the first contact CC and the second contact CX are provided in positions that overlap in the Z direction and are electrically connected to each other.

Description

Technical Field

[0001] The embodiments relate to semiconductor memory devices.

Background Art

[0002] As a semiconductor memory device capable of storing data non-volatilely, a NAND-type flash memory is known. In a NAND-type flash memory, a three-dimensional memory structure may be adopted for high integration and large capacity.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Improve the integration degree of the semiconductor memory device.

Means for Solving the Problems

[0005] The semiconductor memory device according to the embodiment includes, viewed in a first direction, a first wiring layer provided in a first region, a plurality of second wiring layers provided above the first wiring layer, spanning the first region and a second region aligned in a second direction intersecting the first region and the first direction, spaced apart from each other in the first direction, wherein the plurality of second wiring layers have a plurality of first terrace portions provided within the second region so as not to overlap with the upper second wiring layer in the first direction, and a first bridge portion extending in the second direction, the plurality of first terrace portions and the first bridge portion aligned in a third direction intersecting the first and second directions, a third wiring layer provided in the first region above the plurality of second wiring layers, and a plurality of fourth wiring layers provided above the third wiring layer, spanning the first and second regions, spaced apart from each other in the first direction, wherein the plurality of fourth wiring layers are provided within the second region so as not to overlap with the upper fourth wiring layer in the first direction, and in a position that overlaps with the first bridge portion when viewed in the first direction. The device comprises a plurality of second terrace portions provided therein, and a second bridge portion extending in a second direction and positioned to overlap with the plurality of first terrace portions when viewed in a first direction, wherein the plurality of second terrace portions and the second bridge portion are arranged in a third direction, extend in a first direction within a first region, contact a first wiring layer, and the portion passing through the plurality of second wiring layers functions as a plurality of first memory cells; a second memory pillar extending in a first direction within a first region, contact a third wiring layer, and the portion passing through the plurality of fourth wiring layers functions as a plurality of second memory cells; a first contact in a second region that contacts one of the plurality of first terrace portions and extends in a first direction; a second contact in a second region that extends in a first direction above the first contact, passes through the plurality of fourth wiring layers and is electrically connected to the first contact; and a third contact in a second region that contacts one of the plurality of second terrace portions and extends in a first direction. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a block diagram showing an example of the configuration of a memory system according to the first embodiment. [Figure 2] Figure 2 is a perspective view showing an example of the appearance of a semiconductor memory device according to the first embodiment. [Figure 3]Figure 3 is a perspective view showing an overview of the bonding structure of the semiconductor memory device according to the first embodiment. [Figure 4] Figure 4 is a circuit diagram showing an example of the circuit configuration of a memory cell array provided in a semiconductor memory device according to the first embodiment. [Figure 5] Figure 5 is a plan view showing an example of a planar layout of a memory cell array in a semiconductor memory device according to the first embodiment. [Figure 6] Figure 6 is a schematic cross-sectional view showing an example of the cross-sectional structure of a bonded first memory layer and a second memory layer provided in a semiconductor memory device according to the first embodiment. [Figure 7] Figure 7 is a plan view showing an example of a planar layout in the memory area of ​​a memory cell array in a semiconductor storage device according to the first embodiment. [Figure 8] Figure 8 is a cross-sectional view along line VIII-VIII in Figure 7, showing an example of the cross-sectional structure in the memory region of a memory cell array in a semiconductor memory device according to the first embodiment. [Figure 9] Figure 9 is a cross-sectional view along the line IX-IX in Figure 8, showing an example of the cross-sectional structure of a memory pillar in a semiconductor memory device according to the first embodiment. [Figure 10] Figure 10 is a plan view showing an example of a planar layout in the extraction region of a memory cell array in a semiconductor memory device according to the first embodiment. [Figure 11] Figure 11 is a cross-sectional view along the line XI-XI in Figure 10, showing an example of the cross-sectional structure in the extraction region of the memory cell array of the semiconductor memory device according to the first embodiment. [Figure 12] Figure 12 is a cross-sectional view along line XII-XII in Figure 10, showing an example of the cross-sectional structure in the extraction region of the memory cell array of the semiconductor memory device according to the first embodiment. [Figure 13] Figure 13 is a cross-sectional view showing an example of the cross-sectional structure of a first memory layer, a second memory layer, and a junction layer provided between them, which are included in a semiconductor memory device according to the first embodiment. [Figure 14]Figure 14 is a cross-sectional view along line XIV-XIV in Figure 13, showing an example of the cross-sectional structure of the first memory layer, the second memory layer, and the junction layer provided between them in the semiconductor memory device according to the first embodiment. [Figure 15] Figure 15 is a cross-sectional view along the line XV-XV in Figure 13, showing an example of the cross-sectional structure of the first memory layer, the second memory layer, and the junction layer provided between them in the semiconductor memory device according to the first embodiment. [Figure 16] Figure 16 is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device according to the first embodiment. [Figure 17] Figure 17 is a cross-sectional view showing an example of a cross-sectional structure near two bonding pads provided in the bonding layer between the first memory layer and the second memory layer of a semiconductor memory device according to the first embodiment, and which are bonded to each other. [Figure 18] Figure 18 is a flowchart showing an example of the manufacturing process for a memory cell array in a semiconductor memory device according to the first embodiment. [Figure 19] Figure 19 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a semiconductor memory device according to the first embodiment. [Figure 20] Figure 20 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a semiconductor memory device according to the first embodiment. [Figure 21] Figure 21 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a semiconductor memory device according to the first embodiment. [Figure 22] Figure 22 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a semiconductor memory device according to the first embodiment. [Figure 23] Figure 23 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a semiconductor memory device according to the first embodiment. [Figure 24] Figure 24 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a semiconductor memory device according to the first embodiment. [Figure 25] Figure 25 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a semiconductor memory device according to the first embodiment. [Figure 26] Figure 26 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a semiconductor memory device according to the first embodiment. [Figure 27] FIG. 27 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of the semiconductor memory device according to the first embodiment. [Figure 28] FIG. 28 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of the semiconductor memory device according to the first embodiment. [Figure 29] FIG. 29 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of the semiconductor memory device according to the first embodiment. [Figure 30] FIG. 30 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of the semiconductor memory device according to the first embodiment. [Figure 31] FIG. 31 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of the semiconductor memory device according to the first embodiment. [Figure 32] FIG. 32 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of the semiconductor memory device according to the first embodiment. [Figure 33] FIG. 33 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of the semiconductor memory device according to the first embodiment. [Figure 34] FIG. 34 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of the semiconductor memory device according to the first embodiment. [Figure 35] FIG. 35 is a cross-sectional view showing an example of a cross-sectional structure of a first memory layer and a second memory layer included in the semiconductor memory device according to the first modification of the first embodiment, and a bonding layer provided therebetween. [Figure 36] FIG. 36 is a cross-sectional view showing an example of a cross-sectional structure of a first memory layer and a second memory layer included in the semiconductor memory device according to the second modification of the first embodiment, and a bonding layer provided therebetween. [Figure 37] FIG. 37 is a cross-sectional view showing an example of a cross-sectional structure in a lead-out region of a memory cell array included in the semiconductor memory device according to the third modification of the first embodiment. [Figure 38] FIG. 38 is a cross-sectional view showing an example of a cross-sectional structure of a first memory layer and a second memory layer included in the semiconductor memory device according to the second embodiment, and a bonding layer provided therebetween. [Figure 39]Figure 39 is a cross-sectional view along the line XXXIX-XXXIX in Figure 38, showing an example of the cross-sectional structure of the first memory layer, the second memory layer, and the junction layer provided between them in the semiconductor memory device according to the second embodiment. [Figure 40] Figure 40 is a cross-sectional view showing an example of the cross-sectional structure of a first memory layer, a second memory layer, and a junction layer provided between them, which are included in a semiconductor memory device according to a first modified example of the second embodiment. [Figure 41] Figure 41 is a cross-sectional view showing an example of the cross-sectional structure of a first memory layer, a second memory layer, and a junction layer provided between them, which are included in a semiconductor memory device according to a second modified example of the second embodiment. [Figure 42] Figure 42 is a plan view showing an example of a planar layout in the extraction region of a memory cell array in a semiconductor memory device according to the third embodiment. [Figure 43] Figure 43 is a cross-sectional view along the line XLIII-XLIII in Figure 42, showing an example of the cross-sectional structure in the extraction region of the memory cell array of the semiconductor memory device according to the third embodiment. [Figure 44] Figure 44 is a plan view showing an example of a planar layout of a memory cell array in a semiconductor memory device according to the fourth embodiment. [Figure 45] Figure 45 is a schematic cross-sectional view showing an example of the cross-sectional structure of a bonded first memory layer and a second memory layer in a semiconductor memory device according to the fourth embodiment. [Figure 46] Figure 46 is a plan view showing an example of a planar layout in the extraction area of ​​a memory cell array in a semiconductor memory device according to the fourth embodiment. [Figure 47] Figure 47 is a plan view showing an example of a planar layout in the extraction region of a memory cell array in a semiconductor memory device according to the fifth embodiment. [Figure 48] Figure 48 is a cross-sectional view showing an example of the cross-sectional structure of a first memory layer, a second memory layer, and a junction layer provided between them, which are included in a semiconductor memory device according to the fifth embodiment. [Figure 49]Figure 49 is a plan view showing an example of a planar layout in the extraction region of a memory cell array in a semiconductor memory device according to the sixth embodiment. [Figure 50] Figure 50 is a plan view showing an example of a planar layout of a memory cell array in a semiconductor memory device according to the seventh embodiment. [Figure 51] Figure 51 is a schematic cross-sectional view showing an example of the cross-sectional structure of a bonded first memory layer and a second memory layer provided in a semiconductor memory device according to the seventh embodiment. [Figure 52] Figure 52 is a plan view showing an example of a planar layout in the extraction region of a memory cell array in a semiconductor memory device according to the seventh embodiment. [Figure 53] Figure 53 is a cross-sectional view showing an example of the cross-sectional structure of a first memory layer, a second memory layer, and a junction layer provided between them, which are included in a semiconductor memory device according to the seventh embodiment. [Figure 54] Figure 54 is a plan view showing an example of a planar layout of a memory cell array in a semiconductor memory device according to the eighth embodiment. [Figure 55] Figure 55 is a schematic cross-sectional view showing an example of the cross-sectional structure of a bonded first memory layer and a second memory layer provided in a semiconductor memory device according to the eighth embodiment. [Figure 56] Figure 56 is a plan view showing an example of a planar layout in the extraction region of a memory cell array in a semiconductor memory device according to the eighth embodiment. [Modes for carrying out the invention]

[0007] Embodiments are described below with reference to the drawings. The drawings are schematic, and the dimensions and proportions shown are not necessarily the same as those of actual objects. In the following description, components having substantially the same function and configuration are denoted by the same reference numeral. When elements with similar configurations are to be specifically distinguished, different letters or numbers may be added to the end of the same reference numeral.

[0008] In the following description, "connected" to another second element means that the first element is connected to the second element indirectly, either through an intermediate element that is always or selectively conductive, or directly without an intermediate element.

[0009] 1. First Embodiment 1.1 Configuration 1.1.1 Memory System A semiconductor memory device according to the first embodiment will now be described. Figure 1 is a block diagram showing an example of the configuration of a memory system according to the first embodiment. Memory system 1 is a memory device configured to be connected to an external host device (not shown). Memory system 1 is, for example, an SD TM The memory is a card-like memory card, UFS (Universal Flash Storage), or SSD (Solid State Drive). The memory system 1 includes a memory controller 2 and a semiconductor storage device 3.

[0010] The memory controller 2 is composed of an integrated circuit, such as a System on a Chip (SoC). The memory controller 2 controls the semiconductor memory device 3 based on requests from an external host device. Specifically, the memory controller 2 writes data requested to be written by the external host device to the semiconductor memory device 3. The memory controller 2 also reads data requested to be read from the semiconductor memory device 3 and outputs it to the external host device.

[0011] The semiconductor memory device 3 is, for example, a NAND flash memory capable of storing data non-volatilely.

[0012] Communication between the memory controller 2 and the semiconductor memory device 3 conforms to, for example, an SDR (Single Data Rate) interface, a toggle DDR (Double Data Rate) interface, or an ONFI (Open NAND Flash Interface).

[0013] 1.1.2 Semiconductor Memory Devices Next, the internal configuration of the semiconductor memory device 3 according to the first embodiment will be described with reference to the block diagram shown in Figure 1. The semiconductor memory device 3 includes, for example, a plurality of memory cell arrays 10, input / output circuits 11, logic control circuits 12, registers 13, a sequencer 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0014] Multiple memory cell arrays 10 are sets of memory cell transistors and components connected to the memory cell transistors. Each memory cell array 10 includes multiple block BLKs. For example, each memory cell array 10 includes n+1 block BLK0 to BLKn (where n is an integer greater than or equal to 1). A block BLK is a collection of multiple memory cell transistors capable of storing data non-volatilely. A block BLK is used, for example, as an erase unit when erasing data stored by a memory cell transistor. Each memory cell array 10 is also provided with multiple bit lines and multiple word lines. Each memory cell transistor is associated, for example, with a combination of one bit line and one word line. The following description describes the case where two memory cell arrays 10-1 and 10-2 are provided. The circuit configurations of memory cell arrays 10-1 and 10-2 are substantially identical. In the following description, block BLKs included in memory cell array 10-1 are given the suffix "_1". Block BLKs included in memory cell array 10-2 are given the suffix "_2". In other words, the semiconductor memory device 3 includes multiple blocks BLK0_1 to BLKn_1 and multiple blocks BLK0_2 to BLKn_2. When memory cell arrays 10-1 and 10-2 are not distinguished, they are not denoted without a suffix. Note that there may be three or more memory cell arrays 10. The detailed configuration of the memory cell array 10 will be described later.

[0015] The input / output circuit 11 is an interface circuit that controls the transmission and reception of input / output signals between it and the memory controller 2. The input / output signals include, for example, data DAT, command CMD, address information ADD, and status information STA. The input / output circuit 11 inputs and outputs data DAT between the sense amplifier module 17 and the memory controller 2, respectively. The input / output circuit 11 outputs command CMD and address information ADD, each transferred from the memory controller 2, to register 13. The input / output circuit 11 outputs status information STA, transferred from register 13, to the memory controller 2.

[0016] The logic control circuit 12 receives control signals input from the memory controller 2. Based on these control signals, the logic control circuit 12 controls the input / output circuit 11 and the sequencer 14, respectively. For example, the logic control circuit 12 notifies the input / output circuit 11 that the input / output signal it has received is a command CMD or address information ADD, etc. The logic control circuit 12 commands the input / output circuit 11 to input or output the input / output signal. The logic control circuit 12 controls the sequencer 14 to enable the semiconductor memory device 3. The logic control circuit 12 also outputs a signal to the memory controller 2 indicating whether the semiconductor memory device 3 is ready or busy.

[0017] Register 13 temporarily stores command CMD, address information ADD, and status information STA. Command CMD includes, for example, instructions to cause the sequencer 14 to perform read, write, erase, etc. Address information ADD includes, for example, block address BA, page address PA, and column address CA. For example, block address BA, page address PA, and column address CA are used for selecting block BLK, word lines, and bit lines, respectively. Status information STA is updated based on the control of the sequencer 14 and transferred to the input / output circuit 11.

[0018] The sequencer 14 controls the overall operation of the semiconductor memory device 3. For example, based on the command CMD stored in register 13, the sequencer 14 controls the driver module 15, the row decoder module 16, the sense amplifier module 17, etc., and performs read operations, write operations, erase operations, etc.

[0019] The driver module 15 generates multiple voltages of different magnitudes used in read, write, and erase operations. The driver module 15 supplies the generated voltages to the row decoder module 16 and the sense amplifier module 17, etc. The driver module 15 also applies the generated voltages to the signal lines corresponding to the word lines selected based on the page address PA stored in register 13, for example.

[0020] The row decoder module 16 selects a corresponding block BLK within a memory cell array 10, for example, based on a block address BA stored in register 13. The row decoder module 16 then transfers the voltage of a signal line applied by the driver module 15 to a selected word line within the selected block BLK.

[0021] The sense amplifier module 17 includes a sense amplifier capable of determining data based on the voltage of the associated bit line, and a latch circuit for temporarily storing data. In a write operation, the sense amplifier module 17 applies a desired voltage to each bit line according to the write data DAT received from the input / output circuit 11. In a read operation, the sense amplifier module 17 determines the data stored in the memory cell transistor based on the magnitude of the bit line voltage. Subsequently, the sense amplifier module 17 transfers the determination result as read data DAT to the input / output circuit 11.

[0022] 1.1.3 Appearance of semiconductor memory devices The semiconductor memory device 3 according to the first embodiment is formed by bonding together three semiconductor circuit boards, each having a semiconductor circuit formed on it, and then separating the bonded semiconductor circuit boards chip by chip. That is, the semiconductor memory device 3 according to the first embodiment includes a structure formed by bonding a first semiconductor board, a second semiconductor board, and a third semiconductor board together. Each of the first to third semiconductor boards is, for example, a silicon board. The following describes the case in which the second semiconductor board and the third semiconductor board are removed during the manufacturing process of the semiconductor memory device 3. Depending on the structure of the semiconductor memory device 3, parts of the second semiconductor board and the third semiconductor board may remain after bonding.

[0023] Figure 2 is a perspective view showing an example of the appearance of a semiconductor memory device according to the first embodiment. Hatching has been added to Figure 2 to improve the visibility of the drawing, but this does not necessarily relate to the material or characteristics of the components to which the hatching has been added. As shown in Figure 2, the semiconductor memory device 3 has a structure in which, for example, a first semiconductor substrate W1, a control circuit layer 100, a junction layer B1, a junction layer B2, a first memory layer 200, a junction layer B3, a junction layer B4, a second memory layer 300, and a wiring layer 400 are stacked in order.

[0024] In the following explanation, the plane on which the first semiconductor substrate W1 is stretched is defined as the XY plane. Of the directions in which the stacked structure is stacked, the direction from the first semiconductor substrate W1 toward the wiring layer 400 is defined as the Z1 direction, and the direction from the wiring layer 400 toward the first semiconductor substrate W1 is defined as the Z2 direction. The Z1 and Z2 directions are approximately perpendicular to the first semiconductor substrate W1. When the Z1 and Z2 directions are not distinguished, each of them will simply be referred to as the Z direction.

[0025] The control circuit layer 100 includes a control circuit formed using a first semiconductor substrate W1. The first semiconductor substrate W1 has impurity diffusion regions, etc., according to the design of the control circuit. The control circuit layer 100 includes, for example, an input / output circuit 11, a logic control circuit 12, a register 13, a sequencer 14, a driver module 15, a low decoder module 16, and a sense amplifier module 17.

[0026] The bonding layer B1 is formed using the first semiconductor substrate W1. The bonding layer B1 includes a plurality of bonding pads that are electrically connected to a control circuit provided on the control circuit layer 100 and form a part of the semiconductor circuit.

[0027] The junction layer B2 is formed using a second semiconductor substrate (not shown). The junction layer B2 includes a plurality of junction pads that are electrically connected to the memory cell array 10-1 provided on the first memory layer 200 and form a part of the semiconductor circuit, and a plurality of junction pads that are electrically connected to the wiring for connecting the memory cell array 10-2 provided on the second memory layer 300 and the control circuit provided on the control circuit layer 100 and form a part of the semiconductor circuit.

[0028] The first memory layer 200 includes a memory cell array 10-1 formed using a second semiconductor substrate (not shown).

[0029] The bonding layer B3 is formed after the second semiconductor substrate is removed. The bonding layer B3 includes a plurality of bonding pads that are electrically connected to a plurality of bonding pads provided on the bonding layer B2 and form a part of the semiconductor circuit.

[0030] The junction layer B4 is formed using a third semiconductor substrate (not shown), and includes a plurality of junction pads that are electrically connected to the memory cell array 10-2 provided on the second memory layer 300 and form a part of the semiconductor circuit.

[0031] The second memory layer 300 includes a memory cell array 10-2 formed using a third semiconductor substrate (not shown).

[0032] The wiring layer 400 is formed after the first to third semiconductor substrates are bonded together. The wiring layer 400 includes wiring connected to semiconductor circuits provided on the second memory layer 300, as well as a plurality of pads PD. The plurality of pads PD are exposed on the surface of the semiconductor memory device 3. The plurality of pads PD are used to connect the semiconductor memory device 3 to the memory controller 2, etc.

[0033] Figure 3 is a perspective view showing an overview of the bonding structure of a semiconductor memory device according to the first embodiment. The bonding of the first to third semiconductor substrates will be explained using Figure 3. As shown in Figure 3, the semiconductor memory device 3 further includes a plurality of bonding pads BP1, BP2, BP3, and BP4, and a plurality of wiring PW.

[0034] As shown in Figure 3, the multiple bonding pads BP1 included in bonding layer B1 and the multiple bonding pads BP2 included in bonding layer B2 are connected to each other. As a result, the control circuit provided in the control circuit layer 100 and the memory cell array 10-1 provided in the first memory layer 200 are electrically connected to each other via bonding pads BP1 and BP2. In addition, the control circuit provided in the control circuit layer 100 and the wiring PW for connecting the control circuit to the memory cell array 10-2 provided in the first memory layer 200 passing through the memory cell array 10-1 in the Z direction are electrically connected to each other via bonding pads BP1 and BP2. The space between bonding layers B1 and B2 corresponds to the boundary between the layer formed using the first semiconductor substrate W1 and the layer formed using the second semiconductor substrate (not shown).

[0035] Multiple bonding pads BP3 contained in bonding layer B3 and multiple bonding pads BP4 contained in bonding layer B4 are connected to each other. As a result, the wiring PW provided in the first memory layer 200 and the memory cell array 10-2 provided in the second memory layer 300 are electrically connected to each other via bonding pads BP3 and BP4. That is, the control circuit provided in the control circuit layer 100 and the memory cell array 10-2 provided in the second memory layer 300 are electrically connected to each other via bonding pads BP1, BP2, BP3, and BP4, and wiring PW. The space between bonding layers B3 and B4 corresponds to the boundary between a layer formed using a second semiconductor substrate (not shown) and a layer formed using a third semiconductor substrate (not shown).

[0036] 1.1.4 Circuit configuration of memory cell array Below, an example of the circuit configuration of the memory cell array 10 provided in the semiconductor memory device 3 according to the first embodiment will be described. Figure 4 is a circuit diagram showing an example of the circuit configuration of the memory cell array provided in the semiconductor memory device according to the first embodiment. Figure 4 shows the circuit configuration in one block BLK. The block BLK includes, for example, five string units SU0 to SU4.

[0037] Each string unit SU includes multiple NAND strings NS, each associated with a bit line BL0 to BLm (where m is an integer greater than or equal to 1). Each NAND string NS includes, for example, seven memory cell transistors MT0 to MT6 and selection transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage film, and stores data nonvolatilously based on the amount of charge in the charge storage film. Selection transistors ST1 and ST2 are used to select the string unit SU during various operations.

[0038] In each NAND string NS, memory cell transistors MT0 to MT6 are connected in series in this order. The drain of selection transistor ST1 is connected to the associated bit line BL, and the source of selection transistor ST1 is connected to the drain of memory cell transistor MT6. The drain of selection transistor ST2 is connected to the source of memory cell transistor MT0, and the source of selection transistor ST2 is connected to the source line SL.

[0039] Within the same block BLK, the control gates of memory cell transistors MT0 to MT6 are connected to word lines WL0 to WL6, respectively. Within string units SU0 to SU4, the gates of selection transistors ST1 are connected to selection gate lines SGD0 to SGD4, respectively. Within the same block BLK, the gate of selection transistor ST2 is connected to selection gate line SGS.

[0040] Each bit line BL0 to BLm is assigned a different column address CA. Each bit line BL is shared among multiple block BLKs by a NAND string NS, which is assigned the same column address CA. Each word line WL0 to WL6 is provided for each block BLK. The source line SL is shared, for example, among multiple block BLKs.

[0041] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU is called, for example, a cell unit CU. For example, the storage capacity of a cell unit CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data". A cell unit CU may have a storage capacity of 2 pages of data or more, depending on the number of bits of data stored by the memory cell transistors MT.

[0042] The circuit configuration of each memory cell array 10 in the semiconductor memory device 3 according to the first embodiment is not limited to the above description. For example, the number of string units SU included in each block BLK can be designed to any number. The number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can each be designed to any number.

[0043] 1.1.5 Structure of a memory cell array The following describes an example of the structure of a plurality of memory cell arrays 10 provided in the semiconductor memory device 3 according to the first embodiment. The structures of the two memory cell arrays 10-1 and 10-2 provided in the semiconductor memory device 3 according to the first embodiment are similar. In the following description, the X direction corresponds to the extension direction of the word line WL. The Y direction corresponds to the extension direction of the bit line BL. In the plan view, hatching is added as appropriate to improve the visibility of the drawing. The hatching added to the plan view is not necessarily related to the material or properties of the component to which the hatching is added. In the cross-sectional view, the illustration of the components is omitted as appropriate to improve the visibility of the drawing. Also, in the following description, the Z2 direction is considered upward and the Z1 direction is considered downward.

[0044] 1.1.5.1 Overview Figure 5 is a plan view showing an example of a planar layout of a memory cell array in a semiconductor memory device according to the first embodiment. Figure 5 shows regions corresponding to six blocks BLK0 to BLK5. The sequential numbers at the end of each block BLK are assigned in ascending order from the top of the page. In each memory cell array 10, for example, the layout shown in Figure 5 is repeatedly arranged in the Y direction. Blocks BLK with even sequential numbers at the end are called "BLKe", and blocks with odd sequential numbers are called "BLKo".

[0045] Each memory cell array 10 includes stacked wiring, which is composed of multiple wiring layers (e.g., word lines WL0 to WL6, and selection gate lines SGS and SGD) stacked apart from each other in the Z direction. As shown in Figure 5, each memory cell array 10 includes multiple members SLT and multiple members SHE. The planar layout of the memory cell array 10 is divided, for example, in the X direction into memory areas MA1 and MA2, and a draw-out area HA. ​​The draw-out area HA is located between memory area MA1 and memory area MA2.

[0046] Memory areas MA1 and MA2 are areas used for data storage, containing multiple NAND strings NS. The lead area HA is an area used for connections between the stacked wiring and the low decoder module 16.

[0047] Multiple SLT members each extend along the X direction and are aligned in the Y direction. Each SLT member traverses the memory areas MA1 and MA2, and the extraction area HA in the X direction at the boundary region between adjacent blocks BLK. In other words, each region demarcated by an SLT member corresponds to one block BLK in each memory cell array 10. Each SLT member has a structure in which, for example, a plate-shaped contact is embedded inside an insulator. Each SLT member separates adjacent stacked wiring through it.

[0048] As shown in Figure 5, in this embodiment, among the multiple SLT members arranged in the Y direction, the SLT members arranged in odd-numbered positions are called "SLTo," and the SLT members arranged in even-numbered positions are called "SLTe." Each memory cell array 10 has multiple SLTo and SLTe members arranged alternately in the Y direction.

[0049] The extension area HA includes the stair area STP and the bridge area BRG. The stair area STP is provided across two block BLKs so as to straddle member SLTe. The bridge area BRG is provided in each block BLK between the stair area STP and member SLTo. That is, in each block BLK, one stair area STP and one bridge area BRG are provided side by side in the Y direction.

[0050] Multiple members SHE are arranged in memory areas MA1 and MA2, respectively. The multiple members SHE corresponding to memory area MA1 are each provided across memory area MA1 in the X direction and aligned in the Y direction. The multiple members SHE corresponding to memory area MA2 are each provided across memory area MA2 in the X direction and aligned in the Y direction. The right-hand end of each member SHE corresponding to memory area MA1 and the left-hand end of each member SHE corresponding to memory area MA2 are each included in the lead-out area HA. ​​For example, in memory areas MA1 and MA2, four members SHE are each arranged between adjacent members SLT in the Y direction. Each pair of regions demarcated by members SLT and SHE in memory area MA1 and each pair of regions demarcated by members SLT and SHE in memory area MA2 corresponds to one string unit SU in the memory cell array 10. Each member SHE has, for example, a structure in which an insulator is embedded. Each member SHE separates adjacent selection gate lines SGD through the member SHE.

[0051] The planar layout of the plurality of memory cell arrays 10 provided in the semiconductor memory device 3 according to the first embodiment is not limited to the layout described above. For example, the number of members SHE arranged between adjacent members SLT can be designed to be any number. The number of string units SU formed between adjacent members SLT can be changed based on the number of members SHE arranged between adjacent members SLT.

[0052] As shown in Figures 2 and 3, the semiconductor memory device 3 according to the first embodiment has a memory cell array 10-1 provided on the first memory layer 200 and a memory cell array 10-2 provided on the second memory layer 300, which are bonded together via junction layers B3 and B4. The outline of the bonding structure will be described below.

[0053] Figure 6 is a schematic cross-sectional view illustrating an example of the cross-sectional structure of a bonded first memory layer and second memory layer in a semiconductor memory device according to the first embodiment. Figure 6 shows the first memory layer 200, the second memory layer 300, and junction layers B3 and B4. As shown in Figure 6, the memory cell array 10-1 of the first memory layer 200 and the memory cell array 10-2 of the second memory layer 300 are bonded in the Z direction with a shift of one block BLK in the Y direction via junction layers B3 and B4.

[0054] Specifically, block BLK(i-1)_1 of memory cell array 10-1 is placed above block BLKi_2 of memory cell array 10-2 (where i is an integer satisfying 1 ≤ i ≤ n). That is, above even-numbered blocks BLKe_2 of memory cell array 10-2, odd-numbered blocks BLKo_1 of memory cell array 10-1 are placed. Above odd-numbered blocks BLKo_2 of memory cell array 10-2, even-numbered blocks BLKe_1 of memory cell array 10-1 are placed.

[0055] As shown in Figure 6, no block BLK in memory cell array 10-1 is provided above block BLK0_2 in memory cell array 10-2. Also, although not shown, no block BLK in memory cell array 10-2 is provided below block BLKn_1 (the last block BLK aligned in the Y direction) in memory cell array 10-1. Block BLK0_2 in memory cell array 10-2 and block BLKn_1 in memory cell array 10-1 are dummy blocks. The word line WL and selection gate lines SGD and SGS formed in the dummy block are not connected to the row decoder module 16. Therefore, the memory pillar MP formed in the dummy block does not store data.

[0056] In the two bonded memory cell arrays 10-1 and 10-2, the SLT components included in each are positioned to overlap approximately in the Z direction. Specifically, the SLTe component of memory cell array 10-1 is positioned above the SLTo component of memory cell array 10-2, and the SLTo component of memory cell array 10-1 is positioned above the SLTe component of memory cell array 10-2. In other words, one SLTo and one SLTe component are positioned to overlap in the Z direction. Of the SLT components adjacent to a dummy block, one that is not adjacent to another block BLK does not overlap with the other SLT components in the Z direction.

[0057] As shown in Figure 6, the stepped region STP of memory cell array 10-1 and the stepped region STP of memory cell array 10-2 are located side by side in the Y direction and at different positions in the Z direction in a plan view. Specifically, the bridge region BRG of memory cell array 10-2 is provided below the stepped region STP of memory cell array 10-1. The bridge region BRG of memory cell array 10-1 is provided above the stepped region STP of memory cell array 10-2. In other words, if a stepped region STP is provided in one of the memory cell arrays 10-1 and 10-2 at a position overlapping in the Z direction near a member SLT in any block BLK (excluding dummy blocks), forming a stepped structure, then a bridge region BRG is provided in the other, forming a structure in which multiple wiring layers 22 and 23 are stacked.

[0058] The detailed bonding structure of memory cell arrays 10-1 and 10-2 will be described later.

[0059] 1.1.5.2 Memory Area This section and the following section will refer to the structure common to memory cell arrays 10-1 and 10-2. The second and third semiconductor substrates used in the manufacture of memory cell arrays 10-1 and 10-2 are collectively referred to as semiconductor substrate W.

[0060] (Flat layout) Figure 7 is a plan view showing an example of a planar layout in the memory region of a memory cell array in a semiconductor memory device according to the first embodiment. While Figure 7 shows the structure of a single block BLK within memory region MA1 as a representative example, the structure of memory region MA2 is similar to that of memory region MA1. As shown in Figure 7, in memory regions MA1 and MA2, the memory cell array 10 includes a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL. Furthermore, each component SLT includes contacts LI and spacers SP.

[0061] Each memory pillar MP functions, for example, as a single NAND string NS. Multiple memory pillar MPs are arranged in a staggered pattern, for example, 24 rows in the Y direction, in the region between two adjacent members SLT. In the example shown in Figure 7, one member SHE overlaps each of the 5th, 10th, 15th, and 20th memory pillar MPs, counting from the top of the paper.

[0062] Multiple bit lines BL each extend in the Y direction and are aligned in the X direction. Each bit line BL is positioned to overlap with at least one memory pillar MP for each string unit SU. In the example shown in Figure 7, two bit lines BL are positioned to overlap with one memory pillar MP. If multiple bit lines BL overlap with a memory pillar MP, one bit line BL and the corresponding memory pillar MP are electrically connected via a contact CV. If only one bit line BL overlaps with a memory pillar MP, that bit line BL and the corresponding memory pillar MP are electrically connected via a contact CV.

[0063] For example, the contact CV between a memory pillar MP in contact with a component SHE and the corresponding bit line BL is omitted. In other words, the contact CV between a memory pillar MP and a bit line BL in contact with two different selection gate lines SGD is omitted. The number and arrangement of memory pillars MP and component SHE between adjacent component SLTs are not limited to the configuration shown in Figure 7 and can be changed as appropriate. For example, the number of bit lines BL overlapping each memory pillar MP can be designed to be any number.

[0064] Contact LI is a conductor extending in the XZ plane. The lower surface of contact LI is in contact with a source wire SL (not shown). Spacer SP is an insulator provided on the side of contact LI. In other words, spacer SP is provided in contact with contact LI so as to sandwich it in the Y direction.

[0065] (Cross-sectional structure) Figure 8 is a cross-sectional view along line VIII-VIII in Figure 7, showing an example of the cross-sectional structure in the memory region of a memory cell array in a semiconductor memory device according to the first embodiment. As shown in Figure 8, the memory cell array 10 further includes wiring layers 21-26, insulating layers 41-46, and contacts CV, V1, and V2.

[0066] An insulating layer 41, a wiring layer 22, and an insulating layer 42 are stacked in this order on top of a semiconductor substrate W (not shown). The wiring layer 22 is formed, for example, as a plate stretched along the X direction on the XY plane. The wiring layer 22 is used as a selectable gate line SGS. The wiring layer 22 contains, for example, tungsten (W) or molybdenum (Mo).

[0067] Multiple wiring layers 23 and multiple insulating layers 43 are alternately stacked above the insulating layer 42. Each wiring layer 23 is formed, for example, as a plate stretched along the X direction on the XY plane. Each wiring layer 23 is used as a word line WL0 to WL6, in order from the wiring layer 22 side. The multiple wiring layers 23 contain, for example, tungsten or molybdenum.

[0068] Above the uppermost insulating layer 43, the wiring layer 24, insulating layer 44, and insulating layer 45 are stacked in this order. The wiring layer 24 is formed, for example, as a plate stretched along the X direction on the XY plane. The wiring layer 24 is used as a selected gate wire SGD. The wiring layer 24 contains, for example, tungsten or molybdenum.

[0069] Multiple wiring layers 25 and an insulating layer 46 are stacked in this order above the insulating layer 45. Each wiring layer 25 is formed, for example, in a line extending along the Y direction. Each wiring layer 25 is used as a bit line BL. In areas not shown, the multiple wiring layers 25 are aligned along the X direction. The multiple wiring layers 25 contain, for example, copper.

[0070] Multiple wiring layers 26 are provided above the multiple wiring layers 25 and inside the insulating layer 46. Each wiring layer 26 is a wiring that relays the connection between the corresponding bit line BL (i.e., wiring layer 25) and the sense amplifier module 17. The multiple wiring layers 26 include, for example, copper.

[0071] Although not shown in the diagram, a junction layer is formed above the insulating layer 46. For example, in memory cell array 10-1, a junction layer B2 is provided above the insulating layer 46. In memory cell array 10-2, a junction layer B4 is provided above the insulating layer 46.

[0072] Subsequently, the semiconductor substrate W is removed, and a wiring layer 21 is provided. The wiring layer 21 is formed, for example, in the shape of a plate stretched along the X direction on the XY plane. The wiring layer 21 is used as a source wire SL. The wiring layer 21 contains, for example, polysilicon doped with impurities such as phosphorus.

[0073] Although not shown in the diagram, a wiring layer or junction layer is provided below the wiring layer 21. For example, a junction layer B3 is provided below the wiring layer 21 in memory cell array 10-1. A wiring layer 400 is provided below the wiring layer 21 in memory cell array 10-2.

[0074] Each memory pillar MP is provided extending along the Z direction. Each memory pillar MP penetrates the wiring layers 22-24 and the insulating layers 41-44. Each memory pillar MP has a cross-sectional area (XY cross-sectional area) that increases along the XY plane from bottom to top, for example. Each memory pillar MP includes, for example, a core film 30, a semiconductor film 31, and a multilayer film 32. The core film 30 is provided extending along the Z direction. For example, the upper end of the core film 30 is located within the insulating layer 45, and the lower end of the core film 30 is located within the wiring layer 21. The core film 30 includes, for example, an insulator such as silicon oxide (SiO). The semiconductor film 31 covers the periphery of the core film 30, for example. At the lower end and the sides near the lower end of the memory pillar MP, a portion of the semiconductor film 31 is in contact with the wiring layer 21. The semiconductor film 31 includes, for example, silicon. The multilayer film 32 covers the sides of the semiconductor film 31, except for the portion where the semiconductor film 31 and the wiring layer 21 are in contact.

[0075] In the structure of the memory pillar MP shown in Figure 8, the portion where the memory pillar MP intersects with the wiring layer 22 functions as a selection transistor ST2. The portions where the memory pillar MP intersects with each wiring layer 23 function as memory cell transistors MT0 to MT6, respectively. The portion where the memory pillar MP intersects with the wiring layer 24 functions as a selection transistor ST1.

[0076] Columnar contacts CV are provided on the upper surface of the semiconductor film 31 within the memory pillar MP. In the region shown in Figure 8, two of the six memory pillar MPs are shown with two corresponding contacts CV. For memory pillar MPs in this region that do not overlap with member SHE and to which no contacts CV are connected, other contacts CV are connected in a region not shown.

[0077] Each contact CV has a wiring layer 25, i.e., one bit line BL, in contact with its upper surface. One contact CV is connected to each wiring layer 25 in each of the spaces separated by members SLT and SHE. In other words, each wiring layer 25 is electrically connected, for example, to one memory pillar MP in each region between adjacent members SLT and SHE, and to one memory pillar MP in each region between two adjacent members SHE.

[0078] Contacts V1 and V2 are provided inside the insulating layer 46. Contact V1 contacts one wiring layer 25 on its lower surface and one wiring layer 26 on its upper surface, connecting the two. The lower surface of contact V2 contacts one wiring layer 26, and its upper surface is exposed from the insulating layer 46. Contact V2 connects the wiring layer 26 to a bonding pad included in the bonding layer provided on the upper side of the memory cell array 10. The wiring layers 25 and 26, along with contacts CV, V1 and V2, are collectively referred to as the upper wiring MUL.

[0079] The SLT members are formed, for example, to extend along the XZ plane. Each SLT member penetrates the wiring layers 22-24 and the insulating layers 41-44. Each SLT member has a width in the Y direction that increases from bottom to top.

[0080] Within the component SLT, the contact LI is provided so as to extend along the XZ plane, and the spacer SP is provided between the contact LI and the wiring layers 22-24. The upper end of the contact LI is located, for example, within the insulating layer 45. The lower end of the contact LI is in contact with, for example, the wiring layer 21. Note that the contact LI may be omitted depending on the structure of the memory cell array 10.

[0081] Component SHE is formed, for example, as a plate extending along the XZ plane, and separates the wiring layer 24 and the insulating layer 44. The upper end of component SHE is located within the insulating layer 45. The lower end of component SHE is located, for example, within the uppermost insulating layer 43. Component SHE includes an insulator such as silicon oxide. The upper end of component SHE and the upper end of component SLT may or may not be aligned. Similarly, the upper end of component SHE and the upper end of the memory pillar MP may or may not be aligned.

[0082] Figure 9 is a cross-sectional view along the line IX-IX in Figure 8, showing an example of the cross-sectional structure of a memory pillar in a semiconductor memory device according to the first embodiment. More specifically, Figure 9 shows the cross-sectional structure of a memory pillar MP in a layer parallel to the surface of a semiconductor substrate W (not shown) and including a wiring layer 23. As shown in Figure 9, the laminated film 32 includes, for example, a tunnel insulating film 33, a charge storage film 34, and a block insulating film 35.

[0083] In a cross-section including the wiring layer 23, the core film 30 is provided, for example, in the central part of the memory pillar MP. The semiconductor film 31 surrounds the sides of the core film 30. The tunnel insulating film 33 surrounds the sides of the semiconductor film 31. The charge storage film 34 surrounds the sides of the tunnel insulating film 33. The block insulating film 35 surrounds the sides of the charge storage film 34. The wiring layer 23 surrounds the sides of the block insulating film 35.

[0084] The semiconductor film 31 is used as the channel (current path) for the memory cell transistors MT0 to MT6 and the selection transistors ST1 and ST2. The tunnel insulating film 33 and the block insulating film 35 each contain, for example, silicon oxide. The charge storage film 34 has the function of storing charge and contains, for example, silicon nitride (SiN). With this configuration, each memory pillar MP can function as one NAND string NS.

[0085] 1.1.5.3 Drawer area (Flat layout) Figure 10 is a plan view showing an example of a planar layout in the extraction region of a memory cell array in a semiconductor memory device according to the first embodiment. Figure 10 shows the extraction region HA and a portion of the neighboring memory regions MA1 and MA2. The region shown in Figure 10 corresponds to blocks BLK0 to BLK2. Note that some insulating layers have been omitted in Figure 10 for the sake of simplicity.

[0086] The memory cell array 10 includes a plurality of contacts CC and CX in the extraction region HA. Contact CC is a contact that is electrically connected to one of the wiring layers 22 to 24 included in the memory cell array 10. Contact CX is a contact that is insulated from the wiring layers 22 to 24 included in the memory cell array 10 and passes through the stacked wiring in the Z direction. The plurality of contacts CX provided in the memory cell array 10-1 function as wiring PW that connects the plurality of contacts CC provided in the memory cell array 10-2 to the low decoder module 16 provided in the control circuit layer 100.

[0087] As shown in Figure 10, the selected gate line SGD includes a first portion SGDa located within the memory area MA1 and the extraction area HA near the memory area MA1, and a second portion SGDb located within the memory area MA2 and the extraction area HA near the memory area MA2. Furthermore, each of the first portion SGDa and the second portion SGDb has portions divided into five in the Y direction by multiple members SHE. Each portion of the selected gate line SGD divided in the Y direction by multiple members SHE is insulated from one another. That is, in one block BLK, the selected gate line SGD is divided into 10 portions.

[0088] Furthermore, in the first portion SGDa and the second portion SGDb of the selection gate line SGD, an inner contact region and an outer contact region are provided side by side in the X direction. The inner contact region is provided on the side of the lead-out region HA, and the outer contact region is provided on the side of the adjacent memory region MA1 or MA2. The inner contact region is distinguished by adding "e" to the end, and the outer contact region is distinguished by adding "o" to the end.

[0089] For each of the 10 divided selection gate lines SGD, one contact CC and one contact CX are provided in the inner contact area SGDe and one contact CX in the outer contact area SGDo, respectively. Specifically, for example, in the selection gate line SGD within an even-numbered block BLKe, a contact CC is provided in the inner contact area SGDe and a contact CX is provided in the outer contact area SGDo. In the selection gate line SGD within an odd-numbered block BLKo, a contact CX is provided in the inner contact area SGDe and a contact CC is provided in the outer contact area SGDo. Alternatively, in the selection gate line SGD within an even-numbered block BLKe, a contact CX may be provided in the inner contact area SGDe and a contact CC in the outer contact area SGDo. In the selection gate line SGD within an odd-numbered block BLKo, a contact CC may be provided in the inner contact area SGDe and a contact CX may be provided in the outer contact area SGDo.

[0090] Corresponding contacts CC on the first portion SGDa and the second portion SGDb of the selection gate line SGD are electrically connected to each other via an upper wiring layer (not shown). Corresponding contacts CX on the first portion SGDa and the second portion SGDb of the selection gate line SGD are electrically connected to each other via an upper wiring layer (not shown).

[0091] As shown in Figure 10, in the lead-out region HA, each wiring layer included in the multilayer wiring has a terrace portion that does not overlap with the wiring layer above it. The shape of the terrace portion of the multilayer wiring in the lead-out region HA is similar to a step, terrace, or rimstone. Contact CC is connected at the terrace portion of each wiring layer included in the multilayer wiring.

[0092] In the staircase region of the STP, a stadium-like staircase structure is formed in the stacked wiring. In a plan view, the stadium-like staircase structure is formed such that the terrace portion of the upper wiring layer surrounds the terrace portion of the lower wiring layer on all four sides. In other words, the stadium-like staircase structure has a structure that is recessed in a step-like manner toward the center. The stadium-like staircase structure is provided so as to straddle member SLTe and has a structure that is symmetrical with respect to member SLTe.

[0093] Multiple wiring layers 23 include an inclined section IP in the lead-out area HA. ​​The inclined section IP is a step that includes the ends of multiple (four in the example shown in Figure 10) continuously stacked wiring layers 23, arranged in a rectangular shape in plan view. Part of the inclined section IP is provided so as to cross the staircase area STP in the Y direction. In the inclined section IP, the ends of the multiple continuously stacked wiring layers 23 are inclined at approximately the same angle in the diagonal directions in the XZ and YZ planes, forming a slope. The inclined section IP is provided so as to surround the portion of the stadium-shaped staircase structure that is on the memory area MA2 side from the central part along the X direction. The staircase area STP is divided into staircase areas STPa and STPb by the inclined section IP. Staircase areas STPa and STPb are provided side by side in the X direction.

[0094] The staircase region STPa includes the area between the memory region MA1 and the inclined portion IP outside the inclined portion IP of the staircase region STP. Terrace portions of word lines WL3 to WL6 are provided in the staircase region STPa. Specifically, the terrace portion of word line WL3 is surrounded by word line WL4. The terrace portion of word line WL4 is surrounded by word line WL5. The terrace portion of word line WL5 is surrounded by word line WL6. In other words, in the staircase region STPa, the stadium-like staircase structure has a staircase-like structure in three directions: from the terrace portion of word line WL3, in the direction ascending toward the memory region MA1, and in each direction ascending toward the two bridge regions BRG which are provided so as to sandwich the staircase region STP on either side in the Y direction.

[0095] The staircase region STPb is the region that includes the inside of the inclined portion IP of the staircase region STP. The terrace portions of the selection gate line SGS and word lines WL0 to WL2 are provided in the staircase region STPb. Specifically, the terrace portion of the selection gate line SGS is surrounded by word line WL0. The terrace portion of word line WL0 is surrounded by word line WL1. The terrace portion of word line WL1 is surrounded by word line WL2. In other words, in the staircase region STPb, the stadium-like staircase structure has a staircase-like structure in three directions: from the terrace portion of the selection gate line SGS, in the direction ascending toward the memory region MA2, and in each direction ascending toward the two bridge regions BRG which are provided so as to sandwich the staircase region STP on either side in the Y direction.

[0096] Multiple wiring layers 22 and 23 include a bridge portion in the bridge region BRG. Each of the multiple wiring layers 22 and 23 is connected to a portion provided in the memory region MA1 and a portion provided in the memory region MA2 via the bridge portion. That is, the portion provided in the memory region MA1 and the portion provided in the memory region MA2 of each of the multiple wiring layers 22 and 23 are at the same potential.

[0097] Multiple contact CCs are further provided, corresponding to the terrace portions of the selection gate line SGS and word lines WL0 to WL6. As shown in Figure 10, the multiple contact CCs are arranged in the X direction in the staircase region STP. For example, each contact CC provided in the staircase region STP corresponds, from left to right on the page, to word lines WL6, WL5, WL4, WL3, selection gate line SGS, and word lines WL0, WL1, WL2.

[0098] Multiple contacts CX are arranged in the X direction within the bridge region BRG. The distance of multiple contacts CX located in block BLKe from member SLTo is designed to be approximately equal to the distance of multiple contacts CC located in block BLKo from member SLTe. The distance of multiple contacts CX located in block BLKo from member SLTo is designed to be approximately equal to the distance of multiple contacts CC located in block BLKe from member SLTe.

[0099] As shown in Figure 10, the memory cell array 10 according to the first embodiment has a structure in which multiple contacts CC and CX are arranged in a total of two rows, one row each in the Y direction, within a region sandwiched between two members SLT in the Y direction. This structure is called a "two-lane contact structure".

[0100] (Cross-sectional structure) Figure 11 is a cross-sectional view along line XI-XI in Figure 10, showing an example of the cross-sectional structure of the extraction region of the memory cell array in the semiconductor memory device according to the first embodiment. Figure 11 shows the extraction region HA of block BLK1, and the XZ cross-section of multiple contacts CC and CX. Figure 11 corresponds to a cross-section including the step region STP. Figure 12 is a cross-sectional view along line XII-XII in Figure 10, showing an example of the cross-sectional structure of the extraction region of the memory cell array in the semiconductor memory device according to the first embodiment. Figure 12 shows a YZ cross-section of part of the extraction region HA of blocks BLK0 to BLK2, multiple contacts CC and CX, and multiple members SLT.

[0101] As shown in Figure 11, the stacked wiring included in the memory cell array 10 has a structure in the staircase region STPa that descends from memory region MA1 to memory region MA2, which is part of the stadium-like staircase structure. In the staircase region STPb, it has a structure that ascends from memory region MA1 to memory region MA2, which is part of the stadium-like staircase structure.

[0102] Each wiring layer 22-24 includes a thin film portion THN and a thick film portion THK. Each thin film portion THN is stretched in the X direction and has, for example, a first thickness D1 in the Z direction. The thick film portion THK is provided on each terrace portion of each stepped region STP. Each thick film portion THK has, for example, a second thickness D2 in the Z direction that is thicker than the first thickness D1. For example, the second thickness D2 in the Z direction of the thick film portion THK is approximately equal to the sum of the first thickness D1 and the thickness in the Z direction of the insulating layer 42-44 provided one layer above the wiring layer 22-24. The thick film portion THK may be omitted depending on the configuration of another contact provided corresponding to contact CC among contacts CC and CX, and such other contact configurations will be described later.

[0103] As shown in Figure 11, in the stepped regions STPa and STPb, the multiple thick film portions THK provided on each wiring layer 22 and 23 are arranged in the X direction. Each thick film portion THK is spaced apart in the X direction from the side surface of the thick film portion THK of the wiring layer 23 or 24 located one layer above the wiring layer 22 or 23. In other words, the multiple thick film portions THK provided in one stepped region STP are spaced apart from each other in the X direction. Furthermore, each thick film portion THK is spaced apart in the X direction from the inclined portion IP provided on the upper layer of the thick film portion THK.

[0104] In the terrace portion of the wiring layer 24 corresponding to the selected gate line SGD, a thick film portion THK is provided in either the outer contact region SGDo or the inner contact region SGDe, and a thin film portion THN is provided in the other. Specifically, the terrace portion of the region where contact CC is provided is thickened. In the example of block BLK1 (i.e., odd-numbered block BLKo) shown in Figure 11, a thick film portion THK is provided in the outer contact region SGDo. Although not shown, in even-numbered block BLKe, a thick film portion THK is provided in the inner contact region SGDe. A thin film portion THN is provided in the region where a thick film portion THK is not provided.

[0105] As shown in Figure 12, each thick film portion THK of wiring layers 22 and 23 is provided across two block BLKs so as to straddle member SLTe in the Y direction. In other words, each thick film portion THK is in contact with one of the multiple member SLTe in the Y direction. Although not shown, the thick film portion THK of wiring layer 24 corresponding to the selected gate line SGD is provided so as to straddle all member SLTs in the Y direction, except for the member SLTs at both ends of the member SLTs that are aligned in the Y direction. In other words, the thick film portion THK of wiring layer 24 in each block BLK is in contact with member SLTo at one Y-direction end and with member SLTe at the other Y-direction end. Each thick film portion THK of each wiring layer 22 and 23 is spaced apart in the Y direction from the side surface of wiring layer 23 or 24 provided one layer above the wiring layer 22 or 23.

[0106] As shown in Figures 11 and 12, the memory cell array 10 further includes an insulating layer 40, a plurality of wiring layers 28 and 29, and a plurality of contacts VY, V3 and V4 in the extraction region HA.

[0107] Multiple contacts CC and CX are provided extending in the Z direction. Each contact CC and CX passes through (penetrates) the wiring layers 22, 23, and 24, and the insulating layers 41, 42, 43, 44, and 45, which are located at the position where the contact CC and CX are positioned in a plan view, in the Z direction. The upper surface of each contact CC and CX is in contact with the corresponding contact VY. The lower surface of each contact CC and CX is located inside the insulating layer 40. Contacts CC and CX provided in this manner, penetrating the multilayer wiring in the Z direction, are called "penetrating contacts". Each of the contacts CC and CX has, for example, an increasing cross-sectional area (XY cross-sectional area) along the XY plane from bottom to top.

[0108] Each of the multiple contacts CC and CX includes a conductor 27 and a plurality of insulators 47. The conductor 27 functions as the conductive portion of the contacts CC and CX. The conductor 27 has a shape that extends in the Z direction and penetrates in the Z direction through at least a portion of the plurality of wiring layers 22-24 and at least a portion of the insulator layers 41-45. The conductor 27 includes, for example, tungsten or molybdenum. The plurality of insulators 47 include, for example, silicon oxide.

[0109] Each contact CC contains a conductor 27 that penetrates the thick film portion THK and is connected in the XY plane to one of the wiring layers 22, 23, and 24 on which the thick film portion THK is provided. The wiring layer 22, 23, or 24 to which the conductor 27 is connected is the wiring layer 22, 23, or 24 to which the contact CC corresponds. Each contact CX contains no electrical connection to any of the wiring layers 22, 23, and 24 included in the memory cell array 10. The lower end of the conductor 27 is located inside the insulating layer 40.

[0110] Multiple insulators 47 included in each contact CC and CX are provided so as to surround the sides of the conductor 27 in the portion of the wiring layers 22, 23, and 24 through which the conductor 27 penetrates the thin-film portion THN. The multiple insulators 47 insulate the conductor 27 from the thin-film portion THN of the wiring layers through which the conductor 27 penetrates. That is, each contact CC is connected to the wiring layers 22, 23, and 24 that penetrate the thick-film portion THK, and is insulated from the wiring layers that penetrate the thin-film portion THN. Each contact CX penetrates the thin-film portion THN of all three wiring layers 22, 23, and 24, and is therefore insulated from these wiring layers 22, 23, and 24. Note that the configuration of the contact CC is not limited to the above configuration, as long as the contact CC is connected to the corresponding wiring layer 22, 23, or 24 and insulated from the other wiring layers 22, 23, or 24.

[0111] The insulating layer 40 is provided below the insulating layer 41 and is provided in the layer corresponding to the wiring layer 21 in the memory areas MA1 and MA2. The insulating layer 40 includes, for example, polysilicon. For example, amorphous silicon layers corresponding to the wiring layer 21 and the insulating layer 40 are formed, and the portions of the memory areas MA1 and MA2 corresponding to the wiring layer 21 are selectively doped with impurities such as phosphorus, and then heat-treated to form the structures corresponding to the wiring layer 21 and the insulating layer 40.

[0112] Multiple wiring layers 28 are provided above multiple contacts CC and CX, respectively. Multiple wiring layers 29 are provided above multiple wiring layers 28 and inside the insulating layer 46. Multiple wiring layers 28 and 29 are wiring that relays the connection between the word line WL and the row decoder module 16. Multiple wiring layers 28 and 29 include, for example, copper. Multiple wiring layers 28 are provided on the same layer as multiple wiring layers 25, for example. Multiple wiring layers 29 are provided on the same layer as multiple wiring layers 26, for example.

[0113] Multiple contacts VY are provided above multiple contacts CC and CX and inside the insulating layer 45. Each contact VY contacts the conductor 27 of the corresponding contact CC or CX on its lower surface and the corresponding wiring layer 28 on its upper surface, connecting the two. Multiple contacts V3 and V4 are provided inside the insulating layer 46. Each contact V3 contacts one wiring layer 28 on its lower surface and one wiring layer 29 on its upper surface, connecting the two. The lower surface of each contact V4 contacts one wiring layer 29, and its upper surface is exposed from the insulating layer 46 and connects to a junction pad included in a junction layer provided on the upper side of the memory cell array 10, for example. The wiring layers 28 and 29, as well as contacts VY, V3, and V4, are collectively referred to as the upper layer wiring HUL.

[0114] 1.1.6 Bonding structure between memory layers Figures 13 to 15 are cross-sectional views showing an example of the cross-sectional structure of the first memory layer, the second memory layer, and the junction layer provided between them in the semiconductor memory device according to the first embodiment. The cross-section in Figure 13 corresponds to the YZ cross-section shown in Figure 12. Figure 13 shows the regions corresponding to blocks BLK0 to BLK2 in the memory cell array 10-1 and blocks BLK1 to BLK3 in the memory cell array 10-2. Figures 14 and 15 are cross-sectional views along the XIV-XIV and XV-XV lines in Figure 13, respectively. Figures 14 and 15 show the regions corresponding to block BLK1 in the memory cell array 10-1 and block BLK2 in the memory cell array 10-2. In addition, Figures 14 and 15 also show cross-sections of contacts CC and CX passing through the wiring layer 24 corresponding to the selected gate line SGD in the Z direction, similar to Figure 11.

[0115] As shown in Figures 13 to 15, the bonding layer B3 includes an insulating layer 52. Multiple bonding pads BP3 are provided so as to pass through the insulating layer 52 in the Z direction. The bonding layer B4 includes an insulating layer 51. Multiple bonding pads BP4 are provided so as to pass through the insulating layer 51 in the Z direction.

[0116] The first memory layer 200 further includes a plurality of contacts VZ. The plurality of contacts VZ are located below the plurality of contacts CC and CX and inside the insulating layer 40 in the memory cell array 10-1. Each contact VZ has its upper surface in contact with the conductor 27 of the corresponding contact CC or CX, and its lower surface is exposed from the insulating layer 40 and connects to, for example, a bonding pad BP3 included in the bonding layer B3 provided on the lower side of the memory cell array 10.

[0117] Contacts CC and CX included in memory cell array 10-1 are connected via corresponding contact VZ to a plurality of junction pads BP3 provided on the junction layer B3 on the lower side of memory cell array 10-1. Contacts CC and CX included in memory cell array 10-2 are connected via upper layer wiring HUL to a plurality of junction pads BP4 on the upper side of memory cell array 10-2. At the boundary between junction layers B3 and B4, junction pads BP3 and BP4 are arranged opposite each other and connected in the Z direction. Contact CX included in memory cell array 10-1 is connected to contact CC included in memory cell array 10-2 via junction pads BP3 and BP4, contact VZ, and upper layer wiring HUL provided on memory cell array 10-2. Contact CX included in memory cell array 10-2 is connected to contact CC included in memory cell array 10-1 via junction pads BP3 and BP4, contact VZ, and upper layer wiring HUL provided on memory cell array 10-2. In other words, when contact CX is formed on one of the memory cell arrays 10-1 and 10-2 at a position where they overlap in the Z direction, contact CC is formed on the other, and contacts CC and CX are connected via bonding pads BP3 and BP4, contact VZ, and the upper layer wiring HUL provided on the memory cell array 10-2. The contacts CC, CX, and VZ connected in the Z direction, bonding pads BP3 and BP4, and the upper layer wiring HUL provided on each of the memory cell arrays 10-1 and 10-2 can be considered as a single through-contact penetrating the memory cell arrays 10-1 and 10-2. This through-contact is electrically connected to one of the wiring layers included in one of the memory cell arrays 10-1 and 10-2, and is insulated from the other wiring layers.

[0118] In the two bonded memory cell arrays 10, the contact CC provided in one step region STP and the contact CX provided in the other bridge region BRG are located in positions that correspond to each other and overlap approximately in the Z direction.

[0119] As shown in Figures 14 and 15, in the terrace portion of the selection gate line SGD located in the Z-direction overlapping position of memory cell arrays 10-1 and 10-2, the position where the contact CC corresponding to each selection gate line SGD is provided is shifted in the X-direction and does not overlap in the Z-direction. In the cross-sections shown in Figures 14 and 15, since memory cell array 10-1 corresponds to block BLK1, for example, contact CC is provided in the outer contact area SGDo and contact CX is provided in the inner contact area SGDe. On the other hand, since memory cell array 10-2 corresponds to block BLK2, contact CX is provided in the outer contact area SGDo and contact CC is provided in the inner contact area SGDe. The contacts CC and CX located in the Z-direction overlapping position are connected to each other via junction pads BP3 and BP4, contact VZ, and the upper layer wiring HUL provided in memory cell array 10-2. Therefore, contacts CC, CX, and VZ, junction pads BP3 and BP4, and the upper layer wiring HUL of memory cell arrays 10-1 and 10-2 can be considered as a single through-contact. The through-contact is connected to one of the select gate lines SGD of either memory cell array 10-1 or 10-2, and is isolated from the other wiring layers. In this way, the select gate lines SGD of memory cell arrays 10-1 and 10-2 are electrically isolated from each other.

[0120] Figure 16 is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device according to the first embodiment. Figure 16 shows a structure in which a control circuit layer 100, a first memory layer 200, a second memory layer 300, and a wiring layer 400 are bonded to each other. Figure 16 corresponds to the cross-section shown in Figure 15. Note that in Figure 16, the Z1 direction is shown as the top of the paper. As shown in Figure 16, the control circuit layer 100 is provided with a plurality of transistors TR.

[0121] The first semiconductor substrate W1 includes a plurality of insulators STI and a plurality of impurity diffusion regions DR. The plurality of insulators STI are formed near the surface of the first semiconductor substrate W1 in the Z1 direction. In a plan view, the region surrounded by the insulators STI defines an active region used for forming a transistor TR. The impurity diffusion regions DR are formed in the active region and are formed corresponding to the source region and drain region of the transistor TR, respectively. For example, if the transistor TR is an N-type transistor, a P-type well region is provided as the active region, and an N-type impurity diffusion region is provided as the impurity diffusion region DR. If the transistor TR is a P-type transistor, an N-type well region is provided as the active region, and a P-type impurity diffusion region is provided as the impurity diffusion region DR.

[0122] An insulating layer 70 is provided on the Z1 direction surface of the first semiconductor substrate W1. Wiring layers of a control circuit layer 100 are formed within the insulating layer 70. The control circuit layer 100 includes a plurality of gate electrodes GC, a plurality of contacts C0, C1, C2, C3, C4, and C5, and a plurality of wiring layers 71, 72, 73, 74, 75, and 76. Each gate electrode GC is the gate portion of the corresponding transistor TR. Each gate electrode GC is provided between adjacent impurity diffusion regions DR and in a position overlapping with the well region in the Z1 direction, via a gate insulating film. Each contact C0 is provided in contact with the corresponding impurity diffusion region DR or gate electrode GC. Each wiring layer 71 is provided in contact with the corresponding contact C0. Each contact C1 is provided in contact with the corresponding wiring layer 71. Each wiring layer 72 is provided in contact with the corresponding contact C1. Each contact C2 is provided in contact with the corresponding wiring layer 72. Each wiring layer 73 is provided in contact with its corresponding contact C2. Each contact C3 is provided in contact with its corresponding wiring layer 73. Each wiring layer 74 is provided in contact with its corresponding contact C3. Each contact C4 is provided in contact with its corresponding wiring layer 74. Each wiring layer 75 is provided in contact with its corresponding contact C4. Each contact C5 is provided in contact with its corresponding wiring layer 75. Each wiring layer 76 is provided in contact with its corresponding contact C5. The Z1 direction surface of wiring layer 76 is exposed from the insulator layer 70. Contacts C0, wiring layer 71, contact C1, wiring layer 72, contact C2, wiring layer 73, contact C3, wiring layer 74, contact C4, wiring layer 75, contact C5, and wiring layer 76 are provided so as to overlap in the Z1 direction in this order.

[0123] An insulating layer 53 is provided on the Z1 direction surface of the insulating layer 70. Multiple bonding pads BP1 are provided on the insulating layer 53. Multiple bonding pads BP1 are provided opposite to multiple bonding pads BP2 in the Z direction and are in contact with each other. Multiple bonding pads BP1 are connected to the corresponding wiring layer 76 at the end on the first semiconductor substrate W1 side. The insulating layer 53 corresponds to bonding layer B1.

[0124] With the above configuration, each memory pillar MP provided in the first memory layer 200 and the second memory layer 300 is connected to a transistor TR provided in the control circuit layer 100 via a plurality of corresponding wiring layers, a plurality of contacts, and a plurality of bonding pads. In addition, the wiring layers corresponding to each word line WL and the selection gate lines SGS and SGD provided in the first memory layer 200 and the second memory layer 300 are connected to a transistor TR provided in the control circuit layer 100 via a plurality of corresponding wiring layers, a plurality of contacts, and a plurality of bonding pads.

[0125] Figure 17 is a cross-sectional view showing an example of the cross-sectional structure near two bonding pads provided in the bonding layer between the first memory layer and the second memory layer of a semiconductor memory device according to the first embodiment, and which are bonded to each other. Figure 17 shows a bonding pad BP3 formed in contact with the first memory layer 200, a bonding pad BP4 formed in contact with the second memory layer 300, and contacts CX, VZ, V3, and V4 connected thereto, as well as a wiring layer 29. Although Figure 17 shows the case where contact CX is connected to bonding pad BP3, the same applies when contact CC is connected to bonding pad BP3.

[0126] As shown in Figure 17, bonding pads BP3 and BP4 may have different tapered shapes depending on the etching direction during formation. Specifically, bonding pad BP3, formed in contact with the first memory layer 200, may have a tapered shape that narrows in the Z2 direction, for example. Bonding pad BP4, formed in contact with the second memory layer 300, may have a tapered shape that narrows in the Z1 direction, for example. Therefore, the portion where bonding pads BP3 and BP4 are joined together may not have straight sidewalls in the cross-sectional shape along the Z direction, and the shape of the cross-section may be non-rectangular. In addition, pairs of bonding pads BP3 and BP4 that are positioned opposite each other may be joined with a shift depending on the alignment during the joining process. Therefore, a step may be formed between the side surface of bonding pad BP3 and the side surface of bonding pad BP4. Pairs of bonding pads BP3 and BP4 that are positioned opposite each other may have a boundary or may be integrated.

[0127] Although not shown in the figures, the cross-sectional structure near the two bonding pads BP1 and BP2, which are provided in bonding layers B1 and B2 between the control circuit layer 100 and the first memory layer 200 and are bonded to each other, is similar to the structure shown in Figure 17.

[0128] 1.2 Manufacturing method Figure 18 is a flowchart showing an example of the manufacturing process for a memory cell array in a semiconductor memory device according to the first embodiment. Figures 19 to 34 are cross-sectional views showing an example of a cross-sectional structure during the manufacturing process of a semiconductor memory device according to the first embodiment. Figures 19 to 22 correspond to the cross-section shown in Figure 11. Figure 23 is a cross-sectional view showing the structure of even-numbered blocks BLKe and odd-numbered blocks BLKo simultaneously in the XZ cross-section of the memory cell array 10. Figures 24 to 29 correspond to the cross-section shown in Figure 12. Figures 30, 32, and 33 are cross-sectional views showing the structure of the memory area MA1 and the extraction area HA simultaneously in the YZ cross-section of the memory cell array 10. Figures 31 and 34 correspond to the cross-section shown in Figure 16. Note that the control circuit layer 100 and the junction layer B1 are omitted in Figures 32 and 33.

[0129] As shown in Figure 18, in the manufacturing process of the extraction area HA, processes S101 to S120 are executed in order. Below, an example of the manufacturing process of the semiconductor memory device 3 will be described with reference to Figures 19 to 34 as appropriate. In the following description, the manufacturing process of memory area MA1 is shown as a representative example, but the manufacturing process of memory area MA2 is similar to that of memory area MA1.

[0130] In this embodiment, as a method for forming the multiple wiring layers 22, 23, and 24 corresponding to the selected gate lines SGS and SGD, and the word lines WL0 to WL6, for example, a method in which structures corresponding to each wiring layer 22, 23, and 24 are formed using sacrificial members 62, 63, and 64, respectively, and then the sacrificial members 62, 63, and 64 are replaced with a conductive material to form each wiring layer 22, 23, and 24 (hereinafter referred to as "replacement") will be described.

[0131] First, memory cell arrays 10-1 and 10-2 are formed in the processes S101 to S113. The structure formed in the processes S101 to S113 is a structure common to memory cell arrays 10-1 and 10-2.

[0132] First, processes S101 and S102 are executed in order, and a staircase structure is formed in the draw-out area HA.

[0133] Specifically, as shown in Figure 19, a sacrificial member 61 is first laminated on the semiconductor substrate W. The sacrificial member 61 is a layer corresponding to the wiring layer 21 and the insulating layer 40. The sacrificial member 61 contains, for example, polysilicon. Then, an insulating layer 41, a sacrificial member 62, and an insulating layer 42 are laminated on the sacrificial member 61 in that order. Seven layers of sacrificial member 63 and seven layers of insulating layer 43 are laminated alternately, one layer at a time, on the insulating layer 42. A sacrificial member 64 and an insulating layer 44 are laminated on the uppermost insulating layer 43 in that order. The thickness of each of the sacrificial members 62, 63, and 64 in the Z direction is equivalent to the first thickness D1. The insulating layers 41, 42, 43, and 44 contain, for example, silicon oxide. The sacrificial members 62, 63, and 64 contain, for example, silicon nitride.

[0134] Next, a mask 65 is formed covering the memory regions MA1 and MA2, and the region within the extraction region HA where the selected gate line SGD is to be formed. The mask 65 is formed, for example, by photolithography. Subsequently, one layer of insulating layer 44 and sacrificial member 64 is removed by anisotropic etching using the mask 65. A sacrificial member 66 is provided in the region where the insulating layer 44 and sacrificial member 64 have been removed. The sacrificial member 66 is provided as a reference for planarization during the planarization performed in S104. The sacrificial member 66 includes, for example, silicon nitride.

[0135] Subsequently, as shown in Figure 20, a stadium-like staircase structure is formed in the staircase area STP (S102). The stadium-like staircase structure is formed by the following three stages of processing.

[0136] In the first stage, the sacrificial member 66 is removed in the region corresponding to the stair region STP. Specifically, a mask is first formed by photolithography or the like, with an opening in the portion corresponding to the stair region STP. Then, the sacrificial member 66 provided in the stair region STP is removed by anisotropic etching using this mask. At this time, the sacrificial member 66 provided in the bridge region BRG remains without being removed.

[0137] In the second stage, the four insulating layers 43 and four sacrificial members 63 from the top are processed into a stepped shape, with each step consisting of one insulating layer 43 and one sacrificial member 63. Specifically, first, a mask is formed by photolithography or the like, with openings in the parts corresponding to the lowest steps of the stepped regions STPa and STPb. Then, one step of insulating layer 43 and sacrificial member 63 is removed by anisotropic etching using this mask. Next, the part of the mask corresponding to the second lowest step of the stepped regions STPa and STPb is removed. After that, one step of insulating layer 43 and sacrificial member 63 is removed by anisotropic etching using this mask. In this way, by repeatedly reducing the mask area and performing anisotropic etching, the insulating layers 43 and sacrificial members 63 are processed into a stepped shape. This type of processing is called "slimming".

[0138] In the third stage, multi-stage processing is performed on the portion corresponding to the inclined IP, so that the staircase structure formed in the staircase region STPb corresponds to the wiring layer below the staircase structure formed in the staircase region STPa. Multi-stage processing is a process that removes multiple sets of insulating layers and sacrificial members in the processing area all at once. Specifically, first, a mask is formed by photolithography or the like, with an opening in the area corresponding to the inside of the inclined IP. Then, anisotropic etching using this mask removes, for example, four sets of insulating layers 43 and sacrificial members 63. As a result, the insulating layer 42 and sacrificial member 62, as well as the three insulating layers 43 and three sacrificial members 63 from the bottom, are processed into a staircase-like structure where one set consists of an insulating layer 42 and a sacrificial member 62, or one insulating layer 43 and one sacrificial member 63. In addition, the inclined IP is formed when multiple stages are removed by multi-stage processing.

[0139] Next, the S103 process is executed, and as shown in Figure 21, a structure corresponding to the thick film portion THK of the wiring layers 22 and 23 in the stadium-like staircase structure is formed in the lead-out region HA.

[0140] Specifically, terrace portions corresponding to the selected gate line SGS and word lines WL0 to WL6 are formed. First, a portion of the insulating layers 42 and 43 exposed on the upper surface of the stadium-like staircase structure is removed. Then, sacrificial material is formed on the sacrificial members 62 and 63, and the sacrificial members 62 and 63 in the staircase portion are thickened. At this time, the sacrificial member 66 provided in the bridge region BRG is also thickened in the same way. The sacrificial material is the same material as the sacrificial members 62 and 63, and includes, for example, SiN. Subsequently, of the sacrificial material thickened in the staircase portion of the sacrificial members 62 and 63, the portion in contact with the side surface of the sacrificial member 63 or 64 provided one layer above the sacrificial member 62 or 63 via the insulating layer 42 or 43, and the portion provided in the inclined portion IP and its vicinity are removed. As a result, the thickened portions of the sacrificial members 62 and 63 corresponding to the thickened portion THK are formed. The thickness in the Z direction of the sacrificial members 62 and 63 corresponding to the thickened portion THK becomes equivalent to the second thickness D2.

[0141] Next, the S104 process is performed, and as shown in Figure 22, the stair region STP and the bridge region BRG are flattened.

[0142] Specifically, the stadium-like staircase structure is first embedded with an insulating layer 45. The insulating layer 45 includes, for example, TEOS (Tetra Ethoxy Silane). Subsequently, a portion of the insulating layer 45 and sacrificial members 66 in the staircase region STP and bridge region BRG are removed and flattened. In this process, the sacrificial members 66 are used as markers, and removal is carried out to a depth where the sacrificial members 66 are completely removed. The surfaces of the insulating layers 43 and 45 after removal are flattened, for example, by CMP (Chemical Mechanical Polishing).

[0143] Next, the S105 process is executed, and as shown in Figure 23, the thick film portion THK is formed in the selected gate line SGD.

[0144] Specifically, first, the insulating layer 44 in the portion corresponding to the mask 65 and the selected gate line SGD is removed. Next, a sacrificial material is formed on the sacrificial member 64, and the sacrificial member 64 in the stepped portion is thickened. The sacrificial material is the same material as the sacrificial member 64, and includes, for example, SiN. Subsequently, depending on the block BLK in which the selected gate line SGD is provided, a portion of the thickened sacrificial material on the sacrificial member 64 is removed. In Figure 23, the left side of the paper shows the structure of even-numbered blocks BLKe, and the right side shows the structure of odd-numbered blocks BLKo. In even-numbered blocks BLKe, the inner contact region SGDe is thickened, and the thickened portion of the outer contact region SGDo is removed. In odd-numbered blocks BLKo, the outer contact region SGDo is thickened, and the thickened portion of the inner contact region SGDe is removed. Subsequently, the insulating layer 45 is embedded so as to fill the thickened portion of the sacrificial member 64. The surface of the insulating layer 45 is planarized, for example, by CMP.

[0145] Next, processes S106 and S107 are executed to form a configuration that corresponds to multiple contact CCs and CXs.

[0146] Specifically, the process in S106 is performed first, and as shown in Figure 24, multiple holes CH are formed. The multiple holes CH are provided at positions corresponding to multiple contacts CC and CX. First, a mask is formed by photolithography or the like, with openings in the areas corresponding to each contact CC and CX. Then, multiple holes CH corresponding to each contact CC and CX are formed by anisotropic etching using this mask. Each hole CH passes through (penetrates) the insulating layers 41, 42, 43, and 45, and the sacrificial members 62, 63, and 64, which are provided at corresponding positions in a plan view, in the Z direction. At the bottom of each hole CH, the sacrificial member 61 is exposed.

[0147] Next, as shown in Figure 24, wet etching through each hole CH removes the peripheral portions of the sacrificial members 62, 63, and 64 that are exposed on the side surface of each hole CH. This creates multiple grooves on the side surface of each hole CH, in which the sacrificial members 62, 63, and 64 are recessed radially along the XY plane relative to the insulating layers 41, 42, 43, and 45.

[0148] Although not shown in the diagram, a hole corresponding to the memory pillar MP may be formed simultaneously with the process in S106. The hole corresponding to the memory pillar MP passes through (penetrates) the insulating layers 41, 42, 43, and 45, and the sacrificial members 62, 63, and 64, which are located at corresponding positions in a plan view, in the Z direction, and the sacrificial member 61 is exposed at the bottom. The depth of the hole corresponding to the memory pillar MP may be equal to or different from the depth of the multiple holes CH. The hole corresponding to the memory pillar MP is filled with a sacrificial member.

[0149] Subsequently, the process in S107 is performed, and as shown in Figure 25, the insulator 47 and sacrificial members 67 are formed. First, an insulator 47 is deposited on the inner wall of each hole CH. In the parts where the sacrificial members 62, 63, and 64 are not thickened, the insulator 47 is deposited so as to fill any of the multiple grooves formed in S106. On the other hand, in the parts where any of the sacrificial members 62, 63, and 64 are thickened, the insulator 47 is deposited so as to cover the surface of the groove, leaving a recessed area in the center. The insulator 47 contains, for example, SiO.

[0150] Next, a portion of the insulator 47 provided on the inner wall of each hole CH is removed by wet etching or the like. In this case, in the parts where the sacrificial members 62, 63, and 64 are not thickened, the insulator 47 embedded in the groove is not completely removed, and none of the sacrificial members 62, 63, and 64 are exposed on the side surface of each hole CH. On the other hand, in the parts where any of the sacrificial members 62, 63, and 64 are thickened, the insulator 47 provided to cover the surface of the groove is removed, and the sacrificial member 62, 63, or 64 is exposed on the side surface of each hole CH.

[0151] Subsequently, as shown in Figure 25, a sacrificial member 67 is embedded in the hole CH. The sacrificial member 67 includes, for example, amorphous silicon.

[0152] After the process in S107, a memory pillar MP may be formed. Specifically, first, the sacrificial member embedded in the hole corresponding to the memory pillar MP is removed. Then, the laminated film 32, the semiconductor film 31, and the core film 30 are deposited in the hole in this order. In this case, the semiconductor film 31 does not need to be in contact with the sacrificial member 61 at the bottom.

[0153] Next, the S108 process is executed, and the slit SH corresponding to the member SLT is formed.

[0154] Specifically, first, a mask is formed by photolithography or the like, with openings in the regions corresponding to each component SLT. Then, as shown in Figure 26, multiple slits SH corresponding to each component SLT are formed by anisotropic etching using this mask. Each slit SH passes through (penetrates) the insulating layers 41, 42, 43, 44, and 45, as well as the sacrificial members 62, 63, and 64, which are located at corresponding positions in a plan view, in the Z direction. At the bottom of each slit SH, the sacrificial member 61 is exposed.

[0155] Next, the process in S109 is performed, and as shown in Figure 27, the sacrificial members 62, 63, and 64 corresponding to the stacked wiring are replaced.

[0156] Specifically, first, sacrificial members 62, 63, and 64 are removed through slit SH by wet etching. At this time, the three-dimensional structure of the structure from which the sacrificial members 62, 63, and 64 have been removed is supported by a plurality of memory pillars MP (not shown) and a plurality of support pillars (not shown) appropriately arranged in the extraction region HA. Then, a conductor (e.g., tungsten or molybdenum) is embedded through slit SH into the space from which the sacrificial members 62, 63, and 64 have been removed. For example, CVD (Chemical Vapor Deposition) is used to form the conductor in this process. Subsequently, the conductor formed inside slit SH is removed by etch-back processing, and adjacent conductor layers in the Z direction are separated from each other. As a result, a wiring layer 22 that functions as a selective gate line SGS, a plurality of wiring layers 23 that function as word lines WL0 to WL6 respectively, and a wiring layer 24 that functions as a selective gate line SGD are formed. Note that the wiring layers 22, 23, and 24 formed in this process may contain barrier metal. In this case, when forming the conductor after removing the sacrificial members 62, 63, and 64, for example, titanium nitride (TiN) is deposited as a barrier metal, and then tungsten or molybdenum is formed as the conductor. Also, the wiring layers 22, 23, and 24 may include an insulating film. In this case, when forming the conductor after removing the sacrificial members 62, 63, and 64, for example, a metal oxide film such as aluminum oxide (AlO) is deposited as an insulating film, and then the barrier metal and conductor (tungsten or molybdenum) are formed.

[0157] Next, the process in S110 is performed, and as shown in Figure 28, member SLT is formed in the slit SH. In addition, although not shown, member SHE is formed from the memory area MA1 to the first portion SGDa of the selected gate line SGD, and from the memory area MA2 to the second portion SGDb of the selected gate line SGD (S116).

[0158] Specifically, first, an insulating portion (spacer SP) is formed to cover the sides and bottom of the slit SH. Then, a portion of the spacer SP provided at the bottom of the slit SH is removed, and a portion of the sacrificial member 61 is exposed at the bottom of the slit SH. Next, a conductor (contact LI) is formed inside the slit SH, and the conductor formed outside the slit SH is removed, for example, by CMP. After that, multiple grooves are formed parallel to the member SLT in the region corresponding to member SHE between adjacent member SLT in the Y direction. Then, by embedding an insulating film in each groove, member SHE is formed that divides the wiring layer 24 in the Y direction.

[0159] Next, the S111 process is performed, and as shown in Figure 29, the sacrificial member 67 embedded in the hole CH is replaced, and contacts CC and CX are formed.

[0160] Specifically, first, the sacrificial members 67 embedded in each hole CH are removed by wet etching. At this time, if each wiring layer 22, 23, and 24 contains an insulating film such as aluminum oxide, the insulating film in contact with the sacrificial member 67 is also removed. Then, multiple conductors 27 are embedded in the holes CH. Each conductor 27 embedded in the hole CH corresponding to contact CC is in contact with the wiring layers 22, 23, and 24 in the lateral direction in grooves formed in each terrace portion of the wiring layers 22, 23, and 24. On the other hand, each conductor 27 embedded in the hole CH corresponding to contact CX is insulated from the wiring layers 22, 23, and 24. Also, each conductor 27 is in contact with the sacrificial member 61 at its bottom. Finally, the conductor formed on the upper surface of the laminated structure is removed, for example by CMP, exposing the surfaces corresponding to the upper ends of the multiple contacts CC and CX.

[0161] Next, processes S112 to S113 are performed, and as shown in Figure 30, upper layer wiring MUL and HUL, and bonding layers provided above the memory layer are formed. Bonding layer B2 is formed above the first memory layer 200, and bonding layer B4 is formed above the second memory layer 300.

[0162] Specifically, after the insulating layer 45 is further stacked, a contact CV is formed above each memory pillar MP. Also, a contact VY is formed above each contact CC and CX. Subsequently, a wiring layer 25 is formed above each contact CV, and a wiring layer 28 is formed above each contact VY. An insulating layer 46 is formed above the insulating layer 45. A contact V1 is formed above each wiring layer 25, and a contact V3 is formed above each wiring layer 28. A wiring layer 26 is formed above each contact V1, and a wiring layer 29 is formed above each contact V3. A contact V2 is formed above each wiring layer 26, and a contact V4 is formed above each wiring layer 29. Contacts CV, VY, V1, V2, V3, and V4, as well as wiring layers 25, 26, 28, and 29, are formed, for example, by forming holes or grooves at the positions of the insulating layer 45 or 46 on which the contacts or wiring are formed, and filling the holes or grooves with a conductor. This forms the upper layer wiring MUL and HUL (S112). The upper layer wiring MUL has a pattern in which wiring layers 25 and 26 extend in the Y direction or X direction and are routed within the memory cell array 10, and is connected to a structure provided on the upper layer of the memory cell array 10.

[0163] Next, an insulating layer 51 is laminated on top of the insulating layer 46. Then, a plurality of grooves corresponding to bonding pads BP are formed above the plurality of contacts V2 and V4. These plurality of grooves have a tapered shape that narrows in the Z1 direction, for example, and the corresponding contacts V2 or V4 are exposed at the bottom surface. Then, a conductive material such as copper is embedded in the plurality of grooves to form bonding pads BP. In memory cell array 10-1, bonding pad BP2 corresponds to bonding pad BP, and in memory cell array 10-2, bonding pad BP4 corresponds to bonding pad BP. This forms bonding layers B2 or B4 which are provided above the first memory layer 200 or the second memory layer 300 (S113).

[0164] Next, the process in S114 is performed, and as shown in Figure 31, the separately manufactured control circuit layer 100 and the first memory layer 200 are bonded together in the Z direction.

[0165] Specifically, a first memory layer 200 and a bonding layer B2 are bonded to a control circuit layer 100 and a bonding layer B1 manufactured using a first semiconductor substrate W1, with the first memory layer 200 and bonding layer B2 reversed in the Z direction from the Z1 direction side. At this time, bonding pads BP2 provided on bonding layer B2 and bonding pads BP1 provided on bonding layer B1 are bonded so that they are in contact with each other in the Z direction.

[0166] Next, the memory cell array 10-1, after the control circuit layer 100 and the first memory layer 200 have been bonded, is subjected to processes S115 to S116 to form the wiring layer 21 and the insulating layer 40. At this time, the semiconductor films 31 of the multiple memory pillars MP are connected to the wiring layer 21.

[0167] First, the semiconductor substrate W and the sacrificial member 61 are removed (S115). This exposes the ends of multiple memory pillars MP, multiple members SLT, and multiple contacts CC and CX. The laminated film 32 is also removed at the exposed ends of each memory pillar MP. This exposes the semiconductor film 31 of the memory pillar MP. In memory regions MA1 and MA2, at least a portion of the sacrificial member 61 provided in the portion penetrated in the Z direction by the memory pillar MP may be left intact. Also, at least a portion of the sacrificial member 61 in the extraction region HA may be left intact.

[0168] Next, a layer that will become the source line SL is formed on the Z1 direction surface of the insulating layer 41. Specifically, an amorphous silicon layer is deposited, for example, so as to be in contact with the semiconductor film 31 of each memory pillar MP and the exposed end of the member SLT. Then, the amorphous silicon layers provided in the memory regions MA1 and MA2 are doped with an impurity such as phosphorus and subjected to heat treatment to activate the doped impurity and crystallize the amorphous silicon into polysilicon. As a result, the polysilicon layers provided in the memory regions MA1 and MA2 become conductive and function as wiring layers 21. On the other hand, the polysilicon layer formed in the lead-out region HA does not have conductivity and therefore functions as an insulating layer 40 (S116).

[0169] Next, the process in S117 is performed, forming the bonding layer B3 and contact VZ located below the first memory layer 200 (in the Z1 direction). The bonding pad BP3 and contact VZ in the bonding layer B3 are formed, for example, by dual damascene machining.

[0170] Specifically, an insulating layer 52 is laminated on the lower surface (Z1 direction surface) of the wiring layer 21 and the insulating layer 40. Subsequently, multiple grooves corresponding to bonding pads BP3 and contacts VZ are formed at positions that overlap with multiple contacts CC and CX in the insulating layer 52 in the Z direction. These multiple grooves are formed in two stages, with the first stage grooves provided in the insulating layer 52 and the second stage grooves provided in the insulating layer 40. These multiple grooves have a tapered shape, for example, narrowing in the Z2 direction, and the corresponding contacts CC or CX are exposed at the bottom surface of the second stage grooves. Subsequently, a conductor is embedded in these multiple grooves, forming multiple contacts VZ and multiple bonding pads BP3. This forms the bonding layer B3 and contacts VZ provided below (Z1 direction) the first memory layer 200, as shown in Figure 33.

[0171] Next, the process in S118 is performed, and as shown in Figure 34, the first memory layer 200 and the second memory layer 300 are bonded together in the Z direction.

[0172] Specifically, the second memory layer 300 and bonding layer B4 are bonded to the first memory layer 200 and bonding layer B3 from the Z1 direction side, in reverse in the Z direction. At this time, the bonding pad BP4 provided on bonding layer B4 and the bonding pad BP3 provided on bonding layer B3 are bonded so that they are in contact with each other in the Z direction. The first memory layer 200 and the second memory layer 300 are bonded so that their respective memory cell arrays 10-1 and 10-2 are shifted by 1 block BLK in the Y direction and overlap in the Z direction, as shown in Figure 6.

[0173] Subsequently, the memory cell array 10-2, after the first memory layer 200 and the second memory layer 300 have been bonded together, is subjected to the processes S119 to S120 to form the wiring layer 21 and the insulating layer 41. This process is the same as the processes S115 to S116 for the first memory layer 200. After that, the wiring layer 400 is provided below the second memory layer 300 (in the Z1 direction). Multiple pads PD are formed on the wiring layer 400.

[0174] Furthermore, the semiconductor memory device 3 may include wiring and contacts other than those described above. For example, the memory cell array 10-1 may include wiring and contacts for routing wiring connected to the memory pillar MP included in the memory cell array 10-2. For example, the memory cell arrays 10-1 and 10-2 may include wiring and contacts for connecting pads PD provided on the wiring layer 400 to various control circuits included in the control circuit layer 100. These wirings can function as wiring PW. In addition, each junction layer B1, B2, B3, and B4 may include junction pads for connecting to wiring other than those described above.

[0175] The structure of the semiconductor memory device 3 is formed by the manufacturing process described above. However, the manufacturing process described above is merely an example and is not limited to it. For example, other processes may be inserted between each manufacturing step, or some steps may be omitted or integrated. Furthermore, each manufacturing step may be rearranged to the extent possible.

[0176] 1.3 Effects of the First Embodiment According to the first embodiment, the integration density of the semiconductor memory device 3 can be improved. This effect will be described in detail below.

[0177] The semiconductor memory device 3 according to the first embodiment has a structure in which memory cell arrays 10-1 and 10-2 overlap in the Z direction, and the stair regions STP included in memory cell arrays 10-1 and 10-2 are arranged alternately in the Y direction. This structure allows the draw-out region HA, which has a stadium-like stair structure, to be provided in a position that overlaps in the Z direction. Therefore, the expansion of the draw-out region HA is suppressed, and the area occupied by memory regions MA1 and MA2 in one semiconductor memory device 3 can be increased, thereby improving the integration density of the semiconductor memory device 3.

[0178] Furthermore, the semiconductor memory device 3 according to the first embodiment has a configuration in which memory cell arrays 10-1 and 10-2 are stacked, and the block BLK contained in each is driven independently. With this configuration, when reading or writing data to the memory cell, one block BLK in the memory cell arrays 10-1 and 10-2 can be selectively driven, thereby suppressing a decrease in the reliability of the memory cell.

[0179] Furthermore, the structure of the extraction area HA of memory cell arrays 10-1 and 10-2 is substantially identical. Therefore, since there is little need to add special processes to either memory cell array 10-1 or 10-2, an increase in manufacturing costs in the manufacturing process can be suppressed.

[0180] 1.4 Variations The semiconductor memory device 3 according to the first embodiment described above can be modified in various ways. Below, the differences between the first embodiment and the first, second, and third modifications of the first embodiment will be described.

[0181] 1.4.1 First Variation Figure 35 is a cross-sectional view showing an example of the cross-sectional structure of a first memory layer, a second memory layer, and a junction layer provided between them, which are included in a semiconductor memory device according to a first modified example of the first embodiment. The cross-section shown in Figure 35 corresponds to the cross-section shown in Figure 13 of the first embodiment.

[0182] As shown in Figure 35, the semiconductor memory device 3 according to the first modification of the first embodiment does not include a plurality of bonding pads BP3 and BP4 for connecting a plurality of contacts CC provided on the first memory layer 200 and a plurality of contacts CX provided on the second memory layer 300, nor a plurality of contacts VZ corresponding to the plurality of contacts CC in the first memory layer 200. That is, the plurality of contacts CC provided on the first memory layer 200 are connected to the wiring layers 22 to 24 corresponding to the contacts CC, are in contact with bonding pad BP2 at the top, and are provided inside the insulating layer 41 at the bottom. The plurality of contacts CX provided on the second memory layer 300 are dummy contacts that are not connected to any of the wiring layers 22 to 24. On the other hand, the plurality of bonding pads BP3 and BP4 for connecting the plurality of contacts CX provided on the first memory layer 200 and the plurality of contacts CC provided on the second memory layer 300, as well as the plurality of contacts VZ in the first memory layer 200, are provided in the same manner as in the first embodiment. In this configuration, the wiring layers 22, 23, and 24 provided on the second memory layer 300 are connected to the low decoder module 16 provided on the control circuit layer 100.

[0183] 1.4.2 Second Variation Figure 36 is a cross-sectional view showing an example of the cross-sectional structure of a first memory layer, a second memory layer, and a junction layer provided between them, which are included in a semiconductor memory device according to a second modified example of the first embodiment. The cross-section shown in Figure 36 corresponds to the cross-section shown in Figure 14 of the first embodiment.

[0184] As shown in Figure 36, in the semiconductor memory device 3 according to the second modification of the first embodiment, a plurality of contacts CC corresponding to the selected gate line SGD, included in each of the memory cell arrays 10-1 and 10-2, are provided in positions that overlap in the Z direction. In this case, the wiring layer 29 included in the memory cell array 10-2 extends, for example, in the X direction and is routed to a position that does not overlap in the Z direction with the contacts CC corresponding to the selected gate line SGD provided in the memory cell array 10-1. The memory cell array 10-1 includes a plurality of contacts CX corresponding to the selected gate line SGD of the memory cell array 10-2, and these plurality of contacts CX are connected to the corresponding plurality of contacts CC included in the memory cell array 10-2 via bonding pads BP3 and BP4, contact VZ, and the upper wiring HUL of the memory cell array 10-2. The plurality of contacts CX that pass through the thin film portion THN of the selected gate line SGD included in the memory cell array 10-2 become dummy contacts that are not connected to the wiring layer 24 included in the memory cell array 10-1.

[0185] 1.4.3 Third Variation Figure 37 is a cross-sectional view showing an example of the cross-sectional structure in the extraction region of a memory cell array in a semiconductor memory device according to a third modified example of the first embodiment. The cross-section shown in Figure 37 corresponds to the cross-section shown in Figure 12 of the first embodiment.

[0186] As shown in Figure 37, the memory cell array 10 of the semiconductor memory device 3 according to the third modification of the first embodiment further includes insulating layers 48 and 49. The insulating layers 48 and 49 include, for example, silicon oxide. In addition, each wiring layer 22, 23, and 24 of the memory cell array 10 does not include a thick film portion.

[0187] The third modification of the first embodiment differs from the first embodiment in the shape of the contact CC and the structure of the portion to which the contact CC connects with the corresponding wiring layers 22, 23, and 24. Specifically, the conductor 27 included in the contact CC according to the first embodiment connects to the corresponding wiring layers 22, 23, and 24 in the XY plane direction at the thick film portion THK of the wiring layers 22, 23, and 24. On the other hand, the conductor 27 included in the contact CC according to the third modification connects to the corresponding wiring layers 22, 23, and 24 in the Z direction at the upper surface of the wiring layers 22, 23, and 24.

[0188] In the manufacturing process of the memory cell array 10 according to the third modified example of the first embodiment, step S103 in the first embodiment is omitted, and instead, a step is inserted in which an insulating layer 48 and a thick sacrificial member are stacked in that order. The thick sacrificial member includes, for example, silicon nitride. In this case, the stacked thick sacrificial member is greater than the first thickness D1 and is equivalent to, for example, the second thickness D2. Also, after step S107, a step is inserted in which a part of the thick sacrificial member is removed through a hole CH. Also, in the step of embedding a sacrificial member 67 in the hole CH, the sacrificial member 67 is embedded in the part of the thick sacrificial member from which a part was removed. In step S109, sacrificial members 62, 63, and 64 are removed, and at the same time, the entire thick sacrificial member is removed through a slit SH. In step S110, at the same time as the formation of the spacer SP of member SLT, an insulating layer 49 is formed in the part from which the thick sacrificial member was removed. In step S111, a portion of the insulating layer 48 is removed until the upper surface of the corresponding wiring layer 22, 23, or 24 is exposed.

[0189] 2. Second Embodiment Next, a semiconductor memory device according to the second embodiment will be described. The semiconductor memory device 3 according to the second embodiment differs from the semiconductor memory device 3 according to the first embodiment in the shape of the contacts in each memory cell array 10, and the configuration of the connection portions with the corresponding contacts in each wiring layer 22, 23, and 24. In the following description, the configuration and manufacturing method equivalent to that of the first embodiment will be omitted, and the configuration that differs from that of the first embodiment will be described mainly.

[0190] 2.1 Configuration Figure 38 is a cross-sectional view showing an example of the cross-sectional structure of the first memory layer, the second memory layer, and the junction layer provided between them in the semiconductor memory device according to the second embodiment. Figure 39 is a cross-sectional view along the line XXXIX-XXXIX in Figure 38, showing an example of the cross-sectional structure of the first memory layer, the second memory layer, and the junction layer provided between them in the semiconductor memory device according to the second embodiment. Figures 38 and 39 correspond to Figures 13 and 15 in the first embodiment. Each memory cell array 10 in the semiconductor memory device 3 according to the second embodiment includes multiple contacts CO and CZ instead of multiple contacts CC and CX. In addition, the wiring layers 22, 23, and 24 included in each memory cell array 10 do not include thick film portions, and their thickness in the Z direction is substantially the same.

[0191] As shown in Figures 38 and 39, multiple contacts CO are provided in each memory cell array 10 of the semiconductor memory device 3 according to the first embodiment, at the same locations where multiple contacts CC are provided. A contact CO is a contact that is electrically connected to one of the wiring layers 22 to 24 included in the corresponding memory cell array 10. A contact CZ is a contact that is insulated from the wiring layers 22 to 24 included in the corresponding memory cell array 10 and passes through the stacked wiring in the Z direction. Multiple contacts CZ provided in memory cell array 10-1 function as wiring PWs that connect multiple contacts CO provided in memory cell array 10-2 and the low decoder module 16 provided in the control circuit layer 100. Each memory cell array 10 has a two-lane contact structure with multiple contacts CO and CZ.

[0192] Multiple contacts CO each extend in the Z direction and contact the terrace portion of the corresponding wiring layer 22, 23, or 24 at their bottom. That is, multiple contacts CO are not through-contacts. Multiple contacts CZ each extend in the Z direction, are insulated from the wiring layers 22-24 included in the memory cell array 10, and are through-contacts that pass through the stacked wiring in the Z direction.

[0193] The upper surfaces of each contact CO and CZ are in contact with the corresponding contact VY. The lower surface of each contact CZ in memory cell array 10-1 is in contact with the corresponding contact VZ. The lower surface of each contact CZ in memory cell array 10-2 is located within the insulating layer 40. Each of the contacts CO and CZ has, for example, an increasing cross-sectional area (XY cross-sectional area) along the XY plane from bottom to top.

[0194] Each of the multiple contact COs and CZs includes a conductor 27. The conductor 27 functions as the conductive portion of the contact COs and CZs. The conductor 27 includes, for example, tungsten or molybdenum.

[0195] Each contact CO contains a conductor 27 that contacts contact VY at its upper end and contacts one of the wiring layers 22, 23, and 24 at its lower end. The wiring layer 22, 23, or 24 to which the conductor 27 contained in each contact CO is connected is the wiring layer 22, 23, or 24 to which the contact CO corresponds. Each contact CO contains a conductor 27 that connects the wiring layer 22, 23, or 24 to which the contact CO corresponds and to contact VY.

[0196] The conductor 27 contained in each contact CZ is not electrically connected to any of the wiring layers 22, 23, and 24 contained in the memory cell array 10. The conductor 27 contained in each contact CZ is in contact with contact VY at its upper end, and its lower end is located inside the insulating layer 41. The conductor 27 contained in each contact CZ provided in the memory cell array 10-1 is in contact with the corresponding contact VZ at its lower end. The conductor 27 contained in each contact CZ provided in the memory cell array 10-1 connects contacts VY and VZ.

[0197] Each of the multiple contact CZs includes an insulator 47. The insulator 47 includes, for example, silicon oxide. The insulator 47 included in each contact CZ is provided so as to surround the sides of the conductor 27. The insulator 47 insulates the conductor 27 from the wiring layers 22, 23, and 24.

[0198] The configuration of contact CO is not limited to the above configuration, as long as the contact CO is connected to the corresponding wiring layer 22, 23, or 24 and insulated from the other wiring layers 22, 23, or 24.

[0199] Contact CZ in memory cell array 10-1 is connected via contact VZ to a plurality of junction pads BP3 provided on the junction layer B3 on the lower side of memory cell array 10-1. Contact CO in memory cell array 10-2 is connected via upper layer wiring HUL to a plurality of junction pads BP4 on the upper side of memory cell array 10-2. At the boundary between junction layers B3 and B4, junction pads BP3 and BP4 are arranged opposite each other and connected in the Z direction. Contact CZ in memory cell array 10-1 is connected to contact CO in memory cell array 10-2 via junction pads BP3 and BP4. At a position where memory cell arrays 10-1 and 10-2 overlap in the Z direction, if contact CZ is formed on one, contact CO is formed on the other. Note that contact CZ formed on memory cell array 10-2 is not connected to contact CO formed on memory cell array 10-1. In other words, contact CZ formed on memory cell array 10-2 becomes a dummy contact. For example, the upper layer wiring HUL corresponding to the contact CZ formed on the memory cell array 10-2 may be omitted.

[0200] In two bonded memory cell arrays 10, contact CO, provided in the step region STP of one memory cell array 10, and contact CZ, provided in the bridge region BRG of the other memory cell array 10, are located in positions that correspond to each other and overlap approximately in the Z direction.

[0201] As shown in Figure 39, in the terrace portion of the selection gate line SGD located in positions that overlap in the Z direction of memory cell arrays 10-1 and 10-2, the positions where contact COs corresponding to each selection gate line SGD are provided are shifted in the X direction and do not overlap in the Z direction. In the cross-section shown in Figure 39, since memory cell array 10-1 corresponds to block BLK1, contact COs are provided in the outer contact area SGDo and contact CZs are provided in the inner contact area SGDe. On the other hand, since memory cell array 10-2 corresponds to block BLK2, contact CZs are provided in the outer contact area SGDo and contact COs are provided in the inner contact area SGDe. In the inner contact area SGDe where contact COs are provided in memory cell array 10-2, contact COs and CZs located in positions that overlap in the Z direction are connected to each other via bonding pads BP3 and BP4, contact VZ, and the upper layer wiring HUL provided in memory cell array 10-2.

[0202] 2.2 Manufacturing process The manufacturing process for the memory cell array 10 of the semiconductor memory device 3 according to the second embodiment differs from that of the first embodiment in the parts relating to the manufacturing process of contact CO and CZ. The manufacturing process will be described below.

[0203] After the completion of the process in S105 shown in Figure 18, a plurality of contact CZs are formed. Specifically, a hole corresponding to each of the plurality of contact CZs is created, and the inner wall of the hole is covered with an insulator 47. Subsequently, a conductor 27 is provided inside the hole. The plurality of contact CZs may also be formed as vias passing through the wiring layers 22, 23, and 24 and the insulator layers 41, 42, 43, 44, and 45 in the Z direction.

[0204] Next, holes are formed corresponding to each of the multiple contacts CO. Each of these multiple holes has a different length in the Z direction due to the corresponding wiring layer 22, 23, or 24. At the bottom of each of these multiple holes, the corresponding sacrificial member 62, 63, or 64 is exposed.

[0205] Subsequently, in the S109 process, when the multilayer wiring is replaced, the metal corresponding to the conductor 27 is also poured into the holes corresponding to multiple contacts CO. This forms multiple contacts CO. Furthermore, the S111 process is omitted.

[0206] 2.3 Effects according to the second embodiment According to the second embodiment, the integration density of the semiconductor memory device 3 can be improved, similar to the first embodiment.

[0207] Furthermore, according to the second embodiment, since the multiple contacts CO are not through-contacts, the contacts CO do not pass through a wiring layer other than the wiring layer to which they correspond. Therefore, short circuits caused by contacts unintentionally connecting to a wiring layer other than the wiring layer to which they correspond can be suppressed.

[0208] 2.4 Variations The semiconductor memory device 3 according to the second embodiment described above can be modified in various ways. Below, the differences between the first and second modified examples of the second embodiment and the second embodiment will be explained.

[0209] 2.4.1 First Variation Figure 40 is a cross-sectional view showing an example of the cross-sectional structure of the first memory layer, the second memory layer, and the junction layer provided between them in a semiconductor memory device according to the first modification of the second embodiment. The memory cell array 10 in the semiconductor memory device 3 according to the first modification of the second embodiment includes a plurality of contacts CS instead of a plurality of contacts CO. Also, similar to the memory cell array 10 in the semiconductor memory device 3 according to the first embodiment, each of the wiring layers 22, 23, and 24 includes a thick film portion THK and a thin film portion THN.

[0210] Each of the multiple contacts CS includes a conductor 27 and an insulator 47. The conductor 27 included in the multiple contacts CS is in contact with the corresponding contact VY on its upper surface and with the insulator 47 on its bottom surface. Near the bottom, the conductor 27 included in the multiple contacts CS is in contact with the thick film portion THK of the corresponding wiring layer 22, 23, or 24 in the XY plane. The conductor 27 included in the multiple contacts CS passes through the insulator layer 45 in the Z direction, but does not pass through the wiring layers 22, 23, and 24 other than the corresponding wiring layer 22, 23, or 24, as well as the insulator layers 41, 42, 43, and 44 in the Z direction. The insulator 47 included in the multiple contacts CS extends in the Z direction and penetrates the wiring layers 22 and 23 and the insulator layers 41, 42, and 43, which are provided below the wiring layers 22, 23, or 24 to which the contact CS corresponds. The insulator 47 has protrusions that extend radially along the XY plane in the portion that passes through the insulating layers 41, 42, and 43 in the Z direction. The insulator 47 is in contact with the conductor 27 at its upper end, and its lower end is located inside the insulating layer 40.

[0211] The manufacturing process of the memory cell array 10 according to the first modified example of the second embodiment will be described in terms of differences from the manufacturing process of the memory cell array 10 according to the first embodiment. When performing the S106 process, after forming multiple holes CH corresponding to multiple contacts CS, instead of removing a portion of the sacrificial members 62, 63, and 64, the peripheral portions exposed on the sides of each hole CH of the insulating layers 41, 42, 43, 44, and 45 are removed by wet etching. As a result, multiple grooves are formed on the side of each hole CH, in which the insulating layers 41, 42, 43, 44, and 45 are recessed radially along the XY plane relative to the insulating layer 40 and the sacrificial members 62, 63, and 64. Subsequently, the insulating material 47 is embedded in the hole CH by the S107 process, and a portion of the insulating material 47 is removed by further wet etching. At this time, the insulating material 47 embedded in the layer below the thickened portion of the sacrificial member 62, 63, or 64 through which the hole CH passes is not removed. After that, the sacrificial member 67 is embedded in the hole CH. The sacrificial member 67 is in contact with the thickened portion of the corresponding sacrificial member 62, 63, or 64 at its bottom. Subsequently, in step S111, the sacrificial member 67 is replaced with the conductor 27, thereby connecting the conductor 27 with the corresponding wiring layer 22, 23, or 24.

[0212] 2.4.2 Second Variation Figure 41 is a cross-sectional view showing an example of the cross-sectional structure of a first memory layer, a second memory layer, and a junction layer provided between them in a semiconductor memory device according to a second modification of the second embodiment. The memory cell array 10 in the semiconductor memory device 3 according to the second modification of the second embodiment includes a plurality of contacts CS instead of a plurality of contacts CO. The memory cell array 10 further includes insulating layers 48 and 49. The insulating layers 48 and 49 include, for example, silicon oxide.

[0213] Each of the multiple contacts CS includes a conductor 27 and an insulator 47. The conductor 27 included in the multiple contacts CS is in contact with the corresponding contact VY on its upper surface and with the insulator 47 on its lower surface. The conductor 27 included in the multiple contacts CS is in contact with the corresponding wiring layers 22, 23, or 24 in the Z direction near the bottom. The conductor 27 included in the multiple contacts CS passes through the insulator layers 45, 48, and 49 in the Z direction, but does not pass through the wiring layers 22, 23, and 24, as well as the insulator layers 41, 42, 43, and 44 in the Z direction. The insulator 47 included in the multiple contacts CS extends in the Z direction and penetrates the wiring layers 22 and 23 and the insulator layers 41, 42, and 43, which are provided beneath the wiring layers 22, 23, or 24 to which the contact CS corresponds. The insulator 47 has protrusions that extend radially along the XY plane in the portion that passes through the insulating layers 41, 42, and 43 in the Z direction. The insulator 47 is in contact with the conductor 27 at its upper end, and its lower end is located inside the insulating layer 40.

[0214] The manufacturing process of the memory cell array 10 according to the second modified example of the second embodiment will be described in terms of differences from the manufacturing process of the memory cell array 10 according to the first modified example of the second embodiment. First, step S103 is omitted, and instead, a step is inserted in which the insulating layer 48 and the thick sacrificial member are laminated in that order. The thick sacrificial member includes, for example, silicon nitride. The thick sacrificial member laminated at this time is greater than the first thickness D1 and is equivalent to, for example, the second thickness D2. After the insulator 47 is embedded, a step is inserted in which a part of the thick sacrificial member is removed through the hole CH. In the step of embedding the sacrificial member 67 in the hole CH, the sacrificial member 67 is embedded in the part from which the thick sacrificial member was removed. In step S109, the sacrificial members 62, 63, and 64 are removed, and at the same time, the entire thick sacrificial member is removed through the slit SH. In step S110, the insulating layer 49 is formed in the part from which the thick sacrificial member was removed, at the same time as the spacer SP of the member SLT is formed. In step S111, a portion of the insulating layer 48 is removed until the upper surface of the corresponding wiring layer 22, 23, or 24 is exposed.

[0215] 3. Third Embodiment Next, a semiconductor memory device according to the third embodiment will be described. The semiconductor memory device 3 according to the third embodiment differs from the semiconductor memory device 3 according to the first embodiment in the stepped structure of each memory cell array 10. In the following description, the configuration equivalent to that of the first embodiment will be omitted from the description, and the configuration that differs from that of the first embodiment will be described mainly.

[0216] 3.1 Structure of a memory cell array Figure 42 is a plan view showing an example of a planar layout in the extraction region of a memory cell array in a semiconductor memory device according to the third embodiment. Figure 42 shows regions corresponding to three blocks BLK0 to BLK2. Figure 43 is a cross-sectional view of the extraction region of the memory cell array in a semiconductor memory device according to the third embodiment, along the line XLIII-XLIII in Figure 42. Figure 43 shows the extraction region HA of block BLK1, as well as the XZ cross-section of contacts CC and CX.

[0217] As shown in Figures 42 and 43, each memory cell array 10 includes an inclined IPB in the extraction region HA. The inclined IPB is a step that includes the ends of a plurality of continuously stacked wiring layers 23, arranged in a rectangular shape in plan view. A portion of the inclined IPB is provided so as to cross the stair region STP in the Y direction. In the inclined IPB, the ends of the plurality of continuously stacked wiring layers 23 are inclined at approximately the same angle in the diagonal directions in the XZ and YZ planes, forming a slope. The inclined IPB divides the stair region STP into stair regions STP1 and STP2.

[0218] Staircase region STP1 is the region of staircase region STP that is outside the inclined section IPB. Staircase region STP2 is the region of staircase region STP that is inside the inclined section IPB. Staircase regions STP1 and STP2 are provided so as to straddle member SLTe in the Y direction and are aligned with each other in the X direction. A stadium-like staircase structure is provided in each of staircase regions STP1 and STP2. Staircase region STP1 is provided with terrace sections corresponding to, for example, word lines WL3 to WL6. Staircase region STP2 is provided with terrace sections corresponding to, for example, the selection gate line SGS and word lines WL0 to WL2. Multiple contact CCs are provided corresponding to each terrace section of each stadium-like staircase structure.

[0219] The staircase regions STP1 and STP2 are provided with an inclined section IP, and the staircase regions STPa and STPb, respectively, which are divided by the inclined section IP. The staircase region STPa is the area outside the inclined section IP. The staircase region STPa is provided with a stadium-like staircase structure that ascends in the direction toward the memory region MA1. The staircase region STPb is the area inside the inclined section IP. The staircase region STPb is provided with a stadium-like staircase structure that ascends in the direction toward the memory region MA2.

[0220] The number of steps in each inclined section IP is smaller than the number of steps in the inclined section IPB. In the examples shown in Figures 42 and 43, the inclined section IPB is a step that includes the ends of four continuously stacked wiring layers 23, whereas each inclined section IP is a step that includes the ends of two continuously stacked wiring layers 23.

[0221] The respective memory cell arrays 10-1 and 10-2 are bonded together in the Z direction, similar to the first embodiment.

[0222] 3.2 Effects According to the third embodiment, the integration density of the semiconductor memory device 3 can be improved, similar to the first embodiment.

[0223] Furthermore, according to the third embodiment, multiple stadium-shaped staircase structures with different corresponding wiring layers can be arranged in the X direction within the same block BLK. Since each stadium-shaped staircase structure is formed in the same process, the total number of processing steps is reduced, and an increase in the manufacturing cost of the memory cell array 10 can be suppressed.

[0224] 3.3 Variant Examples The semiconductor memory device 3 according to the third embodiment described above is subject to various modifications. For example, modifications corresponding to the first to third modifications in the first embodiment, and modifications corresponding to the second embodiment and the first to second modifications in the second embodiment may be applied to the semiconductor memory device 3 according to the third embodiment.

[0225] 4. Fourth Embodiment Next, a semiconductor memory device according to the fourth embodiment will be described. The semiconductor memory device 3 according to the fourth embodiment differs from the semiconductor memory device 3 according to the first embodiment in the stepped structure of each memory cell array 10. In the following description, the configuration equivalent to that of the first embodiment will be omitted from the description, and the configuration that differs from that of the first embodiment will be described mainly.

[0226] 4.1 Structure of a memory cell array 4.1.1 Overview Figure 44 is a plan view showing an example of a planar layout of a memory cell array in a semiconductor memory device according to the fourth embodiment. Figure 44 shows regions corresponding to three blocks BLK0 to BLK2.

[0227] In the fourth embodiment, each region demarcated by a plurality of members SLTo in each memory cell array 10 corresponds to one block BLK in each memory cell array 10. Each member SLTo separates adjacent stacked wiring through the member SLTo.

[0228] In the fourth embodiment, each memory cell array 10 comprises multiple SLTe components, which are divided in the X direction by one or more division regions SR provided in the extraction region HA. In the example shown in Figure 44, the SLTe component is divided into three in the X direction by two division regions SR. That is, by being divided in the division regions SR, the SLTe component does not divide each of the multiple wiring layers 23 and 24 corresponding to the selected gate line SGS and word lines WL0 to WL6, respectively, in the Y direction. In other words, wiring layers 23 and 24 adjacent in the Y direction via the SLTe component are connected to each other in the Y direction via the division regions SR. That is, the division regions SR are connection regions for wiring layers 23 and 24 adjacent in the Y direction via the SLTe component.

[0229] The extension area HA includes one staircase area STP and two bridge areas BRG within a single block BLK. The staircase area STP is provided so as to straddle member SLTe. The bridge areas BRG are provided in each block BLK between the staircase area STP and two members SLTo that are provided so as to sandwich the block BLK.

[0230] Figure 45 is a schematic cross-sectional view illustrating an example of the cross-sectional structure of a bonded first memory layer and second memory layer in a semiconductor memory device according to the fourth embodiment. Figure 45 shows the first memory layer 200, the second memory layer 300, and junction layers B3 and B4. As shown in Figure 45, the memory cell array 10-1 of the first memory layer 200 and the memory cell array 10-2 of the second memory layer 300 are bonded in the Z direction with a shift in the Y direction by half a block BLK via junction layers B3 and B4.

[0231] Specifically, block BLKi_1 of memory cell array 10-1 is placed above block BLKi_2 and block BLK(i+1)_2 of memory cell array 10-2, and block BLK(i+1)_2 of memory cell array 10-2 is placed below block BLKi_1 and block BLK(i+1)_1 of memory cell array 10-1 (where i is an integer satisfying 0 ≤ i ≤ n-1). No dummy blocks are provided.

[0232] Above the component SLTo of the memory cell array 10-2, the component SLTe of the memory cell array 10-1 is provided. Above the component SLTe of the memory cell array 10-2, the component SLTo of the memory cell array 10-1 is provided. That is, one component SLTo and one component SLTe are provided so as to overlap in the Z direction.

[0233] The stepped region STP of memory cell array 10-1 and the stepped region STP of memory cell array 10-2 are located side by side in the Y direction and at different positions in the Z direction. Specifically, the bridge region BRG of memory cell array 10-2 is provided below the stepped region STP of memory cell array 10-1. The bridge region BRG of memory cell array 10-1 is provided above the stepped region STP of memory cell array 10-2. In other words, if a stepped region STP is provided in one of the memory cell arrays 10-1 and 10-2 at positions overlapping in the Z direction near the member SLT, forming a stepped structure, then the bridge region BRG is provided in the other, forming a structure in which multiple wiring layers 22 and 23 are stacked.

[0234] 4.1.2 Planar Layout Figure 46 is a plan view showing an example of a planar layout in the extraction region of the memory cell array in the semiconductor memory device according to the fourth embodiment. In Figure 46, regions corresponding to parts of block BLK0 and block BLK1 are shown.

[0235] As shown in Figure 46, the first part SGDa and the second part SGDb of the selection gate line SGD are divided into 10 parts each within one block BLK by members SLTe and SHE. Each of the first part SGDa and the second part SGDb of the selection gate line SGD has two parts each corresponding to string units SU0 to SU4 within one block BLK. For each of the 10 divided selection gate line SGD, one contact CC and one contact CX are provided in the inner contact region SGDe and one contact CX in the outer contact region SGDo, respectively. Specifically, for example, in a selection gate line SGD located above the plane of the paper above member SLTe which is provided to cross the block BLK, contact CC is provided in the inner contact region SGDe and contact CX is provided in the outer contact region SGDo. In a selection gate line SGD located below the plane of the paper above member SLTe which is provided to cross the block BLK, contact CX is provided in the inner contact region SGDe and contact CC is provided in the outer contact region SGDo.

[0236] Note that the structure of the selected gate line SGD is not limited to the structure described above. For example, each of the first part SGDa and the second part SGDb of the selected gate line SGD may have one part corresponding to string units SU0 to SU4.

[0237] Within a single block BLK, in the staircase region STP, two corresponding contacts CC are provided for each of the selected gate lines SGS and word lines WL0 to WL6. Specifically, for example, pairs of contacts CC corresponding to the same wiring layer are provided at positions approximately symmetrical with respect to member SLTe, and each pair is aligned in the X direction. In addition, in two bridge regions BRG, multiple contacts CX are provided aligned in the X direction in each.

[0238] 4.2 Effects According to the fourth embodiment, the integration density of the semiconductor memory device 3 can be improved, similar to the first embodiment.

[0239] Also, according to the fourth embodiment, two contact CCs corresponding to each wiring layer are provided. As a result, the electrical resistance in the wiring that mediates between each wiring layer and the row decoder module 16 can be reduced. Therefore, the read speed and write speed of the semiconductor memory device 3 can be improved.

[0240] 4.3 Variations The semiconductor memory device 3 according to the fourth embodiment described above can be variously modified. For example, modifications corresponding to the first to third variations in the first embodiment and modifications corresponding to the second embodiment and the first to second variations of the second embodiment may be applied to the semiconductor memory device 3 according to the fourth embodiment.

[0241] 5. The Fifth Embodiment Next, a semiconductor memory device according to the fifth embodiment will be described. The semiconductor memory device 3 according to the fifth embodiment is different from the semiconductor memory device 3 according to the first embodiment in the staircase structure in each memory cell array 10. In the following description, the description of the configuration equivalent to the first embodiment will be omitted, and the configuration different from the first embodiment will be mainly described.

[0242] 5.1 Configuration In the semiconductor memory device 3 according to the fifth embodiment, each NAND string NS includes, for example, 15 memory cell transistors MT0 to MT14 and selection transistors ST1 and ST2. The control gates of the memory cell transistors MT0 to MT14 in the same block BLK are respectively connected to word lines WL0 to WL14.

[0243] 5.2 Structure of the Memory Cell Array FIG. 47 is a plan view showing an example of a planar layout in a lead-out region of a memory cell array included in a semiconductor memory device according to the fifth embodiment. In FIG. 47, regions corresponding to three blocks BLK0 to BLK2 are shown. FIG. 48 is a cross-sectional view showing an example of a cross-sectional structure of a first memory layer and a second memory layer included in a semiconductor memory device according to the fifth embodiment, and a bonding layer provided between the two. In FIG. 48, regions corresponding to blocks BLK0 to BLK2 in the memory cell array 10-1 and blocks BLK1 to BLK3 in the memory cell array 10-2 are shown. The stacked wirings in the memory cell arrays 10-1 and 10-2 shown in FIG. 48 correspond to the selection gate line SGS and the word lines WL0 to WL14 in order from below.

[0244] As shown in FIGS. 47 and 48, the memory cell array 10 includes a two-row staircase structure having, for example, a one-step difference in the Y direction and a two-step staircase difference in the X direction in the staircase region STP. A plurality of contacts CC are provided corresponding to each terrace portion of the two-row staircase structure. Also, a plurality of contacts CX are provided in the bridge region BRG.

[0245] In the memory cell array 10 according to the fifth embodiment, in a region sandwiched in the Y direction by two members SLT, a plurality of contacts CC and CX are provided so as to line up in two columns each in the Y direction, for a total of four columns. This structure is called a "contact four-lane structure".

[0246] Each thick film portion THK in each of the wiring layers 22 and 23 is spaced apart in the X direction from the side surface of the thick film portion THK of the wiring layer 23 or 24 provided in the two upper layers of the wiring layers 22 and 23. Also, each thick film portion THK in each of the wiring layers 22 and 23 is spaced apart in the Y direction from the side surface of the thick film portion THK of the wiring layer 23 or 24 provided in one upper layer of the wiring layers 22 and 23.

[0247] " 5.3 Effects According to the fifth embodiment, the integration density of the semiconductor memory device 3 can be improved, similar to the first embodiment. Furthermore, the memory cell array 10 according to the fifth embodiment includes a four-lane contact structure. This structure further suppresses the increase in the length of the memory cell array 10 in one direction (e.g., the X direction) due to the terrace portions and corresponding contacts CC in the wiring layers 22 and 23 being aligned in one direction, compared to the two-lane contact structure. Therefore, the chip area of ​​the semiconductor memory device 3 can be reduced (expansion suppressed), and the integration density can be further improved.

[0248] 5.4 Variations The semiconductor memory device 3 according to the fifth embodiment described above is subject to various modifications. For example, modifications corresponding to the first to third modifications in the first embodiment, and modifications corresponding to the second embodiment and the first to second modifications in the second embodiment may be applied to the semiconductor memory device 3 according to the fifth embodiment.

[0249] 6. Sixth Embodiment Next, a semiconductor memory device according to the sixth embodiment will be described. The semiconductor memory device 3 according to the sixth embodiment differs from the semiconductor memory device 3 according to the fifth embodiment in the stepped structure of each memory cell array 10. In the following description, the configuration equivalent to that of the fifth embodiment will be omitted, and the configuration that differs from that of the fifth embodiment will be mainly described.

[0250] 6.1 Structure of a memory cell array In the semiconductor memory device 3 according to the sixth embodiment, each memory cell array 10, similar to the fourth embodiment, has regions demarcated by a plurality of members SLTo in each memory cell array 10, each corresponding to one block BLK in each memory cell array 10. Furthermore, the plurality of members SLTe in each memory cell array 10 are divided into multiple sections in the X direction in one or more division regions SR provided in the draw-out region HA. That is, by being divided in the division region SR, the member SLTe does not divide each of the plurality of wiring layers 22 and 23 corresponding to the selected gate line SGS and word lines WL0 to WL14, respectively, in the Y direction. In other words, wiring layers 22 and 23 adjacent in the Y direction via member SLTe are connected to each other in the Y direction via the division region SR. That is, the division region SR is a connection region for wiring layers 22 and 23 adjacent in the Y direction via member SLTe.

[0251] The extension area HA includes one staircase area STP and two bridge areas BRG within a single block BLK. The staircase area STP is provided so as to straddle member SLTe. The bridge areas BRG are provided in each block BLK between the staircase area STP and two members SLTo that are provided so as to sandwich the block BLK.

[0252] In the semiconductor memory device 3 according to the sixth embodiment, similar to the fourth embodiment, the memory cell array 10-1 of the first memory layer 200 and the memory cell array 10-2 of the second memory layer 300 are bonded in the Z direction with a shift in the Y direction by half a block BLK via junction layers B3 and B4. The bonding structure of the memory cell arrays 10-1 and 10-2 of the semiconductor memory device 3 according to the sixth embodiment is substantially the same as the structure shown in Figure 45 of the fourth embodiment.

[0253] Figure 49 is a plan view showing an example of a planar layout in the extraction region of a memory cell array in a semiconductor memory device according to the sixth embodiment. In Figure 49, regions corresponding to parts of block BLK0 and block BLK1 are shown.

[0254] As shown in Figure 49, the first part SGDa and the second part SGDb of the selection gate line SGD are divided into 10 parts each within one block BLK by members SLTe and SHE. Each of the first part SGDa and the second part SGDb of the selection gate line SGD has two parts each corresponding to string units SU0 to SU4 within one block BLK. For each of the 10 divided selection gate line SGD, one contact CC and one contact CX are provided in the inner contact region SGDe and one contact CX in the outer contact region SGDo, respectively. Specifically, for example, in a selection gate line SGD located above the plane of the paper above member SLTe which is provided to cross the block BLK, contact CC is provided in the inner contact region SGDe and contact CX is provided in the outer contact region SGDo. In a selection gate line SGD located below the plane of the paper above member SLTe which is provided to cross the block BLK, contact CX is provided in the inner contact region SGDe and contact CC is provided in the outer contact region SGDo.

[0255] Note that the structure of the selected gate line SGD is not limited to the structure described above. For example, each of the first part SGDa and the second part SGDb of the selected gate line SGD may have one part corresponding to string units SU0 to SU4.

[0256] Within a single block BLK, in the staircase region STP, two corresponding contacts CC are provided for each of the selected gate lines SGS and word lines WL0 to WL14. Specifically, for example, pairs of contacts CC corresponding to the same wiring layer are provided at positions approximately symmetrical with respect to member SLTe, and each pair is aligned in the X direction. In addition, in two bridge regions BRG, multiple contacts CX are provided in two rows each, aligned in the X direction.

[0257] 6.2 Effects According to the sixth embodiment, similar to the fifth embodiment, the integration density of the semiconductor memory device 3 can be improved.

[0258] Also, according to the sixth embodiment, two contact CCs corresponding to each wiring layer are provided. Thereby, the electrical resistance in the wiring that mediates between each wiring layer and the row decoder module 16 can be reduced. Therefore, the read speed and write speed of the semiconductor memory device 3 can be improved.

[0259] 6.3 Variation The semiconductor memory device 3 according to the sixth embodiment described above can be variously modified. For example, modifications corresponding to the first to third variations in the first embodiment and modifications corresponding to the second embodiment and the first to second variations of the second embodiment may be applied to the semiconductor memory device 3 according to the sixth embodiment.

[0260] 7. The Seventh Embodiment Next, a semiconductor memory device according to the seventh embodiment will be described. The semiconductor memory device 3 according to the seventh embodiment is different from the semiconductor memory device 3 according to the fifth embodiment in the staircase structure in each memory cell array 10. In the following description, the description of the configuration equivalent to the fifth embodiment will be omitted, and the configuration different from the fifth embodiment will be mainly described.

[0261] 7.1 Structure of Memory Cell Array FIG. 50 is a plan view showing an example of a plan layout of a memory cell array included in a semiconductor memory device according to the seventh embodiment. In FIG. 50, regions corresponding to six blocks BLK0 to BLK5 are shown.

[0262] In the seventh embodiment, each region partitioned by a plurality of members SLT included in each memory cell array 10 corresponds to one block BLK in each memory cell array 10. Each member SLT divides adjacent laminated wirings via the member SLT.

[0263] The extension area HA includes one staircase area STP and two bridge areas BRG within a single block BLK. The staircase area STP is located in the Y-center of the extension area HA within each block BLK. The two bridge areas BRG are each located between the staircase area STP and two members SLT adjacent to the block BLK in the Y-direction.

[0264] Figure 51 is a schematic cross-sectional view illustrating an example of the cross-sectional structure of a bonded first memory layer and a second memory layer in a semiconductor memory device according to the seventh embodiment. Figure 51 shows the first memory layer 200, the second memory layer 300, and junction layers B3 and B4. As shown in Figure 51, the memory cell array 10-1 of the first memory layer 200 and the memory cell array 10-2 of the second memory layer 300 are bonded in the Z direction with a shift in the Y direction by half a block BLK via junction layers B3 and B4.

[0265] Specifically, block BLKi_1 of memory cell array 10-1 is placed above block BLKi_2 and block BLK(i+1)_2 of memory cell array 10-2, and block BLK(i+1)_2 of memory cell array 10-2 is placed below block BLKi_1 and block BLK(i+1)_1 of memory cell array 10-1 (where i is an integer satisfying 0 ≤ i ≤ n-1). Block BLK0_2 of memory cell array 10-2 and block BLKn_1 of memory cell array 10-1 are dummy blocks.

[0266] A stepped region STP of memory cell array 10-1 is provided above the member SLT of memory cell array 10-2. A stepped region STP of memory cell array 10-2 is provided below the member SLT of memory cell array 10-1. In other words, the member SLT of one memory cell array is bonded so as to overlap the stepped region STP of the other memory cell array.

[0267] The stepped region STP of memory cell array 10-1 and the stepped region STP of memory cell array 10-2 are located side by side in the Y direction and at different positions in the Z direction in a plan view. Specifically, the bridge region BRG of memory cell array 10-2 is located below the stepped region STP of memory cell array 10-1. The bridge region BRG of memory cell array 10-1 is located above the stepped region STP of memory cell array 10-2. In other words, when a stepped region STP is provided in one of the memory cell arrays 10-1 and 10-2 at positions overlapping in the Z direction, forming a stepped structure, the bridge region BRG is provided in the other, forming a structure in which multiple wiring layers 22 and 23 are stacked.

[0268] Figure 52 is a plan view showing an example of a planar layout in the extraction region of a memory cell array in a semiconductor memory device according to the seventh embodiment. In Figure 52, regions corresponding to parts of block BLK0 and block BLK1 are shown. Figure 53 is a cross-sectional view showing an example of the cross-sectional structure of a first memory layer, a second memory layer, and a junction layer provided between them in a semiconductor memory device according to the seventh embodiment. In Figure 53, regions corresponding to parts of block BLK0 and BLK1 in memory cell array 10-1, and parts of block BLK1, and parts of block BLK0 and BLK2 in memory cell array 10-2 are shown. The stacked wiring in memory cell arrays 10-1 and 10-2 shown in Figure 53 corresponds, from bottom to top, to the selected gate line SGS and word lines WL0 to WL14, respectively.

[0269] As shown in Figures 52 and 53, each memory cell array 10 includes a double-row staircase structure in the staircase region STP, for example, having one step in the Y direction and two steps in the X direction. In the example shown in Figures 52 and 53, the one step in the Y direction is provided in two adjacent blocks BLK separated by a member SLT, with a shape symmetrical to the member SLT in the Y direction. Multiple contacts CC are provided in two rows corresponding to each terrace portion of the double-row staircase structure. In addition, multiple contacts CX are provided in two rows in the bridge region BRG. That is, each memory cell array 10 has a 4-lane contact structure.

[0270] Each thick film portion THK in each wiring layer 22 and 23 is spaced apart in the X direction from the side surface of the thick film portion THK of wiring layer 23 or 24, which is located two layers above the wiring layer 22 and 23. In addition, each thick film portion THK in each wiring layer 22 and 23 is spaced apart in the Y direction from the side surface of the thick film portion THK of wiring layer 23 or 24, which is located one layer above the wiring layer 22 and 23.

[0271] As shown in Figure 53, no contact CC of memory cell array 10-1 is provided above the member SLT provided in memory cell array 10-2. Similarly, no contact CC of memory cell array 10-2 is provided below the member SLT provided in memory cell array 10-1. In other words, in memory cell arrays 10-1 and 10-2, one member SLT and the other contact CC are provided so as not to overlap.

[0272] As shown in Figure 52, for example, contact CX is not provided in the terrace portion of the selected gate line SGD. Contact CC, which is connected to the terrace portion of the selected gate line SGD in the memory cell array 10-2, is routed via the upper layer wiring HUL, junction pads BP3 and BP4, and wiring (not shown), and is connected to the low decoder module 16.

[0273] 7.2 Effects According to the seventh embodiment, the integration density of the semiconductor memory device 3 can be improved, similar to the first and fifth embodiments.

[0274] 7.3 Variations The semiconductor memory device 3 according to the seventh embodiment described above is subject to various modifications. For example, modifications corresponding to the first to third modifications in the first embodiment, and modifications corresponding to the second embodiment and the first to second modifications in the second embodiment may be applied to the semiconductor memory device 3 according to the seventh embodiment.

[0275] 8. Eighth Embodiment Next, a semiconductor memory device according to the eighth embodiment will be described. The semiconductor memory device 3 according to the eighth embodiment differs from the semiconductor memory device 3 according to the seventh embodiment in the stepped structure of each memory cell array 10. In the following description, the configuration equivalent to that of the seventh embodiment will be omitted from the description, and the configuration that differs from that of the seventh embodiment will be mainly described.

[0276] 8.1 Structure of a memory cell array Figure 54 is a plan view showing an example of a planar layout of a memory cell array in a semiconductor memory device according to the eighth embodiment. In Figure 54, regions corresponding to three blocks BLK0 to BLK2 are shown. Figure 55 is a schematic cross-sectional view showing an example of a cross-sectional structure of a bonded first memory layer and a second memory layer in a semiconductor memory device according to the eighth embodiment. In Figure 55, the first memory layer 200 and the second memory layer 300, as well as junction layers B3 and B4 are shown.

[0277] As shown in Figure 54, in the semiconductor memory device 3 according to the eighth embodiment, each memory cell array 10, similar to the fourth embodiment, has regions demarcated by a plurality of members SLTo in each memory cell array 10, each corresponding to one block BLK in each memory cell array 10. Furthermore, the plurality of members SLTe in each memory cell array 10 are divided into multiple sections in the X direction in one or more division regions SR provided in the draw-out region HA. That is, by being divided in the division region SR, the member SLTe does not divide each of the plurality of wiring layers 22 and 23 corresponding to the selected gate line SGS and word lines WL0 to WL14, respectively, in the Y direction. In other words, wiring layers 22 and 23 adjacent in the Y direction via member SLTe are connected to each other in the Y direction via the division region SR. That is, the division region SR is the connection region of wiring layers 22 and 23 adjacent in the Y direction via member SLTe.

[0278] As shown in Figure 55, the memory cell array 10-1 of the first memory layer 200 and the memory cell array 10-2 of the second memory layer 300 are bonded together in the Z direction with a 1 / 4 block BLK offset in the Y direction. Specifically, block BLKi_1 of the memory cell array 10-1 is provided above block BLKi_2 and block BLK(i+1)_2 of the memory cell array 10-2, and block BLK(i+1)_2 of the memory cell array 10-2 is provided below block BLKi_1 and block BLK(i+1)_1 of the memory cell array 10-1 (where i is an integer satisfying 0 ≤ i ≤ n-1). No dummy blocks are provided.

[0279] Above the components SLTo and SLTe of memory cell array 10-2, the stepped region STP of memory cell array 10-1 is provided. Below the components SLTo and SLTe of memory cell array 10-1, the stepped region STP of memory cell array 10-2 is provided. In other words, the component SLT of one memory cell array 10 is bonded so as to overlap the stepped region STP of the other memory cell array 10.

[0280] The step region STP of memory cell array 10-1 and the step region STP of memory cell array 10-2 are located side by side in the Y direction and at different positions in the Z direction. Specifically, the bridge region BRG of memory cell array 10-2 is located below the step region STP of memory cell array 10-1. The bridge region BRG of memory cell array 10-1 is located above the step region STP of memory cell array 10-2. In other words, when a step region STP is provided in one of the memory cell arrays 10-1 and 10-2 at positions overlapping in the Z direction, forming a step-like structure, the other array has a bridge region BRG, forming a structure in which multiple wiring layers 22 and 23 are stacked.

[0281] As shown in Figure 56, the first portion SGDa and the second portion SGDb of the selected gate line SGD are divided into 10 parts each within a single block BLK by members SLTe and SHE. Each of the first portion SGDa and the second portion SGDb of the selected gate line SGD has two parts each corresponding to string units SU0 to SU4 within a single block BLK. One contact CC is provided for each of the 10 divided selected gate line SGD parts. As shown in Figure 56, for example, no contact CX is provided in the terrace portion of the selected gate line SGD. The contact CC connected to the terrace portion of the selected gate line SGD in the memory cell array 10-2 is routed via the upper layer wiring HUL, junction pads BP3 and BP4, and wiring (not shown) and connected to the low decoder module 16.

[0282] Note that the structure of the selected gate line SGD is not limited to the structure described above. For example, each of the first part SGDa and the second part SGDb of the selected gate line SGD may have one part corresponding to string units SU0 to SU4.

[0283] The configurations of the two staircase regions STP within a single block BLK are substantially identical. Therefore, within a single block BLK, there are two contact CCs corresponding to the same wiring layer. Furthermore, of the three bridge regions BRG, the two bridge regions BRGs located between the two staircase regions STP and the two members SLTo adjacent to the block BLK each have multiple contact CXs arranged in a single row in the X direction. In the bridge region BRG located between the two staircase regions STP, multiple contact CXs are arranged in two rows in the X direction, flanking the member SLTe.

[0284] 8.2 Effects According to the eighth embodiment, similar to the seventh embodiment, the integration density of the semiconductor memory device 3 can be improved.

[0285] Furthermore, according to the eighth embodiment, two contact CCs are provided for each wiring layer. This makes it possible to reduce the electrical resistance in the wiring mediating each wiring layer and the row decoder module 16. Therefore, the read speed and write speed of the semiconductor memory device 3 can be improved.

[0286] 8.3 Variations The semiconductor memory device 3 according to the eighth embodiment described above is subject to various modifications. For example, modifications corresponding to the first to third modifications in the first embodiment, and modifications corresponding to the second embodiment and the first to second modifications in the second embodiment may be applied to the semiconductor memory device 3 according to the eighth embodiment.

[0287] 9. Others While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0288] 1…Memory system 2…Memory controller 3…Semiconductor memory 10, 10-1, 10-2…memory cell array 11…Input / Output Circuits 12…Logic control circuits 13…Register 14… Sequencer 15…Driver module 16… Raw Decoder Module 17…Sense Amp Module 21, 22, 23, 24, 25, 26, 28, 29, 71, 72, 73, 74, 75, 76...wiring layer 27... Conductors 30…Core film 31… Semiconductor film 32…Multilayer film 33...Tunnel insulating film 34...Charge storage film 35…Block Insulating Film 40, 41, 42, 43, 44, 45, 46, 48, 49, 51, 52, 53, 70… Insulating layer 47. STI…Insulator 61, 62, 63, 64, 66, 67... Sacrificial members 65… Mask 100...Control circuit layer 200...First memory layer 300...Second memory layer 400...Wiring layer B1, B2, B3, B4...bonding layer BL...bit line BLK...block BP1, BP2, BP3, BP4… Connecting pads BRG...Bridge Region CC, CO, CS, CV, CX, CZ, C0, C1, C2, C3, C4, C5, LI, VY, VZ, V1, V2, V3, V4… Contact CH...Hall CU... Cell Unit DR…Impure diffusion region GC…Gateway HA…Drawer area HUL, MUL... Upper layer wiring IP, IPB...Slope part MA1, MA2... Memory area MP...Memory Pillar MT...Memory cell transistor NS...NAND string PD... pad PW...Wiring SGD, SGS... Selectable gate lines SGDe…Inner contact area SGDo…Outer contact area SH...Slit SHE, SLT, SLTe, SLTo… Components SL…Source Line SP...Spacer SR... Divided Area ST1, ST2…Selection transistor STP, STP1, STP2, STPa, STPb...Stairs area SU... String Unit THK...thick film part THN…thin film part TR...Transistor W, W1… Semiconductor substrate WL...Word line

Claims

1. Viewed in the first direction, the first wiring layer is provided in the first region, A plurality of second wiring layers are provided above the first wiring layer, spanning the first region and a second region aligned in a second direction intersecting the first region and the first direction, and spaced apart from each other in the first direction. Here, the plurality of second wiring layers have a plurality of first terrace portions provided within the second region so as not to overlap with the upper second wiring layer in the first direction, and a first bridge portion extending in the second direction, and the plurality of first terrace portions and the first bridge portion are arranged in a third direction intersecting the first direction and the second direction, Above the plurality of second wiring layers, a third wiring layer is provided in the first region, A plurality of fourth wiring layers are provided above the third wiring layer, spanning the first and second regions, and spaced apart from each other in the first direction, Here, the plurality of fourth wiring layers have a plurality of second terrace portions provided in the second region such that they do not overlap with the upper fourth wiring layer in the first direction, and are positioned to overlap with the first bridge portion when viewed in the first direction, and a second bridge portion extending in the second direction and provided to overlap with the plurality of first terrace portions when viewed in the first direction, and the plurality of second terrace portions and the second bridge portion are arranged in the third direction, A first memory pillar having an extension in the first direction within the first region, in contact with the first wiring layer, and having a portion that passes through the plurality of second wiring layers function as a plurality of first memory cells, A second memory pillar extending in the first direction within the first region, in contact with the third wiring layer, and having a portion passing through the plurality of fourth wiring layers that functions as a plurality of second memory cells, Within the second region, a first contact is in contact with one of the plurality of first terrace portions and extends in the first direction, Within the second region, a second contact extends above the first contact in the first direction, passes through the plurality of fourth wiring layers, and is electrically connected to the first contact, Within the second region, a third contact is in contact with one of the plurality of second terrace portions and extends in the first direction, A semiconductor memory device equipped with the following features.

2. The device further comprises a first electrode and a second electrode, which are positioned between the plurality of second wiring layers and the third wiring layers in the first direction, and which are facing each other in the first direction and in contact with each other in the first direction. The first electrode is electrically connected to the first contact, The second electrode is electrically connected to the second contact, The first contact and the second contact are electrically connected via the first electrode and the second electrode. The semiconductor memory device according to claim 1.

3. Within the second region, further comprising a fourth contact extending below the third contact in the first direction and passing through the plurality of second wiring layers, The semiconductor memory device according to claim 1.

4. The first contact passes through the second wiring layer located below one of the multiple first terrace portions in the first direction. The third contact passes in the first direction through the fourth wiring layer located below one of the multiple second terrace portions among the multiple fourth wiring layers. The semiconductor memory device according to claim 1.

5. Each of the plurality of first terrace portions is thicker in the first direction than the other portions of the plurality of second wiring layers. Each of the plurality of second terrace portions is thicker in the first direction than the other portions of the plurality of fourth wiring layers. The semiconductor memory device according to claim 1.

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