Multilayer electronic components

Abstract

The present invention provides a multilayer electronic component that includes a dielectric layer with excellent reliability, high-temperature reliability, and rigidity. [Solution] A stacked electronic component according to one embodiment of the present invention includes a body containing a dielectric layer and internal electrodes arranged alternately with the dielectric layer, and external electrodes disposed on the body, wherein the dielectric layer includes a central portion separated from the internal electrodes and an interface portion disposed between the internal electrodes and the central portion containing Dy, Tb, and Gd, and the central portion may have a lower atomic percentage of Tb content than the interface portion, or may substantially contain no Tb.

Description

[Technical Field]

[0001] This invention relates to a stacked electronic component. [Background technology]

[0002] A multilayer ceramic capacitor (MLCC), a type of multilayer electronic component, is a chip-type capacitor that is mounted on the printed circuit boards of various electronic products such as liquid crystal displays (LCDs) and plasma display panels (PDPs), computers, smartphones, and mobile phones, and plays the role of charging or discharging electricity.

[0003] Multilayer ceramic capacitors offer the advantages of being small yet guaranteeing high capacitance and being easy to mount, making them suitable for use as components in various electronic devices. As computers, mobile devices, and other electronic equipment become smaller and more powerful, the demand for smaller and higher-capacitance multilayer ceramic capacitors is increasing.

[0004] Furthermore, as the operating environments for multilayer ceramic capacitors become more diverse, reliability at high temperatures is also required.

[0005] To achieve miniaturization and higher capacitance in multilayer ceramic capacitors, the thickness of the dielectric layer must be reduced and the number of layers increased. However, the thinner the dielectric layer, the higher the probability of physical defects, which can lead to a higher process failure rate and reduced reliability. Furthermore, while adding Tb to the dielectric layer makes it easier to ensure reliability in high-temperature environments, ceramic green sheets with added Tb have reduced rigidity, which can lead to a higher process failure rate and the occurrence of structural defects in the dielectric layer.

[0006] Therefore, there is a need to develop new multilayer ceramic capacitors with structures that can ensure high-temperature reliability while thinning the dielectric layer. [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] One of the various objectives of the present invention is to provide a highly reliable stacked electronic component.

[0008] One of the various objectives of the present invention is to provide a stacked electronic component with excellent high-temperature reliability.

[0009] One of the various objectives of the present invention is to provide a multilayer electronic component that includes a dielectric layer with excellent rigidity.

[0010] However, the objectives of the present invention are not limited to those described above and can be more easily understood in the process of describing specific embodiments of the present invention. [Means for solving the problem]

[0011] A stacked electronic component according to one embodiment of the present invention includes a body including a dielectric layer and internal electrodes arranged alternately with the dielectric layer, and external electrodes disposed on the body, wherein the dielectric layer includes a central portion separated from the internal electrodes and an interface portion disposed between the internal electrodes and the central portion, and the central portion may have a lower atomic percentage of Tb content or may substantially contain no Tb than the interface portion. [Effects of the Invention]

[0012] One of the various effects of the present invention is to improve the reliability of a multilayer electronic component by arranging Dy, Tb, and Gd at the interface of the dielectric layer and controlling the atomic percentage of Tb content at the interface to be higher than that at the center.

[0013] However, the diverse and significant advantages and effects of the present invention are not limited to the above-described content and can be more easily understood in the process of explaining the specific embodiments of the present invention.

Brief Description of the Drawings

[0014] [Figure 1] A perspective view of a multilayer electronic component according to an embodiment of the present invention is schematically shown. [Figure 2] Shown from FIG. 1 excluding the external electrodes. <00000​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​

[0015] Embodiments of the present invention will be described below with reference to specific embodiments and accompanying drawings. However, embodiments of the present invention can be modified into several other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, embodiments of the present invention are provided to give a more complete explanation of the present invention to a person of the ordinary skill. Accordingly, the shapes and sizes of elements in the drawings may be enlarged or reduced (or highlighted or simplified) for a clearer explanation, and elements indicated by the same reference numerals in the drawings are the same elements.

[0016] Furthermore, in order to clearly illustrate the present invention in the drawings, parts unrelated to the description have been omitted, and the size and thickness of each component shown are arbitrarily indicated for the convenience of explanation; therefore, the present invention is not necessarily limited by the illustrations. Also, components with the same function within the scope of the same concept are described using the same reference numerals. Moreover, throughout the specification, when a part "includes" a certain component, unless otherwise stated to the contrary, it does not mean that other components are excluded, but rather that other components may be further included.

[0017] In drawings, the X direction can be defined as the first direction, the lamination direction, or the thickness (T) direction; the Y direction as the second direction or the length (L) direction; and the Z direction as the third direction or the width (W) direction.

[0018] Multilayer electronic components Figure 1 is a schematic perspective view of a stacked electronic component according to one embodiment of the present invention; Figure 2 is shown from Figure 1 excluding the external electrodes; Figure 3 is shown from Figure 2 excluding the side margins; Figure 4 is a schematic cross-sectional view along the line I-I' in Figure 1; Figure 5 is a schematic cross-sectional view along the line II-II' in Figure 1; Figure 6 is an enlarged view of the K1 region in Figure 5; and Figure 7 is an enlarged view of the K2 region in Figure 5.

[0019] The following describes in detail a multilayer electronic component 100 according to one embodiment of the present invention with reference to Figures 1 to 7. While a multilayer ceramic capacitor (MLCC) will be described as an example of a multilayer electronic component, the present invention is not limited to this and can be applied to various multilayer electronic components using ceramic materials, such as inductors, piezoelectric elements, varistors, or thermistors.

[0020] A stacked electronic component 100 according to one embodiment of the present invention includes a body 110 including a dielectric layer 111 and internal electrodes 121 and 122 arranged alternately with the dielectric layer, and external electrodes 131 and 132 arranged on the body, wherein the dielectric layer 111 includes a central portion CP separated from the internal electrodes and interface portions IP1 and IP2 arranged between the internal electrodes and the central portion and containing Dy, Tb and Gd, and the central portion CP may have a lower atomic percentage of Tb content than the interface portions IP1 and IP2, or may substantially contain no Tb.

[0021] To achieve miniaturization and increased capacitance of multilayer ceramic capacitors, the thickness of the dielectric layer must be reduced and the number of layers increased. However, the thinner the dielectric layer, the higher the probability of physical defects, which can lead to a higher process failure rate and reduced reliability. Furthermore, while adding Tb to the dielectric layer ensures reliability in high-temperature environments and is easy, ceramic green sheets with added Tb have reduced rigidity, which can lead to a higher process failure rate and the occurrence of structural defects in the dielectric layer. Here, rigidity refers to the hard property of remaining unchanged in pattern and volume even when subjected to external pressure.

[0022] In one embodiment of the present invention, by arranging Dy, Tb, and Gd at the interfaces IP1 and IP2 of the dielectric layer 111, and controlling the atomic percentage of Tb content at the interfaces IP1 and IP2 to be higher than that at the central portion CP, it is possible to suppress the occurrence of physical and structural defects in the dielectric layer and improve the high-temperature reliability of the stacked electronic component 100.

[0023] The following describes the various components included in the stacked electronic component 100 according to one embodiment of the present invention.

[0024] The main body 110 may have dielectric layers 111 and internal electrodes 121 and 122 stacked alternately.

[0025] There are no particular restrictions on the specific shape of the main body 110, but as shown in the figure, the main body 110 can be hexahedral or a similar shape. Due to the shrinkage of the ceramic powder contained in the main body 110 during the firing process, the main body 110 is not a perfectly straight hexahedron, but can be substantially hexahedral.

[0026] The main body 110 may have a first surface 1 and a second surface 2 facing each other in a first direction, a third surface 3 and a fourth surface 4 connected to the first surface 1 and the second surface 2 and facing each other in a second direction, and a fifth surface 5 and a sixth surface 6 connected to the first surface 1 and the second surface 2 and connected to the third surface 3 and the fourth surface 4 and facing each other in a third direction.

[0027] As margin regions where internal electrodes 121 and 122 are not placed overlap the dielectric layer 111, steps are created due to the thickness of the internal electrodes 121 and 122, and the corners connecting the first surface with the third, fourth, and fifth surfaces and / or the corners connecting the second surface with the third, fourth, and fifth surfaces may have a shape that is contracted toward the center in the first direction of the main body 110 when viewed with reference to the first or second surface. Alternatively, due to the contraction behavior during the sintering process of the main body, the corners connecting the first surface 1 with the third surface 3, fourth surface 4, fifth surface 5, and sixth surface 6 and / or the corners connecting the second surface 2 with the third surface 3, fourth surface 4, fifth surface 5, and sixth surface 6 may have a shape that is contracted toward the center in the first direction of the main body 110 when viewed with reference to the first or second surface. Alternatively, in order to prevent chipping defects, the corners connecting each face of the main body 110 can be rounded by performing a separate process to round the corners connecting the first face with the third, fourth, fifth, and sixth faces, and / or the corners connecting the second face with the third, fourth, fifth, and sixth faces.

[0028] On the other hand, in order to suppress the step difference caused by the internal electrodes 121 and 122, if the internal electrodes after lamination are cut so that they are exposed on the fifth surface 5 and sixth surface 6 of the main body, and then a single dielectric layer or two or more dielectric layers are laminated on both sides of the capacitance forming portion Ac in the third direction (width direction) to form side margin portions 114 and 115, the portions connecting the first surface with the fifth and sixth surfaces, and the portions connecting the second surface with the fifth and sixth surfaces, may not have a contracted form.

[0029] The multiple dielectric layers 111 forming the main body 110 are in a fired state, and the boundaries between adjacent dielectric layers 111 can be integrated to such an extent that they are difficult to confirm without using a scanning electron microscope (SEM). There is no particular limit to the number of dielectric layers stacked, and it can be determined considering the size of the multilayer electronic component. For example, the main body can be formed by stacking 400 or more dielectric layers.

[0030] Dy, Tb, and Gd may be placed at the interfaces IP1 and IP2 of the dielectric layer 111. Generally, a certain amount of rare earth elements is added to the dielectric layer to improve reliability. On the other hand, the interfaces IP1 and IP2 located at the interface with the internal electrodes 121 and 122 have the greatest influence on the reliability of the multilayer electronic component, more so than the central part CP of the dielectric layer 111. Therefore, in this invention, Dy, Tb, and Gd are placed at the interfaces IP1 and IP2 of the dielectric layer 111 to effectively improve withstand voltage and reliability.

[0031] Furthermore, by controlling the atomic percentage of Tb content in the interface IP1 and IP2 to be higher than that of the central CP, the occurrence of physical and structural defects in the dielectric layer can be suppressed, thereby improving the high-temperature reliability of the stacked electronic component 100. If the Tb content of the central CP is high, the rigidity of the dielectric layer 111 decreases, making it prone to cracking and potentially leading to structural defects in the dielectric layer.

[0032] Furthermore, by arranging Dy, Tb, and Gd at the interfaces IP1 and IP2 of the dielectric layer 111, breakage and unevenness phenomena of the internal electrodes can be suppressed, thereby improving the reliability and capacitance per unit volume of the multilayer electronic component.

[0033] In one embodiment, the dielectric layer 111 may have a total content of Dy, Tb, and Gd of 1.5 moles or less per 100 moles of Ti. This allows the TCC temperature characteristics (X6S) to be satisfied while improving the dielectric strength.

[0034] If the total content of Dy, Tb, and Gd in the dielectric layer 111 exceeds 1.5 moles per 100 moles of Ti, the Curie temperature Tc may move to room temperature while failing to satisfy the X6S temperature characteristics.

[0035] In one embodiment, the dielectric layer 111 may have a Tb content of 0.5 moles or less per 100 moles of Ti. If the Tb content in the dielectric layer 111 exceeds 0.5 moles per 100 moles of Ti, the rigidity of the dielectric layer 111 decreases, making it prone to cracking and potentially leading to structural defects in the dielectric layer.

[0036] The lower limit of the Tb content in the dielectric layer 111 is not particularly limited. For example, the lower limit of the Tb content in the dielectric layer 111 can be 0.2 moles or more per 100 moles of Ti. This can further improve the reliability of the multilayer electronic component 100.

[0037] In one embodiment, the molar ratio of the Gd content to the total Dy and Tb content of the dielectric layer 111 may be 0.2 to 0.67. This can significantly improve the reliability effect of Gd addition.

[0038] If the molar ratio of Gd content to the total Dy and Tb content is less than 0.2, the reliability improvement effect of Gd addition may be insufficient, and if it exceeds 0.67, the dielectric layer may become excessively n-type, degrading the product characteristics.

[0039] On the other hand, the lower limit of the molar ratio of the Gd content to the total Dy and Tb content is preferably 0.2 or higher, and more preferably 0.200 or higher.

[0040] On the other hand, there are no particular limitations on the lower limits of the Dy content and Tb content. For example, the dielectric layer 111 may have a Dy content of 0.2 moles or more per 100 moles of Ti, and a Tb content of 0.2 moles or more per 100 moles of Ti.

[0041] In one embodiment, when At1 is the atomic percentage of Tb content in the interface IP1 and IP2, and At2 is the atomic percentage of Tb content in the central part CP, At1 / At2 may be 5 or more.

[0042] It is preferable that Tb is concentrated in the interface IP1 and IP2 of the dielectric layer to improve reliability, and is not placed in the central part CP as much as possible to suppress a decrease in the rigidity of the dielectric layer 111.

[0043] In this case, the atomic percentage At1 of the Tb content in the interface IP1 and IP2 is preferably 0.2 at% or more and 0.5 at% or less, and the atomic percentage At2 of the Tb content in the central CP is preferably 0.1 at% or less.

[0044] On the other hand, the component analysis of the dielectric layer 110 may be performed by measuring from image images obtained by observing the cross-sections of the main body 110 in the first and second directions using SEM-EDS (Scanning Electron Microscope-Energy Dispersive X-ray Spectrometer), TEM-EDS (Transmission Electron Microscope-Energy Dispersive X-ray Spectrometer), STEM-EDS (Scanning Transmission Electron Microscope-Energy Dispersive X-ray Spectrometer), or FE-SEM-EDS (Field Emission-scanning Electron Microscope-Energy Dispersive X-ray Spectrometer).

[0045] More specifically, the multilayer electronic component 100 is polished up to the halfway point in the third direction to expose the cross-sections of the multilayer electronic component 100 in the first and second directions. After this, the content (mol%) of Ti, Dy, Tb, and Gd in the dielectric layer located in the center of the first direction of the capacitance forming section Ac is measured using FE-SEM-EDS (acceleration voltage: 2kV, magnification: 50,000x). This allows the number of moles of Dy, Tb, and Gd per 100 moles of Ti contained in the dielectric layer to be calculated. On the other hand, by selecting 10 dielectric layers located in the upper, central, and lower parts of the first direction of the capacitance forming section Ac, and calculating the number of moles of Dy, Tb, and Gd per 100 moles of Ti for a total of 30 dielectric layers, the average value of these values ​​can be calculated to further generalize the results.

[0046] On the other hand, the interface IP and central CP of the dielectric layer 111 can be distinguished based on the concentration of each element, and can be distinguished based on the Tb content. Subsequently, the atomic percentage of the Tb content measured at the center of the interface IP in the first direction can be defined as At1, and the atomic percentage of the Tb content measured at the center of the central CP in the first direction can be defined as At2. On the other hand, by selecting 10 dielectric layers located at the top, center, and bottom of the capacitance forming part Ac in the first direction, and determining At1 and At2 for a total of 30 dielectric layers, the average value of these values ​​can be calculated to further generalize the results.

[0047] In one embodiment, the average thickness tdi of the interface may be between 10 nm and 50 nm.

[0048] If the average interface thickness tdi is less than 10 nm, the reliability improvement effect of the interface may be insufficient, and if it exceeds 50 nm, the dielectric layer may become too thick.

[0049] On the other hand, the average thickness tdi of the interface can refer to the respective thicknesses of the first interface IP1 and the second interface IP2. That is, the average thickness of the first interface IP1 can be 10 nm or more and 50 nm or less, and the average thickness of the second interface IP2 can be 10 nm or more and 50 nm or less.

[0050] In one embodiment, the average thickness tdc of the central CP can be 500 nm or less. This makes it easy to thin the dielectric layer 111 and achieve miniaturization and high capacitance of the multilayer electronic component.

[0051] In one embodiment, when the average thickness of the central portion is td and the average thickness of the interface portion is tcl, tcl / td can be 0.02 or more and 0.1 or less.

[0052] On the other hand, the average thickness td of the dielectric layer 111 does not need to be particularly limited. For example, the dielectric layer 111 placed between the internal electrodes 121 and 122 includes a central portion CP, a first interface portion IP1, and a second interface portion IP2, so it may be 600 nm or less.

[0053] Here, the average thickness tdi of the interface and the average thickness tdc of the central part can refer to the thickness in the first direction. The average thickness tdi of the interface and the average thickness tdc of the central part can be measured by scanning the cross-sections of the main body 110 in the first and second directions with a scanning electron microscope (SEM) at 10,000x magnification. More specifically, after dividing the interface containing Dy, Tb, and Gd using SEM-EDS, the thickness of the interface IP1 and the central part CP can be measured at 30 equally spaced points in the second direction, and their respective average values ​​can be measured. The above 30 equally spaced points can be specified by the capacitance forming section Ac described later. Furthermore, by extending such average value measurement to 10 dielectric layers 111 and measuring the average values, the average thickness tdi of the interface and the average thickness tdc of the central part can be further generalized.

[0054] The method for forming the dielectric layer 111 is not particularly limited.

[0055] For example, first, a sol solution containing Tb, Dy, and Gd is coated onto a carrier film 300 to form a first coating layer PIP1. Then, a ceramic slurry containing ceramic powder, an organic solvent, and a binder is applied onto the first coating layer PIP1 to form a ceramic portion PCP. After that, a ceramic green sheet is provided on which a sol solution containing Tb, Dy, and Gd is coated onto the ceramic portion PCP to form a second coating layer PIP2, and then the ceramic green sheet is sintered to form the central portion CP. During the sintering process, Tb, Dy, and Gd contained in the first coating layer PIP1 and the second coating layer PIP2 can react with a portion of the ceramic portion PCP to form interfaces IP1 and IP2, and the remaining area excluding interfaces IP1 and IP2 can become the central portion CP.

[0056] When forming a ceramic green sheet in an ultrathin layer, structural defects such as increased surface roughness and uneven thickness of the ceramic green sheet may occur. By forming a first coating layer PIP1 and a second coating layer PIP2 on both sides of the ceramic part CPC according to one embodiment of the present invention, structural defects of the ceramic green sheet can be compensated for, and reliability can be improved.

[0057] Furthermore, when Tb, Dy, and Gd are directly mixed into a ceramic slurry containing ceramic powder, an organic solvent, and a binder, and this slurry is used to manufacture a ceramic green sheet, the rigidity of the ceramic green sheet increases, potentially leading to a higher process defect rate or the occurrence of structural defects in the dielectric layer.

[0058] When a first coating layer PIP1 and a second coating layer PIP2 are formed on both sides of the ceramic portion CPC according to one embodiment of the present invention, structural defects in the ceramic green sheet can be compensated for, and reliability can be improved.

[0059] The ceramic powder contained in the ceramic green sheet is not particularly limited as long as sufficient capacitance can be obtained. For example, barium titanate-based (BaTiO3) powder can be used as the ceramic powder. More specifically, examples of the ceramic powder include BaTiO3, (Ba 1-x Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1), and Ba(Ti 1-y Zr y )O3 (0 < y < 1), and one or more of them may be used.

[0060] Therefore, in one embodiment, the dielectric layer 111 can contain, as a main component, one or more of BaTiO3, (Ba 1-x Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1), and Ba(Ti 1-y Zr y )O3 (0 < y < 1). Here, the meaning of the main component can be that the number of moles of the components other than the main component with respect to 100 moles of the main component is 30 moles or less.

[0061] The main body 110 includes a capacitance forming portion Ac that is disposed inside the main body 110 and in which a capacitance is formed by including a first internal electrode 121 and a second internal electrode 122 that are disposed so as to face each other with the dielectric layer 111 interposed therebetween, and cover portions 112 and 113 formed on the upper and lower portions in the first direction of the capacitance forming portion Ac.

[0062] Furthermore, the capacitance-forming portion Ac can be formed by repeatedly stacking multiple first internal electrodes 121 and second internal electrodes 122 with a dielectric layer 111 in between, as a portion that contributes to the capacitance formation of the capacitor.

[0063] The cover portions 112 and 113 may include an upper cover portion 112 positioned above the volume-forming portion Ac in the first direction and a lower cover portion 113 positioned below the volume-forming portion Ac in the first direction.

[0064] The upper cover portion 112 and the lower cover portion 113 described above can be formed by stacking a single dielectric layer or two or more dielectric layers in the thickness direction on the upper and lower surfaces of the capacitance forming portion Ac, respectively, and can essentially serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0065] The upper cover portion 112 and the lower cover portion 113 described above do not include internal electrodes and may contain the same material as the dielectric layer 111.

[0066] In other words, the upper cover portion 112 and the lower cover portion 113 may include a ceramic material, for example, a barium titanate (BaTiO3) based ceramic material.

[0067] On the other hand, the thickness of the cover portions 112 and 113 is not particularly limited. However, in order to more easily achieve miniaturization and high capacitance of the stacked electronic component, the thickness tc of the cover portions 112 and 113 may be 15 μm or less.

[0068] The average thickness tc of the cover portions 112 and 113 can represent the size in the first direction, and may be the average value of the sizes of the cover portions 112 and 113 in the first direction measured at five equally spaced points on the upper or lower part of the volume forming portion Ac.

[0069] Furthermore, margin portions 114 and 115 can be arranged on the side surface of the volume-forming portion Ac.

[0070] The margin portions 114 and 115 may include a first margin portion 114 located on the fifth surface 5 of the main body 110 and a second margin portion 115 located on the sixth surface 6. That is, the margin portions 114 and 115 can be located on both end surfaces in the width direction of the ceramic main body 110.

[0071] As shown in Figure 5, the margin portions 114 and 115 can refer to the regions between the interface between both ends of the first internal electrode 121 and the second internal electrode 122 and the body 110 in a cross-section obtained by cutting the body 110 in the width-thickness (WT) direction.

[0072] The margins 114 and 115 can essentially serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0073] The margin portions 114 and 115 may be formed by applying conductive paste to the ceramic green sheet, except where the margin portions are formed, to form internal electrodes.

[0074] Furthermore, in order to suppress the step caused by the internal electrodes 121 and 122, after cutting the laminated internal electrodes so that they are exposed on the fifth and sixth surfaces 5 and 6 of the main body, a single dielectric layer or two or more dielectric layers can be laminated in the third direction (width direction) on both sides of the capacitance forming portion Ac to form margin portions 114 and 115.

[0075] On the other hand, the width of the margin portions 114 and 115 does not need to be particularly limited. However, in order to more easily achieve miniaturization and high capacitance of the multilayer electronic component, the average width of the margin portions 114 and 115 may be 15 μm or less.

[0076] The average width of the margin portions 114 and 115 can represent the average size MW1 in the third direction of the region where the internal electrode is separated from the fifth surface and the average size MW2 in the third direction of the region where the internal electrode is separated from the sixth surface, and can be the average value of the sizes of the margin portions 114 and 115 in the third direction measured at five equally spaced points on the side surface of the capacitance forming portion Ac.

[0077] Therefore, in one embodiment, the average size MW1 and MW2 in the third direction of the region where the internal electrodes 121 and 122 are separated from the fifth and sixth surfaces may be 15 μm or less, respectively.

[0078] In one embodiment, the dielectric layer 111 and internal electrodes 121 and 122 are arranged alternately in a first direction, the main body 110 includes a first surface 1 and a second surface 2 facing in the first direction, a third surface 3 and a fourth surface 4 connected to the first and second surfaces and facing in a second direction, and a fifth surface 5 and a sixth surface 6 connected to the first, second, third and fourth surfaces and facing in a third direction, the external electrodes 131 and 132 are arranged on the third surface 3 and the fourth surface 4, and side margin portions 114 and 115 can be arranged on the fifth and sixth surfaces.

[0079] At this time, the interface portions IP1, IP2 and the central portion CP can be extended to the third surface 3 and the fourth surface 4 and connected to the external electrodes 131 and 132, and can be extended to the fifth surface and the sixth surface and connected to the side margin portions 114 and 115.

[0080] Referring to Figure 7, in order to suppress the step caused by the internal electrodes 121 and 122, if the internal electrodes 121 and 122 are cut so that they are exposed on the fifth and sixth surfaces 5 and 6 of the main body, and then a single dielectric layer or two or more dielectric layers are stacked in the third direction (width direction) on both sides of the capacitance forming portion Ac to form margin portions 114 and 115, then interface portions IP1 and IP2 may not be placed in the margin portions 114 and 115.

[0081] The method of forming margin portions 114 and 115 by laminating a single dielectric layer or two or more dielectric layers in a third direction (width direction) on both sides of the capacitance forming portion Ac is generally applied to miniaturized and high-capacitance models, and the reliability improvement effect of the present invention may become more pronounced. In particular, since the internal electrodes 121 and 122 must be cut so that they are exposed on the fifth surface 5 and sixth surface 6 of the main body, if the rigidity of the ceramic green sheet for the capacitance forming portion deteriorates, there is a high risk of a high process failure rate or structural defects occurring in the dielectric layer. Therefore, according to one embodiment of the present invention, since the rigidity of the dielectric layer can be ensured, even when forming margin portions 114 and 115 by laminating a single dielectric layer or two or more dielectric layers in a third direction (width direction) on both sides of the capacitance forming portion Ac, it is possible to suppress a high process failure rate or the occurrence of structural defects in the dielectric layer.

[0082] The internal electrodes 121 and 122 may include a first internal electrode 121 and a second internal electrode 122. The first internal electrode 121 and the second internal electrode 122 are arranged alternately so as to face each other across the dielectric layer 111 that constitutes the main body 110, and can be exposed on the third surface 3 and the fourth surface 4 of the main body 110, respectively.

[0083] The first internal electrode 121 is separated from the fourth surface 4 and exposed via the third surface 3, and the second internal electrode 122 can be separated from the third surface 3 and exposed via the fourth surface 4. The first external electrode 131 is positioned on the third surface 3 of the main body and connected to the first internal electrode 121, and the second external electrode 132 is positioned on the fourth surface 4 of the main body and connected to the second internal electrode 122.

[0084] In other words, the first internal electrode 121 is not connected to the second external electrode 132, but is connected to the first external electrode 131, and the second internal electrode 122 is not connected to the first external electrode 131, but is connected to the second external electrode 132. Therefore, the first internal electrode 121 can be formed at a certain distance from the fourth surface 4, and the second internal electrode 122 can be formed at a certain distance from the third surface 3. Furthermore, the first internal electrode 121 and the second internal electrode 122 may be arranged at a distance from the fifth and sixth surfaces of the main body 110.

[0085] The conductive metals contained in the internal electrodes 121 and 122 may be one or more of Ni, Cu, Pd, Ag, Au, Pt, In, Sn, Al, W, Ti, and alloys thereof, but the present invention is not limited thereto.

[0086] The average thickness te of the internal electrodes does not need to be particularly limited. Here, the thickness of internal electrodes 121 and 122 can be said to represent the size of internal electrodes 121 and 122 in the first direction.

[0087] However, in order to more easily achieve miniaturization and high capacitance of the multilayer electronic component, the average thickness of the internal electrodes 121 and 122 may be 0.4 μm or less.

[0088] Here, the average thickness te of the internal electrodes can be measured by scanning the cross-sections of the main body 110 in the first and second directions with a scanning electron microscope (SEM) at 10,000x magnification. More specifically, the thickness of one internal electrode 121, 122 can be measured at multiple points, for example, 30 points equally spaced in the second direction, and the average value can be measured. The 30 equally spaced points can be specified in the capacitance forming section Ac. Furthermore, by extending this average value measurement to 10 internal electrodes 121, 122 and measuring the average value, the average thickness of the internal electrodes 121, 122 can be further generalized.

[0089] External electrodes 131 and 132 can be arranged on the third surface 3 and fourth surface 4 of the main body 110.

[0090] The external electrodes 131 and 132 may include a first external electrode 131 and a second external electrode 132, which are arranged on the third surface 3 and fourth surface 4 of the main body 110, respectively, and connected to a first internal electrode 121 and a second internal electrode 122, respectively.

[0091] Referring to Figure 1, the external electrodes 131 and 132 can be positioned to cover both end faces of the side margin portions 114 and 115 in the second direction.

[0092] In this embodiment, a structure in which the stacked electronic component 100 has two external electrodes 131 and 132 is described, but the number and shape of the external electrodes 131 and 132 can be changed depending on the form of the internal electrodes 121 and 122 and other purposes.

[0093] On the other hand, the external electrodes 131 and 132 can be formed using any material that has electrical conductivity, such as metal, and the specific material can be determined by considering electrical properties, structural stability, etc. Furthermore, they can have a multilayer structure.

[0094] For example, the external electrodes 131 and 132 may include electrode layers 131a and 132a placed on the main body 110, and plating layers 131b and 132b formed on the electrode layers 131a and 132a.

[0095] To give a more specific example for the electrode layers 131a and 132a, the electrode layers 131a and 132a may be firing electrodes containing a conductive metal and glass, or resin-based electrodes containing a conductive metal and resin.

[0096] Furthermore, the electrode layers 131a and 132a may be formed in a manner in which a fired electrode and a resin-based electrode are sequentially formed on the main body. Alternatively, the electrode layers 131a and 132a may be formed by transferring a sheet containing a conductive metal onto the main body, or by transferring a sheet containing a conductive metal onto the fired electrode.

[0097] Any material with excellent electrical conductivity can be used as the conductive metal contained in the electrode layers 131a and 132a, but there are no particular limitations. For example, the conductive metal may be one or more of nickel (Ni), copper (Cu), and their alloys.

[0098] The plating layers 131b and 132b play a role in improving mounting characteristics. The types of plating layers 131b and 132b are not particularly limited and can be plating layers containing one or more of Ni, Sn, Pd, and their alloys, and can be formed in multiple layers.

[0099] To give a more specific example for the plating layers 131b and 132b, the plating layers 131b and 132b may be Ni plating layers or Sn plating layers, and may be in a form in which Ni plating layers and Sn plating layers are formed sequentially on the electrode layers 131a and 132a, or may be in a form in which Sn plating layers, Ni plating layers and Sn plating layers are formed sequentially. Furthermore, the plating layers 131b and 132b may include multiple Ni plating layers and / or multiple Sn plating layers.

[0100] The size of the stacked electronic component 100 does not need to be particularly limited.

[0101] However, according to one embodiment of the present invention, since the internal electrodes and dielectric layers can be easily thinned, the reliability and capacity improvement effects per unit volume according to the present invention can be more pronounced in a stacked electronic component 100 having a size of 0603 (length × width, 0.6 mm × 0.3 mm) or less. Furthermore, the structure of the present invention can also be applied to a stacked electronic component 100 having a size of 0201 (length × width, 0.2 mm × 0.1 mm) or less.

[0102] Considering manufacturing tolerances, the size of external electrodes, etc., the reliability and capacity improvement effects per unit volume according to the present invention may become more pronounced when the length of the stacked electronic component 100 is 0.66 mm or less and the width is 0.33 mm or less. Here, the length of the stacked electronic component 100 can mean the maximum size of the stacked electronic component 100 in the second direction, and the width of the stacked electronic component 100 can mean the maximum size of the stacked electronic component 100 in the third direction.

[0103] Manufacturing method for multilayer electronic components The following describes an example of a method for manufacturing a stacked electronic component 100 according to one embodiment of the present invention. However, the method for manufacturing the stacked electronic component 100 of the present invention is not limited thereto.

[0104] Figure 8 is a diagram illustrating the process of manufacturing a ceramic green sheet for a capacitance forming section used in a method for manufacturing a stacked electronic component according to one embodiment of the present invention.

[0105] First, a sol solution containing Tb, Dy, and Gd is coated onto a carrier film 300 to form a first coating layer PIP1. Then, a ceramic slurry containing ceramic powder, an organic solvent, and a binder is applied onto the first coating layer PIP1 to form a ceramic portion PCP. After that, a sol solution containing Tb, Dy, and Gd is coated onto the ceramic portion PCP to form a second coating layer PIP2.

[0106] Subsequently, an internal electrode pattern EP can be formed by printing a conductive paste for internal electrodes containing metal powder, binder, organic solvent, etc., to a predetermined thickness on the second coating layer PIP2 using a screen printing method or gravure printing method, thereby producing a ceramic green sheet AGS for the capacitance forming section.

[0107] Figure 9 is a diagram illustrating the process of forming a laminate in a manufacturing method for a stacked electronic component according to one embodiment of the present invention.

[0108] A laminate can be obtained by stacking ceramic green sheets (AGS) for volume formation in the X direction. In this case, general ceramic green sheets can be stacked on the upper and lower parts of the laminate to form cover parts 112 and 113 after sintering. Here, a general ceramic green sheet can mean a ceramic green sheet composed of ceramic PCP without the first coating layer PIP1 and second coating layer PIP2 described above.

[0109] Next, the laminate is cut to have a predetermined chip size. At this time, the ends of the internal electrode pattern are exposed on both sides of the cut chip facing the third direction.

[0110] Next, the margin-forming sheet can be attached to both sides of the cut chip in the third direction, and then fired to form the main body 110 and the side margin portions 114 and 115. The firing temperature may be, for example, 1000°C or more and 1400°C or less, but the present invention is not limited thereto.

[0111] The sheet used for forming the margin area is not particularly limited, and the general ceramic green sheet described above can be used.

[0112] Next, external electrodes 131 and 132 are formed. For example, if the base electrode layers 131a and 132a include a fired electrode layer, the main body 110 can be dipped in a conductive paste for external electrodes containing metal powder, glass frit, binder, and organic solvent, and then the conductive paste for external electrodes can be fired at a temperature of 500°C to 900°C to form a fired electrode layer.

[0113] For example, if the base electrode layers 131a and 132a include a resin electrode layer, the main body can be dipped in a conductive resin composition containing metal powder, resin, binder, and organic solvent, and then cured at a temperature of 250°C to 550°C to form the resin electrode layer.

[0114] Furthermore, electroplating and / or electroless plating may be performed to form plating layers 131b and 132b on the underlying electrode layers 131a and 132a.

[0115] (Example of experiment) Using the manufacturing method described above, we prepared sample chips of size 0603 (length: approximately 0.6 mm, width: approximately 0.3 mm, thickness: approximately 0.3 mm).

[0116] Without adding Tb, Dy, and Gd to the ceramic PCP portion, Tb, Dy, and Gd were added only to the sol solution for forming the coating layers PIP1 and PIP2, and the number of moles of Tb, Dy, and Gd per 100 moles of Ti contained in the dielectric layer 111 was adjusted to satisfy Tables 1 and 3 below.

[0117] The number of moles of Tb, Dy, and Gd relative to 100 moles of Ti contained in the dielectric layer 111 was measured by analyzing the cross-sections in the first and second directions of the sample chip, which had been polished to the halfway point in the third direction, using FE-SEM-EDS (acceleration voltage: 2kV, magnification: 50,000x).

[0118] Furthermore, the temperature characteristics of test numbers 1, 2, and 3 were experimentally examined and are shown in Table 2 below. In Table 2, the percentage change in capacity (%) from -55°C to 105°C is listed, with the capacity at 25°C being used as the baseline for each test number sample chip.

[0119] To meet the temperature characteristics of the X6S, the capacitance change rate (%) between -55°C and 105°C must be ±22% or less.

[0120] [Table 1]

[0121] [Table 2]

[0122] To meet the temperature characteristics of the X6S, the capacitance change rate (%) between -55°C and 105°C must be ±22% or less.

[0123] Referring to Tables 1 and 2 above, it can be confirmed that in test number 1, where Dy+Tb+Gd is 1.5 moles, the X6S temperature characteristics were satisfied, but in test numbers 2 and 3, where Dy+Tb+Gd exceeds 1.5 moles, the X6S temperature characteristics were not satisfied.

[0124] [Table 3]

[0125] Figures 10, 11, and 12 are graphs showing the results of ultra-accelerated lifetime evaluation (HALT) for 40 sample chips each from test numbers 4, 5, and 6. In Figures 10 to 12, the X-axis represents time in units of hr, and the Y-axis represents insulation resistance (IR) in units of ohms.

[0126] HALT evaluation was performed for 24 hours under temperature conditions of 125°C and voltage conditions of 1.5Vr, and a failure was evaluated if a short circuit occurred in the insulation resistance (IR) value.

[0127] Test No. 5 confirms excellent high-temperature lifespan because the molar ratio of Gd content to the total Dy and Tb content is between 0.2 and 0.67. On the other hand, test No. 4 and test No. 6, where the molar ratio of Gd content to the total Dy and Tb content is less than 0.2 and greater than 0.67, confirm that the high-temperature lifespan has deteriorated.

[0128] Figure 13 is a graph showing the measured breakdown voltage (BDV) for 20 sample chips from test numbers 4, 5, and 6.

[0129] The breakdown voltage was determined by preparing 20 sample chips for each test number, increasing the voltage at a rate of 50 V / sec at 25°C, and the voltage at which a short circuit occurred in the sample chip is shown as BDV in Figure 13.

[0130] Test No. 5 satisfies the requirement that the molar ratio of Gd content to the total Dy and Tb content be between 0.2 and 0.67, and it can be confirmed that the BDV average and spraying are improved compared to Test No. 4, where the molar ratio of Gd content to the total Dy and Tb content is less than 0.2, and Test No. 6, where it is greater than 0.67.

[0131] Although embodiments of the present invention have been described in detail above, the present invention is not limited by the embodiments described above and the accompanying drawings, but is limited by the claims provided. Therefore, within the scope of the technical idea of ​​the present invention as described in the claims, various forms of substitution, modification, and alteration are possible by persons with ordinary skill in the art, and these also fall within the scope of the present invention.

[0132] Furthermore, the expression "one embodiment" as used in this disclosure does not mean that each embodiment is identical to the others, but is provided to highlight and describe the unique and distinct features of each embodiment. However, the present embodiments are not excluded from being realized in combination with features of other embodiments. For example, even if a matter described in one embodiment is not described in another embodiment, it can be understood as a description related to the other embodiment, unless there is a description in the other embodiment that contradicts or is inconsistent with that matter.

[0133] The terms used in this disclosure are used solely to describe one embodiment and are not intended to limit the disclosure. Where otherwise, singular expressions include plural expressions unless the context clearly indicates otherwise. [Explanation of symbols]

[0134] 100 Stacked Electronic Components 110 Main Unit 111 Dielectric layer IP1, IP2 interface part CP center 112, 113 Cover section 114, 115 Margin section 121, 122 Internal electrode 131, 132 External electrode 131a, 132a electrode layer 131b, 132b Plating layer

Claims

1. A body including a dielectric layer and internal electrodes arranged alternately with the dielectric layer, The body includes an external electrode disposed on the main body, The dielectric layer includes a central portion separated from the internal electrode and an interface portion disposed between the internal electrode and the central portion, which includes Dy, Tb, and Gd. A multilayer electronic component wherein the central portion has a lower atomic percentage of Tb content than the interface portion, or substantially contains no Tb.

2. The laminated electronic component according to claim 1, wherein the dielectric layer has a total content of Dy, Tb, and Gd of 1.5 moles or less per 100 moles of Ti.

3. The laminated electronic component according to claim 1, wherein the dielectric layer has a Tb content of 0.5 moles or less per 100 moles of Ti.

4. The laminated electronic component according to claim 1, wherein the dielectric layer has a molar ratio of Gd content to the total content of Dy and Tb of 0.2 or more and 0.67 or less.

5. The dielectric layer has a Tb content of 0.5 moles or less per 100 moles of Ti. The total content of Dy, Tb, and Gd is 1.5 moles or less per 100 moles of Ti. The multilayer electronic component according to claim 1, wherein the molar ratio of the Gd content to the total Dy and Tb content is 0.2 or more and 0.67 or less.

6. The stacked electronic component according to claim 1, wherein At1 is the atomic percentage of the Tb content in the interface and At2 is the atomic percentage of the Tb content in the central part, and At1 / At2 is 5 or more.

7. The stacked electronic component according to claim 1, wherein At1 is the atomic percentage of the Tb content in the interface, and At2 is the atomic percentage of the Tb content in the central part, and At1 is 0.2 at% or more and 0.5 at% or less, and At2 is 0.1 at% or less.

8. The multilayer electronic component according to claim 1, wherein the average thickness of the interface portion is 5 nm or more and 50 nm or less.

9. The stacked electronic component according to claim 1, wherein the average thickness of the central portion is 500 nm or less.

10. The laminated electronic component according to claim 1, wherein when the average thickness of the central portion is td and the average thickness of the interface portion is tcl, tcl / td is 0.02 or more and 0.1 or less.

11. The dielectric layer is BaTiO ３ , (Ba １－ｘ Ca ｘ )TiO ３ (0 < x < 1), Ba(Ti １－ｙ Ca ｙ )O ３ (0 < y < 1), (Ba １－ｘ Ca ｘ )(Ti １－ｙ Zr ｙ )O ３ (0 < x < 1, 0 < y < 1) and Ba(Ti １－ｙ Zr ｙ )O ３ (0 < y < 1), and contains one or more of them as main components. The multilayer electronic component according to claim 1.

12. The dielectric layer and the internal electrode are arranged alternately in the first direction. The main body includes a first and second surface facing the first direction, a third and fourth surface connected to the first and second surfaces and facing the second direction, and a fifth and sixth surface connected to the first, second, third and fourth surfaces and facing the third direction. The external electrodes are arranged on the third and fourth surfaces, The stacked electronic component according to any one of claims 1 to 11, wherein side margins are arranged on the fifth and sixth surfaces.

13. The interface portion and the central portion are extended to the third and fourth surfaces and connected to the external electrodes. The stacked electronic component according to claim 12, wherein extensions are drawn out to the fifth and sixth surfaces and connected to the side margin portion.

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