Memory system

Abstract

This ensures that the command bus is used efficiently while ensuring that refresh or precharge commands are issued at the appropriate time. [Solution] In memory systems 100 and 100a, the memory controller issues a command to the semiconductor memory device that includes an extended flag field F3 and a bank address field F2, which specify whether to precharge one, all, or two banks belonging to different bank groups, and the relative processing timing of the second bank to the first bank in the case of two banks. In the case of two banks, the semiconductor memory device precharges the first bank determined by the bank address field, and precharges the second bank, whose bank address is obtained by inverting the inverting target bit in the bank address field, at the relative processing timing.

Description

Technical Field

[0003]

[0001] The present disclosure relates to a memory system.

Background Art

[0002] As semiconductor memory devices, DDR4 and LPDDR5 having a plurality of bank groups may be used. In such semiconductor memory devices, when continuously issuing active commands to two banks belonging to different bank groups, the interval that must be provided between the issuances of the two active commands can be shortened (Non-Patent Document 1, Non-Patent Document 2). For this reason, active commands and read / write commands can be continuously issued without creating idle cycles on the command bus.

Prior Art Documents

Non-Patent Documents

[0003]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, if active commands and read / write commands are issued continuously, the available cycles on the command bus for issuing refresh or precharge commands are reduced. Delaying the issuance of active commands and read / write commands to issue refresh or precharge commands results in a decrease in the data access performance of the semiconductor memory device. Therefore, a technology is needed that allows for efficient use of the command bus while ensuring the timing for issuing refresh or precharge commands. [Means for solving the problem]

[0005] As one embodiment of this disclosure, a memory system (100, 100a) is provided, comprising a semiconductor memory device (120) having a plurality of bank groups (BG0 to BG3), and a memory controller (110) that issues commands in response to access requests from an arithmetic unit (200) accessing the semiconductor memory device. In this memory system, the memory controller issues a command to the semiconductor memory device as a precharge command, which includes an extended flag field (F3), a bit sequence that specifies one of the following: to precharge one bank, to precharge all banks, or to precharge two banks belonging to different bank groups, and the second relative processing timing with respect to the first bank when two banks are precharged, and a bank address field (F2), a bit sequence that defines the bank address of the bank to be precharged. When the semiconductor memory device is specified by the precharge command to precharge two banks, it performs precharging on the first bank determined by the bank address field, and then performs precharging on the second bank determined by the bank address obtained by inverting a predetermined single bit, which is the inversion target bit, in the bit sequence that defines the bank group in the bank address field, at the relative processing timing specified by the extended flag field.

[0006] With this type of memory system, if a precharge command specifies that two banks should be precharged, a single precharge command can precharge both the first and second banks. This reduces the number of precharge commands that need to be issued, freeing up space on the command bus. As a result, the command bus can be used efficiently while ensuring the timing for issuing precharge commands is secured.

[0007] In another form of the present disclosure, a memory system (100, 100a) is provided, comprising a semiconductor memory device (120) having a plurality of bank groups (BG0 to BG3), and a memory controller (110) that issues commands in response to access requests from an arithmetic unit (200) accessing the semiconductor memory device. In this memory system, the memory controller issues a refresh command to the semiconductor memory device, which includes an extended flag field (F3) which is a bit sequence that specifies either to refresh all banks or to refresh two banks belonging to different bank groups, and the second relative processing timing with respect to the first bank when two banks are refreshed, and a bank address field which is a bit sequence that defines the bank address of the bank to be refreshed. When the semiconductor memory device is specified by the refresh command to refresh two banks, it performs a refresh on the first bank determined by the bank address field, and then performs a refresh on the second bank determined by the bank address obtained by inverting a predetermined single bit, which is the inversion target bit, in the bit sequence that defines the bank group in the bank address field, at the relative processing timing specified by the extended flag field.

[0008] With this type of memory system, if a refresh command specifies that two banks should be refreshed, a single refresh command can refresh both the first and second banks. This reduces the number of refresh commands that need to be issued, freeing up space on the command bus. This allows for efficient use of the command bus while ensuring the timing for issuing refresh commands is sufficient. [Brief explanation of the drawing]

[0009] [Figure 1]This block diagram shows a schematic configuration of a memory system as one embodiment of the present disclosure. [Figure 2] This is a flowchart showing the pre-charge procedure. [Figure 3] This is an explanatory diagram showing the data format of the precharge command in this embodiment. [Figure 4] This is an explanatory diagram showing the contents of the extended flag field in the precharge command. [Figure 5] This is a flowchart showing the refresh process procedure. [Figure 6] This is an explanatory diagram showing the data format of the refresh command in this embodiment. [Figure 7] This is an explanatory diagram showing the contents of the extended flag field in the refresh command. [Figure 8] This is a timing chart showing an example of the operation of the memory system in this embodiment and comparative example. [Figure 9] This is a timing chart illustrating another example of the operation of the memory system in this embodiment. [Figure 10] This block diagram shows the schematic configuration of the memory system in the second embodiment. [Figure 11] This is an explanatory diagram showing an example of the settings in the extended flag field, the first register, and the second register in the second embodiment. [Modes for carrying out the invention]

[0010] A. First Embodiment: A1. System configuration: As shown in Figure 1, the memory system 100 of the first embodiment comprises a memory controller 110 and a semiconductor memory device 120. The memory system 100 reads and writes data to the semiconductor memory device 120 via the memory controller 110 in response to access requests issued from the arithmetic unit 200. The arithmetic unit 200 may be, for example, a CPU or a GPU (Graphics Processing Unit).

[0011] The memory controller 110 is connected to the arithmetic unit 200 via the bus 10 and receives access requests to the semiconductor memory device 120 issued by the arithmetic unit 200. The memory controller 110 is also connected to the semiconductor memory device 120 via the command bus 20 and issues commands represented by bit sequences to the semiconductor memory device 120 in response to access requests. The memory controller 110 issues the above commands in accordance with the clock signal that serves as the basis for the operation of the memory system 100. In addition, the memory controller 110 converts the logical address of the data to be accessed, as contained in commands such as read, write, and active, to the physical address that indicates the storage area on the semiconductor memory device 120 where the data is stored.

[0012] Specifically, if the access request is a write access request requesting to write data to the semiconductor memory device 120, the memory controller 110 issues a write command instructing the semiconductor memory device 120 to write data to the address specified in the access request (hereinafter also referred to as the "access target address"). If the access request is a read access request requesting to read data from the semiconductor memory device 120, the memory controller 110 issues a read command instructing the semiconductor memory device 120 to read data from the access target address. The write command and read command include a column address section that specifies the column address of the access target address.

[0013] Before issuing a write command or a read command to the semiconductor memory device 120, the memory controller 110 issues an active command to the semiconductor memory device 120 in order to make the semiconductor memory device 120 accessible (hereinafter also referred to as "active"). The active command includes a bank number specifying part, a bank address part, and a row address part.

[0014] Also, in the present embodiment, the memory system 100 includes a DRAM (Dynamic Random Access Memory) compliant with the so-called LPDDR5 standard, and a precharge command and a refresh command can be issued as access requests. The precharge command is a command that requests the execution of "precharge", which is an operation of turning off the FET switches between all bit lines and the capacitors of each memory cell and charging the bit lines to Vdd / 2. The refresh command is a command that requests the execution of "refresh", which is an operation of injecting charge into the capacitor of each memory cell at regular intervals, replenishing the charge leaking from such capacitor, and maintaining the stored information.

[0015] The semiconductor memory device 120 is formed by arranging memory cells, which are memory elements, in a matrix, and can perform various operations such as writing data to each memory cell, reading data from each memory cell, precharge, and refresh according to commands issued from the memory controller 110. As described above, the semiconductor memory device 120 of the present embodiment is LPDDR5, and the semiconductor memory device 120 includes bank groups BG0 to BG3. Each of the bank groups BG0 to BG3 includes 4 banks. The bank group BG0 includes banks B0 to B3, the bank group BG1 includes banks B4 to B7, the bank group BG2 includes banks B8 to B11, and the bank group BG3 includes banks B12 to B15.

[0016] In the semiconductor memory device 120, the above-described precharge command and refresh command are issued from the memory controller 110 to the semiconductor memory device 120. A predetermined time called tRP is defined as the shortest period from the issuance of the precharge command until the next precharge command is issued. Also, the refresh command is issued every predetermined period (interval) called tREFi. Further, the shortest period from the completion of the precharge operation until the start of the refresh operation is set in advance. The memory controller 110 issues the precharge command and the refresh command to the semiconductor memory device 120 in accordance with these set periods. In the semiconductor memory device 120, when the precharge command is received, the precharge process described below is executed. Also, in the semiconductor memory device 120, when the refresh command is received, the refresh process described below is executed.

[0017] A2. Precharge Process: The precharge process shown in FIG. 2 is a process for executing precharge in the semiconductor memory device 120, and is executed when the precharge command is received from the memory controller 110 as described above.

[0018] The semiconductor memory device 120 determines whether the value of the extended flag field of the received precharge command is "000" or "001" (step S15). Hereinafter, "step S" will be simply represented as "S".

[0019] As shown in Figure 3, the precharge command of this embodiment includes a command field F1, a bank address field F2, and an extended flag field F3. The command field F1 is a field that indicates the type of command and consists of a total of 7 bits, from bits b8 to b14. "0001111" shown in Figure 3 indicates that it is a precharge command. The bank address field F2 is a field that indicates the bank and consists of 4 bits, from bits b4 to b7. If the bank address field F2 is "0000", it indicates bank B0, and if it is "1111", it indicates bank B15.

[0020] The extended flag field F3 is a field that indicates the number of banks to be precharged and the time difference when two banks are precharged with a time difference as described below, and consists of bits b1 to b3. More specifically, the extended flag field F3 is a field that specifies (i) and (ii) below. (i) Precharge one bank, precharge all banks, or precharge two banks that belong to different bank groups. (ii) The second relative processing timing relative to the first bank when two banks are pre-charged.

[0021] Figure 4 shows a specific example of setting the extended flag field F3 in the precharge command. The following explains the settings for each value from "000" to "111". • "000": Indicates that the pre-charge target is only one bank, as specified in the bank address field F2. Regarding (ii) above, no specific value is set because it is not applicable. • "001": Indicates that all banks are subject to pre-charging. In this case, the bank address specified in the bank address field F2 is invalid. Similar to "000" above, "001" is not subject to (ii) above, so no specific value is set. • "010": Indicates that there are two banks to be precharged. The relative processing timing in (ii) above is simultaneous, meaning that the two banks are precharged at the same time. • "011": Indicates that there are two banks to be precharged. Also indicates that the relative processing timing in (ii) above is delayed by one cycle from the precharge execution of the first bank. "Cycle" refers to the period in the clock cycle. • "100": This indicates that there are two banks subject to precharging. It also indicates that the relative processing timing in (ii) above is delayed by two cycles from the precharging execution of the first bank. • "101": This indicates that there are two banks subject to precharging. It also indicates that the relative processing timing in (ii) above is delayed by 3 cycles from the precharging execution of the first bank. • "110": This indicates that there are two banks subject to precharging. It also indicates that the relative processing timing in (ii) above is delayed by 4 cycles from the precharging execution of the first bank. • "111": This indicates that there are two banks subject to precharging. It also indicates that the relative processing timing in (ii) above is delayed by 5 cycles from the precharging execution of the first bank.

[0022] Here, bits b1 to b3 of the extended flag field F3 have the same meaning as the least significant three bits in the precharge command in conventional LPDDR5. That is, conventionally, if the least significant three bits were "000", it meant that only the one bank specified in the bank address would be subject to precharge. Also, if the least significant three bits were "001", it meant that all banks would be subject to precharge. Therefore, the purpose of using these least significant three bits is the same as in previous systems, and thus it is compatible. Details of the two banks that are subject to precharge when the extended flag field F3 is "010" to "111" will be described later.

[0023] As shown in Figure 2, if it is determined that the value of the extended flag field F3 of the received precharge command is "000" or "001" (S15: YES), the semiconductor memory device 120 determines whether the value of the extended flag field F3 is "000" or not (S20).

[0024] If the value of the extended flag field F3 is determined to be "000" (S20: YES), the semiconductor memory device 120 performs pre-charging only for the bank specified in the bank address field F2 (S25).

[0025] If it is determined that the value of the extended flag field F3 is not "000" (S20: NO), then in this case the value of the extended flag field F3 is "001", and the semiconductor memory device 120 performs a precharge for all banks (S30).

[0026] In S15 described above, if it is determined that the value of the extended flag field F3 of the received precharge command is not "000" or "001" (S15:NO), that is, if it is one of "010" to "111", the semiconductor memory device 120 performs a precharge targeting the bank specified by the bank address field F2 (hereinafter also referred to as the "first bank") (S35).

[0027] The semiconductor memory device 120 performs a precharge targeting the second bank with a delay of the timing specified by the extended flag field F3 (S40). In this embodiment, the "second bank" refers to the bank determined by the bank address obtained by inverting a predetermined bit, which is the inversion target bit, from the bit sequence (bits b4 to b7) that defines the bank group. In this embodiment, the "inversion target bit" is bit b7, which is the most significant bit in the bank address field F2. Therefore, for example, if the bank address field F2 is "0000", the first bank is bank B0, and the second bank is the bank indicated by "1000", i.e., bank B7. For example, if the value of the bank address field F2 is "0111" and the value of the extended flag field F3 is "111", the precharge of bank B6 is performed immediately as the first bank, and then, with a delay of 5 clock cycles, the precharge of bank B15 (1111) is performed as the second bank.

[0028] After the completion of steps S25, S30, and S40 described above, the pre-charge process ends. As described above, when one pre-charge command is received, depending on the value specified in the extended flag field F3, pre-charging of two banks can be performed. Compared to a configuration that requires sending and receiving pre-charge commands specifying each bank, this reduces the issuance of pre-charge commands and enables efficient use of the command bus 20.

[0029] A3. Refresh process: The refresh process shown in Figure 5 is a process for performing a refresh in the semiconductor memory device 120, and as described above, it is executed when a refresh command is received from the memory controller 110.

[0030] The semiconductor memory device 120 determines whether the value of the extended flag field of the received refresh command is "000" or "001" (S55).

[0031] As shown in Figure 6, the refresh command of this embodiment has a format similar to the precharge command described above. Specifically, the refresh command comprises a command field F1, a bank address field F2, and an extended flag field F3. The command field F1 is a field that indicates the type of command and consists of a total of 7 bits, from bits b8 to b14. "0001110" shown in Figure 3 indicates that it is a refresh command. The bank address field F2 is the same as the bank address field F2 of the precharge command described above.

[0032] The extended flag field F3 is the same as the extended flag field F3 of the precharge command described above in that it consists of three bits, b1 to b3. However, the content it indicates differs from that of the extended flag field F3 of the precharge command.

[0033] The extended flag field F3 of the refresh command indicates the number of banks to be refreshed and the time difference when refreshing two banks with a time difference, as described later. More specifically, the extended flag field F3 specifies (i) and (ii) below. (i) Either refresh all banks, or refresh two banks that belong to different bank groups. (ii) The second relative processing timing relative to the first bank when refreshing two banks.

[0034] Figure 7 shows a specific example of setting the extended flag field F3 in the refresh command. The following explains the settings for each value from "000" to "111". • "000": Indicates that there are two banks to be refreshed: the bank specified in the bank address field F2 (first bank) and the bank obtained by inverting the bits to be inverted (second bank). The relative processing timing in (ii) above indicates that it is simultaneous, that is, that the two banks are pre-charged at the same time. • "001": Indicates that all banks are the ones to be refreshed. In this case, the bank address specified in the bank address field F2 becomes invalid. • "010": Indicates that there are two banks to be refreshed. It also indicates that the relative processing timing in (ii) above is delayed by one cycle from the refresh execution of the first bank. • "011": Indicates that there are two banks to be refreshed. It also indicates that the relative processing timing in (ii) above is delayed by two cycles from the refresh execution of the first bank. • "100": Indicates that there are two banks to be refreshed. It also indicates that the relative processing timing in (ii) above is delayed by 3 cycles from the refresh execution of the first bank. • "101": Indicates that there are two banks to be refreshed. It also indicates that the relative processing timing in (ii) above is delayed by 4 cycles from the refresh execution of the first bank. • "110": This indicates that there are two banks to be refreshed. It also indicates that the relative processing timing in (ii) above is delayed by 5 cycles from the refresh execution of the first bank. • "111": Indicates that there are two banks to be refreshed. It also indicates that the relative processing timing in (ii) above is delayed by 6 cycles from the refresh execution of the first bank.

[0035] When the extended flag field F3 is "010" to "111", the two banks targeted for refresh are the same as the first and second banks in the precharge command described above. Here, bits b1 to b3 of the extended flag field F3 in the refresh command have the same meaning as the three least significant bits in the refresh command in conventional LPDDR5. That is, conventionally, when the three least significant bits were "000", it meant that the first and second banks specified in the bank address would be refreshed simultaneously. Also, when the three least significant bits were "001", it meant that all banks would be refreshed. Therefore, the purpose of using these three least significant bits is the same as in previous systems, and thus there is compatibility.

[0036] As shown in Figure 5, if it is determined that the value of the extended flag field F3 of the received refresh command is "000" or "001" (S55: YES), the semiconductor memory device 120 determines whether the value of the extended flag field F3 is "000" or not (S60).

[0037] If the value of the extended flag field F3 is determined to be "000" (S60: YES), the semiconductor memory device 120 performs a refresh on the first and second banks specified in the bank address field F2 (S65).

[0038] If it is determined that the value of the extended flag field F3 is not "000" (S60: NO), then in this case the value of the extended flag field F3 is "001", and the semiconductor memory device 120 performs a refresh on all banks (S70).

[0039] In S55 described above, if it is determined that the value of the extended flag field F3 of the received precharge command is not "000" or "001" (S55:NO), that is, if it is one of "010" to "111", the semiconductor memory device 120 performs a refresh targeting the first bank specified by the bank address field F2 (S75).

[0040] The semiconductor memory device 120 performs a refresh targeting the second bank with a delay of the timing specified by the extended flag field F3 (S80).

[0041] After the completion of steps S65, S70, and S80 described above, the refresh process ends. As described above, when one refresh command is received, depending on the value specified in the extended flag field F3, it is possible to perform refreshes on two banks. Compared to a configuration that requires sending and receiving refresh commands specifying each bank, this reduces the number of refresh commands that need to be issued, enabling efficient use of the command bus 20.

[0042] A4. Example of operation: Examples of operation when the pre-charge and refresh processes described above are performed will be explained using Figures 8 and 9. In Figure 8, the upper timing chart shows the operation in the comparative example, and the lower timing chart shows the operation in the first embodiment.

[0043] In the comparative example shown in the upper part of Figure 8, for example, in order to perform pre-charge and refresh on banks B0 and B7, the memory controller 110 issues a pre-charge command (PRE) specifying bank B0 (0000) at period T2. Period T2 is, for example, the timing when tRP has elapsed since the previous pre-charge for bank B0. Then, at period T6, the memory controller 110 issues a pre-charge command specifying bank B7 (1000). This period T6 is also, for example, the timing when tRP has elapsed since the previous pre-charge for bank B7. After that, the memory controller 110 attempts to issue a refresh command (REF) for the two banks B0 and B7. However, if, for example, "6 cycles" is set as the shortest period between the issuance of a precharge command and the issuance of a refresh command, then the refresh command targeting both banks B0 and B7 will finally be issued at cycle T12, which is 6 cycles later than cycle T6, which is the timing for targeting bank B7, the bank for which the precharge command was issued later than bank B0 and B7.

[0044] In contrast, in the embodiment shown in the lower part of Figure 8, at period T2, a precharge command (PRE) is issued with bank 0 (0000) specified in the bank address field F2 and the extension flag set to "110". In this case, precharging is immediately performed on bank B0. Subsequently, at period T6, which is delayed by 4 periods from period T2, precharging is performed on bank B7 (1000). At this point, at period T8, which is delayed by 6 periods from T2, when the last precharge command was issued, a refresh command (REF) is issued with bank 0 (0000) specified and the extension flag set to "101". In this case, refreshing is immediately performed on bank B0. Subsequently, at period T12, which is delayed by 4 periods from period T8, refreshing is performed on bank B7.

[0045] As is clear from the comparison between the comparative example and this embodiment described above, in this embodiment, when performing the same operation as the comparative example, the issuance of precharge commands is suppressed compared to the comparative example. In addition, the timing of the issuance of refresh commands (REF) can be set to an earlier timing compared to the comparative example. Therefore, in this embodiment, the command bus 20 can be used more efficiently while ensuring the timing of the issuance of refresh commands or precharge commands compared to the comparative example.

[0046] In the example shown in Figure 9, the extended flag field F3 of the precharge command is set to "111", and the extended flag field F3 of the refresh command is set to "110". Therefore, the precharge command issued in period T2 precharges bank B0 as the first bank in period T2, and bank B7 as the second bank is precharged in period T7, which is 5 periods later than period T2. Also, the refresh command issued in period T8 refreshes bank B0 as the first bank in period T8, and bank B7 as the second bank is refreshed in period T13, which is 5 periods later than period T7. In order to perform the precharging and refreshing of the two banks B0 and B7, only two commands are issued between periods T2 and T13. Therefore, similar to the example shown in the lower part of Figure 8, the command bus 20 can be used efficiently while ensuring the timing for issuing the refresh command or precharge command.

[0047] In conventional LPDDR5 standard-compliant systems, refresh commands need to be issued 8 times per microsecond (μs) in high-temperature environments, resulting in one refresh command every 125 nanoseconds (ns). Furthermore, for every refresh command issued, two precharge commands must be issued, resulting in three command issuances every 125 ns (see upper part of Figure 8). On the other hand, in the memory system 100 of this embodiment, only one precharge command needs to be issued for every one refresh command, reducing the number of command issuances to one every 125 ns. Since the time required for one command issuance is 1.25 ns, a 1% reduction in commands is achieved.

[0048] Furthermore, the low address can be changed at a minimum interval of 42ns. Therefore, in systems conforming to the conventional LPDDR5 standard, two precharge commands are issued every 42ns. On the other hand, in the memory system 100 of this embodiment, the number of precharge commands issued can be reduced to one. This allows for a reduction of 1.25ns every 42ns, resulting in approximately a 3% reduction in commands.

[0049] Furthermore, a single command can precharge two banks, and as can be seen from the comparison between the upper and lower panels of Figure 8, the issuance of refresh commands can be brought forward from period T12 to period T8. If the tREFi (refresh interval) is 125ns, then every 125ns, four periods, or 5ns (1.25ns x 4), can be reduced, resulting in a 4% reduction in commands.

[0050] Combining the above command reduction effects, a total improvement of up to approximately 8% in the utilization efficiency of the command bus 20 is expected.

[0051] According to the memory system 100 of the first embodiment described above, when it is specified to precharge two banks by a precharge command, both the first bank and the second bank can be precharged with a single precharge command (PRE), thereby suppressing the issuance of precharge commands and freeing up space on the command bus 20. This allows for efficient use of the command bus 20 while ensuring the timing for issuing precharge commands.

[0052] Furthermore, when the memory controller 110 specifies that one bank should be precharged, the bit pattern of the extended flag field F3 of the precharge command should be such that the least significant three bits are 000. When it specifies that all banks should be precharged, the bit pattern of the extended flag field F3 of the precharge command should be such that the least significant three bits are 001. This allows the least significant three bits to be used in the same way as in previous memory systems. Therefore, compatibility with previous memory systems can be ensured.

[0053] Furthermore, the extended flag field F3 of the precharge command consists of a 3-bit sequence, and five bit patterns can be specified as relative processing timings, indicating a delay period from the execution of precharge targeting the first bank. Therefore, five delay periods can be flexibly set according to the usage status of the command bus 20.

[0054] Furthermore, according to the memory system 100, if a refresh command (REF) specifies that two banks should be refreshed, a single refresh command can refresh both the first and second banks, thereby reducing the number of refresh commands that need to be issued and freeing up space on the command bus 20. This allows for efficient use of the command bus 20 while ensuring the timing for issuing refresh commands.

[0055] Furthermore, when specifying that two banks be refreshed, the memory controller 110 specifies that the bit pattern of the extended flag field F3 of the refresh command is a pattern where the least significant three bits are 000, and when specifying that all banks be refreshed, it specifies that the bit pattern of the extended flag field F3 of the refresh command is a pattern where the least significant three bits are 001. This allows the least significant three bits to be used in the same way as in the previous memory system. Therefore, compatibility with the previous memory system can be ensured.

[0056] Furthermore, the extended flag field of the refresh command consists of a 3-bit sequence, and it is possible to specify six bit patterns that indicate the delay period from the execution of a refresh targeting the first bank as a relative processing timing. Therefore, six delay periods can be flexibly set depending on the usage of the command bus.

[0057] B. Second Embodiment: The memory system 100a of the second embodiment shown in Figure 10 differs from the memory system 100 of the first embodiment in that it includes five first registers 31, 32, 33, 34, and 35, and six second registers 41, 42, 43, 44, 45, and 46. The other components of the memory system 100a of the second embodiment are the same as those of the memory system 100 of the first embodiment, so the same components are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0058] The five first registers 31-35 each have a delay period set corresponding to the five bit patterns "011", "100", "101", "110", and "111" indicated by the extended flag field F3 of the precharge command. Similarly, the six second registers 41-46 each have a delay period set corresponding to the six bit patterns "010", "011", "100", "101", "110", and "111" indicated by the extended flag field F3 of the refresh command, with each of the first registers 31-35 having a delay period set.

[0059] Specifically, as shown in Figure 11, in this embodiment, the following delay times are set corresponding to each of the five bit patterns "011", "100", "101", "110", and "111" indicated by the extended flag field F3 of the precharge command. • "011": 1 cycle delay • "100": 3-cycle delay • "101": 5-period delay • "110": 7-period delay • "111": 8-period delay

[0060] Furthermore, in this embodiment, the following delay times are set in each of the second registers 41 to 46, corresponding to each of the six bit patterns "010", "011", "100", "101", "110", and "111" indicated by the extended flag field F3 of the refresh command. • "010": 1 cycle delay • "011": 2-cycle delay • "100": 5-period delay • "101": 7-period delay • "110": 9-period delay • "111": 12-period delay

[0061] The values ​​set in each of the first registers 31-35 and each of the second registers 41-46 are rewritable. Therefore, the user can pre-set appropriate delay time candidates in the first registers 31-35 and the second registers 41-46, and can also change them thereafter.

[0062] In the pre-charge process, at S40, the delay time set in the register corresponding to the bit pattern specified in the extended flag field F3 among the first registers 31 to 35 is read, and the pre-charge of the second bank is executed with a delay of that amount from the pre-charge of the first bank.

[0063] Similarly, during the refresh process, in S80, the delay time set in the register corresponding to the bit pattern specified in the extended flag field F3 among the second registers 41-46 is read, and the refresh of the second bank is performed with a delay of that amount from the refresh of the first bank.

[0064] The memory system 100a of the second embodiment described above has the same effects as the memory system 100 of the first embodiment. In addition, when the semiconductor memory device 120 performs a precharge on the second bank, it reads the set delay period from the first registers 31 to 35 corresponding to the bit pattern specified by the extended flag field F3, and performs the precharge on the second bank at a timing delayed by the delay period from the precharge on the first bank. Therefore, by adjusting the delay period set in the first registers 31 to 35, the timing of the precharge on the second bank can be adjusted.

[0065] Similarly, when the semiconductor memory device 120 performs a refresh on the second bank, it reads the set delay period from the second registers 41 to 46 corresponding to the bit pattern specified by the extended flag field F3, and performs the refresh on the second bank at a time delayed by the delay period from the refresh on the first bank. Therefore, the timing of the refresh on the second bank can be adjusted by adjusting the delay period set in the second registers 41 to 46.

[0066] C. Other embodiments: (C1) In each embodiment, the bit to be inverted is the most significant bit (bit b7) of the bank address field F2, but the disclosure is not limited thereto. The bit to be inverted may be a predetermined bit from the bit sequence that defines the bank group in the bank address portion.

[0067] (C2) In each embodiment, bits b1 to b3 of the extended flag field F3 of the precharge command and refresh command had the same meaning as the least significant 3 bits in the refresh command in conventional LPDDR5, but this disclosure is not limited thereto. A completely different data format from the conventional precharge command and refresh command may be adopted for the data format of the precharge command and refresh command of this disclosure. In such a configuration, the extended flag field F3 may consist of any number of bits, not limited to 3 bits. Furthermore, the extended flag field F3 may not include the least significant bit. Also, the command field F1 and bank address field F2 may consist of bit sequences with a different number of bits than the number of bits in each embodiment.

[0068] (C3) In each embodiment, only one of the precharge command and the refresh command may be to which the present disclosure applies, and the other command may be processed using the conventional data format and according to the conventional rules. For example, the precharge command may be specified to perform a precharge on only one bank or a precharge on all banks, and the refresh command may be specified to perform a refresh on two banks with a time difference. Alternatively, the precharge command may be specified to perform a precharge on two banks with a time difference, and the refresh command may be specified to refresh two banks simultaneously or all banks simultaneously.

[0069] (C4) Each embodiment is merely an example and can be modified in various ways. For example, the number of bank groups is not limited to four, but can be any number. Also, the number of banks included in each bank group is not limited to four, but can be any number.

[0070] This disclosure is not limited to the embodiments described above, and can be implemented in various configurations without departing from its spirit. For example, the technical features in each embodiment corresponding to the technical features in the embodiments described in the summary of the invention can be replaced or combined as appropriate in order to solve some or all of the above-mentioned problems, or to achieve some or all of the above-mentioned effects. Furthermore, if a technical feature is not described as essential in this specification, it can be deleted as appropriate.

[0071] The entity that performs the precharge and refresh processes described in this disclosure (hereinafter referred to as the "control unit") and its method may be implemented by a dedicated computer provided by configuring a processor and memory programmed to perform one or more functions embodied by a computer program. Alternatively, the control unit and its method described in this disclosure may be implemented by a dedicated computer provided by configuring a processor with one or more dedicated hardware logic circuits. Alternatively, the control unit and its method described in this disclosure may be implemented by one or more dedicated computers configured by a combination of a processor and memory programmed to perform one or more functions and a processor configured with one or more hardware logic circuits. Furthermore, the computer program may be stored as instructions executed by the computer on a computer-readable non-transitional tangible recording medium.

[0072] This disclosure may be implemented in the following forms: [Form 1] A memory system (100, 100a) comprising a semiconductor memory device (120) having multiple bank groups (BG0 to BG3), and a memory controller (110) that issues commands in response to access requests from an arithmetic unit (200) accessing the semiconductor memory device, The memory controller, as a precharge command, It is an extended flag field (F3), One of the following: pre-charging one bank, pre-charging all banks, or pre-charging two banks belonging to different bank groups. An extended flag field is a bit string that specifies the second relative processing timing with respect to the first bank when precharging two banks, The bank address field (F2) is a bit sequence that defines the bank address of the bank subject to precharging, A command including the above is issued to the semiconductor memory device, The aforementioned semiconductor memory device, If the aforementioned precharge command specifies that two banks should be precharged, Perform a precharge on the first bank determined by the bank address field, For the second bank, which is determined by the bank address obtained by inverting a predetermined single bit, which is the bit to be inverted, from the bit sequence that defines the bank group in the bank address field, a precharge is performed at the relative processing timing specified by the extended flag field. Memory system. [Form 2] In the memory system described in Embodiment 1, The extended flag field includes the least significant 3 bits in the data format of the precharge command. The aforementioned memory controller When specifying that one bank should be precharged, the bit pattern of the extended flag field is specified to be a pattern in which the least significant 3 bits are 000. A memory system in which, when specifying that all banks be precharged, the bit pattern of the extended flag field is specified to be a pattern in which the least significant 3 bits are 001. [Form 3] The memory system described in Form 2, The aforementioned extended flag field consists of a 3-bit sequence, A memory system in which five bit patterns can be specified as the relative processing timing, indicating a delay period from the execution of pre-charging for the first bank. [Form 4] A memory system as described in form 3, The system further comprises five registers (31-35) in which the delay period is set, corresponding to each of the five bit patterns. The semiconductor memory device is a memory system that, when performing a precharge on the second bank, reads the set delay period from the register corresponding to the bit pattern specified by the extended flag field, and performs the precharge at a timing delayed by the delay period from the execution of the precharge on the first bank. [Form 5] A memory system (100, 100a) comprising a semiconductor memory device (120) having multiple bank groups (BG0 to BG3), and a memory controller (110) that issues commands in response to access requests from an arithmetic unit (200) accessing the semiconductor memory device, The memory controller, as a refresh command, It is an extended flag field (F3), Refreshing all banks, or refreshing two banks belonging to different bank groups, An extended flag field is a bit string that specifies the second relative processing timing with respect to the first bank when refreshing two banks, The bank address field is a bit sequence that defines the bank address of the bank to be refreshed, A command including the above is issued to the semiconductor memory device, The aforementioned semiconductor memory device, If the refresh command specifies that two banks should be refreshed, Perform a refresh on the first bank specified by the bank address field, For the second bank, which is determined by the bank address obtained by inverting a predetermined single bit, which is the bit to be inverted, from the bit sequence that defines the bank group in the aforementioned bank address field, a refresh is performed at the relative processing timing specified by the extended flag field. Memory system. [Form 6] In the memory system described in Form 5, The extended flag field includes the least significant 3 bits in the data format of the refresh command. The aforementioned memory controller When specifying that two banks should be refreshed, the bit pattern of the extended flag field is specified to be a pattern where the least significant 3 bits are 000. A memory system in which, when specifying that all banks should be refreshed, the bit pattern of the extended flag field is specified to be a pattern in which the least significant 3 bits are 001. [Form 7] The memory system described in form 6, The aforementioned extended flag field consists of a 3-bit sequence, A memory system in which six bit patterns can be specified as the relative processing timing, indicating a delay period from the execution of a refresh targeting the first bank. [Form 8] The memory system described in form 7, The system further comprises six registers (41-46) in which the delay period is set, corresponding to each of the six bit patterns. The semiconductor memory device is a memory system that, when performing a refresh on the second bank, reads the set delay period from the register corresponding to the bit pattern specified by the extended flag field, and performs the refresh at a timing delayed by the delay period from the refresh performed on the first bank. [Explanation of Symbols]

[0073] BG0~BG3…Bank group, F2…Bank address field, F3…Extended flag field, 100,100a…Memory system, 110…Memory controller, 120…Semiconductor memory device, 200…Arithmetic unit

Claims

1. A memory system (100, 100a) comprising a semiconductor memory device (120) having multiple bank groups (BG0 to BG3), and a memory controller (110) that issues commands in response to access requests from an arithmetic unit (200) that accesses the semiconductor memory device, The memory controller, as a precharge command, Extended flag field (F3), One of the following: making one bank precharged, making all banks precharged, or precharged two banks belonging to different bank groups. An extended flag field is a bit string that specifies the second relative processing timing with respect to the first bank when precharging two banks, The bank address field (F2) is a bit sequence that defines the bank address of the bank subject to precharging, A command including the above is issued to the semiconductor memory device, The aforementioned semiconductor memory device, If the aforementioned precharge command specifies that two banks should be precharged, Perform a precharge on the first bank determined by the bank address field, For the second bank, which is determined by the bank address obtained by inverting a predetermined single bit, which is the bit to be inverted, from the bit sequence that defines the bank group in the bank address field, a precharge is performed at the relative processing timing specified by the extended flag field. Memory system.

2. In the memory system according to claim 1, The extended flag field includes the least significant three bits in the data format of the precharge command. The aforementioned memory controller When specifying that one bank be precharged, the bit pattern of the extended flag field is specified to be a pattern in which the least significant three bits are 000. A memory system in which, when specifying that all banks be precharged, the bit pattern of the extended flag field is specified to be a pattern in which the least significant three bits are 001.

3. The memory system according to claim 2, The aforementioned extended flag field consists of a 3-bit sequence, A memory system in which five bit patterns can be specified as the relative processing timing, indicating a delay period from the execution of pre-charging for the first bank.

4. The memory system according to claim 3, The system further comprises five registers (31-35) in which the delay period is set, corresponding to each of the five bit patterns. The semiconductor memory device is a memory system that, when performing a precharge on the second bank, reads the set delay period from the register corresponding to the bit pattern specified by the extended flag field, and performs the precharge at a timing delayed by the delay period from the execution of the precharge on the first bank.

5. A memory system (100, 100a) comprising a semiconductor memory device (120) having multiple bank groups (BG0 to BG3), and a memory controller (110) that issues commands in response to access requests from an arithmetic unit (200) that accesses the semiconductor memory device, The memory controller, as a refresh command, Extended flag field (F3), Either refresh all banks, or refresh two banks belonging to different bank groups. An extended flag field is a bit string that specifies the second relative processing timing with respect to the first bank when refreshing two banks, The bank address field is a bit sequence that defines the bank address of the bank to be refreshed, A command including the above is issued to the semiconductor memory device, The aforementioned semiconductor memory device, If the refresh command specifies that two banks should be refreshed, Perform a refresh on the first bank specified by the bank address field, For the second bank, which is determined by the bank address obtained by inverting a predetermined single bit, which is the bit to be inverted, from the bit sequence that defines the bank group in the aforementioned bank address field, a refresh is performed at the relative processing timing specified by the extended flag field. Memory system.

6. In the memory system according to claim 5, The extended flag field includes the least significant three bits in the data format of the refresh command. The aforementioned memory controller When specifying that two banks should be refreshed, the bit pattern of the extended flag field is specified to be a pattern where the least significant three bits are 000. A memory system in which, when specifying that all banks should be refreshed, the bit pattern of the extended flag field is specified to be a pattern in which the least significant three bits are 001.

7. A memory system according to claim 6, The aforementioned extended flag field consists of a 3-bit sequence, A memory system in which six bit patterns can be specified as the relative processing timing, indicating a delay period from the execution of a refresh targeting the first bank.

8. A memory system according to claim 7, The system further comprises six registers (41-46) in which the delay period is set, corresponding to each of the six bit patterns. The semiconductor memory device is a memory system that, when performing a refresh on the second bank, reads the set delay period from the register corresponding to the bit pattern specified by the extended flag field, and performs the refresh at a timing delayed by the delay period from the refresh performed on the first bank.

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