Method and apparatus for optimizing the program / erase voltage of a charge trap type memory element using 3D trap analysis

Abstract

The present invention relates to a method and apparatus for optimizing the program / erase voltage of a charge trap type memory element by three-dimensional trap analysis. [Solution] Different trap control voltages are applied to memory elements, and the low-frequency noise of the memory elements corresponding to each trap control voltage is measured. Based on the low-frequency noise, the trap distribution in the memory elements for each trap control voltage is extracted, and the trap distribution is analyzed according to the depth of the memory element to detect the trap control voltage that has the maximum trap distribution in the charge trap layer of the memory element. This makes it possible to detect at least one of the optimal program voltage or erase voltage for the memory element.

Description

Technical Field

[0001] The present invention generally relates to the optimization of memory elements, and more particularly, to the optimization of program / erase voltages of charge trap type memory elements by three-dimensional trap analysis. This patent was supported by the Korea Research Foundation (RS-2023-00280841) with funds from the Ministry of Science and ICT.

Background Art

[0002] As a traditional method for extracting the amount of charge trapped in the charge trap layer of a charge trap type memory element, C-V measurement and charge pumping measurement have been used. However, C-V measurement has the disadvantage that the amount of trapped charge can only be known indirectly, and in the charge pumping method, the depth of the trap that can be measured depends on the gate voltage, so the trap in the charge trap layer could not be measured during program / erase.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present disclosure provides a method and apparatus for checking the trap distribution from the interface to the trap layer during program / erase because the depth of the trap depends on the frequency.

[0004] The present disclosure provides an optimization method and apparatus for program / erase voltages of charge trap type memory elements by three-dimensional trap analysis.

Means for Solving the Problems

[0005] In this disclosure, a method for operating a computing device for optimizing the program voltage and erase voltage of a charge trap type memory element by three-dimensional trap analysis may include the steps of: applying different trap control voltages to the memory element and measuring the low-frequency noise of the memory element corresponding to each trap control voltage; extracting the trap distribution in the memory element for each trap control voltage based on the low-frequency noise; and analyzing the trap distribution according to the depth of the memory element and detecting the trap control voltage having the maximum trap distribution in the charge trap layer of the memory element.

[0006] In this disclosure, a computing device for optimizing the program voltage and erase voltage of a charge trap type memory element by three-dimensional trap analysis includes a memory and a processor connected to the memory and configured to execute at least one instruction word stored in the memory, wherein the processor may be configured to apply different trap control voltages to the memory elements, measure the low-frequency noise of the memory elements corresponding to each trap control voltage, extract the trap distribution in the memory elements for each trap control voltage based on the low-frequency noise, analyze the trap distribution according to the depth of the memory element, and detect a trap control voltage that has the maximum trap distribution in the charge trap layer of the memory element. [Effects of the Invention]

[0007] This disclosure allows for the optimization of at least one of the program voltage or erase voltage of a charge-trapped memory element based on frequency analysis and depth analysis. Specifically, this disclosure allows for the detection of at least one of the optimal program voltage or erase voltage of the charge-trapped memory element by analyzing the trap distribution due to the voltage applied to the charge-trapped memory element according to depth. This enables the charge-trapped memory element to operate based on at least one of the optimal program voltage or erase voltage. Consequently, the memory window of the charge-trapped memory element is increased. Furthermore, the electrical stress applied to the charge-trapped memory element during operation can be minimized, thereby suppressing or preventing degradation of the charge-trapped memory element. This extends the lifespan of the charge-trapped memory element and reduces unnecessary power consumption. [Brief explanation of the drawing]

[0008] [Figure 1] This diagram schematically illustrates computing devices in various embodiments. [Figure 2] This diagram schematically illustrates the operation methods of a computing device in various embodiments. [Figure 3] Figure 2 is a diagram that shows in detail the steps for measuring each of the low-frequency noises. [Figure 4] This figure exemplifies a three-dimensional graph showing the relationship between the trap control voltage, trap distribution, and depth, as represented in the step of detecting the trap control voltage in Figure 2. [Modes for carrying out the invention]

[0009] In the following, this disclosure provides a method and apparatus for optimizing the program / erase voltage of a charge-trapped memory element by three-dimensional trap analysis. Generally, a charge-trapped memory element includes a substrate having a source electrode, a drain electrode, and a channel region between the source electrode and the drain electrode; a tunnel layer stacked on the channel region to allow charges injected from the channel region to pass through; a charge trap layer stacked on the tunnel layer to trap charges from the tunnel layer; and a gate electrode formed on the charge trap layer, and at least one other component may be added between adjacent components. For example, a block layer, such as an insulating layer, may be added between the charge trap layer and the gate electrode. Here, the tunnel layer and the charge trap layer, or when a block layer is added, the tunnel layer, the charge trap layer, and the block layer may be called oxide layers. The memory window of a charge-trapped memory element is maximized when the maximum amount of charge is trapped in the charge trap layer during a program operation and the maximum amount of charge is detrapped in the charge trap layer during an erase operation. In order to trap the maximum amount of charge in the charge trap layer, the trap distribution must be small in the interface region between the tunnel layer and the charge trap layer and in the tunnel layer. On the other hand, since the location (depth) where traps concentrate within a charge-trapped memory element differs depending on the applied voltage, it is necessary to strategically analyze this. Therefore, this disclosure proposes a technique for obtaining an optimized program / erase voltage through low-frequency noise analysis and depth analysis.

[0010] Various embodiments of this disclosure will be described below with reference to the accompanying drawings.

[0011] Figure 1 is a schematic diagram showing the computing device 100 in various embodiments.

[0012] Referring to Figure 1, the computing device 100 is for optimizing the program voltage and erase voltage of a charge trap memory element by three-dimensional trap analysis and may include at least one of the following: a camera module 110, a communication module 120, an input module 130, an output module 140, a measurement module 150, a memory 160, or a processor 170. In some embodiments, at least one of the components of the computing device 100 (e.g., the camera module 110, the communication module 120) may be omitted, or at least one other component may be added. In some embodiments, at least two of the components of the computing device 100 may be implemented as a single integrated circuit. In some embodiments, the components of the computing device 100 may be distributed across at least two devices, which may be connected to each other in a communicative manner.

[0013] The camera module 110 may capture images with the computing device 100. Here, the camera module 110 may be, but is not limited to, an RGB camera. For example, the camera module 110 may include at least one of a lens, an image sensor, an image signal processor, or a flash.

[0014] The communication module 120 may perform communication with an external device (not shown) on the computing device 100. The communication module 120 may establish a communication channel between the computing device 100 and the external device and communicate with the external device via the communication channel. For example, the external device may include at least one of an electronic device, a base station, a server, or a satellite. The communication module 120 may include at least one of a wired communication module or a wireless communication module. For example, the wireless communication module may communicate with the external device via at least one of a telecommunications network or a short-range communication network.

[0015] The input module 130 may input commands to be used for at least one component of the computing device 100. The input module 130 may include at least one of the following: an input unit configured for a user to directly input commands or data to the computing device 100, or a sensor unit configured to detect the surrounding environment and generate data. For example, the input unit may include at least one of the following: a microphone, a mouse, or a keyboard. In some embodiments, the input unit may include at least one of the following: a touch circuitry configured to detect touches, or a sensor circuitry configured to measure the intensity of the force generated by a touch.

[0016] The output module 140 may output information to the outside of the computing device 100. The output module 140 may include at least one of a display module that outputs information visually, or an audio module that outputs information audibly. For example, the display module may include at least one of a display, a hologram device, or a projector. In one embodiment, the display module may be combined with at least one of the touch circuit or sensor circuit of the input module 130 to be implemented as a touchscreen. For example, the audio module may include at least one of a speaker or a receiver.

[0017] The measurement module 150 may measure the low-frequency noise of the charge-trap memory element. The low-frequency noise may include noise generated by the drain current of the charge-trap memory element and noise corresponding to the flat-band voltage of the charge-trap memory element.

[0018] Memory 160 may store various data used by at least one component of computing device 100. For example, memory 160 may include at least one of volatile memory or non-volatile memory. The data may include input data or output data for a program or instructions related thereto. The program may be stored as software in memory 160 and may include at least one of an operating system, middleware, or an application.

[0019] Processor 170 may execute the program in memory 160 and control at least one component of computing device 100. Thereby, processor 170 can perform data processing or operations. At this time, processor 170 may execute the instructions stored in memory 160.

[0020] In various embodiments, processor 170 may determine at least one of an optimal program voltage or an erase voltage for a charge trap type memory element based on three-dimensional trap analysis. In the charge trap type memory element, during the program operation, as many charges as possible are trapped in the charge trap layer, and during the erase operation, as many charges as possible are detrapped in the charge trap layer, so that the memory window becomes maximum. In order to trap as many charges as possible in the charge trap layer, the interface region between the charge trap layer and the tunnel layer and the trap distribution in the tunnel layer must be reduced. On the other hand, depending on the applied voltage, the position (depth) where traps are concentrated in the charge trap type memory element is different. Therefore, processor 170 can determine at least one of an optimal program voltage or an erase voltage based on low-frequency noise analysis and depth analysis.

[0021] Specifically, the processor 170 may apply different trap control voltages to the charge trap type memory element via the measurement module 150 to measure the low-frequency noise of the charge trap type memory element respectively. At this time, the trap control voltage includes different pairs of program voltage and erase voltage, and at least one of the program voltage or the erase voltage may be different from each other. The processor 170 may analyze the low-frequency noise and extract the trap distributions in the charge trap type memory element for the trap control voltages respectively. The processor 170 may analyze the trap distribution according to the depth of the charge trap type memory element and detect the trap control voltage having the maximum trap distribution in the charge trap layer of the charge trap type memory element. At this time, the detected trap control voltage is optimized for the charge trap type memory element and may include at least one of the program voltage or the erase voltage. Thereby, the charge trap type memory element can operate based on the detected trap control voltage.

[0022] FIG. 2 is a diagram schematically showing a method of operating the computing device 100 in various embodiments. FIG. 3 is a diagram showing in detail the step of measuring the low-frequency noise in FIG. 2 (step 220). FIG. 4 is an exemplary diagram showing a three-dimensional graph indicating the relationship between the trap control voltage, the trap distribution, and the depth represented by the step of detecting the trap control voltage in FIG. 2 (step 240).

[0023] Referring to Figure 2, first, in step 210, the computing device 100 may set parameters for trap analysis of the charge trap memory element. Specifically, the processor 170 may set parameters based on information input via at least one of the camera module 110, the communication module 120, or the input module 130. The parameters may include factors extracted from the charge trap memory element and factors applied to the charge trap memory element. Here, the parameters may include temperature conditions and voltage ranges. The voltage range indicates the range between the lower and upper limits to which the trap control voltage belongs, and the voltage ranges for the program voltage and the erase voltage may be different or the same.

[0024] Next, in step 220, the computing device 100 may apply different trap control voltages to the charge trap memory elements and measure the low-frequency noise of the charge trap memory elements corresponding to each trap control voltage. Specifically, the processor 170 may apply different trap control voltages based on set parameters. Here, the processor 170 may determine the trap control voltages within a set voltage range. The trap control voltages include different pairs of program voltages and erase voltages, where at least one of the program voltage or erase voltage may be different from the other. This allows the processor 170 to measure the low-frequency noise of the charge trap memory elements corresponding to each trap control voltage. The low-frequency noise may include noise generated by the drain current of the charge trap memory elements and noise corresponding to the flat-band voltage of the charge trap memory elements, corresponding to each trap control voltage. This will be explained in more detail with reference to Figure 3.

[0025] Referring to Figure 3, first, in step 310, the processor 170 may initialize the charge trap memory element. Specifically, the processor 170 may apply an arbitrary erase voltage to the charge trap memory element via the measurement module 150. This allows the applied erase voltage to detrap any charge trapped in the charge trap memory element. Here, the applied erase voltage may be within or outside the voltage range set in step 210, for example, it may be the upper limit of the set voltage range.

[0026] Next, in step 320, the processor 170 may select a pair of program voltages and erase voltages. The trap control voltages include different pairs of program voltages and erase voltages, where at least one of the program voltages or erase voltages may be different from the other. Thus, the processor 170 can select a pair of program voltages and erase voltages by selecting one of the trap control voltages.

[0027] Next, in step 330, the processor 170 may apply a selected program voltage to the charge trap memory element. Specifically, the processor 170 may apply a selected program voltage to the charge trap memory element via the measurement module 150. This allows charge to be trapped in the charge trap memory element by the applied program voltage. Next, in step 340, the processor 170 may measure the first low-frequency noise of the charge trap memory element. Specifically, the processor 170 may measure the first low-frequency noise in correspondence with the selected program voltage via the measurement module 150.

[0028] Next, in step 350, the processor 170 may apply a selected erase voltage to the charge-trap memory element. Specifically, the processor 170 may apply a selected erase voltage to the charge-trap memory element via the measurement module 150. This allows the applied erase voltage to detrap the charge in the charge-trap memory element. Next, in step 360, the processor 170 may measure the second low-frequency noise of the charge-trap memory element. Specifically, the processor 170 may measure the second low-frequency noise in correspondence with the selected erase voltage via the measurement module 150.

[0029] Next, in step 370, the processor 170 may determine whether the measurement is complete for the charge trap memory element. Specifically, the processor 170 may determine whether all trap control voltages, i.e., all pairs of program voltage and erase voltage, have been measured. If it is determined in step 370 that the measurement is not complete, the processor 170 may, in step 325, select one of the other trap control voltages, i.e., the other pair of program voltage and erase voltage. The processor 170 may then return to step 330. In this manner, the processor 170 can repeatedly measure the first and second low-frequency noises corresponding to all trap control voltages, i.e., all pairs of program voltage and erase voltage. If it is determined in step 370 that the measurement is complete, the processor 170 may proceed to step 230 in Figure 2.

[0030] Continuing to refer to Figure 2, in step 230, the computing device 100 may extract the trap distributions in the charge trap memory elements for each trap control voltage based on low-frequency noise. Specifically, the processor 170 may extract the trap distributions in the trap-controlled memory elements for each trap control voltage using the drain current and the normalized power spectral density (nPSD) of the flat-band voltage. At this time, the processor 170 may calculate the trap distributions using the following formula (1).

[0031]

number

[0032] Here, I D The drain current is JPEG2026111525000003.jpg77 shows the spectral density of noise generated by the drain current, S vfb This represents the spectral density of noise corresponding to the flat-band voltage and can be calculated as shown in equation (2) below. α is the Coulomb scattering coefficient, μ eff is the effective mobility of the charge, Cox is the capacitance of the oxide layer of the charge-trapped memory element, and g m This may represent the transconductance of a charge-trap type memory element.

[0033]

number

[0034] Here, q is the amount of charge, and k B is the Boltzmann constant, T is the absolute temperature, λ is the interface between the charge trap layer and the tunnel layer, and the tunnel distance (depth) of the tunnel layer, N t∫ represents the charge trap density, f represents the frequency, W represents the width of the channel region into which charge is injected through the tunnel layer to the charge trap layer, and L represents the length of the channel region.

[0035] Finally, in step 240, the computing device 100 may analyze the trap distribution according to the depth of the charge trap memory element and detect the trap control voltage that has the maximum trap distribution in the charge trap layer of the charge trap memory element. At this time, the detected trap control voltage is optimized for the charge trap memory element and may include at least one of the program voltage or erase voltage. Specifically, the processor 170 may analyze the trap distribution according to the depth of the charge trap memory element and confirm the depth of the charge trap layer of the charge trap memory element corresponding to each trap control voltage. At this time, the processor 170 may calculate the depth of the charge trap memory element using the following formula (3). This allows the processor 170 to confirm the relationship between the trap control voltage, trap distribution, and depth. For example, the processor 170 may represent the relationship between the trap control voltage, trap distribution, and depth in a three-dimensional graph, as shown in Figure 4. This may show the depth of the tunnel layer of the charge trap memory element and the trap distribution at the depth of the charge trap layer due to the trap control voltage. Therefore, the processor 170 can compare the trap distribution at different depths of the charge trap layer and detect the trap control voltage that has the maximum trap distribution in the charge trap layer.

[0036]

number

[0037] Here, Depth may represent the depth of the charge trap memory element, λ may represent the interface and tunnel distance between the charge trap layer and the tunnel layer, f may represent the frequency, and τ0 may represent the time constant in the interface region between the charge trap layer and the tunnel layer of the charge trap memory element.

[0038] More specifically, the processor 170 may extract trap distributions for program voltages based on a first low-frequency noise. Next, the processor 170 may analyze the trap distributions for program voltages according to the depth of the charge-trap memory element and detect the program voltage having the maximum trap distribution in the charge-trap layer of the charge-trap memory element. On the other hand, the processor 170 may extract trap distributions for erase voltages based on a second low-frequency noise. Next, the processor 170 may analyze the trap distributions for erase voltages according to the depth of the charge-trap memory element and detect the erase voltage having the maximum trap distribution in the charge-trap layer of the charge-trap memory element.

[0039] According to this disclosure, the computing device 100 can optimize the program voltage or erase voltage of a charge trap memory element. That is, the processor 170 can set at least one of the optimal program voltage or erase voltage for the trap memory element. As a result, the charge trap memory element can operate based on at least one of the optimal program voltage or erase voltage.

[0040] This disclosure enables the optimization of at least one of the program voltage or erase voltage of a charge-trapped memory element based on frequency analysis and depth analysis. Specifically, this disclosure can analyze the trap distribution due to the applied voltage in the charge-trapped memory element according to depth and detect at least one of the optimal program voltage or erase voltage for the charge-trapped memory element. This allows the charge-trapped memory element to operate based on at least one of the optimal program voltage or erase voltage. Consequently, the memory window of the charge-trapped memory element is increased. Furthermore, the electrical stress applied to the charge-trapped memory element during operation can be minimized, thereby suppressing or preventing degradation of the charge-trapped memory element. This extends the lifespan of the charge-trapped memory element and reduces unnecessary power consumption.

[0041] In summary, this disclosure provides a method for operating a computing device 100 for optimizing the program voltage and erase voltage of a charge-trapped memory element by three-dimensional trap analysis.

[0042] In this disclosure, the operation method of the computing device 100 may include the steps of: applying different trap control voltages to charge trap memory elements and measuring the low-frequency noise of the charge trap memory elements corresponding to each trap control voltage (step 220); extracting the trap distribution in the charge trap memory elements for each trap control voltage based on the low-frequency noise (step 230); and analyzing the trap distribution according to the depth of the charge trap memory elements and detecting the trap control voltage having the maximum trap distribution in the charge trap layer of the charge trap memory elements (step 240).

[0043] In this disclosure, the trap control voltage may include at least one of the program voltage or the erase voltage.

[0044] In this disclosure, low-frequency noise may include noise generated in the drain current of the charge-trapped memory element corresponding to each trap control voltage, and noise corresponding to the flat-band voltage of the charge-trapped memory element.

[0045] In this disclosure, the step of detecting the trap control voltage (step 230) may include the step of analyzing the trap distribution according to the depth of the charge trap memory element, confirming the depth of the charge trap layer of the charge trap memory element corresponding to each trap control voltage, and comparing the trap distribution at the depth of the charge trap layer to detect the trap control voltage having the maximum trap distribution in the charge trap layer.

[0046] In this disclosure, the step of extracting each trap distribution (step 230) may be performed by using the above formulas (1) and (2) to extract each trap distribution.

[0047] In this disclosure, the depth of the charge trap memory element may be calculated using the above formula (3).

[0048] In this disclosure, the trap control voltages include different pairs of program voltages and erase voltages, where at least one of the program voltages or erase voltages is different from the other, and the step of measuring low-frequency noise for each (step 220) may be repeated for each pair.

[0049] In this disclosure, the step of measuring low-frequency noise (step 220) includes the steps of applying a pair of program voltages to a charge-trap memory element to measure a first low-frequency noise of the charge-trap memory element (steps 330 and 340), and applying a pair of erase voltages to the charge-trap memory element to measure a second low-frequency noise of the charge-trap memory element (steps 350 and 360), wherein the first low-frequency noise measured from the pair may be used to detect a program voltage having the maximum trap distribution in the charge-trap layer, and the second low-frequency noise measured from the pair may be used to detect an erase voltage having the maximum trap distribution in the charge-trap layer.

[0050] In this disclosure, the computing device 100 includes a memory 160 and a processor 170 connected to the memory 160 and configured to execute at least one instruction word stored in the memory 160, wherein the processor 170 may be configured to apply different trap control voltages to charge trap memory elements, measure the low-frequency noise of the charge trap memory elements corresponding to each trap control voltage, extract the trap distribution in the charge trap memory elements with respect to the trap control voltage based on the low-frequency noise, analyze the trap distribution according to the depth of the charge trap memory elements, and detect the trap control voltage having the maximum trap distribution in the charge trap layer of the charge trap memory elements.

[0051] In this disclosure, the trap control voltage may include at least one of the program voltage or the erase voltage.

[0052] In this disclosure, low-frequency noise may include noise generated in the drain current of the charge-trapped memory element corresponding to each trap control voltage, and noise corresponding to the flat-band voltage of the charge-trapped memory element.

[0053] In this disclosure, the processor 170 may be configured to analyze the trap distribution according to the depth of the charge trap memory element, confirm the depth of the charge trap layer of the charge trap memory element corresponding to each trap control voltage, compare the trap distribution at the depth of the charge trap layer, and detect the trap control voltage having the maximum trap distribution in the charge trap layer.

[0054] In this disclosure, the processor 170 may use the above formulas (1) and (2) to extract the trap distribution, respectively.

[0055] In this disclosure, the processor 170 may use the above formula (3) to calculate the depth of each charge trap memory element.

[0056] In this disclosure, the trap control voltages include different pairs of program voltages and erase voltages, where at least one of the program voltages or erase voltages is different from the other, and the processor 170 may be configured to repeatedly measure low-frequency noise with respect to the pair.

[0057] In this disclosure, the processor 170 is configured to measure a first low-frequency noise of a charge-trap memory element by applying a pair of program voltages to the charge-trap memory element, and to measure a second low-frequency noise of the charge-trap memory element by applying an erase voltage of the same pair to the charge-trap memory element, wherein the first low-frequency noise measured from the pair is used to detect a program voltage having the maximum trap distribution in the charge-trap layer, and the second low-frequency noise measured from the pair is used to detect an erase voltage having the maximum trap distribution in the charge-trap layer.

[0058] The above-described apparatus may be implemented by hardware components, software components, and / or combinations of hardware and software components. For example, the apparatus and components described in the embodiments may be implemented using one or more general-purpose or special-purpose computers, such as processors, controllers, ALUs (arithmetic logic units), digital signal processors, microcomputers, FPGAs (field programmable gate arrays), PLUs (programmable logic units), microprocessors, or various devices capable of executing and responding to instructions. The processing unit may execute an operating system (OS) and one or more software applications running on the OS. The processing unit may also respond to software execution, access data, record, manipulate, process, and generate data. For convenience of understanding, it may be described as if a single processing unit is used, but those skilled in the art will understand that the processing unit may include multiple processing elements and / or multiple types of processing elements. For example, the processing unit may include multiple processors or one processor and one controller. Other processing configurations, such as parallel processors, are also possible.

[0059] Software may include computer programs, code, instructions, or a combination of one or more of these, which may configure a processing unit to operate as desired, or which may instruct the processing unit independently or collectively. Software and / or data may be embodied in any kind of machine, component, physical device, computer recording medium, or device for interpretation based on the processing unit or for providing instructions or data to the processing unit. Software may be distributed across a networked computer system, and may be recorded or executed in a distributed manner. Software and data may be recorded on one or more computer-readable recording media.

[0060] The methods according to the embodiment may be implemented in the form of program instructions executable by various computer means and recorded on a computer-readable medium. In this case, the medium may continuously record computer-executable programs or may temporarily record them for execution or download. Furthermore, the medium may be various recording or storage means in the form of a combination of one or more hardware components, and may be a medium directly connected to a computer system or distributed on a network. Examples of mediums include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, and devices configured to record program instructions such as ROM, RAM, and flash memory. Other examples of mediums include recording media and storage media managed by app stores that distribute applications, and sites and servers that supply and distribute various other software.

[0061] The various embodiments described herein and the terminology used herein should be understood not to limit the technology described herein to any particular embodiment, but to include various modifications, equivalents, and / or substitutes of the applicable embodiments. In connection with the description of the drawings, similar reference numerals have been used for similar components. Singular expressions may also include plural expressions unless the context clearly indicates otherwise. In this specification, expressions such as “A or B,” “A and / or B,” “A, B or C,” or “A, B, and / or C” may include all possible combinations of the items listed together. Expressions such as “first,” “second,” “first,” or “second” modify the applicable component regardless of order or importance, and are used only to distinguish one component from another, and not to limit the applicable component. When it is stated that a component (e.g., component 1) is "connected (functionally or communicatively)" or "linked" to another component (e.g., component 2), such component may be directly connected to such other component, or it may be connected via another component (e.g., component 3).

[0062] According to various embodiments, each component of the above-described components (e.g., a module or program) may include one or more individuals. According to various embodiments, one or more components or steps of the above-described components may be omitted, or one or more other components or steps may be added. Alternatively or additionally, multiple components (e.g., a module or program) may be integrated into a single component. In this case, the integrated component may perform one or more functions of each of the multiple components in the same or similar manner as those performed by the respective components among the multiple components before integration. According to various embodiments, steps performed by a module, program, or other component may be performed sequentially, in parallel, iteratively, or heuristically, or one or more steps may be performed in a different order, or omitted, or one or more other steps may be added. [Explanation of Symbols]

[0063] 100 computing devices 110 Camera Module 120 Communication Modules 130 Input Modules 140 Output Modules 150 measurement modules 160 memory 170 processors

Claims

1. A method for operating a computing device for optimizing the program voltage and erase voltage of a charge trap type memory element by three-dimensional trap analysis, The steps include: applying different trap control voltages to the memory elements using the measurement module of the processor of the computing device, and measuring the low-frequency noise of the memory elements corresponding to each trap control voltage; The processor performs the steps of: extracting the trap distribution in the memory element with respect to the trap control voltage based on the low-frequency noise; The processor performs the steps of: analyzing the trap distribution according to the depth of the memory element and determining a target trap control voltage that has the maximum trap distribution in the charge trap layer of the memory element; Includes, The low-frequency noise includes noise generated by the drain current of the memory element and noise corresponding to the flat-band voltage of the memory element, which correspond to the respective trap control voltages. The step of extracting the aforementioned trap distribution is: Using the spectral density of the noise generated by the drain current and the spectral density of the noise corresponding to the flat band voltage, the trap distribution in the memory element for each of the trap control voltages is extracted. The step of determining the target trap control voltage is: The steps include: confirming the trap distribution corresponding to the depth of the charge trap layer for each of the trap control voltages, based on the relationship between the trap distribution and the depth belonging to the charge trap layer; The steps include: determining the target trap control voltage from among the trap control voltages, based on the result of comparing the trap distribution corresponding to the depth belonging to the charge trap layer among the trap control voltages, and selecting the trap control voltage having the maximum trap distribution from among the trap control voltages; including, How computing devices operate.

2. The target trap control voltage includes at least one of the program voltage or the erase voltage. A method for operating the computing device according to claim 1.

3. The step of extracting the aforementioned trap distribution is: The trap distribution is extracted using the following formula: 、 Here, I Ｄ The drain current is The spectral density of the noise generated by the drain current is S ｖｆｂ μ is the spectral density of the noise corresponding to the flat band voltage, α is the Coulomb scattering coefficient, and ｅｆｆ g is the effective charge mobility, Cox is the capacitance of the oxide layer of the memory element, and g is the capacitance of the oxide layer of the memory element. ｍ k is the transconductance of the memory element, q is the amount of charge, and k is the amount of charge. Ｂ is the Boltzmann constant, T is the absolute temperature, λ is the interface between the charge trap layer and the tunnel layer and the tunneling distance of the tunnel layer, and N ｔ is the charge trap density, f is the frequency, W is the width of the channel region into which charge is injected into the charge trap layer, and L is the length of the channel region. A method for operating the computing device according to claim 1.

4. The depth of the memory element is calculated using the following formula: Here, Depth is the depth of the memory element, λ is the interface between the charge trap layer and the tunnel layer and the tunnel distance of the tunnel layer, f is the frequency, and τ ０ This indicates the time constant in the interface region between the charge trap layer and the tunnel layer of the memory element. A method for operating the computing device according to claim 1.

5. The trap control voltage includes a different pair of program voltages and erase voltages, wherein at least one of the program voltages or erase voltages is different from the other. The step of measuring each of the aforementioned low-frequency noises is: The following is repeatedly performed on the aforementioned pair: A method for operating the computing device according to claim 1.

6. The step of measuring each of the aforementioned low-frequency noises is: The steps include applying a pair of program voltages to the memory element to measure the first low-frequency noise of the memory element, The steps include applying the erase voltage of the pair to the memory element to measure the second low-frequency noise of the memory element, Includes, The first low-frequency noise measured from the pair is used to detect the program voltage having the maximum trap distribution in the charge trap layer. The second low-frequency noise measured from the pair is used to detect the erase voltage having the maximum trap distribution in the charge trap layer. A method for operating the computing device according to claim 5.

7. A computing device for optimizing the program voltage and erase voltage of a charge trap type memory element by three-dimensional trap analysis, Memory and A processor connected to the memory and configured to execute at least one instruction word stored in the memory, Includes, The aforementioned processor, The measurement module applies different trap control voltages to the memory elements and measures the low-frequency noise of the memory elements corresponding to each trap control voltage. Based on the low-frequency noise, the trap distribution in the memory element for each of the trap control voltages is extracted. The system is configured to analyze the trap distribution according to the depth of the memory element and detect a target trap control voltage that has the maximum trap distribution in the charge trap layer of the memory element. The low-frequency noise includes noise generated by the drain current of the memory element and noise corresponding to the flat-band voltage of the memory element, which correspond to the respective trap control voltages. In extracting the trap distribution, the processor Using the spectral density of the noise generated by the drain current and the spectral density of the noise corresponding to the flat band voltage, the trap distribution in the memory element for each of the trap control voltages is extracted. In determining the target trap control voltage, the processor Based on the relationship between the trap distribution and the depth belonging to the charge trap layer, the trap distribution corresponding to the depth belonging to the charge trap layer is confirmed for each of the trap control voltages. Based on the result of comparing the trap distribution corresponding to the depth belonging to the charge trap layer among the trap control voltages, the trap control voltage having the maximum trap distribution is determined from among the trap control voltages as the target trap control voltage. Computing device.

8. The target trap control voltage includes at least one of the program voltage or the erase voltage. The computing device according to claim 7.

Images